AU2001283257A1 - Direct build-up layer on an encapsulated die package - Google Patents

Direct build-up layer on an encapsulated die package

Info

Publication number
AU2001283257A1
AU2001283257A1 AU2001283257A AU8325701A AU2001283257A1 AU 2001283257 A1 AU2001283257 A1 AU 2001283257A1 AU 2001283257 A AU2001283257 A AU 2001283257A AU 8325701 A AU8325701 A AU 8325701A AU 2001283257 A1 AU2001283257 A1 AU 2001283257A1
Authority
AU
Australia
Prior art keywords
microelectronic die
layer
active surface
die package
encapsulation material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001283257A
Inventor
Harry Fujimoto
Qing Ma
Xiao-Chun Mu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001283257A1 publication Critical patent/AU2001283257A1/en
Abandoned legal-status Critical Current

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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Micromachines (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Chemical Treatment Of Metals (AREA)
  • Air Bags (AREA)
  • Die Bonding (AREA)

Abstract

A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s), wherein the encapsulation material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then disposed on the first dielectric material layer. The conductive trace(s) is in electrical contact with the microelectronic die active surface. At least one conductive trace extends adjacent the microelectronic die active surface and adjacent the encapsulation material surface.
AU2001283257A 2000-08-16 2001-08-10 Direct build-up layer on an encapsulated die package Abandoned AU2001283257A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US64096100A 2000-08-16 2000-08-16
US09/640,961 2000-08-16
PCT/US2001/025060 WO2002015266A2 (en) 2000-08-16 2001-08-10 Direct build-up layer on an encapsulated die package

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AU2001283257A1 true AU2001283257A1 (en) 2002-02-25

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EP (1) EP1354351B1 (en)
CN (1) CN100426492C (en)
AT (1) ATE429032T1 (en)
AU (1) AU2001283257A1 (en)
DE (1) DE60138416D1 (en)
HK (1) HK1055844A1 (en)
MY (1) MY141327A (en)
WO (1) WO2002015266A2 (en)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100389494C (en) * 2002-05-23 2008-05-21 威盛电子股份有限公司 IC package and its preparing process
DE10320579A1 (en) * 2003-05-07 2004-08-26 Infineon Technologies Ag Semiconductor wafer having an upper side, semiconductor chip positions with integrated circuits for first chips, central and edge regions and an equalizing layer useful in semiconductor technology
FR2857157B1 (en) * 2003-07-01 2005-09-23 3D Plus Sa METHOD FOR INTERCONNECTING ACTIVE AND PASSIVE COMPONENTS AND HETEROGENEOUS COMPONENT WITH LOW THICKNESS THEREFROM
DE10343053A1 (en) * 2003-09-16 2005-04-07 Siemens Ag Electronic component and arrangement with an electronic component
US7338836B2 (en) * 2003-11-05 2008-03-04 California Institute Of Technology Method for integrating pre-fabricated chip structures into functional electronic systems
DE102004022884B4 (en) 2004-05-06 2007-07-19 Infineon Technologies Ag Semiconductor device with a rewiring substrate and method of making the same
JP4343044B2 (en) 2004-06-30 2009-10-14 新光電気工業株式会社 Interposer, manufacturing method thereof, and semiconductor device
JP5193898B2 (en) 2009-02-12 2013-05-08 新光電気工業株式会社 Semiconductor device and electronic device
JP5535494B2 (en) 2009-02-23 2014-07-02 新光電気工業株式会社 Semiconductor device
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
FR2943176B1 (en) * 2009-03-10 2011-08-05 3D Plus METHOD FOR POSITIONING CHIPS WHEN MANUFACTURING A RECONSTITUTED PLATE
JP5106460B2 (en) 2009-03-26 2012-12-26 新光電気工業株式会社 Semiconductor device, manufacturing method thereof, and electronic device
JP5330065B2 (en) 2009-04-13 2013-10-30 新光電気工業株式会社 Electronic device and manufacturing method thereof
FR2946795B1 (en) * 2009-06-12 2011-07-22 3D Plus METHOD FOR POSITIONING CHIPS WHEN MANUFACTURING A RECONSTITUTED PLATE
JP5296636B2 (en) 2009-08-21 2013-09-25 新光電気工業株式会社 Manufacturing method of semiconductor package
JP5541618B2 (en) 2009-09-01 2014-07-09 新光電気工業株式会社 Manufacturing method of semiconductor package
JP5325736B2 (en) 2009-10-06 2013-10-23 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
JP5249173B2 (en) 2009-10-30 2013-07-31 新光電気工業株式会社 Semiconductor device mounting wiring board and method for manufacturing the same
JP5543754B2 (en) 2009-11-04 2014-07-09 新光電気工業株式会社 Semiconductor package and manufacturing method thereof
EP2330618A1 (en) 2009-12-04 2011-06-08 STMicroelectronics (Grenoble 2) SAS Rebuilt wafer assembly
JP5581519B2 (en) 2009-12-04 2014-09-03 新光電気工業株式会社 Semiconductor package and manufacturing method thereof
JP5584011B2 (en) 2010-05-10 2014-09-03 新光電気工業株式会社 Manufacturing method of semiconductor package
JP5826532B2 (en) 2010-07-15 2015-12-02 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
US9064883B2 (en) 2011-08-25 2015-06-23 Intel Mobile Communications GmbH Chip with encapsulated sides and exposed surface
US9082825B2 (en) 2011-10-19 2015-07-14 Panasonic Corporation Manufacturing method for semiconductor package, semiconductor package, and semiconductor device
KR101332916B1 (en) 2011-12-29 2013-11-26 주식회사 네패스 Semiconductor package and method of manufacturing the same
US8912670B2 (en) 2012-09-28 2014-12-16 Intel Corporation Bumpless build-up layer package including an integrated heat spreader
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US9190380B2 (en) 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
US9159690B2 (en) 2013-09-25 2015-10-13 Intel Corporation Tall solders for through-mold interconnect
CN107256848A (en) * 2017-05-25 2017-10-17 日月光封装测试(上海)有限公司 Semiconductor package assembly and a manufacturing method thereof
WO2019103676A1 (en) * 2017-11-24 2019-05-31 Fingerprint Cards Ab Ultra-thin fingerprint sensor component and manufacturing method
CN115148615B (en) * 2022-09-05 2022-11-15 长电集成电路(绍兴)有限公司 Method for repairing chip packaging structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2599893B1 (en) * 1986-05-23 1996-08-02 Ricoh Kk METHOD FOR MOUNTING AN ELECTRONIC MODULE ON A SUBSTRATE AND INTEGRATED CIRCUIT CARD
US5291066A (en) * 1991-11-14 1994-03-01 General Electric Company Moisture-proof electrical circuit high density interconnect module and method for making same
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5527741A (en) * 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers

Also Published As

Publication number Publication date
WO2002015266A2 (en) 2002-02-21
CN1535479A (en) 2004-10-06
HK1055844A1 (en) 2004-01-21
EP1354351B1 (en) 2009-04-15
CN100426492C (en) 2008-10-15
EP1354351A2 (en) 2003-10-22
ATE429032T1 (en) 2009-05-15
DE60138416D1 (en) 2009-05-28
WO2002015266A3 (en) 2003-08-14
MY141327A (en) 2010-04-16

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