CN115148615B - Method for repairing chip packaging structure - Google Patents
Method for repairing chip packaging structure Download PDFInfo
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- CN115148615B CN115148615B CN202211080720.4A CN202211080720A CN115148615B CN 115148615 B CN115148615 B CN 115148615B CN 202211080720 A CN202211080720 A CN 202211080720A CN 115148615 B CN115148615 B CN 115148615B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02321—Reworking
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention provides a method for repairing a chip packaging structure, which comprises the following steps: after the first welding connection body is removed through corrosion, photoresist is coated on the chip wiring layer to form a first solidified dielectric layer, and the first conductive column and the first metal barrier layer are encapsulated in the first solidified dielectric layer; grinding the first solidified dielectric layer to remove the first metal barrier layer to obtain a second solidified dielectric layer, and forming a chip deplating packaging body; preparing a second externally-connected conductive part on the first metal barrier layer corresponding to the chip deplating packaging body and the first conductive column to obtain a repaired chip packaging structure; the method solves the problems that the copper layer in the chip wiring layer is corroded in the repairing method of the chip packaging structure in the prior art, and chemical liquid medicine permeates and corrodes the copper layer in the chip wiring layer, so that the structural integrity of the copper layer in the chip wiring layer is guaranteed, and the stability of the repaired chip packaging structure is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a repairing method suitable for a chip packaging structure.
Background
Currently, in the chip package structure shown in fig. 1, the chip package structure includes a chip package body P1, a chip wiring layer 13, a first conductive pillar 12, a first metal interposer 11, and a first solder joint body 10; the chip package body P1 provides insulation package protection for the chip 100; the chip wiring layer 13 comprises a copper layer 13a and a dielectric layer 13b, and the dielectric layer 13b provides a dielectric insulation protection function for the copper layer 13 a; since various abnormal conditions in the process of the production line may cause process defects in the first solder connections 10, the first metal interposers 11 and/or the first conductive pillars 12, and thus the quality requirements of the product cannot be met, the first external connection conductive components composed of the first solder connections 10, the first metal interposers 11 and the first conductive pillars 12, which are poor, need to be etched to prepare new defect-free external connection conductive components, and when the new defect-free first external connection conductive components are prepared again, the coating and the photolithography opening of the photoresist need to be completed on the flat base surface, so all the first external connection conductive components on the surface of the wiring layer are usually etched and removed by using the surface of the wiring layer 13 as a reference surface.
In the conventional deplating process of the first external connection conductive part, the first solder joint body 10 and the first metal interposer 11 are usually etched away by using a nitric acid system chemical liquid with a special proportion, and then the first conductive pillar 12 is etched away by using another nitric acid system chemical liquid with a special proportion, because the first conductive pillar 12 is usually a copper material and the first conductive pillar 12 is in physical contact with the copper layer 13a in the chip wiring layer 13, in the process of etching the first conductive pillar, due to the permeability of the liquid etching liquid, the chemical liquid inevitably reacts with the copper layer 13a to etch away part of the copper layer 13a, so that the structural integrity of the copper layer in the chip wiring layer is damaged, and further, adverse effects are brought to signal transmission and power supply of a chip.
Therefore, the repairing method of the chip packaging structure in the prior art has the problem of corroding the copper layer in the wiring layer of the chip, so that the structural integrity of the copper layer in the wiring layer is damaged, and further, the signal transmission and the power supply of the chip are adversely affected.
Disclosure of Invention
Aiming at the defects in the prior art, the repairing method of the chip packaging structure provided by the invention solves the problem that the repairing method of the chip packaging structure in the prior art has the problem that the copper layer in the chip wiring layer is corroded so as to damage the structural integrity of the copper layer.
The invention provides a method for repairing a chip packaging structure, wherein the chip packaging structure comprises a chip wiring layer and a first externally-connected conductive component to be repaired, the first externally-connected conductive component comprises a first conductive column connected with the chip wiring layer, a first welding body used for being connected with an external packaging substrate, and a first metal intermediate layer arranged between the first conductive column and the first welding body, and the method comprises the following steps: after the first welding body is corroded and removed, photoresist is coated on the chip wiring layer to form a first solidified dielectric layer, and the first conductive posts and the first metal intermediate layer are encapsulated in the first solidified dielectric layer; grinding the first solidified dielectric layer to remove the first metal intermediate layer to obtain a second solidified dielectric layer, and forming a chip deplating packaging body; and preparing a second externally-connected conductive part on the first metal barrier layer corresponding to the chip deplating packaging body and the first conductive column to obtain the repaired chip packaging structure.
Optionally, a second external conductive component is prepared on the first metal barrier layer of the chip deplated package body corresponding to the first conductive pillar, so as to obtain a repaired chip package structure, including: depositing a first metal barrier layer on the second cured dielectric layer; coating photoresist on the first metal barrier layer, and exposing and developing the photoresist to obtain a sacrificial dielectric layer with an opening array, wherein the opening array corresponds to the first conductive column below the first metal barrier layer; and preparing a second external conductive part on the opening array, and cleaning and removing the sacrificial dielectric layer and the first metal barrier layer positioned below the sacrificial dielectric layer to obtain the repaired chip packaging structure.
Optionally, the second externally connected conductive component includes, in order, a second conductive pillar, a second metal barrier layer, and a second solder body.
Optionally, the first solder connector body or/and the second solder connector body comprises a solder mass of a tin-based alloy.
Optionally, when the second solder joint body is a tin-based alloy solder bump, the repaired chip package structure is obtained after the sacrificial dielectric layer and the first metal barrier layer located below the sacrificial dielectric layer are cleaned and removed, and the method includes: cleaning and removing the sacrificial dielectric layer and the first metal barrier layer positioned below the sacrificial dielectric layer; and processing the tin-based alloy solder block by a high-temperature reflow process to form a tin-based alloy solder ball, thereby obtaining the repaired chip packaging structure.
Optionally, the first conductive pillar or/and the second conductive pillar comprises a copper pillar.
Optionally, the second metal barrier layer comprises a nickel barrier layer.
Optionally, the first metal barrier layer comprises a titanium barrier layer and a copper seed layer.
Optionally, the titanium barrier layer and the copper seed layer are respectively deposited by a magnetron sputtering method.
Optionally, the resin system of the photoresist material comprises one or any combination of polyimide-based resin, polyamide-based resin, acrylic-based resin, epoxy-based resin, PBO-based resin, silicone-based resin, benzocyclobutene-based resin.
Compared with the prior art, the invention has the following beneficial effects:
after the first welding body is removed through corrosion, preparing a first curing dielectric layer for encapsulating a first conductive post and a first metal barrier layer on the surface of a first metal intermediate layer, then grinding and removing part of the first curing dielectric layer and the first metal barrier layer to obtain a second curing dielectric layer for encapsulating the first conductive post, and finally preparing a second external conductive component connected with the first metal barrier layer on the second curing dielectric layer to obtain a repaired chip packaging structure; according to the chip packaging structure, the first conductive column does not need to be removed through chemical liquid corrosion, and the second external conductive part connected with the external packaging substrate is prepared on the first conductive column again to complete the repair of the chip packaging structure, so that the problem that the chemical liquid permeates and corrodes the copper layer in the chip wiring layer is solved, the structural integrity of the copper layer in the chip wiring layer is guaranteed, the stability of the repaired chip packaging structure is improved, and meanwhile, a complete signal transmission path and a complete power supply path are provided for a chip.
Drawings
FIG. 1 is a schematic structural diagram of a chip package structure in the prior art;
fig. 2 is a schematic flow chart illustrating a method for repairing a chip package structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram illustrating a first welded body removed by etching according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram illustrating a first cured dielectric layer according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a chip deplated package according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a deposited metal sputtering layer according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a method for fabricating a sacrificial dielectric layer with an array of openings according to one embodiment of the present invention;
FIG. 8 is a schematic diagram of a second externally conductive component according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram illustrating a structure of a sacrificial dielectric layer and a part of a metal sputtering layer after being cleaned and removed according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a repaired chip package structure according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 2 is a schematic flow chart illustrating a method for repairing a chip package structure according to an embodiment of the present invention; the chip packaging structure comprises a chip packaging body, a chip wiring layer and a first external connection conductive part to be repaired, wherein the chip packaging body comprises a conductive pin for leading out a chip built-in integrated circuit, an underfill layer for packaging the conductive pin and a plastic packaging layer for packaging the chip; the first externally-connected conductive component comprises a first conductive pillar connected with the chip wiring layer, a first welding body used for being connected with an external packaging substrate (not shown), and a first metal intermediate layer arranged between the first conductive pillar and the first welding body, and the repairing method of the chip packaging structure specifically comprises the following steps:
step S101, after removing the first solder joint body by etching, coating a photoresist on the chip wiring layer to form a first cured dielectric layer, and encapsulating the first conductive pillar and the first metal interposer in the first cured dielectric layer;
as shown in fig. 3, the chip package structure to be repaired is put into a nitric acid system chemical solution with a special mixture ratio to corrode the first solder joint body 10; the model of a commercial product used for corroding the tin-based alloy material in the first welding connector body can be 3880, and the model of a commercial product used for corroding a chemical corrosive used for nickel and/or copper materials can be Ni636E.
It should be noted that, in the embodiment, the material of the first solder joint body is usually a tin-based alloy solder, the first metal interposer is a nickel barrier layer, and the first conductive pillar is a copper pillar, so that the materials of the first solder joint body, the first metal interposer and the first conductive pillar are different, and the nitric acid chemical solution that corrodes the first solder joint body does not cause structural damage to the first metal interposer, the first conductive pillar and the copper layer in the chip wiring layer. In addition, the process defects and/or unavoidable frictional damages generated in the process operations proposed in the background of the present application with respect to the first solder connections 10, the first metal interposer 11 and/or the first conductive pillars 12 include, but are not limited to, outer surface defects with respect to the first solder connections 10, the first metal interposer 11 and/or the first conductive pillars 12, electrical connection defects between the first solder connections 10 and the first metal interposer 11, and electrical connection defects between the first metal interposer 11 and the first conductive pillars 12; but does not include the electrical connection defect of the first conductive pillar 12 and the copper layer 13a, i.e., the electrical connection of the first conductive pillar 12 and the copper layer 13a is normal by default in this application.
As shown in fig. 4, a layer of photoresist is coated on the chip wiring layer, and is cured at a high temperature to obtain a first cured dielectric layer 20, and the first conductive pillars 12 and the first metal interposer 11 are encapsulated and protected.
Step S102, grinding the first solidified dielectric layer to remove the first metal intermediate layer to obtain a second solidified dielectric layer, and forming a chip deplating packaging body;
the first cured dielectric layer 20 shown in fig. 4 is polished to remove the photoresist-encapsulated first metal interposer 11 until the first conductive pillars 12 under the first metal interposer 11 are exposed, so as to obtain a second cured dielectric layer 20' shown in fig. 5, and the chip package structure with the first solder connections 10 and the first metal interposer 11 removed is used as the chip deplating package shown in fig. 5.
Wherein the second cured dielectric layer 20' obtained after the grinding process also provides a flat base surface for the subsequent preparation of the second external conductive component.
Step S103, preparing a second external conductive component on the first metal barrier layer of the chip deplating packaging body corresponding to the first conductive column to obtain the repaired chip packaging structure.
In this embodiment, a second external conductive component is prepared on the first metal blocking layer corresponding to the chip deplating package and the first conductive pillar, so as to obtain a repaired chip package structure, which specifically includes: depositing a first metal barrier layer on the second cured dielectric layer; coating photoresist on the first metal barrier layer, and exposing and developing the photoresist to obtain a sacrificial dielectric layer with an opening array, wherein the opening array corresponds to the first conductive column positioned below the first metal barrier layer; and preparing a second external conductive part on the opening array, and cleaning and removing the sacrificial dielectric layer and the metal barrier layer positioned below the sacrificial dielectric layer to obtain the repaired chip packaging structure.
It should be noted that, as shown in fig. 6, a first metal barrier layer 21 is deposited on the surface of the second cured dielectric layer 20' obtained after grinding; the first metal barrier layer 21 comprises a titanium barrier layer and a copper seed layer respectively; the first metallic barrier layer 21 is preferably deposited by magnetron sputtering.
As shown in fig. 7, a layer of photoresist is coated on the first metal barrier layer 21, and the sacrificial dielectric layer 22 with an array of openings is obtained through the steps of low temperature baking, exposure, development, and the like, so as to obtain the chip pre-repair body.
The opening arrays correspond to the first conductive pillars 12 located below the first metal barrier layer 21 one to one;
as shown in fig. 8, the chip pre-repair body was placed in an electroplating bath and a magnetron sputtering chamber to prepare a second externally-connected conductive part; wherein the second externally conductive component comprises a second conductive pillar 23, a second metal barrier layer 24 and a second solder body 25. The second welding body comprises a tin-based alloy welding mass, the second metal barrier layer comprises a nickel barrier layer, and the second conductive column comprises a copper column.
Optionally, the chip pre-repair body is placed in a copper electroplating bath to be electroplated to prepare a copper column, then the copper column is transferred to a magnetron sputtering cavity to be sputtered with a nickel barrier layer, and finally the copper column is transferred to a tin-based alloy electroplating bath to be electroplated to prepare a tin-based alloy solder block.
The sacrificial dielectric layer 22 and a portion of the first metal barrier layer 21 under the sacrificial dielectric layer shown in fig. 8 are removed by cleaning, so as to obtain the structural diagram shown in fig. 9.
The tin-based alloy solder bump is processed by a high-temperature reflow process to form a tin-based alloy solder ball, and the repaired chip packaging structure shown in fig. 10 is obtained.
It should be noted that, in this embodiment, the first soldered body and the second soldered body may be formed by a tin-based alloy solder bump or a tin-based alloy solder ball formed by a tin-based alloy solder, and the tin-based alloy solder bump and the tin-based alloy solder ball are different only in shape, and the tin-based alloy solder ball is formed by performing a high temperature reflow process on the tin-based alloy solder bump.
Compared with the prior art, the embodiment has the following beneficial effects:
after the first welding body is removed through corrosion, preparing a first curing dielectric layer for encapsulating the first conductive post and the first metal intermediate layer on the surface of the first metal intermediate layer, then grinding and removing part of the first curing dielectric layer and the first metal barrier layer to obtain a second curing dielectric layer for encapsulating the first conductive post, and finally preparing a second external conductive component connected with the first metal barrier layer on the second curing dielectric layer to obtain a repaired chip packaging structure; according to the chip packaging structure, the first conductive column does not need to be removed through chemical liquid corrosion, and the second external conductive part connected with the external packaging substrate is prepared on the first conductive column again to complete the repair of the chip packaging structure, so that the problem that the chemical liquid permeates and corrodes the copper layer in the chip wiring layer is solved, the structural integrity of the copper layer in the chip wiring layer is guaranteed, the stability of the repaired chip packaging structure is improved, and meanwhile, a complete signal transmission path and a complete power supply path are provided for a chip.
In this embodiment, the height of the second conductive pillar is smaller than the height of the first conductive pillar.
It should be noted that, in the conventional production, process defects are usually caused on the first solder joint body and/or friction damage which is difficult to avoid is generated in the process operation, and the first conductive pillar located between the chip wiring layer and the first solder joint body also needs to meet certain height requirements, such as: 30um, 40um, 50um; according to the invention, the first conductive column does not need to be completely corroded, the second external conductive component is prepared again only on the basis of the first conductive column, and the height of the second conductive column is smaller than that of the first conductive column, so that the cost of a copper material for preparing the first conductive column in the prior art can be saved.
In this embodiment, the resin system of the photoresist material includes one or any combination of polyimide-based resin, polyamide-based resin, acrylic-based resin, epoxy-based resin, PBO-based resin, silicone-based resin, and benzocyclobutene-based resin.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
Claims (9)
1. A method for repairing a chip packaging structure is characterized in that the chip packaging structure comprises a chip packaging body, a chip wiring layer and a first externally-connected conductive component to be repaired, wherein the first externally-connected conductive component comprises a first conductive column connected with the chip wiring layer, a first welding body used for being connected with an external packaging substrate and a first metal intermediate layer arranged between the first conductive column and the first welding body, and the repairing method comprises the following steps:
after the first welding body is corroded and removed, photoresist is coated on the chip wiring layer to form a first solidified dielectric layer, and the first conductive posts and the first metal intermediate layer are encapsulated in the first solidified dielectric layer;
grinding the first solidified dielectric layer to remove the first metal intermediate layer to obtain a second solidified dielectric layer, and forming a chip deplating packaging body;
depositing a first metal barrier layer on the second cured dielectric layer;
coating photoresist on the first metal barrier layer, and exposing and developing the photoresist to obtain a sacrificial dielectric layer with an opening array, wherein the opening array corresponds to the first conductive column below the first metal barrier layer;
and preparing a second external conductive part on the opening array, and cleaning and removing the sacrificial dielectric layer and the first metal barrier layer positioned below the sacrificial dielectric layer to obtain the repaired chip packaging structure.
2. The method for repairing a chip package structure according to claim 1, wherein the second externally-connected conductive component sequentially comprises a second conductive pillar, a second metal barrier layer and a second solder joint body.
3. The method for repairing a chip package structure according to claim 2, wherein the first solder connections or/and the second solder connections comprise solder bumps of tin-based alloy.
4. The method for repairing a chip package structure according to claim 3, wherein when the second solder connections are solder bumps of tin-based alloy, the repaired chip package structure is obtained after the sacrificial dielectric layer and the first metal barrier layer located below the sacrificial dielectric layer are cleaned and removed, and the method comprises:
cleaning and removing the sacrificial dielectric layer and the first metal barrier layer positioned below the sacrificial dielectric layer;
and processing the tin-based alloy solder block by a high-temperature reflow process to form a tin-based alloy solder ball, thereby obtaining the repaired chip packaging structure.
5. The method for repairing a chip package structure according to claim 2, wherein the first conductive pillar or/and the second conductive pillar comprises a copper pillar.
6. The method for repairing a chip package structure according to claim 2, wherein the second metal barrier layer comprises a nickel barrier layer.
7. The method for repairing a chip package structure of claim 1, wherein the first metal barrier layer comprises a titanium barrier layer and a copper seed layer.
8. The method for repairing a chip package structure according to claim 7, wherein the titanium barrier layer and the copper seed layer are deposited by magnetron sputtering, respectively.
9. The method for repairing a chip package structure according to any one of claims 1 to 8, wherein the resin system of the photoresist material comprises one or any combination of polyimide-based resin, polyamide-based resin, acrylic-based resin, epoxy-based resin, PBO-based resin, silicone-based resin, and benzocyclobutene-based resin.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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