JP2024003147A - Substrate for semiconductor device, method of manufacturing the same, and semiconductor device - Google Patents

Substrate for semiconductor device, method of manufacturing the same, and semiconductor device Download PDF

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JP2024003147A
JP2024003147A JP2023193533A JP2023193533A JP2024003147A JP 2024003147 A JP2024003147 A JP 2024003147A JP 2023193533 A JP2023193533 A JP 2023193533A JP 2023193533 A JP2023193533 A JP 2023193533A JP 2024003147 A JP2024003147 A JP 2024003147A
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semiconductor device
metal
substrate
mother substrate
metal part
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宏史 中川
Hiroshi Nakagawa
佑也 五郎丸
Yuya Goromaru
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Maxell Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a substrate for a semiconductor device capable of manufacturing a semiconductor device that can be mounted with a good reliability on a mounting substrate having wires formed densely, and to provide a semiconductor device manufactured by using the substrate for a semiconductor device.
SOLUTION: A substrate for a semiconductor device comprises: a recessed part 20 formed on a matrix substrate 10 and that is smaller than a bottom face size of a semiconductor device; and a metal part 11 that is at least to be an electrode part 11b, being formed with a step at a predetermined position over an inner surface of one recessed part 20 and an outside surface of the concerned recessed part 20.
SELECTED DRAWING: Figure 2
COPYRIGHT: (C)2024,JPO&INPIT

Description

本発明は、母型基板上に金属部が形成された半導体装置用基板と、この半導体装置用基板を用いた半導体装置に関する。 The present invention relates to a semiconductor device substrate in which a metal portion is formed on a mother substrate, and a semiconductor device using this semiconductor device substrate.

半導体素子支持用の基板上に半導体素子を搭載し、半導体素子と外部導出用の金属端子とを配線接続した上で、樹脂等の保護材で半導体素子を含む基板全体を被覆した旧来の構造の半導体装置は、その構造上、小型化には限界があった。これに対し、半導体素子搭載部分や電極部分となる金属部を形成し、この金属部上に半導体素子を搭載し配線等の処理後、半導体素子や配線等のある金属部の表面側を樹脂等の封止材で封止し、金属部が底部に一部露出した構成とされる半導体装置は、その高さを低くして省スペース化が図れ、チップサイズなど超小型の半導体装置の分野で利用が進んでいる。 The conventional structure is to mount a semiconductor element on a substrate for supporting the semiconductor element, connect the semiconductor element with metal terminals for external lead-out, and then cover the entire substrate including the semiconductor element with a protective material such as resin. Due to the structure of semiconductor devices, there is a limit to miniaturization of semiconductor devices. On the other hand, a metal part that will become a semiconductor element mounting part or an electrode part is formed, and after mounting the semiconductor element on this metal part and processing wiring, etc., the surface side of the metal part where the semiconductor element and wiring are located is coated with resin, etc. Semiconductor devices are encapsulated with an encapsulating material with a part of the metal part exposed at the bottom, and the height can be lowered to save space, making it suitable for use in the field of ultra-small semiconductor devices such as chip sizes. Its use is progressing.

こうした半導体装置は、主に、導電性を有する母型基板上に半導体素子搭載部分や電極部分となる金属部を、メッキ(電鋳)により、半導体装置の所望個数分まとめて形成し、半導体素子が搭載され配線等の処理を経た金属部の表面側を封止材で封止した後、母型基板のみを除去し、一体にまとまった状態の多数の半導体装置を個別に切り分ける、といった製造過程を経て製造される。このような半導体装置の製造方法の一例として、特開2002-9196号公報に開示されるものがある。 These semiconductor devices are mainly formed by plating (electroforming) metal parts that will serve as semiconductor element mounting parts and electrode parts on a conductive motherboard, and then forming the desired number of semiconductor devices. A manufacturing process that involves sealing the front side of the metal part with a sealant after it has been mounted and processed with wiring, etc., then removing only the mother board and cutting into individual semiconductor devices. Manufactured through. An example of a method for manufacturing such a semiconductor device is disclosed in Japanese Unexamined Patent Publication No. 2002-9196.

特開2002-9196号公報Japanese Patent Application Publication No. 2002-9196 特開2004-214265号公報Japanese Patent Application Publication No. 2004-214265

特許文献1には、半導体素子搭載部分や電極部分の裏面のいずれか一方もしくは両方を樹脂封止した際、封止材の裏面よりも若干突出(スタンドオフ)させるように構成した半導体装置が開示されている。このように、半導体素子搭載部分や電極部分の裏面を封止材の裏面から突出させることで、半導体装置を実装基板に実装する際に、半導体装置の電極部分(リード)と実装基板の電極部分(パッド)との接合を良好にすることができる。 Patent Document 1 discloses a semiconductor device configured so that when one or both of the back surfaces of a semiconductor element mounting part and an electrode part are sealed with resin, they are slightly protruded (standoff) from the back surface of the sealing material. has been done. In this way, by making the back side of the semiconductor element mounting part and the electrode part protrude from the back side of the sealing material, when mounting the semiconductor device on the mounting board, the electrode part (lead) of the semiconductor device and the electrode part of the mounting board can be easily separated. (pad) can be bonded well.

近年、電子機器の小型化を実現するために、実装基板の電極部分や配線部分が密集して形成されつつあるが、上記半導体装置の構造では、半導体素子搭載部分や電極部分の裏面全体が封止材の裏面から突出しているため、半導体装置の半導体素子搭載部分(ダイパッド)や電極部分(リード)と実装基板の電極部分(パッド)や配線部分が所望せぬ箇所で接触するおそれがある。 In recent years, in order to achieve miniaturization of electronic devices, the electrodes and wiring portions of mounting boards are becoming densely packed together. Since it protrudes from the back surface of the retaining material, there is a risk that the semiconductor element mounting portion (die pad) or electrode portion (lead) of the semiconductor device may come into contact with the electrode portion (pad) or wiring portion of the mounting board at an undesired location.

本発明の目的は、金属部の裏面から突出部を部分的に突出させ、配線が密集して形成された実装基板にも信頼性良く実装可能な半導体装置を製造できる半導体装置用基板、当該半導体装置用基板を用いて製造される半導体装置を提供することにある。 An object of the present invention is to provide a substrate for a semiconductor device, which allows a semiconductor device to be manufactured with a protruding portion partially protruding from the back surface of a metal portion, and which can be reliably mounted even on a mounting board where wiring is formed densely. An object of the present invention is to provide a semiconductor device manufactured using a device substrate.

本発明に係る半導体装置用基板は、母型基板10上に少なくとも電極部11bとなる金属部11が形成されており、金属部11の母型基板面側には部分的に突出する突出部11dが設けられていることを特徴とする。 In the semiconductor device substrate according to the present invention, at least a metal portion 11 serving as an electrode portion 11b is formed on a mother substrate 10, and a protruding portion 11d partially protrudes from the surface of the mother substrate 11 of the metal portion 11. It is characterized by being provided with.

また、金属部11の母型基板面側とは反対側の面には窪み部11eが設けられていることを特徴とする。 Further, a feature is that a recessed portion 11e is provided on the surface of the metal portion 11 opposite to the mother board surface side.

また、突出部11dと窪み部11eが金属部11の厚み方向において重なる位置に設けられていることを特徴とする。 Further, the protruding portion 11d and the recessed portion 11e are provided at positions that overlap in the thickness direction of the metal portion 11.

また、突出部11dの突出形状と窪み部11の窪み形状が相似形であることを特徴とする。 Further, the protruding shape of the protruding portion 11d and the recessed shape of the recessed portion 11 are similar in shape.

本発明に係る半導体装置用基板の製造方法は、母型基板10上に少なくとも電極部11bとなる金属部11が形成されており、金属部11の母型基板面側には部分的に突出する突出部11dが設けられている半導体装置用基板の製造方法であって、母型基板10上に、第一レジスト層12を形成する工程と、母型基板10の第一レジスト層12で覆われていない露出領域に凹部20を形成する工程と、第一レジスト層12を除去する工程と、母型基板10上に、第二レジスト層16を形成する工程と、母型基板10の第二レジスト層16で覆われていない露出領域に、金属部11を形成する工程と、第二レジスト層16を除去する工程とを有することを特徴とする。 In the method for manufacturing a substrate for a semiconductor device according to the present invention, at least a metal portion 11 serving as an electrode portion 11b is formed on a mother substrate 10, and the metal portion 11 partially protrudes from the surface of the mother substrate. A method for manufacturing a semiconductor device substrate provided with a protrusion 11d, which includes the steps of forming a first resist layer 12 on a mother substrate 10, and covering the mother substrate 10 with the first resist layer 12. a step of forming a recess 20 in an exposed area that is not exposed, a step of removing the first resist layer 12, a step of forming a second resist layer 16 on the mother substrate 10, and a step of removing the second resist layer 16 of the mother substrate 10. The method is characterized by comprising a step of forming the metal portion 11 in an exposed region not covered with the layer 16, and a step of removing the second resist layer 16.

また、金属部11を形成する工程において、母型基板10及び凹部20の表面に、金属部11をめっき成長させることを特徴とする。さらに、金属部11を形成する工程において、第二レジスト層16の厚さを越えて金属部11をめっき成長させることを特徴とする。 Further, in the step of forming the metal part 11, the metal part 11 is grown by plating on the surfaces of the mother mold substrate 10 and the recessed part 20. Furthermore, in the step of forming the metal part 11, the metal part 11 is grown by plating to exceed the thickness of the second resist layer 16.

本発明に係る半導体装置は、半導体素子14と電気的に接続する電極部11bとなる金属部11を有し、金属部11上への半導体素子14の搭載、半導体素子14と金属部11との電気的接続、封止材19による封止がなされる半導体装置であって、封止材19の裏面から金属部11の裏面が露出されており、金属部11の裏面には封止材19の裏面より突出形成された突出部11dが設けられ、突出部11dを除く金属部11の裏面と封止材19の裏面とが略同一平面となっていることを特徴とする。 The semiconductor device according to the present invention has a metal part 11 that becomes an electrode part 11b that is electrically connected to a semiconductor element 14. This is a semiconductor device that is electrically connected and sealed with a sealing material 19, and the back surface of the metal part 11 is exposed from the back surface of the sealing material 19. It is characterized in that a protruding portion 11d is provided to protrude from the back surface, and the back surface of the metal portion 11 excluding the protruding portion 11d and the back surface of the sealing material 19 are substantially on the same plane.

また、金属部11の表面には窪み部11eが設けられていることを特徴とする。 Further, the metal part 11 is characterized in that a recessed part 11e is provided on the surface thereof.

また、突出部11dと窪み部11eが金属部11の厚み方向において重なる位置に設けられていることを特徴とする。 Further, the protruding portion 11d and the recessed portion 11e are provided at positions that overlap in the thickness direction of the metal portion 11.

また、突出部11dの突出形状と窪み部11の窪み形状が相似形であることを特徴とする。 Further, the protruding shape of the protruding portion 11d and the recessed shape of the recessed portion 11 are similar in shape.

本発明によれば、突出部11dのみが金属部11の裏面より部分的に突出形成されることになり、係る金属部11を備えた半導体装置は、電極や配線が密集した実装基板に対しても、容易かつ的確で信頼性の良い実装が可能となる。また、突出部11dの径や幅を実装基板の電極に対応して小さく形成せざるを得なくても、金属部11の表面(表面積)は突出部11dに比べ大きく形成することができ、搭載する半導体素子14の選択自由度を拡げることができる。 According to the present invention, only the protruding portion 11d is formed to partially protrude from the back surface of the metal portion 11, and a semiconductor device including such a metal portion 11 can be mounted on a mounting board with dense electrodes and wiring. It also enables easy, accurate, and reliable implementation. Further, even if the diameter and width of the protrusion 11d must be made small to correspond to the electrodes of the mounting board, the surface (surface area) of the metal part 11 can be made larger than the protrusion 11d, and the mounting The degree of freedom in selecting the semiconductor element 14 to be used can be expanded.

本発明の第1の実施形態に係る半導体装置用基板の部分平面図である。FIG. 1 is a partial plan view of a semiconductor device substrate according to a first embodiment of the present invention. 本発明の第1の実施形態に係る半導体装置用基板の断面図及び平面図である。1 is a cross-sectional view and a plan view of a semiconductor device substrate according to a first embodiment of the present invention. FIG. 本発明の第1の実施形態に係る半導体装置の断面図及び底面図である。1 is a cross-sectional view and a bottom view of a semiconductor device according to a first embodiment of the present invention. FIG. 本発明の第1の実施形態に係る半導体装置用基板の製造方法における工程説明図である。FIG. 3 is a process explanatory diagram of a method for manufacturing a semiconductor device substrate according to a first embodiment of the present invention. 本発明の第1の実施形態に係る半導体装置用基板の製造方法における工程説明図である。FIG. 3 is a process explanatory diagram of a method for manufacturing a semiconductor device substrate according to a first embodiment of the present invention. 本発明の第1の実施形態に係る半導体装置の製造方法における工程説明図である。FIG. 3 is a process explanatory diagram of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 本発明の他実施形態に係る半導体装置の断面図及び底面図である。FIG. 6 is a cross-sectional view and a bottom view of a semiconductor device according to another embodiment of the present invention.

(第1実施形態)
以下、本発明の第1実施形態に係る半導体装置用基板及び半導体装置について、図1ないし図6に基づいて説明する。本実施形態に係る半導体装置用基板1は、図2に示すように、導電性を有する材質からなる母型基板10と、この母型基板10上に形成され、本基板を用いて製造される半導体装置70における電極部11bとなる金属部11とを備える構成である。
(First embodiment)
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device substrate and a semiconductor device according to a first embodiment of the present invention will be described below with reference to FIGS. 1 to 6. As shown in FIG. 2, the semiconductor device substrate 1 according to the present embodiment includes a mother substrate 10 made of a conductive material, and is formed on the mother substrate 10 and manufactured using the present substrate. This configuration includes a metal portion 11 serving as an electrode portion 11b in the semiconductor device 70.

母型基板10は、ステンレス(SUS430等)やアルミニウム、銅等の導電性の金属板(厚さ約0.1mm)で形成され、半導体装置の製造工程で除去されるまで、半導体装置用基板1の要部をなすものである。 The mother board 10 is made of a conductive metal plate (approximately 0.1 mm thick) made of stainless steel (SUS430, etc.), aluminum, copper, etc., and is used as the semiconductor device substrate 1 until it is removed in the semiconductor device manufacturing process. It forms the main part of

金属部11は、ニッケルや銅、又はニッケル-コバルト等のニッケル合金からなり、メッキ形成されるものであり、図1に示すように、母型基板10表面で、一又は複数配置される状態を一つの単位として、製造する半導体装置の数だけ多数整列状態で並べられた形態で形成されることとなる。 The metal part 11 is made of nickel, copper, or a nickel alloy such as nickel-cobalt, and is formed by plating, and as shown in FIG. As one unit, as many semiconductor devices as the number of semiconductor devices to be manufactured are arranged in an array.

この金属部11の母型基板面側(裏面)には、突出部11dが形成されている。係る突出部11dは、金属部11の裏面から部分的に突出するように形成されている。また、母型基板面側とは反対側の面である金属部11の表面、より詳しくは、突出部11dの直上位置に窪み部11eが形成されている。そして、金属部11の上端部には、庇状に張り出す張出部11cが形成されている。 A protruding portion 11d is formed on the mother board surface side (back surface) of this metal portion 11. The protruding portion 11d is formed so as to partially protrude from the back surface of the metal portion 11. Further, a recess 11e is formed on the surface of the metal portion 11, which is the surface opposite to the mother board surface, more specifically, at a position directly above the protrusion 11d. A projecting portion 11c projecting like an eave is formed at the upper end of the metal portion 11.

金属部11は、大部分を電解メッキに適した、例えば、ニッケルやニッケル合金等で形成されるが、金属部11の裏面側には、半導体装置実装時のハンダ付けを適切に行えるようにするために、ニッケル等の主材質部よりハンダぬれ性の良好な金属、例えば金や銀、錫、パラジウム、ハンダ等の薄膜17が配設される構成である。この薄膜17には、エッチングによる母型基板10の除去の際に、エッチング液による金属部11の侵食劣化を防ぐ機能を与えることもできる。この薄膜17の厚さは、0.01~1μm程度とするのが好ましい。 The metal part 11 is mostly made of a material suitable for electrolytic plating, such as nickel or a nickel alloy, but the back side of the metal part 11 is made of a metal material suitable for electrolytic plating, and the back side of the metal part 11 is made of a material suitable for soldering when a semiconductor device is mounted. Therefore, a thin film 17 of a metal having better solder wettability than the main material such as nickel, such as gold, silver, tin, palladium, or solder, is disposed. This thin film 17 can also have a function of preventing erosion and deterioration of the metal portion 11 caused by the etching solution when the mother substrate 10 is removed by etching. The thickness of this thin film 17 is preferably about 0.01 to 1 μm.

また、金属部11の表面には表面金属層13が形成されている。この表面金属層13は、半導体素子14の電極との接合性に優れる金や銀、パラジウム等からなるメッキ膜として形成され、母型基板10ごとのメッキにより金属部11の表面に所定の厚さ、例えば、金メッキの場合は約0.1~1μm、銀メッキの場合は約1~10μmの厚さがメッキ形成される。 Further, a surface metal layer 13 is formed on the surface of the metal portion 11 . This surface metal layer 13 is formed as a plating film made of gold, silver, palladium, etc., which has excellent bonding properties with the electrodes of the semiconductor element 14, and is coated on the surface of the metal part 11 with a predetermined thickness by plating each mother board 10. For example, in the case of gold plating, the thickness is approximately 0.1 to 1 μm, and in the case of silver plating, the thickness is approximately 1 to 10 μm.

そして、この半導体装置用基板1を用いて製造される半導体装置70は、図3に示すように、半導体装置用基板1から得られる金属部11に加えて、金属部11のうちの電極部11bと電気的に接続する半導体素子14と、半導体素子14や金属部11の表面側を覆って封止する封止材19とを備える構成である。 As shown in FIG. 3, a semiconductor device 70 manufactured using this semiconductor device substrate 1 includes, in addition to the metal portion 11 obtained from the semiconductor device substrate 1, an electrode portion 11b of the metal portion 11. The configuration includes a semiconductor element 14 that is electrically connected to the semiconductor element 14 , and a sealing material 19 that covers and seals the semiconductor element 14 and the surface side of the metal part 11 .

この半導体装置70では、底部に金属部11の裏面側が電極や放熱パッド等として露出した状態となり、この露出する金属部11の裏面から突出部11dが突出形成されるとともに、突出部11dを除く金属部11の裏面側と、装置外装の一部として現れる封止材19の裏面側とが略同一平面上に位置する構成である。半導体装置70における底部以外の各面は、装置外装をなす封止材19のみがそれぞれ現れた状態となっている(図3(B)参照)。 In this semiconductor device 70, the back side of the metal part 11 is exposed at the bottom as an electrode, a heat dissipation pad, etc., and a protrusion 11d is formed protruding from the back surface of the exposed metal part 11, and the metal part other than the protrusion 11d is The configuration is such that the back side of the portion 11 and the back side of the sealing material 19 appearing as part of the device exterior are located on substantially the same plane. Each surface of the semiconductor device 70 other than the bottom is in a state where only the sealing material 19 forming the device exterior is exposed (see FIG. 3(B)).

半導体素子14は、微細な電子回路が形成されたいわゆるチップであり、半導体素子14表面に設けられた電極が電極部11bと直接接合され、半導体素子14と電極部11bとを電気的に接続することとなる。 The semiconductor element 14 is a so-called chip on which a fine electronic circuit is formed, and an electrode provided on the surface of the semiconductor element 14 is directly bonded to the electrode part 11b to electrically connect the semiconductor element 14 and the electrode part 11b. It happens.

封止材19は、物理的強度の高い熱硬化性エポキシ樹脂等であり、金属部11や半導体素子14を覆った状態で封止し、構造的に弱い部分を外部から隔離した保護状態とするものである。なお、半導体素子14がLED等の発光素子の場合、透光性の材質が用いられる。 The sealing material 19 is a thermosetting epoxy resin or the like with high physical strength, and covers and seals the metal part 11 and the semiconductor element 14 to protect the structurally weak parts from the outside. It is something. Note that when the semiconductor element 14 is a light emitting element such as an LED, a light-transmitting material is used.

この封止材19は、十分な物理的強度を有しており、半導体装置70の外装の一部として十分に内部を保護する機能を果し、母型基板10を半導体装置側から引き剥がすなど力を加えて物理的に除去する場合にも、割れ等の破損もなく金属部11との一体化状態を維持することとなる。 This sealing material 19 has sufficient physical strength and functions as a part of the exterior of the semiconductor device 70 to sufficiently protect the inside, and can be used to remove the mother substrate 10 from the semiconductor device side, etc. Even when it is physically removed by applying force, the state of integration with the metal part 11 is maintained without any damage such as cracking.

次に、本実施形態に係る半導体装置用基板の製造方法及び半導体装置用基板を用いた半導体装置の製造方法の各工程について説明する。 Next, each step of the method of manufacturing a semiconductor device substrate and the method of manufacturing a semiconductor device using the semiconductor device substrate according to the present embodiment will be described.

半導体装置用基板の製造工程として、まず、母型基板10を用意し、この母型基板10上に金属部11(電極部11b)の突出部11dを形成するための凹部20に対応する第一レジスト層12を配設する(図4(A)参照)。具体的には、母型基板10の表面側に感光性レジスト材を配設し、この感光性レジスト材に対して、凹部20(突出部11d)の形成位置に対応する所定パターンのマスクフィルムを載せた状態で、紫外線照射による露光での硬化、非照射部分のレジスト剤を除去する現像等の処理を行い、凹部20(突出部11d)の形成位置が露出するように第一レジスト層12を形成する。第一レジスト層12は、母型基板10表面に凹部20を形成する際に使用するエッチング液に対する耐溶解性を備えた絶縁性材で形成されるものであり、詳しくは、アルカリ現像タイプの感光性レジスト材を母型基板10に所定の厚さ、例えば5~50μmの範囲、本実施形態では20μmの厚さとなるようにして密着配設される。 As a manufacturing process for a semiconductor device substrate, first, a mother substrate 10 is prepared, and a first cavity 20 corresponding to the concave portion 20 for forming the protruding portion 11d of the metal portion 11 (electrode portion 11b) is formed on the mother substrate 10. A resist layer 12 is provided (see FIG. 4(A)). Specifically, a photosensitive resist material is provided on the front surface side of the mother substrate 10, and a mask film with a predetermined pattern corresponding to the formation position of the recessed portion 20 (projection portion 11d) is applied to the photosensitive resist material. In this state, the first resist layer 12 is cured by exposure to ultraviolet rays, developed to remove the resist agent in non-irradiated areas, and the first resist layer 12 is formed so that the formation position of the recess 20 (protrusion 11d) is exposed. Form. The first resist layer 12 is formed of an insulating material that is resistant to dissolution in the etching solution used when forming the recesses 20 on the surface of the mother substrate 10. A resist material is closely attached to the master substrate 10 to a predetermined thickness, for example in the range of 5 to 50 μm, and in this embodiment, 20 μm.

続いて、母型基板10の第一レジスト層12から露出する領域に凹部20を形成する(図4(B)参照)。具体的には、母型基板10の表面側のうち第一レジスト層12で覆われていない露出領域に対して、エッチングを施すことで凹部20を形成する。凹部20の形状としては円形や多角形が考えられ、凹部20の深さは5~30μmが望ましい。なお、凹部20の形成方法としては、エッチングに限らず、レーザー加工やブラスト処理によって形成しても良い。 Subsequently, a recess 20 is formed in a region of the mother substrate 10 exposed from the first resist layer 12 (see FIG. 4(B)). Specifically, the recess 20 is formed by etching an exposed region of the front surface of the mother substrate 10 that is not covered with the first resist layer 12 . The shape of the recess 20 may be circular or polygonal, and the depth of the recess 20 is preferably 5 to 30 μm. Note that the method for forming the recesses 20 is not limited to etching, and may be formed by laser processing or blasting.

続いて、母型基板10に形成された第一レジスト層12を除去(溶解除去、膨潤除去)することで、凹部20が形成された母型基板10を得る(図4(C)参照)。 Subsequently, the first resist layer 12 formed on the mother substrate 10 is removed (dissolved, removed by swelling) to obtain the mother substrate 10 in which the recesses 20 are formed (see FIG. 4C).

続いて、この母型基板10上に金属部11(電極部11b)を形成するための第二レジスト層16を配設する(図5(A)参照)。具体的には、母型基板10の表面側に感光性レジスト材を配設し、この感光性レジスト材に対して、金属部11(電極部11b)の形成位置に対応する所定パターンのマスクフィルムを載せた状態で、紫外線照射による露光での硬化、非照射部分のレジスト剤を除去する現像等の処理を行い、凹部を含む金属部11(電極部11b)の形成位置が露出するように第二レジスト層16を形成する。第二レジスト層16は、金属部11や表面金属層13を形成する際に使用するメッキ液に対する耐溶解性を備えた絶縁性材で形成されるものであり、詳しくは、アルカリ現像タイプの感光性レジスト材を母型基板10に所定の厚さ、例えば10~80μmの範囲、本実施形態では50μmの厚さとなるようにして密着配設される。なお、第一レジスト層12及び第二レジスト層16については、感光性レジストに限られるものではなく、エッチング液やメッキ液に対し変質せず強度の高い塗膜が得られる塗料を、母型基板10上における凹部20並びに金属部11の配置部分が露出されるように、電着塗装等により必要な塗膜厚さとなるように塗装して形成することもできる。 Subsequently, a second resist layer 16 for forming the metal portion 11 (electrode portion 11b) is provided on the mother substrate 10 (see FIG. 5(A)). Specifically, a photosensitive resist material is provided on the front surface side of the mother board 10, and a mask film with a predetermined pattern corresponding to the formation position of the metal part 11 (electrode part 11b) is applied to the photosensitive resist material. With the metal part 11 (electrode part 11b) placed thereon, treatments such as curing by exposure to ultraviolet rays and development to remove the resist agent in non-irradiated areas are carried out so that the formation position of the metal part 11 (electrode part 11b) including the recessed part is exposed. A second resist layer 16 is formed. The second resist layer 16 is made of an insulating material that is resistant to dissolution in the plating solution used when forming the metal part 11 and the surface metal layer 13. A resist material is closely attached to the mother mold substrate 10 to a predetermined thickness, for example, in the range of 10 to 80 μm, and in this embodiment, 50 μm. Note that the first resist layer 12 and the second resist layer 16 are not limited to photosensitive resists, and paints that do not change in quality with etching solutions or plating solutions and can provide a strong coating film can be used on the mother substrate. It can also be formed by electro-deposition coating or the like to a required thickness so that the concave portion 20 and the metal portion 11 are exposed.

続いて、母型基板10の第二レジスト層16から露出する領域に金属部11(電極部11b)を形成する(図5(B)参照)。具体的には、母型基板10の表面側のうち第二レジスト層16で覆われていない露出領域に対して、めっき前処理として、脱脂、酸浸漬、化学エッチング、電解処理、ストライクメッキなどを選択して施した後、ハンダぬれ性に優れる金属によって薄膜17をめっき形成し、この薄膜17上に、めっき(電鋳)により金属を積層して金属部11(電極部11b)を形成しており、本実施例では、ステンレスの母型基板10の露出領域に対して、化学エッチングを施した後、0.01~1μm厚の金の薄膜17をめっき成長させ、この薄膜17上にめっき(電鋳)により、例えば20~100μmの範囲、本実施形態では70μmの厚のニッケルを積層して金属部11(電極部11b)を形成している。なお、めっき前処理は、母型基板10及び金属部11(薄膜17)の材質によって、取捨選択して行うものであり、その中の化学エッチングとは、母型基板10自体を溶解して、その表面の酸化被膜(不活性膜)を除去するものであり、母型基板10の表面は粗面となる。また、薄膜17の形成は、半導体装置のハンダ付け対策を目的とする場合、メッキで金属部11の主材質部を形成する前に限られるものではなく、半導体装置70の完成後(母型基板10除去後)、封止材19から露出した金属部11の裏面にめっきにより薄膜17を形成するようにしてもかまわない。 Subsequently, a metal portion 11 (electrode portion 11b) is formed in a region of the mother substrate 10 exposed from the second resist layer 16 (see FIG. 5(B)). Specifically, the exposed area of the front surface of the mother board 10 that is not covered with the second resist layer 16 is subjected to degreasing, acid immersion, chemical etching, electrolytic treatment, strike plating, etc. as a plating pretreatment. After selective application, a thin film 17 is formed by plating with a metal having excellent solder wettability, and metal is laminated on this thin film 17 by plating (electroforming) to form the metal part 11 (electrode part 11b). In this example, after chemically etching the exposed area of the stainless steel master substrate 10, a thin gold film 17 with a thickness of 0.01 to 1 μm is grown by plating, and then the thin film 17 is plated ( The metal portion 11 (electrode portion 11b) is formed by laminating nickel with a thickness of 20 to 100 μm, for example, 70 μm in this embodiment, by electroforming. The plating pre-treatment is selectively performed depending on the materials of the mother substrate 10 and the metal part 11 (thin film 17), and chemical etching is performed by dissolving the mother substrate 10 itself. The oxide film (inactive film) on the surface is removed, and the surface of the mother substrate 10 becomes rough. Further, when the purpose of forming the thin film 17 is to prevent soldering of a semiconductor device, the formation of the thin film 17 is not limited to before forming the main material part of the metal part 11 by plating, but after the completion of the semiconductor device 70 ( 10), the thin film 17 may be formed by plating on the back surface of the metal portion 11 exposed from the sealing material 19.

ここで、金属部11を形成する際に、第二レジスト層16の厚さを越えてめっき成長させることで、金属部11の上端部に張出部11cが形成される。この張出部11cが存在することにより、半導体装置の製造工程において、封止材19で封止する際に、封止材19が張出部11cにくい込み状に位置した状態で硬化されるため、母型基板10を金属層11及び封止材19から引き剥がし除去する場合でも、封止材19と張出部11cとの食い付き効果により、金属部11は封止材19内に確実に残留し、母型基板10とともにくっついて引き離されることはなく、金属層11のズレや欠落等を防止することができる。なお、金属部11を形成する際に、第二レジスト層16の厚さを越えない範囲でめっき成長すれば、上端部に張出部のないストレート状の金属部11を得ることができる。 Here, when forming the metal part 11, the overhang part 11c is formed at the upper end of the metal part 11 by growing the plating to exceed the thickness of the second resist layer 16. Due to the presence of the overhanging portion 11c, when sealing with the encapsulant 19 is performed in the manufacturing process of a semiconductor device, the encapsulant 19 is hardened in a state where it is embedded in the overhanging portion 11c. Even when the mother board 10 is peeled off and removed from the metal layer 11 and the sealing material 19, the metal part 11 is reliably inserted into the sealing material 19 due to the biting effect of the sealing material 19 and the overhanging part 11c. The metal layer 11 remains, sticks together with the mother board 10, and is not separated, thereby preventing the metal layer 11 from shifting or missing. Note that when forming the metal part 11, if the plating is grown within a range that does not exceed the thickness of the second resist layer 16, a straight metal part 11 without an overhang at the upper end can be obtained.

また、金属部11の裏面にはこの裏面の一部から部分的に突出する突出部11dが形成されており、金属部11の上面には窪み部11eが形成されている。この窪み部11eは突出部11dの直上、つまり、突出部11dと窪み部11eは金属部11の厚み方向において重なる位置に形成されている。これは、金属部11をめっき形成する際、金属部11を構成する金属は母型基板10の第二レジスト層16で覆われていない露出領域である凹部20の底面(内面)を含む母型基板10の表面からめっき成長され、凹部20内に金属部11を構成する金属がめっき成長されることで突出部11dが形成される一方で、突出部11d(凹部20)の直上に位置する金属部11の表面においては、凹部20の形状に倣って窪み部11eが形成されるためである。なお、突出部11dと窪み部11eは相似、つまり、突出部11dの突出形状と窪み部11eの窪み形状が相似形となっており、突出部11dの高さ寸法と窪み部11e(凹部20)の深さ寸法は、突出部11dの高さ寸法≧窪み部11e(凹部20)の深さ寸法の関係にある。 Furthermore, a protrusion 11d is formed on the back surface of the metal part 11, and a protrusion 11d that partially protrudes from a part of the back surface, and a recess 11e is formed on the top surface of the metal part 11. The recess 11e is formed directly above the protrusion 11d, that is, at a position where the protrusion 11d and the recess 11e overlap in the thickness direction of the metal portion 11. This is because when forming the metal part 11 by plating, the metal constituting the metal part 11 is applied to the mother mold substrate 10 including the bottom surface (inner surface) of the recess 20 which is an exposed area not covered with the second resist layer 16 of the mother mold substrate 10. The protrusion 11d is formed by plating and growing the metal forming the metal part 11 in the recess 20 from the surface of the substrate 10, while the metal located directly above the protrusion 11d (recess 20) This is because a recessed portion 11e is formed on the surface of the portion 11, following the shape of the recessed portion 20. Note that the protrusion 11d and the recess 11e are similar, that is, the protrusion shape of the protrusion 11d and the recess shape of the recess 11e are similar, and the height dimension of the protrusion 11d and the recess 11e (recess 20) are similar. The depth dimension is in the relationship: height dimension of the protruding portion 11d≧depth dimension of the depressed portion 11e (recessed portion 20).

続いて、所望の形状の金属部11が得られたら、金属部11(電極部11b)の表面に表面金属層13を形成する(図5(B)参照)。具体的には、金属部11(電極部11b)の表面に、1~10μm厚の銀の表面金属層13をめっき形成している。なお、表面金属層13をめっき形成する際に、例えば金属部11がニッケルからなり、表面金属層13が密着形成しにくい場合には、表面金属層13のめっきの前にあらかじめ金属部11表面に下地めっき(銅ストライク、ニッケルストライク、銀ストライク、又は金ストライク)を行い、表面金属層13の金属部11への密着性を高めることが望ましい。 Subsequently, after obtaining the metal part 11 in the desired shape, a surface metal layer 13 is formed on the surface of the metal part 11 (electrode part 11b) (see FIG. 5(B)). Specifically, a silver surface metal layer 13 having a thickness of 1 to 10 μm is plated on the surface of the metal portion 11 (electrode portion 11b). When forming the surface metal layer 13 by plating, for example, if the metal part 11 is made of nickel and it is difficult to form the surface metal layer 13 in close contact, the surface of the metal part 11 may be plated before plating the surface metal layer 13. It is desirable to perform base plating (copper strike, nickel strike, silver strike, or gold strike) to improve the adhesion of the surface metal layer 13 to the metal part 11.

続いて、母型基板10に形成された第二レジスト層16を除去(溶解除去、膨潤除去)することで、母型基板10に金属部11(電極部11b)が形成された半導体装置用基板が得られる(図5(C)参照)。係る金属部11は、母型基板10表面において、一又は複数配置される電極部11bを一つの単位として、製造する半導体装置の数だけ多数整列状態で並べられた形態で形成されることとなり、本実施形態では、6つの電極部11bを一つの単位としている。 Subsequently, the second resist layer 16 formed on the mother substrate 10 is removed (dissolved, removed by swelling), thereby producing a semiconductor device substrate in which the metal portion 11 (electrode portion 11b) is formed on the mother substrate 10. is obtained (see FIG. 5(C)). Such metal parts 11 are formed on the surface of the mother substrate 10 in a form in which one or more electrode parts 11b are arranged as one unit, and a number of metal parts 11 are arranged in an array corresponding to the number of semiconductor devices to be manufactured. In this embodiment, six electrode parts 11b are used as one unit.

なお、母型基板10の表面側には第一レジスト層12や第二レジスト層16を形成するが、母型基板10の裏面側にもレジスト層を形成しても良い。裏面側のレジスト層は、硬化状態でエッチング液とメッキ液への耐性のある材質で、且つ不要となったら容易に溶解除去可能なレジスト材、例えば、厚さ約50μmのアルカリ現像タイプの感光性フィルムレジストを熱圧着等により配設し、そのままマスクなしに紫外線照射による露光等の処理を経て、裏面全面にわたり硬化形成されるものとすることができる。この裏面側のレジスト層については、レジストに限られるものではなく、例えばカバーフィルムであっても良く、要は耐溶解性・絶縁性を有するものであれば良い。 Although the first resist layer 12 and the second resist layer 16 are formed on the front side of the mother substrate 10, a resist layer may also be formed on the back side of the mother substrate 10. The resist layer on the back side is made of a material that is resistant to etching solutions and plating solutions in the hardened state, and can be easily dissolved and removed when no longer needed, such as a photosensitive alkaline developable type with a thickness of about 50 μm. A film resist can be disposed by thermocompression bonding or the like, and then subjected to a treatment such as exposure to ultraviolet rays without a mask to be cured over the entire back surface. The resist layer on the back side is not limited to a resist, and may be a cover film, for example, as long as it has dissolution resistance and insulation properties.

次に、得られた半導体装置用基板1を用いた半導体装置の製造について説明すると、まず、半導体装置用基板1における電極部11b(金属部11)上に、半導体素子14を載置して、半導体素子14の電極とこれに対応する各電極部11b(金属部11)とを電気的接続状態とする(図6(A)参照)。この電気的接続は、はんだ付けによって行われる。なお、半導体素子14を載置する際、半導体素子14の電極は電極部11b(金属部11)の窪み部を避けた位置にて電気的接続することが好ましい。また、本実施形態では、半導体素子14と電極部11bとの電気的接続をフリップチップ方式で行っているが、もちろん、金、銅等の導電性線材からなるワイヤを用いたワイヤボンディング方式で行っても良い。 Next, manufacturing of a semiconductor device using the obtained semiconductor device substrate 1 will be described. First, the semiconductor element 14 is placed on the electrode portion 11b (metal portion 11) of the semiconductor device substrate 1. The electrodes of the semiconductor element 14 and the corresponding electrode portions 11b (metal portions 11) are electrically connected (see FIG. 6A). This electrical connection is made by soldering. Note that when mounting the semiconductor element 14, it is preferable that the electrodes of the semiconductor element 14 be electrically connected at a position that avoids the recessed part of the electrode part 11b (metal part 11). Further, in this embodiment, the electrical connection between the semiconductor element 14 and the electrode part 11b is performed by a flip-chip method, but of course, it is also performed by a wire bonding method using a wire made of conductive wire material such as gold or copper. It's okay.

続いて、母型基板10の表面側を熱硬化性エポキシ樹脂等の封止材19で封止し、半導体素子14を外部から隔離した保護状態とする(図6(B)参照)。詳細には、母型基板10の表面側を上型となるモールド金型に装着し、母型基板10に下型の役割を担わせつつ、モールド金型内に封止材19となるエポキシ樹脂を圧入するという過程で封止が実行され、母型基板10上では、一つの半導体装置となる複数の電極部11bが多数整列状態のままで一様に封止され、半導体装置が多数つながった状態で現れることとなる。 Subsequently, the front side of the mother board 10 is sealed with a sealing material 19 such as a thermosetting epoxy resin, and the semiconductor element 14 is placed in a protected state isolated from the outside (see FIG. 6(B)). In detail, the front side of the mother board 10 is attached to a mold that will serve as an upper mold, and while the mother board 10 is made to play the role of a lower mold, an epoxy resin that will be a sealing material 19 is placed in the mold. Sealing is performed in the process of press-fitting, and on the mother board 10, a large number of electrode parts 11b forming one semiconductor device are uniformly sealed while remaining aligned, and a large number of semiconductor devices are connected. It will appear in the state.

続いて、母型基板10を除去し、各半導体装置の底部に電極部11b(金属部11)が露出した状態を得る(図6(C)参照)。ステンレス製である母型基板10の除去には、半導体装置側から母型基板10を物理的に引き剥がして除去する方法を用いる。母型基板10に強度及び剥離性に優れるステンレスを用いることで、半導体装置側から母型基板10を引き剥がして速やかに分離除去することができる。 Subsequently, the mother substrate 10 is removed to obtain a state in which the electrode portion 11b (metal portion 11) is exposed at the bottom of each semiconductor device (see FIG. 6C). To remove the motherboard 10 made of stainless steel, a method is used in which the motherboard 10 is physically peeled off from the semiconductor device side. By using stainless steel, which has excellent strength and removability, for the mother substrate 10, the mother substrate 10 can be peeled off from the semiconductor device side and quickly separated and removed.

この他、母型基板10を除去する方法として、母型基板10をエッチング(溶解)させる方法を用いることもできる。このエッチングの場合、母型基板10は溶解するが薄膜17や金属部11の材質が冒されないような選択エッチング性を有するエッチング液を用いることとなる。溶解させて除去する場合では、半導体装置側に過大な力が加わらないため、母型基板10の除去に伴う悪影響が生じる確率を小さくできる。母型基板10をエッチング除去する場合は、耐食性を得るためにも金属部11の形成に先立って薄膜17を形成することが望ましい。 In addition, as a method for removing the mother substrate 10, a method of etching (dissolving) the mother substrate 10 can also be used. In the case of this etching, an etching solution having a selective etching property that dissolves the mother substrate 10 but does not damage the materials of the thin film 17 and the metal portion 11 is used. In the case of removing by melting, excessive force is not applied to the semiconductor device side, so that the probability that an adverse effect will occur due to the removal of the mother substrate 10 can be reduced. When removing the mother substrate 10 by etching, it is desirable to form the thin film 17 prior to forming the metal portion 11 in order to obtain corrosion resistance.

母型基板10が除去された半導体装置の底部では、封止材19の裏面側から突出部11dが部分的に突出されるとともに、突出部11dを除く金属部11の裏面と、封止材19の裏面とが略同一平面上に位置する状態となっている。母型基板10の除去後、多数つながった状態の半導体装置を一つ一つ切り離せば、一つの半導体装置70としての完成品となる。 At the bottom of the semiconductor device from which the mother substrate 10 has been removed, the protrusion 11d partially protrudes from the back side of the sealing material 19, and the back surface of the metal part 11 excluding the protrusion 11d and the sealing material 19 The rear surface of the holder and the back surface of the holder are located on substantially the same plane. After the mother substrate 10 is removed, a large number of connected semiconductor devices are separated one by one to form a completed semiconductor device 70.

このように、本実施形態に係る半導体装置用基板1は、母型基板10上に形成された電極部11bに突出部11dを有することから、この半導体装置用基板1を用いた半導体装置70の底部において、突出部11dの高さ寸法分だけ封止材19の裏面から突出形成されることによる配線逃げ構造が得られるので、電極部11bの裏面全体が突出された形態に比べ、所望する実装基板の電極部分や配線部分以外での電極部11bの接触・接合を避けることができ、信頼性に優れた半導体装置を得ることができる。また、この突出部11dは電極部11b(金属部11)の一部から部分的に突出形成されたものなので、半導体装置の実装基板への搭載自由度を増すことができる。 As described above, since the semiconductor device substrate 1 according to the present embodiment has the protruding portion 11d on the electrode portion 11b formed on the mother substrate 10, the semiconductor device 70 using this semiconductor device substrate 1 can be At the bottom, a wiring escape structure is obtained by protruding from the back surface of the sealing material 19 by the height of the protruding portion 11d, so that it is easier to achieve desired mounting than when the entire back surface of the electrode portion 11b is protruded. Contact and bonding of the electrode portion 11b at areas other than the electrode portions and wiring portions of the substrate can be avoided, and a highly reliable semiconductor device can be obtained. Further, since the protruding portion 11d is partially formed to protrude from a part of the electrode portion 11b (metal portion 11), the degree of freedom in mounting the semiconductor device on the mounting board can be increased.

また、半導体装置70内部において、金属部11の上端周縁を張出部11cとして略庇状に張り出し形成し、封止材19による封止状態で張出部11cが封止材19に囲まれて固定されること(アンカー効果)で、樹脂同士で密着し強固に一体化した封止材19に張出部11cが食込んで、金属部11に加わる外力に対する抵抗体の役割を果たすこととなり、母型基板10にステンレス等を用い、半導体装置側から母型基板10を物理的に引き剥がして除去する場合など、金属部11裏面側に装置外装から引離そうとする外力が加わっても、該張出部11cが金属部11の移動を妨げ、金属部11の他部分に対するズレ等をなくすことができ、製造時における歩留りを向上させられると共に、半導体装置としての強度を高められ、使用時の耐久性や半導体装置動作の信頼性も高められる。しかも、金属部11の表面に窪み部11eを有することで、この窪み部11e内に封止材19が入り込むことになるので、張出部11cによる食い付き効果と相まって、金属部11と封止材19との密着をより強固にでき、半導体装置としての強度を高められ、半導体素子14の保護をより確実にできる。 Further, inside the semiconductor device 70, the upper end periphery of the metal part 11 is formed to protrude into a substantially eave-like shape as a protruding part 11c, and the protruding part 11c is surrounded by the encapsulant 19 in a sealed state with the encapsulant 19. By being fixed (anchor effect), the overhanging part 11c bites into the sealing material 19, which is tightly integrated with the resins, and plays the role of a resistor against external force applied to the metal part 11. When the mother substrate 10 is made of stainless steel or the like and the mother substrate 10 is physically peeled off and removed from the semiconductor device side, even if an external force is applied to the back side of the metal part 11 to separate it from the device exterior, The protruding portion 11c prevents the metal portion 11 from moving and eliminates misalignment of the metal portion 11 with respect to other portions, improving the yield during manufacturing, increasing the strength of the semiconductor device, and increasing the strength of the semiconductor device during use. The durability of the semiconductor device and the reliability of the operation of the semiconductor device can also be improved. Moreover, by having the recessed part 11e on the surface of the metal part 11, the sealing material 19 enters into the recessed part 11e, so that, combined with the biting effect of the overhanging part 11c, the sealing material 19 and the metal part 11 are sealed. The adhesion with the material 19 can be made stronger, the strength of the semiconductor device can be increased, and the semiconductor element 14 can be protected more reliably.

上記実施形態において、突出部11dの形状としては、丸状、円状、多角状、球体状、錐体状、柱体状が挙げられ、突出部11dと金属部11(裏面)との境はなだらかに連続する面となるように形成されるのが好ましい。また、上記実施形態において、半導体素子14は電極部11b上に搭載しているが、金属部11として半導体素子搭載部を設け、この半導体素子搭載部上に半導体素子14を搭載するようにしても良い。なお、金属部11(半導体素子搭載部、電極部11b)上に半導体素子14を搭載するための接着材としては、固体状、粘体状、液体状のものがあり、例えば、はんだ、銀ペースト、樹脂ペースト、ダイアタッチフィルムが挙げられる。 In the above embodiment, the shape of the protrusion 11d includes round, circular, polygonal, spherical, pyramidal, and columnar shapes, and the boundary between the protrusion 11d and the metal part 11 (back surface) is It is preferable that the surface be formed into a gently continuous surface. Further, in the above embodiment, the semiconductor element 14 is mounted on the electrode part 11b, but a semiconductor element mounting part may be provided as the metal part 11 and the semiconductor element 14 may be mounted on this semiconductor element mounting part. good. Note that the adhesive for mounting the semiconductor element 14 on the metal part 11 (semiconductor element mounting part, electrode part 11b) may be solid, viscous, or liquid, such as solder, silver paste, Examples include resin paste and die attach film.

また、上記実施形態において、図3に示すように、金属部11(電極部11b)を直線状に形成することで、半導体装置の底部(封止材19の裏面)における有効利用面積(金属部11形成領域を除く領域)を最大限にできるので、実装基板における配線が複雑に配置されていても不具合を起こすおそれを減少させることができる。また、図7に示すように、半導体装置の底部(封止材19の裏面)において、金属部11の一端を外周部分に配設し、金属部11の他端を中心部分に集中するように配設すれば、隣り合う金属部11の配置間隔を一定にすることができる。係る構成は、半導体素子14の電極(実装基板の電極)が多数設けられているときに有効である。 In the above embodiment, as shown in FIG. 3, by forming the metal part 11 (electrode part 11b) in a straight line, the effective usable area (metal part 11 (excluding the formation area) can be maximized, so even if the wiring on the mounting board is arranged in a complicated manner, the risk of causing a problem can be reduced. Further, as shown in FIG. 7, at the bottom of the semiconductor device (the back surface of the sealing material 19), one end of the metal part 11 is arranged in the outer peripheral part, and the other end of the metal part 11 is arranged in the central part. If provided, the spacing between adjacent metal parts 11 can be made constant. Such a configuration is effective when a large number of electrodes of the semiconductor element 14 (electrodes of the mounting board) are provided.

1 半導体装置用基板
10 母型基板
11 金属部
11b 電極部
11c 張出部
11d 突出部
11e 窪み部
12 第一レジスト層
13 表面金属層
14 半導体素子
15 ワイヤ
16 第二レジスト層
17 薄膜
19 封止材
20 凹部
70 半導体装置
Reference Signs List 1 Semiconductor device substrate 10 Mother substrate 11 Metal portion 11b Electrode portion 11c Projection portion 11d Projection portion 11e Recessed portion 12 First resist layer 13 Surface metal layer 14 Semiconductor element 15 Wire 16 Second resist layer 17 Thin film 19 Sealing material 20 recess 70 semiconductor device

Claims (5)

母型基板(10)上に形成された、半導体装置の底面サイズよりも小さい凹部(20)と、1つの前記凹部(20)内表面および該凹部(20)の外側の面にわたる所定位置に段差をつけて形成された、少なくとも電極部(11b)となる金属部(11)とを備えることを特徴とする半導体装置用基板。 A recess (20) smaller than the bottom size of the semiconductor device formed on the mother substrate (10), and a step at a predetermined position spanning the inner surface of one of the recesses (20) and the outer surface of the recess (20). 1. A substrate for a semiconductor device, comprising: a metal portion (11) which is formed by attaching at least a metal portion (11) to serve as an electrode portion (11b). 前記金属部(11)の裏面に金属の薄膜(17)が形成されていることを特徴とする請求項1に記載の半導体装置用基板。 The substrate for a semiconductor device according to claim 1, characterized in that a metal thin film (17) is formed on the back surface of the metal part (11). 前記凹部(20)の深さが5~30μmであることを特徴とする請求項1または2に記載の半導体装置用基板。 The substrate for a semiconductor device according to claim 1 or 2, wherein the depth of the recess (20) is 5 to 30 μm. 母型基板(10)上に、半導体装置の底面サイズよりも小さい露出領域を有する第一レジスト層(12)を形成する工程と、
前記母型基板(10)にエッチングを施して凹部(20)を形成する工程と、
前記母型基板(10)上に形成した前記第一レジスト層(12)を除去する工程と、
前記母型基板(10)上に、1つの前記凹部(20)内表面および該凹部(20)の外側の面にわたる所定位置に対応する露出領域を有する第二レジスト層(16)を形成する工程と、
前記母型基板(10)の前記第二レジスト層(16)に覆われていない露出領域にめっきにより、段差のついた金属部(11)を形成する工程と、
前記前記母型基板(10)に形成した前記第二レジスト層(16)を除去する工程とを有することを特徴とする半導体装置用基板の製造方法。
forming a first resist layer (12) having an exposed area smaller than the bottom surface size of the semiconductor device on the mother substrate (10);
etching the mother substrate (10) to form a recess (20);
removing the first resist layer (12) formed on the mother substrate (10);
forming, on the mother substrate (10), a second resist layer (16) having an exposed area corresponding to a predetermined position spanning the inner surface of one of the recesses (20) and the outer surface of the recess (20); and,
forming a stepped metal part (11) by plating on an exposed area of the mother substrate (10) that is not covered with the second resist layer (16);
A method for manufacturing a substrate for a semiconductor device, comprising the step of removing the second resist layer (16) formed on the mother substrate (10).
半導体素子(14)と、前記半導体素子(14)と電気的に接続する電極部(11b)となる金属部(11)とが封止材(19)によって封止された半導体装置であって、
前記金属部(11)の裏面には、部分的に突出して実装基板と接合される突出部(11d)が設けられており、
前記金属部(11)の裏面が段差を有した形状に形成されていることを特徴とする半導体装置。
A semiconductor device in which a semiconductor element (14) and a metal part (11) serving as an electrode part (11b) electrically connected to the semiconductor element (14) are sealed with a sealing material (19),
A protrusion (11d) is provided on the back surface of the metal part (11), and is partially protruded and joined to the mounting board;
A semiconductor device characterized in that the back surface of the metal part (11) is formed in a shape with a step.
JP2023193533A 2020-11-30 2023-11-14 Substrate for semiconductor device, method of manufacturing the same, and semiconductor device Pending JP2024003147A (en)

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