JP6806436B2 - Substrates for semiconductor devices, their manufacturing methods, and semiconductor devices - Google Patents

Substrates for semiconductor devices, their manufacturing methods, and semiconductor devices Download PDF

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JP6806436B2
JP6806436B2 JP2015226212A JP2015226212A JP6806436B2 JP 6806436 B2 JP6806436 B2 JP 6806436B2 JP 2015226212 A JP2015226212 A JP 2015226212A JP 2015226212 A JP2015226212 A JP 2015226212A JP 6806436 B2 JP6806436 B2 JP 6806436B2
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metal
semiconductor device
substrate
metal portion
master substrate
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JP2017098315A (en
JP2017098315A5 (en
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中川　宏史
宏史 中川
佑也 五郎丸
佑也 五郎丸
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Maxell Holdings Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Description

本発明は、基板上にリードが形成された半導体装置用基板、該半導体装置用基板を用いて製造される半導体装置に関する。 The present invention relates to a semiconductor device substrate in which leads are formed on the substrate, and a semiconductor device manufactured by using the semiconductor device substrate.

半導体素子支持用の基板上に半導体素子を搭載し、半導体素子と外部導出用の金属端子とを配線接続した上で、樹脂等の保護材で半導体素子を含む基板全体を被覆した旧来の構造の半導体装置は、その構造上、小型化には限界があった。これに対し、半導体素子搭載部分や電極部分となる金属部を形成し、この金属部上に半導体素子を搭載し配線等の処理後、半導体素子や配線等のある金属部の表面側を樹脂等の封止材で封止し、金属部が底部に一部露出した構成とされる半導体装置は、その高さを低くして省スペース化が図れ、チップサイズなど超小型の半導体装置の分野で利用が進んでいる。 A conventional structure in which a semiconductor element is mounted on a substrate for supporting the semiconductor element, the semiconductor element and a metal terminal for external derivation are connected by wiring, and the entire substrate including the semiconductor element is covered with a protective material such as resin. Due to the structure of semiconductor devices, there is a limit to miniaturization. On the other hand, a metal portion to be a semiconductor element mounting portion or an electrode portion is formed, and after the semiconductor element is mounted on the metal portion and processing such as wiring is performed, the surface side of the metal portion having the semiconductor element or wiring is made of resin or the like. In the field of ultra-small semiconductor devices such as chip size, semiconductor devices that are sealed with the sealing material of the above and have a structure in which the metal part is partially exposed at the bottom can reduce the height to save space. The use is progressing.

こうした半導体装置は、主に、導電性を有する母型基板上に半導体素子搭載部分や電極部分となる金属部を、メッキ（電鋳）により、半導体装置の所望個数分まとめて形成し、半導体素子が搭載され配線等の処理を経た金属部の表面側を封止材で封止した後、母型基板のみを除去し、一体にまとまった状態の多数の半導体装置を個別に切り分ける、といった製造過程を経て製造される。このような半導体装置の製造方法の一例として、特開２００２−９１９６号公報に開示されるものがある。 In such a semiconductor device, mainly, a desired number of semiconductor device mounting portions and metal portions to be electrode portions are formed by plating (electrocasting) on a conductive mother die substrate, and the semiconductor element is formed. After sealing the surface side of the metal part that has undergone processing such as wiring with a sealing material, only the master substrate is removed, and a large number of semiconductor devices in an integrated state are individually separated. Manufactured via. As an example of a method for manufacturing such a semiconductor device, there is one disclosed in JP-A-2002-9196.

特開２００２−９１９６号公報JP-A-2002-9196 特開２００４−２１４２６５号公報Japanese Unexamined Patent Publication No. 2004-214265

特許文献１には、半導体素子搭載部分や電極部分の裏面のいずれか一方もしくは両方を樹脂封止した際、封止材の裏面よりも若干突出（スタンドオフ）させるように構成した半導体装置が開示されている。このように、半導体素子搭載部分や電極部分の裏面を封止材の裏面から突出させることで、半導体装置を実装基板に実装する際に、半導体装置の電極部分（リード）と実装基板の電極部分（パッド）との接合を良好にすることができる。 Patent Document 1 discloses a semiconductor device configured so that when one or both of the back surface of a semiconductor element mounting portion and an electrode portion is resin-sealed, the semiconductor device is configured to slightly protrude (standoff) from the back surface of the sealing material. Has been done. By projecting the back surface of the semiconductor element mounting portion and the electrode portion from the back surface of the sealing material in this way, when the semiconductor device is mounted on the mounting substrate, the electrode portion (lead) of the semiconductor device and the electrode portion of the mounting substrate are used. Good bonding with (pad) can be achieved.

近年、電子機器の小型化を実現するために、実装基板の電極部分や配線部分が密集して形成されつつあるが、上記半導体装置の構造では、半導体素子搭載部分や電極部分の裏面全体が封止材の裏面から突出しているため、半導体装置の半導体素子搭載部分（ダイパッド）や電極部分（リード）と実装基板の電極部分（パッド）や配線部分が所望せぬ箇所で接触するおそれがある。 In recent years, in order to realize miniaturization of electronic devices, electrode portions and wiring portions of mounting substrates have been densely formed. However, in the structure of the semiconductor device, the entire back surface of the semiconductor element mounting portion and the electrode portion is sealed. Since it protrudes from the back surface of the stop material, the semiconductor element mounting portion (die pad) or electrode portion (lead) of the semiconductor device may come into contact with the electrode portion (pad) or wiring portion of the mounting substrate at an undesired location.

本発明の目的は、半導体素子搭載部分や電極部分の一部を封止材の裏面から突出させて、得られる半導体装置の小型化を図れるとともに、配線が密集して形成された実装基板にも容易で信頼性良く実装可能な半導体装置を製造できる、半導体装置用基板とその製造方法、並びに、この半導体装置用基板を用いて製造される半導体装置を提供することにある。 An object of the present invention is to project a part of a semiconductor element mounting portion or an electrode portion from the back surface of a sealing material to reduce the size of the obtained semiconductor device, and also to a mounting substrate formed with dense wiring. easy and can be manufactured reliably mountable semiconductor device, the substrate and a manufacturing method thereof for a semiconductor device, and to provide a semiconductor equipment to be manufactured using this semiconductor device substrate.

本発明に係る半導体装置用基板は、母型基板１０上に少なくとも電極部１１ｂとなる金属部１１が形成されており、金属部１１の母型基板面側には部分的に突出する突出部１１ｄが設けられていることを特徴とする。 In the substrate for a semiconductor device according to the present invention, at least a metal portion 11 to be an electrode portion 11b is formed on a master substrate 10, and a protruding portion 11d that partially protrudes from the master substrate surface side of the metal portion 11 Is provided.

また、金属部１１の母型基板面側とは反対側の面には窪み部１１ｅが設けられていることを特徴とする。 Further, a recessed portion 11e is provided on the surface of the metal portion 11 opposite to the surface side of the master substrate.

また、突出部１１ｄと窪み部１１ｅが金属部１１の厚み方向において重なる位置に設けられていることを特徴とする。 Further, the protruding portion 11d and the recessed portion 11e are provided at overlapping positions in the thickness direction of the metal portion 11.

また、突出部１１ｄの突出形状と窪み部１１の窪み形状が相似形であることを特徴とする。 Further, the protruding shape of the protruding portion 11d and the recessed shape of the recessed portion 11 are similar to each other.

本発明に係る半導体装置用基板の製造方法は、母型基板１０上に少なくとも電極部１１ｂとなる金属部１１が形成されており、金属部１１の母型基板面側には部分的に突出する突出部１１ｄが設けられている半導体装置用基板の製造方法であって、母型基板１０上に、第一レジスト層１２を形成する工程と、母型基板１０の第一レジスト層１２で覆われていない露出領域に凹部２０を形成する工程と、第一レジスト層１２を除去する工程と、母型基板１０上に、第二レジスト層１６を形成する工程と、母型基板１０の第二レジスト層１６で覆われていない露出領域に、金属部１１を形成する工程と、第二レジスト層１６を除去する工程とを有することを特徴とする。 In the method for manufacturing a substrate for a semiconductor device according to the present invention, at least a metal portion 11 to be an electrode portion 11b is formed on a master substrate 10, and the metal portion 11 partially protrudes from the master substrate surface side. A method for manufacturing a substrate for a semiconductor device provided with a protruding portion 11d, which is a step of forming a first resist layer 12 on a master substrate 10 and being covered with a first resist layer 12 of the master substrate 10. A step of forming a recess 20 in an unexposed region, a step of removing the first resist layer 12, a step of forming a second resist layer 16 on the master substrate 10, and a second resist of the master substrate 10. It is characterized by having a step of forming a metal portion 11 in an exposed region not covered by the layer 16 and a step of removing the second resist layer 16.

また、金属部１１を形成する工程において、母型基板１０及び凹部２０の表面に、金属部１１をめっき成長させることを特徴とする。さらに、金属部１１を形成する工程において、第二レジスト層１６の厚さを越えて金属部１１をめっき成長させることを特徴とする。 Further, in the step of forming the metal portion 11, the metal portion 11 is plated and grown on the surfaces of the master substrate 10 and the recess 20. Further, in the step of forming the metal portion 11, the metal portion 11 is plated and grown beyond the thickness of the second resist layer 16.

本発明に係る半導体装置は、半導体素子１４と電気的に接続する電極部１１ｂとなる金属部１１を有し、金属部１１上への半導体素子１４の搭載、半導体素子１４と金属部１１との電気的接続、封止材１９による封止がなされる半導体装置であって、封止材１９の裏面から金属部１１の裏面が露出されており、金属部１１の裏面には封止材１９の裏面より突出形成された突出部１１ｄが設けられ、突出部１１ｄを除く金属部１１の裏面と封止材１９の裏面とが略同一平面となっていることを特徴とする。 The semiconductor device according to the present invention has a metal portion 11 serving as an electrode portion 11b that is electrically connected to the semiconductor element 14, the semiconductor element 14 is mounted on the metal portion 11, and the semiconductor element 14 and the metal portion 11 are connected to each other. A semiconductor device that is electrically connected and sealed by a sealing material 19. The back surface of the metal portion 11 is exposed from the back surface of the sealing material 19, and the back surface of the metal portion 11 is covered with the sealing material 19. A projecting portion 11d formed so as to project from the back surface is provided, and the back surface of the metal portion 11 excluding the projecting portion 11d and the back surface of the sealing material 19 are substantially flush with each other.

また、金属部１１の表面には窪み部１１ｅが設けられていることを特徴とする。 Further, the surface of the metal portion 11 is provided with a recessed portion 11e.

また、突出部１１ｄと窪み部１１ｅが金属部１１の厚み方向において重なる位置に設けられていることを特徴とする。 Further, the protruding portion 11d and the recessed portion 11e are provided at overlapping positions in the thickness direction of the metal portion 11.

また、突出部１１ｄの突出形状と窪み部１１の窪み形状が相似形であることを特徴とする。 Further, the protruding shape of the protruding portion 11d and the recessed shape of the recessed portion 11 are similar to each other.

本発明によれば、金属部１１の裏面に部分的に突出形成された突出部１１ｄが設けられているので、係る金属部１１を備えた半導体装置は、電極や配線が密集した実装基板に対しても、容易で的確な実装が可能となる。また、突出部１１ｄの径や幅を実装基板の電極に対応して小さく形成せざるを得なくても、金属部１１の表面（表面積）は突出部１１ｄに比べ大きく形成することができ、搭載する半導体素子１４の選択自由度を拡げることができる。 According to the present invention, since the collision detecting portion 11d which is partially protruded to the rear surface of the metal portion 11 is provided, a semiconductor device having the metal portion 11 of the the mounting substrate electrodes and wirings are densely On the other hand, easy and accurate implementation is possible. Further, even if forced to form correspondingly small diameter and width of collision detecting section 11d to the electrode of the mounting substrate, the surface (surface area) of the metal part 11 can be larger than in the collision detecting portion 11d , The degree of freedom in selection of the mounted semiconductor element 14 can be expanded.

本発明の第１の実施形態に係る半導体装置用基板の部分平面図である。It is a partial plan view of the substrate for a semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置用基板の断面図及び平面図である。It is sectional drawing and plan view of the substrate for a semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の断面図及び底面図である。It is sectional drawing and bottom view of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置用基板の製造方法における工程説明図である。It is a process explanatory drawing in the manufacturing method of the substrate for a semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置用基板の製造方法における工程説明図である。It is a process explanatory drawing in the manufacturing method of the substrate for a semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法における工程説明図である。It is a process explanatory drawing in the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の他実施形態に係る半導体装置の断面図及び底面図である。It is sectional drawing and bottom view of the semiconductor device which concerns on other Embodiment of this invention.

（第１実施形態）
以下、本発明の第１実施形態に係る半導体装置用基板及び半導体装置について、図１ないし図６に基づいて説明する。本実施形態に係る半導体装置用基板１は、図２に示すように、導電性を有する材質からなる母型基板１０と、この母型基板１０上に形成され、本基板を用いて製造される半導体装置７０における電極部１１ｂとなる金属部１１とを備える構成である。 (First Embodiment)
Hereinafter, the semiconductor device substrate and the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 6. As shown in FIG. 2, the semiconductor device substrate 1 according to the present embodiment is formed on a master substrate 10 made of a conductive material and the master substrate 10, and is manufactured by using this substrate. It is configured to include a metal portion 11 serving as an electrode portion 11b in the semiconductor device 70.

母型基板１０は、ステンレス（ＳＵＳ４３０等）やアルミニウム、銅等の導電性の金属板（厚さ約０．１ｍｍ）で形成され、半導体装置の製造工程で除去されるまで、半導体装置用基板１の要部をなすものである。 The base substrate 10 is made of a conductive metal plate (thickness of about 0.1 mm) such as stainless steel (SUS430 or the like), aluminum, copper, etc., and is a substrate for a semiconductor device 1 until it is removed in the manufacturing process of the semiconductor device. It is the main part of.

金属部１１は、ニッケルや銅、又はニッケル−コバルト等のニッケル合金からなり、メッキ形成されるものであり、図１に示すように、母型基板１０表面で、一又は複数配置される状態を一つの単位として、製造する半導体装置の数だけ多数整列状態で並べられた形態で形成されることとなる。
The metal portion 11 is made of a nickel alloy such as nickel, copper, or nickel-cobalt and is formed by plating. As shown in FIG. 1, one or a plurality of metal portions 11 are arranged on the surface of the master substrate 10. As one unit, as many semiconductor devices as the number of semiconductor devices to be manufactured are arranged in an aligned state.

この金属部１１の母型基板面側（裏面）には、突出部１１ｄが形成されている。係る突出部１１ｄは、金属部１１の裏面から部分的に突出するように形成されている。また、母型基板面側とは反対側の面である金属部１１の表面、より詳しくは、突出部１１ｄの直上位置に窪み部１１ｅが形成されている。そして、金属部１１の上端部には、庇状に張り出す張出部１１ｃが形成されている。 A protruding portion 11d is formed on the surface side (back surface) of the master substrate of the metal portion 11. The protruding portion 11d is formed so as to partially protrude from the back surface of the metal portion 11. Further, a recessed portion 11e is formed on the surface of the metal portion 11 which is a surface opposite to the surface side of the master substrate, and more specifically, at a position directly above the protruding portion 11d. An overhanging portion 11c overhanging in the shape of an eave is formed at the upper end of the metal portion 11.

金属部１１は、大部分を電解メッキに適した、例えば、ニッケルやニッケル合金等で形成されるが、金属部１１の裏面側には、半導体装置実装時のハンダ付けを適切に行えるようにするために、ニッケル等の主材質部よりハンダぬれ性の良好な金属、例えば金や銀、錫、パラジウム、ハンダ等の薄膜１７が配設される構成である。この薄膜１７には、エッチングによる母型基板１０の除去の際に、エッチング液による金属部１１の侵食劣化を防ぐ機能を与えることもできる。この薄膜１７の厚さは、０．０１〜１μｍ程度とするのが好ましい。 Most of the metal portion 11 is made of, for example, nickel or nickel alloy, which is suitable for electrolytic plating, but the back surface side of the metal portion 11 can be appropriately soldered when mounting a semiconductor device. Therefore, a metal having good solder wettability, for example, a thin film 17 such as gold, silver, tin, palladium, or solder is arranged from the main material portion such as nickel. The thin film 17 can also be provided with a function of preventing erosion deterioration of the metal portion 11 by the etching solution when the master substrate 10 is removed by etching. The thickness of the thin film 17 is preferably about 0.01 to 1 μm.

また、金属部１１の表面には表面金属層１３が形成されている。この表面金属層１３は、半導体素子１４の電極との接合性に優れる金や銀、パラジウム等からなるメッキ膜として形成され、母型基板１０ごとのメッキにより金属部１１の表面に所定の厚さ、例えば、金メッキの場合は約０．１〜１μｍ、銀メッキの場合は約１〜１０μｍの厚さがメッキ形成される。 Further, a surface metal layer 13 is formed on the surface of the metal portion 11. The surface metal layer 13 is formed as a plating film made of gold, silver, palladium, etc., which has excellent bondability with the electrodes of the semiconductor element 14, and has a predetermined thickness on the surface of the metal portion 11 by plating each master substrate 10. For example, in the case of gold plating, a thickness of about 0.1 to 1 μm is formed, and in the case of silver plating, a thickness of about 1 to 10 μm is formed.

そして、この半導体装置用基板１を用いて製造される半導体装置７０は、図３に示すように、半導体装置用基板１から得られる金属部１１に加えて、金属部１１のうちの電極部１１ｂと電気的に接続する半導体素子１４と、半導体素子１４や金属部１１の表面側を覆って封止する封止材１９とを備える構成である。 Then, as shown in FIG. 3, the semiconductor device 70 manufactured by using the semiconductor device substrate 1 has an electrode portion 11b of the metal portion 11 in addition to the metal portion 11 obtained from the semiconductor device substrate 1. The configuration includes a semiconductor element 14 that is electrically connected to the semiconductor element 14 and a sealing material 19 that covers and seals the surface side of the semiconductor element 14 and the metal portion 11.

この半導体装置７０では、底部に金属部１１の裏面側が電極や放熱パッド等として露出した状態となり、この露出する金属部１１の裏面から突出部１１ｄが突出形成されるとともに、突出部１１ｄを除く金属部１１の裏面側と、装置外装の一部として現れる封止材１９の裏面側とが略同一平面上に位置する構成である。半導体装置７０における底部以外の各面は、装置外装をなす封止材１９のみがそれぞれ現れた状態となっている（図３（Ｂ）参照）。 In the semiconductor device 70, the back surface side of the metal portion 11 is exposed as an electrode, a heat radiation pad, or the like on the bottom portion, and the protruding portion 11d is formed to protrude from the back surface of the exposed metal portion 11, and the metal excluding the protruding portion 11d is formed. The back surface side of the portion 11 and the back surface side of the sealing material 19 appearing as a part of the exterior of the device are located on substantially the same plane. On each surface of the semiconductor device 70 other than the bottom, only the sealing material 19 forming the exterior of the device appears (see FIG. 3B).

半導体素子１４は、微細な電子回路が形成されたいわゆるチップであり、半導体素子１４表面に設けられた電極が電極部１１ｂと直接接合され、半導体素子１４と電極部１１ｂとを電気的に接続することとなる。 The semiconductor element 14 is a so-called chip in which a fine electronic circuit is formed, and an electrode provided on the surface of the semiconductor element 14 is directly bonded to the electrode portion 11b to electrically connect the semiconductor element 14 and the electrode portion 11b. It will be.

封止材１９は、物理的強度の高い熱硬化性エポキシ樹脂等であり、金属部１１や半導体素子１４を覆った状態で封止し、構造的に弱い部分を外部から隔離した保護状態とするものである。なお、半導体素子１４がＬＥＤ等の発光素子の場合、透光性の材質が用いられる。 The sealing material 19 is a thermosetting epoxy resin or the like having high physical strength, and is sealed while covering the metal portion 11 and the semiconductor element 14, so that the structurally weak portion is isolated from the outside. It is a thing. When the semiconductor element 14 is a light emitting element such as an LED, a translucent material is used.

この封止材１９は、十分な物理的強度を有しており、半導体装置７０の外装の一部として十分に内部を保護する機能を果し、母型基板１０を半導体装置側から引き剥がすなど力を加えて物理的に除去する場合にも、割れ等の破損もなく金属部１１との一体化状態を維持することとなる。 The encapsulant 19 has sufficient physical strength, fulfills a function of sufficiently protecting the inside as a part of the exterior of the semiconductor device 70, and peels off the master substrate 10 from the semiconductor device side. Even when it is physically removed by applying a force, the integrated state with the metal portion 11 is maintained without damage such as cracking.

次に、本実施形態に係る半導体装置用基板の製造方法及び半導体装置用基板を用いた半導体装置の製造方法の各工程について説明する。 Next, each step of the method of manufacturing the semiconductor device substrate and the method of manufacturing the semiconductor device using the semiconductor device substrate according to the present embodiment will be described.

半導体装置用基板の製造工程として、まず、母型基板１０を用意し、この母型基板１０上に金属部１１（電極部１１ｂ）の突出部１１ｄを形成するための凹部２０に対応する第一レジスト層１２を配設する（図４（Ａ）参照）。具体的には、母型基板１０の表面側に感光性レジスト材を配設し、この感光性レジスト材に対して、凹部２０（突出部１１ｄ）の形成位置に対応する所定パターンのマスクフィルムを載せた状態で、紫外線照射による露光での硬化、非照射部分のレジスト剤を除去する現像等の処理を行い、凹部２０（突出部１１ｄ）の形成位置が露出するように第一レジスト層１２を形成する。第一レジスト層１２は、母型基板１０表面に凹部２０を形成する際に使用するエッチング液に対する耐溶解性を備えた絶縁性材で形成されるものであり、詳しくは、アルカリ現像タイプの感光性レジスト材を母型基板１０に所定の厚さ、例えば５〜５０μｍの範囲、本実施形態では２０μｍの厚さとなるようにして密着配設される。 As a manufacturing process of a substrate for a semiconductor device, first, a master substrate 10 is prepared, and a first corresponding to a recess 20 for forming a protruding portion 11d of a metal portion 11 (electrode portion 11b) on the master substrate 10. The resist layer 12 is arranged (see FIG. 4 (A)). Specifically, a photosensitive resist material is arranged on the surface side of the master substrate 10, and a mask film having a predetermined pattern corresponding to the formation position of the recess 20 (protruding portion 11d) is applied to the photosensitive resist material. In the mounted state, the first resist layer 12 is subjected to processing such as curing by exposure to ultraviolet irradiation and development to remove the resist agent in the non-irradiated portion, so that the formation position of the recess 20 (protruding portion 11d) is exposed. Form. The first resist layer 12 is formed of an insulating material having solubility resistance to an etching solution used when forming a recess 20 on the surface of the master substrate 10, and more specifically, an alkali development type photosensitive material. The sex resist material is closely arranged on the matrix substrate 10 so as to have a predetermined thickness, for example, a thickness in the range of 5 to 50 μm, or 20 μm in the present embodiment.

続いて、母型基板１０の第一レジスト層１２から露出する領域に凹部２０を形成する（図４（Ｂ）参照）。具体的には、母型基板１０の表面側のうち第一レジスト層１２で覆われていない露出領域に対して、エッチングを施すことで凹部２０を形成する。凹部２０の形状としては円形や多角形が考えられ、凹部２０の深さは５〜３０μｍが望ましい。なお、凹部２０の形成方法としては、エッチングに限らず、レーザー加工やブラスト処理によって形成しても良い。 Subsequently, a recess 20 is formed in a region exposed from the first resist layer 12 of the master substrate 10 (see FIG. 4B). Specifically, the recess 20 is formed by etching the exposed region on the surface side of the master substrate 10 that is not covered with the first resist layer 12. The shape of the recess 20 may be circular or polygonal, and the depth of the recess 20 is preferably 5 to 30 μm. The method of forming the recess 20 is not limited to etching, and may be formed by laser processing or blasting.

続いて、母型基板１０に形成された第一レジスト層１２を除去（溶解除去、膨潤除去）することで、凹部２０が形成された母型基板１０を得る（図４（Ｃ）参照）。 Subsequently, the first resist layer 12 formed on the master substrate 10 is removed (dissolution removal, swelling removal) to obtain the master substrate 10 on which the recess 20 is formed (see FIG. 4C).

続いて、この母型基板１０上に金属部１１（電極部１１ｂ）を形成するための第二レジスト層１６を配設する（図５（Ａ）参照）。具体的には、母型基板１０の表面側に感光性レジスト材を配設し、この感光性レジスト材に対して、金属部１１（電極部１１ｂ）の形成位置に対応する所定パターンのマスクフィルムを載せた状態で、紫外線照射による露光での硬化、非照射部分のレジスト剤を除去する現像等の処理を行い、凹部を含む金属部１１（電極部１１ｂ）の形成位置が露出するように第二レジスト層１６を形成する。第二レジスト層１６は、金属部１１や表面金属層１３を形成する際に使用するメッキ液に対する耐溶解性を備えた絶縁性材で形成されるものであり、詳しくは、アルカリ現像タイプの感光性レジスト材を母型基板１０に所定の厚さ、例えば１０〜８０μｍの範囲、本実施形態では５０μｍの厚さとなるようにして密着配設される。なお、第一レジスト層１２及び第二レジスト層１６については、感光性レジストに限られるものではなく、エッチング液やメッキ液に対し変質せず強度の高い塗膜が得られる塗料を、母型基板１０上における凹部２０並びに金属部１１の配置部分が露出されるように、電着塗装等により必要な塗膜厚さとなるように塗装して形成することもできる。 Subsequently, a second resist layer 16 for forming the metal portion 11 (electrode portion 11b) is disposed on the master substrate 10 (see FIG. 5 (A)). Specifically, a photosensitive resist material is arranged on the surface side of the master substrate 10, and a mask film having a predetermined pattern corresponding to the formation position of the metal portion 11 (electrode portion 11b) with respect to the photosensitive resist material. The film is cured by exposure to ultraviolet irradiation, developed to remove the resist agent in the non-irradiated portion, and the like so that the formation position of the metal portion 11 (electrode portion 11b) including the recess is exposed. Two resist layers 16 are formed. The second resist layer 16 is formed of an insulating material having solubility resistance to a plating solution used when forming the metal portion 11 and the surface metal layer 13, and more specifically, an alkali development type photosensitive member. The sex resist material is closely arranged on the matrix substrate 10 so as to have a predetermined thickness, for example, a thickness in the range of 10 to 80 μm, or 50 μm in the present embodiment. The first resist layer 12 and the second resist layer 16 are not limited to the photosensitive resist, and a paint that does not deteriorate with respect to the etching solution or the plating solution and can obtain a high-strength coating film can be used as a base substrate. It can also be formed by coating so that the recess 20 and the arrangement portion of the metal portion 11 on the 10 are exposed so as to have a required coating thickness by electrodeposition coating or the like.

続いて、母型基板１０の第二レジスト層１６から露出する領域に金属部１１（電極部１１ｂ）を形成する（図５（Ｂ）参照）。具体的には、母型基板１０の表面側のうち第二レジスト層１６で覆われていない露出領域に対して、めっき前処理として、脱脂、酸浸漬、化学エッチング、電解処理、ストライクメッキなどを選択して施した後、ハンダぬれ性に優れる金属によって薄膜１７をめっき形成し、この薄膜１７上に、めっき（電鋳）により金属を積層して金属部１１（電極部１１ｂ）を形成しており、本実施例では、ステンレスの母型基板１０の露出領域に対して、化学エッチングを施した後、０．０１〜１μｍ厚の金の薄膜１７をめっき成長させ、この薄膜１７上にめっき（電鋳）により、例えば２０〜１００μｍの範囲、本実施形態では７０μｍの厚のニッケルを積層して金属部１１（電極部１１ｂ）を形成している。なお、めっき前処理は、母型基板１０及び金属部１１（薄膜１７）の材質によって、取捨選択して行うものであり、その中の化学エッチングとは、母型基板１０自体を溶解して、その表面の酸化被膜（不活性膜）を除去するものであり、母型基板１０の表面は粗面となる。また、薄膜１７の形成は、半導体装置のハンダ付け対策を目的とする場合、メッキで金属部１１の主材質部を形成する前に限られるものではなく、半導体装置７０の完成後（母型基板１０除去後）、封止材１９から露出した金属部１１の裏面にめっきにより薄膜１７を形成するようにしてもかまわない。 Subsequently, a metal portion 11 (electrode portion 11b) is formed in a region exposed from the second resist layer 16 of the master substrate 10 (see FIG. 5B). Specifically, degreasing, acid immersion, chemical etching, electrolytic treatment, strike plating, etc. are performed as plating pretreatments on the exposed region on the surface side of the master substrate 10 that is not covered by the second resist layer 16. After selection and application, a thin film 17 is plated and formed with a metal having excellent solder wettability, and a metal is laminated on the thin film 17 by plating (electrocasting) to form a metal portion 11 (electrode portion 11b). In this embodiment, the exposed region of the stainless steel matrix substrate 10 is chemically etched, and then a gold thin film 17 having a thickness of 0.01 to 1 μm is plated and grown, and then plated on the thin film 17 ( The metal portion 11 (electrode portion 11b) is formed by laminating nickel having a thickness of, for example, 20 to 100 μm, or 70 μm in the present embodiment, by electrocasting). The plating pretreatment is performed by selecting the materials of the master substrate 10 and the metal portion 11 (thin film 17), and the chemical etching in the master substrate 10 is performed by melting the master substrate 10 itself. The oxide film (inactive film) on the surface is removed, and the surface of the master substrate 10 becomes a rough surface. Further, the formation of the thin film 17 is not limited to before the main material portion of the metal portion 11 is formed by plating when the purpose is to prevent soldering of the semiconductor device, but after the completion of the semiconductor device 70 (matrix substrate). After removing 10), the thin film 17 may be formed by plating on the back surface of the metal portion 11 exposed from the sealing material 19.

ここで、金属部１１を形成する際に、第二レジスト層１６の厚さを越えてめっき成長させることで、金属部１１の上端部に張出部１１ｃが形成される。この張出部１１ｃが存在することにより、半導体装置の製造工程において、封止材１９で封止する際に、封止材１９が張出部１１ｃにくい込み状に位置した状態で硬化されるため、母型基板１０を金属層１１及び封止材１９から引き剥がし除去する場合でも、封止材１９と張出部１１ｃとの食い付き効果により、金属部１１は封止材１９内に確実に残留し、母型基板１０とともにくっついて引き離されることはなく、金属層１１のズレや欠落等を防止することができる。なお、金属部１１を形成する際に、第二レジスト層１６の厚さを越えない範囲でめっき成長すれば、上端部に張出部のないストレート状の金属部１１を得ることができる。 Here, when the metal portion 11 is formed, the overhanging portion 11c is formed at the upper end portion of the metal portion 11 by plating growth exceeding the thickness of the second resist layer 16. Due to the presence of the overhanging portion 11c, when the encapsulant 19 is used to seal the semiconductor device in the manufacturing process, the sealing material 19 is cured in a state where the overhanging portion 11c is difficult to be embedded. Even when the master substrate 10 is peeled off from the metal layer 11 and the sealing material 19, the metal portion 11 is surely contained in the sealing material 19 due to the biting effect between the sealing material 19 and the overhanging portion 11c. It remains and does not stick to and separate from the master substrate 10, and it is possible to prevent the metal layer 11 from being displaced or chipped. When the metal portion 11 is formed, if the plating grows within a range not exceeding the thickness of the second resist layer 16, a straight metal portion 11 having no overhanging portion at the upper end portion can be obtained.

また、金属部１１の裏面にはこの裏面の一部から部分的に突出する突出部１１ｄが形成されており、金属部１１の上面には窪み部１１ｅが形成されている。この窪み部１１ｅは突出部１１ｄの直上、つまり、突出部１１ｄと窪み部１１ｅは金属部１１の厚み方向において重なる位置に形成されている。これは、金属部１１をめっき形成する際、金属部１１を構成する金属は母型基板１０の第二レジスト層１６で覆われていない露出領域である凹部２０の底面（内面）を含む母型基板１０の表面からめっき成長され、凹部２０内に金属部１１を構成する金属がめっき成長されることで突出部１１ｄが形成される一方で、突出部１１ｄ（凹部２０）の直上に位置する金属部１１の表面においては、凹部２０の形状に倣って窪み部１１ｅが形成されるためである。なお、突出部１１ｄと窪み部１１ｅは相似、つまり、突出部１１ｄの突出形状と窪み部１１ｅの窪み形状が相似形となっており、突出部１１ｄの高さ寸法と窪み部１１ｅ（凹部２０）の深さ寸法は、突出部１１ｄの高さ寸法≧窪み部１１ｅ（凹部２０）の深さ寸法の関係にある。 Further, a protruding portion 11d that partially protrudes from a part of the back surface is formed on the back surface of the metal portion 11, and a recessed portion 11e is formed on the upper surface of the metal portion 11. The recessed portion 11e is formed directly above the protruding portion 11d, that is, at a position where the protruding portion 11d and the recessed portion 11e overlap in the thickness direction of the metal portion 11. This is because when the metal portion 11 is plated and formed, the metal constituting the metal portion 11 is a master mold including the bottom surface (inner surface) of the recess 20 which is an exposed region not covered by the second resist layer 16 of the master mold substrate 10. The protruding portion 11d is formed by plating growth from the surface of the substrate 10 and plating growth of the metal constituting the metal portion 11 in the concave portion 20, while the metal located directly above the protruding portion 11d (recessed portion 20). This is because the recessed portion 11e is formed on the surface of the portion 11 following the shape of the recessed portion 20. The protruding portion 11d and the recessed portion 11e are similar, that is, the protruding shape of the protruding portion 11d and the recessed shape of the recessed portion 11e are similar to each other, and the height dimension of the protruding portion 11d and the recessed portion 11e (recessed portion 20). The depth dimension of is in the relationship of the height dimension of the protruding portion 11d ≧ the depth dimension of the recessed portion 11e (recessed portion 20).

続いて、所望の形状の金属部１１が得られたら、金属部１１（電極部１１ｂ）の表面に表面金属層１３を形成する（図５（Ｂ）参照）。具体的には、金属部１１（電極部１１ｂ）の表面に、１〜１０μｍ厚の銀の表面金属層１３をめっき形成している。なお、表面金属層１３をめっき形成する際に、例えば金属部１１がニッケルからなり、表面金属層１３が密着形成しにくい場合には、表面金属層１３のめっきの前にあらかじめ金属部１１表面に下地めっき（銅ストライク、ニッケルストライク、銀ストライク、又は金ストライク）を行い、表面金属層１３の金属部１１への密着性を高めることが望ましい。 Subsequently, when the metal portion 11 having a desired shape is obtained, the surface metal layer 13 is formed on the surface of the metal portion 11 (electrode portion 11b) (see FIG. 5B). Specifically, a silver surface metal layer 13 having a thickness of 1 to 10 μm is plated on the surface of the metal portion 11 (electrode portion 11b). When the surface metal layer 13 is plated and formed, for example, when the metal portion 11 is made of nickel and the surface metal layer 13 is difficult to form in close contact with the surface metal layer 13, the surface of the metal portion 11 is formed in advance before the surface metal layer 13 is plated. It is desirable to perform base plating (copper strike, nickel strike, silver strike, or gold strike) to improve the adhesion of the surface metal layer 13 to the metal portion 11.

続いて、母型基板１０に形成された第二レジスト層１６を除去（溶解除去、膨潤除去）することで、母型基板１０に金属部１１（電極部１１ｂ）が形成された半導体装置用基板が得られる（図５（Ｃ）参照）。係る金属部１１は、母型基板１０表面において、一又は複数配置される電極部１１ｂを一つの単位として、製造する半導体装置の数だけ多数整列状態で並べられた形態で形成されることとなり、本実施形態では、６つの電極部１１ｂを一つの単位としている。 Subsequently, the second resist layer 16 formed on the master substrate 10 is removed (dissolution removal, swelling removal) to form a metal portion 11 (electrode portion 11b) on the master substrate 10 for a semiconductor device substrate. Is obtained (see FIG. 5 (C)). The metal portion 11 is formed on the surface of the master substrate 10 in a form in which one or a plurality of electrode portions 11b are arranged in an aligned state as many as the number of semiconductor devices to be manufactured, with one or a plurality of electrode portions 11b as one unit. In the present embodiment, the six electrode portions 11b are used as one unit.

なお、母型基板１０の表面側には第一レジスト層１２や第二レジスト層１６を形成するが、母型基板１０の裏面側にもレジスト層を形成しても良い。裏面側のレジスト層は、硬化状態でエッチング液とメッキ液への耐性のある材質で、且つ不要となったら容易に溶解除去可能なレジスト材、例えば、厚さ約５０μｍのアルカリ現像タイプの感光性フィルムレジストを熱圧着等により配設し、そのままマスクなしに紫外線照射による露光等の処理を経て、裏面全面にわたり硬化形成されるものとすることができる。この裏面側のレジスト層については、レジストに限られるものではなく、例えばカバーフィルムであっても良く、要は耐溶解性・絶縁性を有するものであれば良い。 Although the first resist layer 12 and the second resist layer 16 are formed on the front surface side of the master substrate 10, a resist layer may also be formed on the back surface side of the master substrate 10. The resist layer on the back side is a material that is resistant to the etching solution and plating solution in the cured state, and is a resist material that can be easily dissolved and removed when it is no longer needed, for example, alkali-developed type photosensitive with a thickness of about 50 μm. The film resist can be arranged by thermal pressure bonding or the like, and can be cured and formed over the entire back surface of the film resist through a treatment such as exposure by ultraviolet irradiation without a mask. The resist layer on the back surface side is not limited to the resist, and may be, for example, a cover film, in short, any one having solubility resistance and insulating properties.

次に、得られた半導体装置用基板１を用いた半導体装置の製造について説明すると、まず、半導体装置用基板１における電極部１１ｂ（金属部１１）上に、半導体素子１４を載置して、半導体素子１４の電極とこれに対応する各電極部１１ｂ（金属部１１）とを電気的接続状態とする（図６（Ａ）参照）。この電気的接続は、はんだ付けによって行われる。なお、半導体素子１４を載置する際、半導体素子１４の電極は電極部１１ｂ（金属部１１）の窪み部を避けた位置にて電気的接続することが好ましい。また、本実施形態では、半導体素子１４と電極部１１ｂとの電気的接続をフリップチップ方式で行っているが、もちろん、金、銅等の導電性線材からなるワイヤを用いたワイヤボンディング方式で行っても良い。 Next, the manufacture of the semiconductor device using the obtained semiconductor device substrate 1 will be described. First, the semiconductor element 14 is placed on the electrode portion 11b (metal portion 11) of the semiconductor device substrate 1 and then mounted. The electrodes of the semiconductor element 14 and the corresponding electrode portions 11b (metal portions 11) are electrically connected (see FIG. 6A). This electrical connection is made by soldering. When mounting the semiconductor element 14, it is preferable that the electrodes of the semiconductor element 14 are electrically connected at a position avoiding the recessed portion of the electrode portion 11b (metal portion 11). Further, in the present embodiment, the semiconductor element 14 and the electrode portion 11b are electrically connected by a flip-chip method, but of course, a wire bonding method using a wire made of a conductive wire such as gold or copper is used. You may.

続いて、母型基板１０の表面側を熱硬化性エポキシ樹脂等の封止材１９で封止し、半導体素子１４を外部から隔離した保護状態とする（図６（Ｂ）参照）。詳細には、母型基板１０の表面側を上型となるモールド金型に装着し、母型基板１０に下型の役割を担わせつつ、モールド金型内に封止材１９となるエポキシ樹脂を圧入するという過程で封止が実行され、母型基板１０上では、一つの半導体装置となる複数の電極部１１ｂが多数整列状態のままで一様に封止され、半導体装置が多数つながった状態で現れることとなる。 Subsequently, the surface side of the master substrate 10 is sealed with a sealing material 19 such as a thermosetting epoxy resin to put the semiconductor element 14 in a protected state isolated from the outside (see FIG. 6B). Specifically, an epoxy resin that serves as a sealing material 19 in the mold while mounting the surface side of the master substrate 10 on a mold mold that is an upper mold and allowing the master substrate 10 to play the role of a lower mold. Sealing was executed in the process of press-fitting, and on the master substrate 10, a large number of electrode portions 11b serving as one semiconductor device were uniformly sealed in an aligned state, and a large number of semiconductor devices were connected. It will appear in the state.

続いて、母型基板１０を除去し、各半導体装置の底部に電極部１１ｂ（金属部１１）が露出した状態を得る（図６（Ｃ）参照）。ステンレス製である母型基板１０の除去には、半導体装置側から母型基板１０を物理的に引き剥がして除去する方法を用いる。母型基板１０に強度及び剥離性に優れるステンレスを用いることで、半導体装置側から母型基板１０を引き剥がして速やかに分離除去することができる。 Subsequently, the master substrate 10 is removed to obtain a state in which the electrode portion 11b (metal portion 11) is exposed at the bottom of each semiconductor device (see FIG. 6C). To remove the master substrate 10 made of stainless steel, a method of physically peeling the master substrate 10 from the semiconductor device side to remove it is used. By using stainless steel having excellent strength and peelability for the master substrate 10, the master substrate 10 can be peeled off from the semiconductor device side and quickly separated and removed.

この他、母型基板１０を除去する方法として、母型基板１０をエッチング（溶解）させる方法を用いることもできる。このエッチングの場合、母型基板１０は溶解するが薄膜１７や金属部１１の材質が冒されないような選択エッチング性を有するエッチング液を用いることとなる。溶解させて除去する場合では、半導体装置側に過大な力が加わらないため、母型基板１０の除去に伴う悪影響が生じる確率を小さくできる。母型基板１０をエッチング除去する場合は、耐食性を得るためにも金属部１１の形成に先立って薄膜１７を形成することが望ましい。 In addition, as a method for removing the master substrate 10, a method of etching (melting) the master substrate 10 can also be used. In the case of this etching, an etching solution having selective etching property is used so that the matrix substrate 10 is dissolved but the materials of the thin film 17 and the metal portion 11 are not affected. In the case of melting and removing, since an excessive force is not applied to the semiconductor device side, the probability of adverse effects due to the removal of the master substrate 10 can be reduced. When the base substrate 10 is removed by etching, it is desirable to form the thin film 17 prior to the formation of the metal portion 11 in order to obtain corrosion resistance.

母型基板１０が除去された半導体装置の底部では、封止材１９の裏面側から突出部１１ｄが部分的に突出されるとともに、突出部１１ｄを除く金属部１１の裏面と、封止材１９の裏面とが略同一平面上に位置する状態となっている。母型基板１０の除去後、多数つながった状態の半導体装置を一つ一つ切り離せば、一つの半導体装置７０としての完成品となる。 At the bottom of the semiconductor device from which the master substrate 10 has been removed, the protruding portion 11d partially protrudes from the back surface side of the sealing material 19, and the back surface of the metal portion 11 excluding the protruding portion 11d and the sealing material 19 It is in a state where it is located on substantially the same plane as the back surface of. After removing the master substrate 10, if a large number of connected semiconductor devices are separated one by one, a finished product as one semiconductor device 70 can be obtained.

このように、本実施形態に係る半導体装置用基板１は、母型基板１０上に形成された電極部１１ｂに突出部１１ｄを有することから、この半導体装置用基板１を用いた半導体装置７０の底部において、突出部１１ｄの高さ寸法分だけ封止材１９の裏面から突出形成されることによる配線逃げ構造が得られるので、電極部１１ｂの裏面全体が突出された形態に比べ、所望する実装基板の電極部分や配線部分以外での電極部１１ｂの接触・接合を避けることができ、信頼性に優れた半導体装置を得ることができる。また、この突出部１１ｄは電極部１１ｂ（金属部１１）の一部から部分的に突出形成されたものなので、半導体装置の実装基板への搭載自由度を増すことができる。 As described above, since the semiconductor device substrate 1 according to the present embodiment has the protruding portion 11d on the electrode portion 11b formed on the master substrate 10, the semiconductor device 70 using the semiconductor device substrate 1 Since a wiring escape structure can be obtained by forming a protrusion from the back surface of the sealing material 19 by the height dimension of the projecting portion 11d at the bottom portion, a desired mounting is performed as compared with a form in which the entire back surface of the electrode portion 11b is projected. It is possible to avoid contact / bonding of the electrode portion 11b other than the electrode portion and the wiring portion of the substrate, and it is possible to obtain a semiconductor device having excellent reliability. Further, since the protruding portion 11d is partially projected from a part of the electrode portion 11b (metal portion 11), the degree of freedom of mounting the semiconductor device on the mounting substrate can be increased.

また、半導体装置７０内部において、金属部１１の上端周縁を張出部１１ｃとして略庇状に張り出し形成し、封止材１９による封止状態で張出部１１ｃが封止材１９に囲まれて固定されること（アンカー効果）で、樹脂同士で密着し強固に一体化した封止材１９に張出部１１ｃが食込んで、金属部１１に加わる外力に対する抵抗体の役割を果たすこととなり、母型基板１０にステンレス等を用い、半導体装置側から母型基板１０を物理的に引き剥がして除去する場合など、金属部１１裏面側に装置外装から引離そうとする外力が加わっても、該張出部１１ｃが金属部１１の移動を妨げ、金属部１１の他部分に対するズレ等をなくすことができ、製造時における歩留りを向上させられると共に、半導体装置としての強度を高められ、使用時の耐久性や半導体装置動作の信頼性も高められる。しかも、金属部１１の表面に窪み部１１ｅを有することで、この窪み部１１ｅ内に封止材１９が入り込むことになるので、張出部１１ｃによる食い付き効果と相まって、金属部１１と封止材１９との密着をより強固にでき、半導体装置としての強度を高められ、半導体素子１４の保護をより確実にできる。 Further, inside the semiconductor device 70, the upper end peripheral edge of the metal portion 11 is formed as an overhanging portion 11c in a substantially eaves-like shape, and the overhanging portion 11c is surrounded by the sealing material 19 in a sealed state by the sealing material 19. By being fixed (anchor effect), the overhanging portion 11c bites into the sealing material 19 which is firmly integrated with the resins, and acts as a resistor against an external force applied to the metal portion 11. Even if an external force that attempts to separate the metal part 11 from the exterior of the device is applied to the back side of the metal portion 11, such as when stainless steel or the like is used for the base substrate 10 and the master substrate 10 is physically peeled off from the semiconductor device side to remove it. The overhanging portion 11c hinders the movement of the metal portion 11, can eliminate the deviation of the metal portion 11 with respect to other parts, improve the yield at the time of manufacturing, and increase the strength as a semiconductor device at the time of use. Durability and reliability of semiconductor device operation are also improved. Moreover, since the sealing material 19 enters the recessed portion 11e by having the recessed portion 11e on the surface of the metal portion 11, the sealing material 19 is sealed with the metal portion 11 in combination with the biting effect of the overhanging portion 11c. The adhesion with the material 19 can be further strengthened, the strength as a semiconductor device can be increased, and the protection of the semiconductor element 14 can be more reliably performed.

上記実施形態において、突出部１１ｄの形状としては、丸状、円状、多角状、球体状、錐体状、柱体状が挙げられ、突出部１１ｄと金属部１１（裏面）との境はなだらかに連続する面となるように形成されるのが好ましい。また、上記実施形態において、半導体素子１４は電極部１１ｂ上に搭載しているが、金属部１１として半導体素子搭載部１１ａを設け、この半導体素子搭載部１１ａ上に半導体素子１４を搭載するようにしても良い。なお、金属部１１（半導体素子搭載部１１ａ、電極部１１ｂ）上に半導体素子１４を搭載するための接着材としては、固体状、粘体状、液体状のものがあり、例えば、はんだ、銀ペースト、樹脂ペースト、ダイアタッチフィルムが挙げられる。 In the above embodiment, the shape of the protruding portion 11d includes a round shape, a circular shape, a polygonal shape, a spherical shape, a cone shape, and a pillar shape, and the boundary between the protruding portion 11d and the metal portion 11 (back surface) is It is preferable that the surface is formed so as to be a gently continuous surface. Further, in the above embodiment, the semiconductor element 14 is mounted on the electrode portion 11b, but the semiconductor element mounting portion 11a is provided as the metal portion 11, and the semiconductor element 14 is mounted on the semiconductor element mounting portion 11a. You may. The adhesive material for mounting the semiconductor element 14 on the metal portion 11 (semiconductor element mounting portion 11a, electrode portion 11b) includes solid, viscous, and liquid forms, for example, solder and silver paste. , Resin paste, die attach film and the like.

また、上記実施形態において、図３に示すように、金属部１１（電極部１１ｂ）を直線状に形成することで、半導体装置の底部（封止材１９の裏面）における有効利用面積（金属部１１形成領域を除く領域）を最大限にできるので、実装基板における配線が複雑に配置されていても不具合を起こすおそれを減少させることができる。また、図７に示すように、半導体装置の底部（封止材１９の裏面）において、金属部１１の一端を外周部分に配設し、金属部１１の他端を中心部分に集中するように配設すれば、隣り合う金属部１１の配置間隔を一定にすることができる。係る構成は、半導体素子１４の電極（実装基板の電極）が多数設けられているときに有効である。 Further, in the above embodiment, as shown in FIG. 3, by forming the metal portion 11 (electrode portion 11b) in a linear shape, the effective utilization area (metal portion) on the bottom portion (back surface of the sealing material 19) of the semiconductor device is formed. Since the area excluding the 11 forming area) can be maximized, the possibility of causing a problem can be reduced even if the wiring on the mounting board is complicatedly arranged. Further, as shown in FIG. 7, on the bottom portion (back surface of the sealing material 19) of the semiconductor device, one end of the metal portion 11 is arranged on the outer peripheral portion, and the other end of the metal portion 11 is concentrated on the central portion. If they are arranged, the arrangement interval of the adjacent metal portions 11 can be made constant. Such a configuration is effective when a large number of electrodes (electrodes of a mounting substrate) of the semiconductor element 14 are provided.

１ 半導体装置用基板
１０ 母型基板
１１ 金属部
１１ａ 半導体素子搭載部
１１ｂ 電極部
１１ｃ 張出部
１１ｄ 突出部
１１ｅ 窪み部
１２ 第一レジスト層
１３ 表面金属層
１４ 半導体素子
１５ ワイヤ
１６ 第二レジスト層
１７ 薄膜
１９ 封止材
２０ 凹部
７０ 半導体装置 1 Substrate for semiconductor devices 10 Master substrate 11 Metal part 11a Semiconductor element mounting part 11b Electrode part 11c Overhanging part 11d Protruding part 11e Depression part 12 First resist layer 13 Surface metal layer 14 Semiconductor element 15 Wire 16 Second resist layer 17 Thin film 19 Encapsulant 20 Recess 70 Semiconductor device

Claims (9)

母型基板（１０）に凹部（２０）が形成され、前記凹部（２０）を含む前記母型基板（１０）上に少なくとも電極部（１１ｂ）となる金属部（１１）が形成されており、前記金属部（１１）の母型基板面側には部分的に突出する突出部（１１ｄ）が設けられ、前記突出部（１１ｄ）は、前記凹部（２０）内全体に金属を設けることで形成されており、前記金属部（１１）の母型基板面側とは反対側の面には窪み部（１１ｅ）が設けられ、前記突出部（１１ｄ）の突出形状と前記窪み部（１１ｅ）の窪み形状が相似形であることを特徴とする半導体装置用基板。 A recess (20) is formed in the master substrate (10), and a metal portion (11) to be at least an electrode portion (11b) is formed on the master substrate (10) including the recess (20). A protruding portion (11d) that partially protrudes is provided on the surface side of the master substrate of the metal portion (11), and the protruding portion (11d) is formed by providing metal in the entire recess (20). A recessed portion (11e) is provided on the surface of the metal portion (11) opposite to the surface side of the master substrate, and the protruding shape of the protruding portion (11d) and the recessed portion (11e) are provided. A substrate for a semiconductor device, characterized in that the recessed shape is similar . 前記突出部（１１ｄ）と前記窪み部（１１ｅ）が前記金属部（１１）の厚み方向において重なる位置に設けられていることを特徴とする請求項１に記載の半導体装置用基板。 The substrate for a semiconductor device according to claim 1, wherein the protruding portion (11d) and the recessed portion (11e) are provided at positions where they overlap in the thickness direction of the metal portion (11) . 母型基板（１０）に凹部（２０）が形成され、前記凹部（２０）を含む前記母型基板（１０）上に少なくとも電極部（１１ｂ）となる金属部（１１）が形成されており、前記金属部（１１）の母型基板面側には部分的に突出する突出部（１１ｄ）が設けられ、前記突出部（１１ｄ）は、前記凹部（２０）内全体に金属を設けることで形成されている半導体装置用基板の製造方法であって、A recess (20) is formed in the master substrate (10), and a metal portion (11) to be at least an electrode portion (11b) is formed on the master substrate (10) including the recess (20). A protruding portion (11d) that partially protrudes is provided on the surface side of the master substrate of the metal portion (11), and the protruding portion (11d) is formed by providing metal in the entire recess (20). This is a method for manufacturing substrates for semiconductor devices.
前記母型基板（１０）上に、第一レジスト層（１２）を形成する工程と、A step of forming the first resist layer (12) on the master substrate (10) and
前記母型基板（１０）の前記第一レジスト層（１２）で覆われていない露出領域に、凹部（２０）を形成する工程と、A step of forming a recess (20) in an exposed region of the master substrate (10) not covered by the first resist layer (12), and
前記第一レジスト層（１２）を除去する工程と、The step of removing the first resist layer (12) and
前記母型基板（１０）上に、前記凹部（２０）を含む前記金属部（１１）の形成位置が露出するように第二レジスト層（１６）を形成する工程と、A step of forming a second resist layer (16) on the master substrate (10) so that the formation position of the metal portion (11) including the recess (20) is exposed.
前記母型基板（１０）の前記第二レジスト層（１６）で覆われていない露出領域に、前記金属部（１１）を形成する工程と、A step of forming the metal portion (11) in an exposed region of the master substrate (10) not covered by the second resist layer (16).
前記第二レジスト層（１６）を除去する工程とを有することを特徴とする半導体装置用基板の製造方法。A method for manufacturing a substrate for a semiconductor device, which comprises a step of removing the second resist layer (16). 前記金属部（１１）を形成する工程において、前記母型基板（１０）及び前記凹部（２０）の表面に、前記金属部（１１）をめっき成長させることを特徴とする請求項３に記載の半導体装置用基板の製造方法。 The third aspect of claim 3 , wherein in the step of forming the metal portion (11), the metal portion (11) is plated and grown on the surfaces of the master substrate (10) and the recess (20). A method for manufacturing a substrate for a semiconductor device. 前記金属部（１１）を形成する工程において、前記第二レジスト層（１６）の厚さを越えて前記金属部（１１）をめっき成長させることを特徴とする請求項３または４に記載の半導体装置用基板の製造方法。 The semiconductor according to claim 3 or 4, wherein in the step of forming the metal portion (11), the metal portion (11) is plated and grown beyond the thickness of the second resist layer (16). Manufacturing method of substrate for equipment. 半導体素子（１４）と電気的に接続する電極部（１１ｂ）となる金属部（１１）を有し、前記金属部（１１）上への前記半導体素子（１４）の搭載、前記半導体素子（１４）と前記金属部（１１）との電気的接続、封止材（１９）による封止がなされる半導体装置であって、It has a metal portion (11) that serves as an electrode portion (11b) that is electrically connected to the semiconductor element (14), and the semiconductor element (14) is mounted on the metal portion (11), and the semiconductor element (14) is mounted. ) And the metal portion (11), and the semiconductor device is sealed by the sealing material (19).
前記封止材（１９）の裏面から前記金属部（１１）が露出され、前記金属部（１１）の裏面が前記封止材（１９）の裏面と同一平面となっており、前記金属部（１１）の裏面には金属の突出部（１１ｄ）のみが前記封止材（１９）の裏面より突出形成されていることを特徴とする半導体装置。The metal portion (11) is exposed from the back surface of the sealing material (19), and the back surface of the metal portion (11) is flush with the back surface of the sealing material (19). A semiconductor device characterized in that only a metal protrusion (11d) is formed on the back surface of the sealing material (19) so as to protrude from the back surface of the sealing material (19). 前記金属部（１１）の表面には窪み部（１１ｅ）が設けられていることを特徴とする請求項６に記載の半導体装置。The semiconductor device according to claim 6, wherein a recessed portion (11e) is provided on the surface of the metal portion (11). 前記突出部（１１ｄ）と前記窪み部（１１ｅ）が前記金属部（１１）の厚み方向において重なる位置に設けられていることを特徴とする請求項７に記載の半導体装置。 The semiconductor device according to claim 7, wherein the protruding portion (11d) and the recessed portion (11e) are provided at positions where they overlap in the thickness direction of the metal portion (11) . 前記突出部（１１ｄ）の突出形状と前記窪み部（１１ｅ）の窪み形状が相似形であることを特徴とする請求項７または８に記載の半導体装置。 The semiconductor device according to claim 7 or 8, wherein the protruding shape of the protruding portion (11d) and the recessed shape of the recessed portion (11e) are similar to each other .
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