JP2023164634A - Substrate for semiconductor device, manufacturing method thereof, and semiconductor device - Google Patents

Substrate for semiconductor device, manufacturing method thereof, and semiconductor device Download PDF

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JP2023164634A
JP2023164634A JP2023151911A JP2023151911A JP2023164634A JP 2023164634 A JP2023164634 A JP 2023164634A JP 2023151911 A JP2023151911 A JP 2023151911A JP 2023151911 A JP2023151911 A JP 2023151911A JP 2023164634 A JP2023164634 A JP 2023164634A
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metal
semiconductor device
substrate
protrusion
recess
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佑也 五郎丸
Yuya Goromaru
達也 古賀
Tatsuya Koga
真幸 林田
Masayuki Hayashida
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Maxell Ltd
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Maxell Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

To provide a substrate for a semiconductor device capable of manufacturing a semiconductor device that can be easily and reliably mounted even on a mounting board in which wiring is densely formed, a manufacturing method thereof, and a semiconductor device using the substrate for a semiconductor device.SOLUTION: In a substrate for a semiconductor device, a metal portion 11 that becomes at least an electrode portion 11b is formed on a mother board 10, a partially protruding protrusion 11d is provided on the mother board surface side of the metal portion 11, and a metal film 21 is formed only on the surface of the protrusion. A recess 20 is formed in a formation region of the metal portion 11 on the mother board 10. The metal film 21 is formed on the surface inside the recess 20. The protrusion 11d is made of metal and is formed on the metal film 21 and embedded in the recess 20. The metal portion 11 is formed on the mother board 10 and the protrusion 11d.SELECTED DRAWING: Figure 2

Description

本発明は、基板上にリードが形成された半導体装置用基板、該半導体装置用基板を用いて構成される半導体装置に関する。 The present invention relates to a semiconductor device substrate having leads formed on the substrate, and a semiconductor device configured using the semiconductor device substrate.

ガラエポ基板上に半導体素子を搭載し、半導体素子と外部導出用の端子とを配線接続した上で、半導体素子を含む基板表面を樹脂などの保護材で被覆した旧来の構造の半導体装置は、その構造上、小型化には限界があった。これに対して、半導体素子搭載部分や電極部分となる金属部を形成し、この金属部上に半導体素子を搭載し配線などの処理後、半導体素子や配線などのある金属部の表面側を樹脂などの封止材で封止し、金属部が底部に一部露出した構成とされる半導体装置は、その高さを低くして省スペース化が図れ、チップサイズなど超小型の半導体装置を必要とする分野で利用が進んでいる。 Semiconductor devices have a conventional structure in which a semiconductor element is mounted on a glass epoxy substrate, the semiconductor element and the terminal for external output are connected by wiring, and the surface of the substrate containing the semiconductor element is coated with a protective material such as resin. Due to its structure, there were limits to miniaturization. On the other hand, after forming a metal part that becomes the semiconductor element mounting part and electrode part, mounting the semiconductor element on this metal part and processing wiring etc., the surface side of the metal part where the semiconductor element and wiring etc. are located is covered with resin. Semiconductor devices are encapsulated with a sealing material such as, and the metal part is partially exposed at the bottom, so it is possible to reduce the height to save space, and it is necessary to use ultra-small semiconductor devices such as chip size. Its use is progressing in the following fields.

こうした半導体装置は、主に、導電性を有する母型基板上に半導体素子搭載部分や電極部分となる金属部を、めっき（電鋳）により、半導体装置の所望個数分をまとめて形成し、半導体素子が搭載され配線などの処理を経た金属部の表面側を封止材で封止した後、母型基板のみを除去し、一体にまとまった状態の多数の半導体装置を個別に切り分ける、といった製造過程を経て製造される。このような半導体装置の製造方法の一例として、特許文献１に開示されるものがある。 These semiconductor devices are manufactured by forming the desired number of semiconductor devices by plating (electroforming) metal parts that will serve as semiconductor element mounting parts and electrode parts on a conductive motherboard. A manufacturing process in which the surface side of the metal part on which the element is mounted and has undergone processing such as wiring is sealed with a sealing material, then only the mother board is removed, and a large number of integrated semiconductor devices are cut into individual pieces. Manufactured through a process. An example of a method for manufacturing such a semiconductor device is disclosed in Patent Document 1.

特開２００２－９１９６号公報Japanese Patent Application Publication No. 2002-9196 特開２００４－２１４２６５号公報Japanese Patent Application Publication No. 2004-214265

特許文献１には、半導体素子搭載部分および電極部分が封止材によって樹脂封止され、封止材の裏面よりも若干突出（スタンドオフ）させるように構成した半導体装置が開示されている。このように、半導体素子搭載部分および電極部分の裏面を封止材の裏面から突出させることで、半導体装置を実装基板に実装する際に、半導体装置の電極部分（リード）と実装基板の電極部分（パッド）との接合を良好にすることができる。 Patent Document 1 discloses a semiconductor device in which a semiconductor element mounting portion and an electrode portion are resin-sealed with a sealant and are configured to slightly protrude (standoff) from the back surface of the sealant. In this way, by making the back side of the semiconductor element mounting part and the electrode part protrude from the back side of the sealing material, when the semiconductor device is mounted on the mounting board, the electrode part (lead) of the semiconductor device and the electrode part of the mounting board can be easily separated. (pad) can be bonded well.

しかしながら、近年、電子機器の小型化を実現するために、実装基板の電極部分や配線部分が密集して形成されており、上記半導体装置の構造では、半導体素子搭載部分や電極部分の裏面全体が封止材の裏面から突出しているため、半導体装置の半導体素子搭載部分（ダイパッド）や電極部分（リード）と実装基板の電極部分（パッド）や配線部分が所望せぬ箇所で接触するおそれがある。 However, in recent years, in order to realize the miniaturization of electronic devices, the electrode parts and wiring parts of the mounting board have been formed densely. Because it protrudes from the back side of the encapsulant, there is a risk that the semiconductor element mounting part (die pad) or electrode part (lead) of the semiconductor device may come into contact with the electrode part (pad) or wiring part of the mounting board at an undesired location. .

本発明の目的は、半導体素子搭載部分や電極部分から突出部を部分的に突出させ、配線が密集して形成された実装基板にも容易で信頼性良く実装可能な半導体装置を製造できる半導体装置用基板とその製造方法、並びに、この半導体装置用基板を用いた半導体装置を提供することにある。 An object of the present invention is to provide a semiconductor device in which a protruding portion partially protrudes from a semiconductor element mounting portion or an electrode portion, and a semiconductor device that can be easily and reliably mounted even on a mounting board formed with dense wiring. An object of the present invention is to provide a substrate for semiconductor devices, a method for manufacturing the same, and a semiconductor device using this substrate for semiconductor devices.

本発明に係る半導体装置用基板は、母型基板１０上に少なくとも電極部１１ｂとなる金属部１１が形成され、該金属部１１の母型基板面側には部分的に突出する突出部１１ｄが設けられており、金属部１１の母型基板面側において、少なくとも突出部１１ｄの表面に金属膜２１が形成されていることを特徴とする。 In the semiconductor device substrate according to the present invention, at least a metal portion 11 serving as an electrode portion 11b is formed on a mother substrate 10, and a protrusion portion 11d that partially protrudes from the mother substrate surface side of the metal portion 11. It is characterized in that a metal film 21 is formed on at least the surface of the protruding portion 11d on the mother board surface side of the metal portion 11.

また、金属膜２１は、突出部１１ｄの表面のみに形成されていることを特徴とする。 Further, the metal film 21 is characterized in that it is formed only on the surface of the protrusion 11d.

また、金属部１１の母型基板面側とは反対側の面には窪み部１１ｅが設けられていることを特徴とする。 Further, a feature is that a recessed portion 11e is provided on the surface of the metal portion 11 opposite to the mother board surface side.

また、突出部１１ｄと窪み部１１ｅが金属部１１の厚み方向において重なる位置に設けられていることを特徴とする。 Further, the protruding portion 11d and the recessed portion 11e are provided at positions that overlap in the thickness direction of the metal portion 11.

本発明に係る半導体装置用基板の製造方法は、母型基板１０上に少なくとも電極部１１ｂとなる金属部１１が形成され、金属部１１の母型基板面側には部分的に突出する突出部１１ｄが設けられており、金属部１１の母型基板面側において、少なくとも突出部１１ｄの表面に金属膜２１が形成されている半導体装置用基板の製造方法であって、母型基板１０上に第一レジスト層１２を形成する工程と、母型基板１０の第一レジスト層１２で覆われていない露出領域に凹部２０を形成する工程と、少なくとも凹部２０の表面に金属膜２１を形成する工程と、第一レジスト層１２を除去する工程と、母型基板１０上に第二レジスト層１６を形成する工程と、母型基板１０の第二レジスト層１６で覆われていない露出領域に金属層２２を形成する工程とを有することを特徴とする。 In the method for manufacturing a substrate for a semiconductor device according to the present invention, at least a metal portion 11 serving as an electrode portion 11b is formed on a mother substrate 10, and a protruding portion partially protrudes from the surface of the mother substrate 11 of the metal portion 11. 11d, and a metal film 21 is formed on at least the surface of the protrusion 11d on the motherboard surface side of the metal part 11, the method comprising: a step of forming a first resist layer 12; a step of forming a recess 20 in an exposed area not covered with the first resist layer 12 of the mother substrate 10; and a step of forming a metal film 21 on at least the surface of the recess 20. a step of removing the first resist layer 12; a step of forming a second resist layer 16 on the mother substrate 10; and a step of forming a metal layer on exposed areas of the mother substrate 10 that are not covered with the second resist layer 16. 22.

また、金属膜２１を形成する工程において、金属膜２１は凹部２０表面のみに形成することを特徴とする。さらに、金属層２２を形成する工程において、前記凹部２０内（金属膜２１）表面に金属層２２をめっき成長させることで、金属層２２の表面に窪み部１１ｅが形成されることを特徴とする。 Further, in the step of forming the metal film 21, the metal film 21 is formed only on the surface of the recess 20. Furthermore, in the step of forming the metal layer 22, the metal layer 22 is grown by plating on the surface of the recess 20 (metal film 21), thereby forming a recess 11e on the surface of the metal layer 22. .

本発明に係る半導体装置は、半導体素子１４と、該半導体素子１４と電気的に接続する電極部１１ｂとなる金属部１１とを有し、金属部１１上への半導体素子１４の搭載、半導体素子１４と金属部１１との電気的接続、封止材１９による封止がなされる半導体装置であって、封止材１９の底部から露出する金属部１１の裏面には、部分的に突出する突出部１１ｄが設けられており、少なくとも突出部１１ｄの表面に金属膜２１が形成されていることを特徴とする。 The semiconductor device according to the present invention includes a semiconductor element 14 and a metal part 11 that becomes an electrode part 11b that is electrically connected to the semiconductor element 14. 14 and the metal part 11 and the semiconductor device is sealed with the sealing material 19, and the back surface of the metal part 11 exposed from the bottom of the sealing material 19 has a protrusion that partially projects. A feature is that a portion 11d is provided, and a metal film 21 is formed on at least the surface of the protruding portion 11d.

また、金属膜２１は、突出部１１ｄの表面のみに形成されていることを特徴とする。 Further, the metal film 21 is characterized in that it is formed only on the surface of the protrusion 11d.

また、金属部１１の表面には窪み部１１ｅが設けられていることを特徴とする。 Further, the metal part 11 is characterized in that a recessed part 11e is provided on the surface thereof.

また、突出部１１ｄと窪み部１１ｅが金属部１１の厚み方向において重なる位置に設けられていることを特徴とする。 Further, the protruding portion 11d and the recessed portion 11e are provided at positions that overlap in the thickness direction of the metal portion 11.

本発明によれば、金属部１１の裏面には、部分的に突出形成する突出部１１ｄが設けられているので、係る金属部１１を備えた半導体装置は、電極や配線が密集した実装基板に対しても、容易で的確な実装が可能となる。また、突出部１１ｄの形状や寸法を実装基板の電極に対応して小さく形成せざるを得なくても、金属部１１の表面（表面積）は突出部１１ｄに比べ大きく形成することができ、搭載する半導体素子１４の選択自由度を拡げることができる。さらに、少なくとも金属部１１の裏面には金属膜２１が形成されており、該金属膜２１を突出部１１ｄの表面のみに形成することで、当該半導体装置を実装基板に搭載する際に用いられるはんだを金属部１１の裏面全体に広がるのを抑え、突出部１１ｄ以外の位置で実装基板上の電極や配線との不要な接触・接続を防止できる。 According to the present invention, the protruding portion 11d that partially protrudes is provided on the back surface of the metal portion 11, so that a semiconductor device including such a metal portion 11 can be mounted on a mounting board with dense electrodes and wiring. However, it is also possible to implement it easily and accurately. Further, even if the shape and dimensions of the protruding portion 11d must be made small to correspond to the electrodes of the mounting board, the surface (surface area) of the metal portion 11 can be formed larger than the protruding portion 11d, and mounting The degree of freedom in selecting the semiconductor element 14 to be used can be expanded. Further, a metal film 21 is formed at least on the back surface of the metal part 11, and by forming the metal film 21 only on the surface of the protruding part 11d, solder used when mounting the semiconductor device on a mounting board can be used. It is possible to prevent the metal part 11 from spreading over the entire back surface of the metal part 11, and to prevent unnecessary contact and connection with the electrodes and wiring on the mounting board at positions other than the protruding part 11d.

本発明の第１実施形態に係る半導体装置用基板の部分平面図である。FIG. 1 is a partial plan view of a substrate for a semiconductor device according to a first embodiment of the present invention. 本発明の第１実施形態に係る半導体装置用基板の断面図及び平面図である。1 is a cross-sectional view and a plan view of a semiconductor device substrate according to a first embodiment of the present invention. FIG. 本発明の第１実施形態に係る半導体装置の断面図及び底面図である。1 is a cross-sectional view and a bottom view of a semiconductor device according to a first embodiment of the present invention. FIG. 本発明の第１実施形態に係る半導体装置用基板の製造方法における工程説明図である。FIG. 3 is a process explanatory diagram of a method for manufacturing a semiconductor device substrate according to a first embodiment of the present invention. 本発明の第１実施形態に係る半導体装置用基板の製造方法における工程説明図である。FIG. 3 is a process explanatory diagram of a method for manufacturing a semiconductor device substrate according to a first embodiment of the present invention. 本発明の第１実施形態に係る半導体装置の製造方法における工程説明図である。FIG. 3 is a process explanatory diagram of a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 本発明の他実施形態に係る半導体装置の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. 本発明の他実施形態に係る半導体装置の断面図及び底面図である。FIG. 6 is a cross-sectional view and a bottom view of a semiconductor device according to another embodiment of the present invention.

（第１実施形態）
以下、本発明の第１実施形態に係る半導体装置用基板及び半導体装置について、図１ないし図６に基づいて説明する。本実施形態に係る半導体装置用基板１は、図２に示すように、導電性を有する材質からなる母型基板（基板）１０と、この母型基板１０上に形成された電極部１１ｂとなる金属部１１とを備える構成である。係る基板を用いて半導体装置７０が製造される。 (First embodiment)
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device substrate and a semiconductor device according to a first embodiment of the present invention will be described below with reference to FIGS. 1 to 6. As shown in FIG. 2, the semiconductor device substrate 1 according to the present embodiment includes a mother substrate (substrate) 10 made of a conductive material and an electrode portion 11b formed on the mother substrate 10. This configuration includes a metal part 11. A semiconductor device 70 is manufactured using such a substrate.

母型基板１０は、ステンレス（ＳＵＳ４３０等）やアルミニウム、銅等の導電性の金属板（厚さ約０．１ｍｍ）で形成され、半導体装置の製造工程で除去されるまで、半導体装置用基板１の要部をなすものである。 The mother board 10 is made of a conductive metal plate (approximately 0.1 mm thick) made of stainless steel (SUS430, etc.), aluminum, copper, etc., and is used as the semiconductor device substrate 1 until it is removed in the semiconductor device manufacturing process. It forms the main part of

金属部１１は、めっき形成されるものであり、図１に示すように、母型基板１０表面で、一又は複数配置される状態を一つの単位として、製造する半導体装置の数だけ多数整列状態で並べられた形態で形成されることとなる。 The metal parts 11 are formed by plating, and as shown in FIG. 1, one or more metal parts 11 are arranged on the surface of the mother board 10 as one unit, and as many as the number of semiconductor devices to be manufactured are arranged. It will be formed in an arranged form.

この金属部１１の裏面（母型基板面）には、突出部１１ｄが形成されている。係る突出部１１ｄは、金属部１１の裏面から部分的に突出するように形成されている。また、母型基板面側とは反対側の面である金属部１１の表面、より詳しくは、金属部１１の厚み方向における突出部１１ｄの直上位置に窪み部１１ｅが形成されている。そして、金属部１１の上端部には、庇状に張り出す張出部１１ｃが形成されている。 A protruding portion 11d is formed on the back surface (mother substrate surface) of this metal portion 11. The protruding portion 11d is formed so as to partially protrude from the back surface of the metal portion 11. Further, a recessed portion 11e is formed on the surface of the metal portion 11 that is the surface opposite to the mother board surface side, more specifically, at a position directly above the protrusion portion 11d in the thickness direction of the metal portion 11. A projecting portion 11c projecting like an eave is formed at the upper end of the metal portion 11.

金属部１１は、大部分を金属層２２によって構成されており、この金属層２２は、電解めっきに適した、ニッケルや銅、又はニッケル－コバルト等のニッケル合金で形成されている。この金属層２２の裏面側においては、金属層２２よりもはんだぬれ性の良好な金属、例えば、金や銀、錫、パラジウム、はんだ等の金属膜２１が少なくとも突出部１１ｄの表面に形成され、本実施形態では、突出部１１ｄの表面のみに形成される構成である。これにより、金属部１１の裏面全体にはんだが広がるのを抑えられ、例えば、電極や配線が密集した実装基板に対して、適切な実相が可能となる。このように、金属膜２１は突出部１１ｄの表面のみに形成される構成としているが、突出部１１ｄを含む金属層２２の裏面全体に金属膜２１を形成した場合には、半導体装置実装時のはんだ付けをより確実に行うことができ、エッチングによる母型基板１０の除去の際には、エッチング液による金属層２２の侵食劣化を防ぐ機能を与えることもできる。なお、金属層２２の厚さは２０～１００μｍ程度、金属膜２１の厚さは０．０１～１μｍ程度とするのが好ましい。 The metal part 11 is mostly composed of a metal layer 22, and the metal layer 22 is made of nickel, copper, or a nickel alloy such as nickel-cobalt, which is suitable for electrolytic plating. On the back side of this metal layer 22, a metal film 21 made of a metal with better solderability than the metal layer 22, such as gold, silver, tin, palladium, solder, etc., is formed at least on the surface of the protrusion 11d, In this embodiment, the structure is such that it is formed only on the surface of the protrusion 11d. This prevents the solder from spreading over the entire back surface of the metal part 11, making it possible to perform appropriate actual soldering, for example, on a mounting board with dense electrodes and wiring. In this way, the metal film 21 is formed only on the surface of the protrusion 11d, but if the metal film 21 is formed on the entire back surface of the metal layer 22 including the protrusion 11d, it is possible to Soldering can be performed more reliably, and when the mother board 10 is removed by etching, a function can be provided to prevent corrosion and deterioration of the metal layer 22 caused by the etching solution. Note that the thickness of the metal layer 22 is preferably about 20 to 100 μm, and the thickness of the metal film 21 is preferably about 0.01 to 1 μm.

また、金属層２２の表面には、表面金属層２３が形成されている。この表面金属層２３は、半導体素子１４の電極との接合性に優れる金や銀、パラジウム等からなるめっき層として形成され、母型基板１０ごとのめっきにより金属層２２の表面に所定の厚さ、例えば、金めっきの場合は約０．１～１μｍ、銀めっきの場合は約１～１０μｍの厚さがめっき形成される。 Furthermore, a surface metal layer 23 is formed on the surface of the metal layer 22 . This surface metal layer 23 is formed as a plating layer made of gold, silver, palladium, etc., which has excellent bonding properties with the electrodes of the semiconductor element 14, and is plated on each mother substrate 10 to a predetermined thickness on the surface of the metal layer 22. For example, in the case of gold plating, the thickness is approximately 0.1 to 1 μm, and in the case of silver plating, the thickness is approximately 1 to 10 μm.

そして、この半導体装置用基板１を用いて製造される半導体装置７０は、図３に示すように、半導体装置用基板１から得られる金属部１１に加えて、金属部１１のうちの電極部１１ｂと電気的に接続する半導体素子１４と、半導体素子１４や金属部１１（電極部１１ｂ）の表面側を覆って封止する封止材１９とを備える構成である。 As shown in FIG. 3, a semiconductor device 70 manufactured using this semiconductor device substrate 1 includes, in addition to the metal portion 11 obtained from the semiconductor device substrate 1, an electrode portion 11b of the metal portion 11. The configuration includes a semiconductor element 14 that is electrically connected to the semiconductor element 14, and a sealing material 19 that covers and seals the semiconductor element 14 and the surface side of the metal part 11 (electrode part 11b).

この半導体装置７０では、底部（実装基板対向側）に金属部１１の裏面側が電極や放熱パッド等として露出した状態となり、この露出する金属部１１の裏面から突出部１１ｄが突出形成されるとともに、突出部１１ｄを除く金属部１１の裏面と、装置外装の一部として現れる封止材１９の裏面とが略同一平面上に位置する構成である。半導体装置７０における底部以外の各面は、装置外装をなす封止材１９がそれぞれ現れた状態となっている（図３（Ｂ）参照）。 In this semiconductor device 70, the back side of the metal part 11 is exposed at the bottom (the side facing the mounting board) as an electrode, a heat dissipation pad, etc., and a protrusion 11d is formed to protrude from the exposed back side of the metal part 11. The configuration is such that the back surface of the metal part 11 excluding the protrusion 11d and the back surface of the sealing material 19 appearing as part of the device exterior are located on substantially the same plane. Each surface of the semiconductor device 70 other than the bottom is in a state where the sealing material 19 forming the device exterior is exposed (see FIG. 3(B)).

半導体素子１４は、微細な電子回路が形成されたいわゆるチップであり、半導体素子１４の一面に設けられた電極が電極部１１ｂと直接接合され、半導体素子１４と電極部１１ｂとを電気的に接続することとなる。 The semiconductor element 14 is a so-called chip on which a fine electronic circuit is formed, and an electrode provided on one surface of the semiconductor element 14 is directly bonded to the electrode part 11b, thereby electrically connecting the semiconductor element 14 and the electrode part 11b. I will do it.

封止材１９は、物理的強度の高い熱硬化性エポキシ樹脂等であり、金属部１１や半導体素子１４を覆った状態で封止し、構造的に弱い部分を外部から隔離した保護状態とするものである。なお、半導体素子１４がＬＥＤ等の発光素子の場合、透光性・透明性の材質が用いられる。 The sealing material 19 is a thermosetting epoxy resin or the like with high physical strength, and covers and seals the metal part 11 and the semiconductor element 14 to protect the structurally weak parts from the outside. It is something. Note that when the semiconductor element 14 is a light emitting element such as an LED, a light-transmitting/transparent material is used.

この封止材１９は、十分な物理的強度を有しており、半導体装置７０の外装の一部として十分に内部を保護する機能を果し、母型基板１０を半導体装置側から引き剥がすなど力を加えて物理的に除去する場合にも、割れ等の破損もなく金属部１１との一体化状態を維持することとなる。 This sealing material 19 has sufficient physical strength and functions as a part of the exterior of the semiconductor device 70 to sufficiently protect the inside, and can be used to remove the mother substrate 10 from the semiconductor device side, etc. Even when it is physically removed by applying force, the state of integration with the metal part 11 is maintained without any damage such as cracking.

次に、本実施形態に係る半導体装置用基板の製造方法及び半導体装置用基板を用いた半導体装置の製造方法の各工程について説明する。 Next, each step of the method of manufacturing a semiconductor device substrate and the method of manufacturing a semiconductor device using the semiconductor device substrate according to the present embodiment will be described.

半導体装置用基板の製造工程として、まず、母型基板１０を用意し、この母型基板１０上に金属部１１（電極部１１ｂ）の突出部１１ｄを形成するための凹部２０に対応する第一レジスト層１２を配設する（図４（Ａ）参照）。具体的には、母型基板１０の表面側に感光性レジスト材を配設し、このレジスト材に対して、凹部２０（突出部１１ｄ）の形成位置に対応する所定パターンのマスクフィルムを載せた状態で、紫外線照射部分のレジスト材を硬化する露光、非照射部分のレジスト材を除去する現像等の処理を行い、凹部２０（突出部１１ｄ）の形成位置が露出するように第一レジスト層１２を形成する。第一レジスト層１２は、母型基板１０表面に凹部２０を形成する際に使用するエッチング液に対する耐溶解性を備えた絶縁性材で形成されるものであり、詳しくは、アルカリ現像タイプの感光性レジスト材を母型基板１０に所定の厚さ、例えば５～５０μｍの範囲、本実施形態では２０μｍの厚さとなるようにして密着配設される。 As a manufacturing process for a semiconductor device substrate, first, a mother substrate 10 is prepared, and a first cavity 20 corresponding to the concave portion 20 for forming the protruding portion 11d of the metal portion 11 (electrode portion 11b) is formed on the mother substrate 10. A resist layer 12 is provided (see FIG. 4(A)). Specifically, a photosensitive resist material was disposed on the front surface side of the master substrate 10, and a mask film with a predetermined pattern corresponding to the formation position of the recessed portion 20 (projection portion 11d) was placed on this resist material. In this state, the first resist layer 12 is subjected to treatments such as exposure to harden the resist material in the ultraviolet irradiated portions and development to remove the resist material in the non-irradiated portions, so that the formation positions of the recesses 20 (projections 11d) are exposed. form. The first resist layer 12 is formed of an insulating material that is resistant to dissolution in the etching solution used when forming the recesses 20 on the surface of the mother substrate 10. A resist material is closely attached to the master substrate 10 to a predetermined thickness, for example in the range of 5 to 50 μm, and in this embodiment, 20 μm.

続いて、母型基板１０の第一レジスト層１２から露出する領域に凹部２０を形成する（図４（Ｂ）参照）。具体的には、母型基板１０の表面側のうち第一レジスト層１２で覆われていない露出領域に対して、エッチングを施すことで凹部２０を形成する。凹部２０の形状としては、円形や多角形などが考えられ、凹部２０の深さは５～５０μｍが望ましい。なお、凹部２０の形成方法としては、エッチングに限らず、レーザー加工やブラスト処理によって形成しても良い。 Subsequently, a recess 20 is formed in a region of the mother substrate 10 exposed from the first resist layer 12 (see FIG. 4(B)). Specifically, the recess 20 is formed by etching an exposed region of the front surface of the mother substrate 10 that is not covered with the first resist layer 12 . The shape of the recess 20 may be circular or polygonal, and the depth of the recess 20 is preferably 5 to 50 μm. Note that the method for forming the recesses 20 is not limited to etching, and may be formed by laser processing or blasting.

続いて、凹部２０領域にめっき前処理を適宜施したあとに、金属膜２１をめっき形成し、母型基板１０に形成された第一レジスト層１２を除去（溶解除去、膨潤除去）することで、凹部２０表面に金属膜２１が形成された母型基板１０を得る（図４（Ｃ）参照）。めっき前処理としては、脱脂、酸浸漬、化学エッチング、電解処理、活性化処理、ストライクめっきなどが挙げられ、本実施形態では、ステンレス製の母型基板１０の凹部２０領域に対して、化学エッチングを施したあと、０．０１～１μｍ厚の金の金属膜２１をめっき成長させている。ここで、金属膜２１を構成する金属を凹部２０が埋まるまでめっきすることによって、突出部１１ｄを形成することも可能である。 Subsequently, after suitably performing plating pre-treatment on the concave portion 20 region, a metal film 21 is formed by plating, and the first resist layer 12 formed on the mother mold substrate 10 is removed (dissolution removal, swelling removal). , a master substrate 10 having a metal film 21 formed on the surface of the recess 20 is obtained (see FIG. 4C). Examples of pre-plating treatment include degreasing, acid immersion, chemical etching, electrolytic treatment, activation treatment, strike plating, etc. In this embodiment, chemical etching is applied to the concave portion 20 region of the stainless steel mother substrate 10. After this, a gold metal film 21 with a thickness of 0.01 to 1 μm is grown by plating. Here, it is also possible to form the protrusion 11d by plating the metal constituting the metal film 21 until the recess 20 is filled.

続いて、この母型基板１０上に金属部１１（電極部１１ｂ）を形成するための第二レジスト層１６を配設する（図５（Ａ）参照）。具体的には、母型基板１０の表面側に感光性レジスト材を配設し、このレジスト材に対して、金属部１１（電極部１１ｂ）の形成位置に対応する所定パターンのマスクフィルムを載せた状態で、紫外線照射部分のレジスト材を硬化する露光、非照射部分のレジスト材を除去する現像等の処理を行い、凹部２０（金属膜２１）を含む金属部１１（電極部１１ｂ）の形成位置が露出するように第二レジスト層１６を形成する。第二レジスト層１６は、金属層２２や表面金属層２３を形成する際に使用するめっき液に対する耐溶解性を備えた絶縁性材で形成されるものであり、詳しくは、アルカリ現像タイプの感光性レジスト材を母型基板１０に所定の厚さ、例えば１０～８０μｍの範囲、本実施形態では５０μｍの厚さとなるようにして密着配設される。なお、第一レジスト層１２及び第二レジスト層１６については、感光性レジストに限られるものではなく、エッチング液やめっき液に対し変質せず強度の高い塗膜が得られる塗料を、母型基板１０上における凹部２０並びに金属部１１の配置部分が露出されるように、電着塗装等により必要な塗膜厚さとなるように塗装して形成することもできる。 Subsequently, a second resist layer 16 for forming the metal portion 11 (electrode portion 11b) is provided on the mother substrate 10 (see FIG. 5(A)). Specifically, a photosensitive resist material is provided on the front surface side of the mother board 10, and a mask film with a predetermined pattern corresponding to the formation position of the metal part 11 (electrode part 11b) is placed on this resist material. In this state, the metal part 11 (electrode part 11b) including the recessed part 20 (metal film 21) is formed by performing treatments such as exposure to harden the resist material in the ultraviolet irradiated part and development to remove the resist material in the non-irradiated part. A second resist layer 16 is formed so that the positions are exposed. The second resist layer 16 is made of an insulating material that is resistant to dissolution in the plating solution used when forming the metal layer 22 and the surface metal layer 23. A resist material is closely attached to the mother mold substrate 10 to a predetermined thickness, for example, in the range of 10 to 80 μm, and in this embodiment, 50 μm. Note that the first resist layer 12 and the second resist layer 16 are not limited to photosensitive resists, and paints that do not change in quality with etching solutions or plating solutions and can provide a strong coating film can be used on the mother substrate. It can also be formed by electro-deposition coating or the like to a required thickness so that the concave portion 20 and the metal portion 11 are exposed.

続いて、母型基板１０の第二レジスト層１６から露出する領域に金属部１１（電極部１１ｂ）を形成する（図５（Ｂ）参照）。具体的には、まず、母型基板１０の表面側のうち第二レジスト層１６で覆われていない露出領域において、少なくとも金属膜２１形成領域を除く領域に対して、上述のめっき前処理を適宜施し、そのあと、金属膜２１を含む母型基板１０上に、めっき（電鋳）により金属層２２を形成しており、本実施形態では、化学エッチングを施した後、７０μｍ厚のニッケル－コバルトの金属層２２を形成している。ここで、めっき前処理は、母型基板１０や金属膜２１、金属層２２の材質によって、取捨選択して行うものであり、その中の化学エッチングとは、対象物（母型基板１０）自体を溶解して、その表面の酸化被膜（不活性膜）を除去するものであり、対象物の表面は粗面となる。また、金属膜２１の形成は、半導体装置のはんだ付け対策を目的とする場合、金属層２２を形成する前に限られるものではなく、半導体装置７０の完成後（母型基板１０除去後）に行っても良く、例えば、半導体装置７０の完成後（母型基板１０除去後）に、該半導体装置７０（封止材１９）の裏面から露出する突出部１１ｄを除く領域の一部または全体に絶縁材を形成し、突出部１１ｄの表面にめっきにより金属膜２１を形成するようにしても良い。この時、金属膜２１が形成された突出部１１ｄの高さ寸法は、絶縁材の厚さ寸法以上、好ましくは、絶縁材の厚さ寸法より大きく形成するのが良い。また、絶縁材は除去せずに形成したままでも良い。 Subsequently, a metal portion 11 (electrode portion 11b) is formed in a region of the mother substrate 10 exposed from the second resist layer 16 (see FIG. 5(B)). Specifically, first, the above-mentioned pre-plating treatment is applied to at least the exposed area not covered with the second resist layer 16 on the surface side of the mother substrate 10 except for the area where the metal film 21 is formed. After that, a metal layer 22 is formed by plating (electroforming) on the master substrate 10 including the metal film 21. In this embodiment, after chemical etching, a 70 μm thick nickel-cobalt layer is formed. A metal layer 22 is formed. Here, the plating pretreatment is selectively performed depending on the materials of the mother substrate 10, the metal film 21, and the metal layer 22. Among these, chemical etching refers to the process for removing the target object (the mother substrate 10) itself. The oxide film (inactive film) on the surface of the object is removed by dissolving it, and the surface of the object becomes rough. Further, when the purpose is to prevent soldering of a semiconductor device, the formation of the metal film 21 is not limited to before forming the metal layer 22, but may be formed after the completion of the semiconductor device 70 (after removal of the motherboard 10). For example, after the semiconductor device 70 is completed (after the mother substrate 10 is removed), part or all of the area excluding the protruding portion 11d exposed from the back surface of the semiconductor device 70 (sealing material 19) may be An insulating material may be formed, and the metal film 21 may be formed by plating on the surface of the protrusion 11d. At this time, the height of the protrusion 11d on which the metal film 21 is formed is preferably larger than the thickness of the insulating material, preferably larger than the thickness of the insulating material. Further, the insulating material may be left as it is formed without being removed.

また、金属層２２を形成する際に、第二レジスト層１６の厚さを越えてめっき成長させることで、金属部１１（金属層２２）の上端部に張出部１１ｃが形成される。この張出部１１ｃが存在することにより、半導体装置の製造工程において、封止材１９で封止する際に、封止材１９が張出部１１ｃにくい込み状に位置した状態で硬化されるため、金属部１１及び封止材１９から母型基板１０を引き剥がし除去する場合でも、封止材１９と張出部１１ｃとの食い付き効果により、金属部１１は封止材１９内に確実に残留し、母型基板１０とともにくっついて引き離されることはなく、金属部１１のズレや欠落等を防止することができる。なお、金属層２２を形成する際に、第二レジスト層１６の厚さを越えない範囲でめっき成長すれば、上端部に張出部のないストレート状の金属層２２（金属部１１）を得ることができる。 Further, when forming the metal layer 22, by growing the metal layer 22 by plating beyond the thickness of the second resist layer 16, a projecting portion 11c is formed at the upper end of the metal portion 11 (metal layer 22). Due to the presence of the overhanging portion 11c, when sealing with the encapsulant 19 is performed in the manufacturing process of a semiconductor device, the encapsulant 19 is hardened in a state where it is embedded in the overhanging portion 11c. Even when the mother board 10 is peeled off and removed from the metal part 11 and the sealing material 19, the metal part 11 is reliably inserted into the sealing material 19 due to the biting effect of the sealing material 19 and the overhanging part 11c. The metal part 11 remains, sticks together with the mother board 10, and is not separated, thereby preventing the metal part 11 from shifting or missing. Note that when forming the metal layer 22, if the plating is grown within a range that does not exceed the thickness of the second resist layer 16, a straight metal layer 22 (metal part 11) without an overhang at the upper end can be obtained. be able to.

また、金属部１１の裏面（実装基板対向面）には、この裏面の一部から部分的に突出する突出部１１ｄが形成されており、金属部１１の上面には窪み部１１ｅが形成されている。この突出部１１ｄと窪み部１１ｅの位置関係は、窪み部１１ｅが突出部１１ｄの直上、つまり、突出部１１ｄと窪み部１１ｅは、金属部１１の厚み方向（平面視）において重なる位置に形成されている。これは、金属部１１をめっき形成する際、金属部１１を構成する金属層２２は、第二レジスト層１６で覆われていない露出領域である、凹部２０内面を含む母型基板１０の表面からめっき成長されるものであり、こうして金属層２２がめっき成長されることで凹部２０内（金属膜２１表面）に突出部１１ｄが形成される一方で、突出部１１ｄ（凹部２０）の直上に位置する金属層２２の表面においては、凹部２０の形状に倣って窪み部１１ｅが形成されることによるものである。このように、金属部１１の表面および裏面において、突出部１１ｄと窪み部１１ｅが対向して形成され、封止材１９として透光性・透明性の材質を用いることで、半導体装置を実装基板に実装する際に、平面視でも突出部１１ｄの位置を確認（予測）できるので、半導体装置の実装をより簡易的に行うことができる。なお、突出部１１ｄと窪み部１１ｅは相似、つまり、突出部１１ｄの突出形状と窪み部１１ｅの窪み形状が相似形となっており、突出部１１ｄの高さ寸法及び窪み部１１ｅの深さ寸法は、凹部２０の形状・寸法に起因し、突出部１１ｄの高さ寸法≧窪み部１１ｅの深さ寸法の関係にある。 Further, on the back surface of the metal part 11 (the surface facing the mounting board), a protruding part 11d that partially protrudes from a part of this back surface is formed, and a recessed part 11e is formed on the top surface of the metal part 11. There is. The positional relationship between the protruding portion 11d and the recessed portion 11e is such that the recessed portion 11e is formed directly above the protruding portion 11d, that is, the protruding portion 11d and the recessed portion 11e are formed at a position where they overlap in the thickness direction (plan view) of the metal portion 11. ing. This is because when forming the metal part 11 by plating, the metal layer 22 constituting the metal part 11 is removed from the surface of the mother substrate 10 including the inner surface of the recess 20, which is an exposed area not covered with the second resist layer 16. By growing the metal layer 22 by plating, a protrusion 11d is formed inside the recess 20 (on the surface of the metal film 21), while a protrusion 11d is formed directly above the protrusion 11d (recess 20). This is because a recessed portion 11e is formed on the surface of the metal layer 22, following the shape of the recessed portion 20. In this way, the protruding part 11d and the recessed part 11e are formed to face each other on the front and back surfaces of the metal part 11, and by using a translucent/transparent material as the sealing material 19, the semiconductor device can be mounted on the mounting board. When mounting the semiconductor device, the position of the protruding portion 11d can be confirmed (predicted) even in a plan view, so that the semiconductor device can be mounted more easily. Note that the protrusion 11d and the recess 11e are similar, that is, the protrusion shape of the protrusion 11d and the recess shape of the recess 11e are similar, and the height dimension of the protrusion 11d and the depth dimension of the recess 11e are similar. is due to the shape and dimensions of the recess 20, and is in the relationship: height dimension of the protrusion 11d≧depth dimension of the depression 11e.

続いて、所望形状の金属層２２（金属部１１）が得られたら、金属層２２の表面に表面金属層２３を形成する（図５（Ｂ）参照）。具体的には、金属層２２の表面に、１～１０μｍ厚の銀の表面金属層２３をめっき形成している。なお、表面金属層２３をめっき形成する際において、金属層２２がニッケル系金属からなり、表面金属層２３が密着形成しにくい場合には、表面金属層２３をめっき形成する前にあらかじめ金属層２２の表面に下地めっき（銅ストライク、ニッケルストライク、銀ストライク、又は金ストライクなど）を行い、表面金属層２３の金属層２２への密着性を高めることが望ましい。 Subsequently, after obtaining the metal layer 22 (metal portion 11) having a desired shape, a surface metal layer 23 is formed on the surface of the metal layer 22 (see FIG. 5(B)). Specifically, the surface of the metal layer 22 is plated with a silver surface metal layer 23 having a thickness of 1 to 10 μm. In addition, when forming the surface metal layer 23 by plating, if the metal layer 22 is made of a nickel-based metal and it is difficult to form the surface metal layer 23 in close contact with the surface metal layer 23, the metal layer 22 may be plated before forming the surface metal layer 23 by plating. It is desirable to perform base plating (copper strike, nickel strike, silver strike, gold strike, etc.) on the surface of the metal layer 23 to improve the adhesion of the surface metal layer 23 to the metal layer 22.

続いて、母型基板１０に形成された第二レジスト層１６を除去（溶解除去、膨潤除去）することで、母型基板１０に金属部１１（電極部１１ｂ）が形成された半導体装置用基板が得られる（図５（Ｃ）参照）。係る金属部１１は、母型基板１０表面において、一又は複数配置される電極部１１ｂを一つの単位として、製造する半導体装置の数だけ多数整列状態で並べられた形態で形成されることとなり、本実施形態では、６つの電極部１１ｂを一つの単位としている。 Subsequently, the second resist layer 16 formed on the mother substrate 10 is removed (dissolved, removed by swelling), thereby producing a semiconductor device substrate in which the metal portion 11 (electrode portion 11b) is formed on the mother substrate 10. is obtained (see FIG. 5(C)). Such metal parts 11 are formed on the surface of the mother substrate 10 in a form in which one or more electrode parts 11b are arranged as one unit, and a number of metal parts 11 are arranged in an array corresponding to the number of semiconductor devices to be manufactured. In this embodiment, six electrode parts 11b are used as one unit.

なお、母型基板１０の表面側には第一レジスト層１２や第二レジスト層１６を形成しているが、母型基板１０の裏面側にもレジスト層を形成しても良い。裏面側のレジスト層は、硬化状態でエッチング液とめっき液への耐性のある材質で、且つ不要となったら容易に除去可能なレジスト材、例えば、厚さ約５０μｍのアルカリ現像タイプの感光性フィルムレジストを熱圧着等により配設し、そのままマスクなしに紫外線照射による露光等の処理を経て、裏面全面にわたり形成することができる。この裏面側のレジスト層については、レジストに限られるものではなく、例えばカバーフィルムであっても良く、要は耐溶解性・絶縁性を有するものであれば良い。 Although the first resist layer 12 and the second resist layer 16 are formed on the front side of the mother substrate 10, a resist layer may also be formed on the back side of the mother substrate 10. The resist layer on the back side is made of a material that is resistant to etching solutions and plating solutions when cured, and can be easily removed when no longer needed, such as an alkali-developable photosensitive film with a thickness of approximately 50 μm. The resist can be disposed by thermocompression bonding or the like, and then subjected to a treatment such as exposure to ultraviolet rays without a mask to form the entire back surface. The resist layer on the back side is not limited to a resist, and may be a cover film, for example, as long as it has dissolution resistance and insulation properties.

次に、得られた半導体装置用基板１を用いた半導体装置の製造について説明すると、まず、半導体装置用基板１における金属部１１（電極部１１ｂ）上に、半導体素子１４を載置して、半導体素子１４の電極とこれに対応する各電極部１１ｂとを電気的接続状態とする（図６（Ａ）参照）。この電気的接続は、はんだ付けによって行われる。なお、半導体素子１４を載置する際、平面視で半導体素子１４の電極が窪み部１１ｅと重ならないように、半導体素子１４の電極を金属部１１（電極部１１ｂ）の窪み部１１ｅを避けた位置に載置・接続するのが好ましい。また、本実施形態では、半導体素子１４と電極部１１ｂとの電気的接続をフリップチップ方式で行っているが、もちろん、金、銅等の導電性線材からなるワイヤ１５を用いたワイヤボンディング方式で行っても良い（図７参照）。 Next, manufacturing of a semiconductor device using the obtained semiconductor device substrate 1 will be explained. First, the semiconductor element 14 is placed on the metal part 11 (electrode part 11b) of the semiconductor device substrate 1, The electrodes of the semiconductor element 14 and the corresponding electrode portions 11b are electrically connected (see FIG. 6(A)). This electrical connection is made by soldering. Note that when mounting the semiconductor element 14, the electrodes of the semiconductor element 14 were placed avoiding the recessed part 11e of the metal part 11 (electrode part 11b) so that the electrodes of the semiconductor element 14 do not overlap with the recessed part 11e in plan view. It is preferable to place and connect it at a certain position. Further, in this embodiment, the electrical connection between the semiconductor element 14 and the electrode portion 11b is performed by a flip-chip method, but of course, a wire bonding method using a wire 15 made of a conductive wire material such as gold or copper may be used. (See Figure 7).

続いて、母型基板１０の表面側を熱硬化性エポキシ樹脂等の封止材１９で封止し、半導体素子１４を外部から隔離した保護状態とする（図６（Ｂ）参照）。詳しくは、母型基板１０の表面側を上型となるモールド金型に装着し、母型基板１０に下型の役割を担わせつつ、モールド金型内に封止材１９となるエポキシ樹脂を圧入するという過程で封止が実行され、母型基板１０上では、一つの半導体装置となる複数の電極部１１ｂが多数整列状態のままで一様に封止され、半導体装置が多数つながった状態で現れることとなる。 Subsequently, the front side of the mother board 10 is sealed with a sealing material 19 such as a thermosetting epoxy resin, and the semiconductor element 14 is placed in a protected state isolated from the outside (see FIG. 6(B)). Specifically, the front side of the mother board 10 is attached to a mold that will serve as an upper mold, and while the mother board 10 is made to play the role of a lower mold, an epoxy resin that will become a sealing material 19 is placed inside the mold. Sealing is performed in the process of press-fitting, and on the mother substrate 10, a plurality of electrode portions 11b forming one semiconductor device are uniformly sealed while remaining aligned, resulting in a state in which a large number of semiconductor devices are connected. It will appear in

続いて、母型基板１０を除去し、各半導体装置の底部に金属部１１（電極部１１ｂ）が露出した状態を得る（図６（Ｃ）参照）。ステンレス製である母型基板１０の除去には、半導体装置側から母型基板１０を物理的に引き剥がして除去する方法を用いる。母型基板１０に強度及び剥離性に優れるステンレスを用いることで、半導体装置側から母型基板１０を引き剥がして速やかに分離除去することができる。 Subsequently, the mother substrate 10 is removed to obtain a state in which the metal portion 11 (electrode portion 11b) is exposed at the bottom of each semiconductor device (see FIG. 6C). To remove the motherboard 10 made of stainless steel, a method is used in which the motherboard 10 is physically peeled off from the semiconductor device side. By using stainless steel, which has excellent strength and removability, for the mother substrate 10, the mother substrate 10 can be peeled off from the semiconductor device side and quickly separated and removed.

この他、母型基板１０を除去する方法として、母型基板１０をエッチング（溶解）させる方法を用いることもできる。このエッチングの場合、母型基板１０は溶解するが金属膜２１や金属層２２の材質が冒されないような選択エッチング性を有するエッチング液を用いることとなる。溶解させて除去する場合では、半導体装置側に過大な力が加わらないため、母型基板１０の除去に伴う悪影響が生じる確率を小さくできる。母型基板１０をエッチング除去する場合は、耐食性を得るためにも金属層２２の形成に先立って金属膜２１を形成することが望ましい。 In addition, as a method for removing the mother substrate 10, a method of etching (dissolving) the mother substrate 10 can also be used. In the case of this etching, an etching solution having a selective etching property that dissolves the mother substrate 10 but does not damage the materials of the metal film 21 and the metal layer 22 is used. In the case of removing by melting, excessive force is not applied to the semiconductor device side, so that the probability that an adverse effect will occur due to the removal of the mother substrate 10 can be reduced. When removing the mother substrate 10 by etching, it is desirable to form the metal film 21 before forming the metal layer 22 in order to obtain corrosion resistance.

母型基板１０が除去された半導体装置７０の底部では、封止材１９の裏面側から突出部１１ｄが部分的に突出されるとともに、突出部１１ｄを除く金属部１１の裏面と、封止材１９の裏面とが略同一平面上に位置する状態となっている。母型基板１０の除去後、多数つながった状態の半導体装置を一つ一つ切り離せば、一つの半導体装置７０としての完成品となる。 At the bottom of the semiconductor device 70 from which the mother substrate 10 has been removed, the protrusion 11d partially protrudes from the back side of the encapsulant 19, and the back surface of the metal part 11 excluding the protrusion 11d and the encapsulant 19 are located on substantially the same plane. After the mother substrate 10 is removed, a large number of connected semiconductor devices are separated one by one to form a completed semiconductor device 70.

このように、本実施形態に係る半導体装置用基板１及びこの半導体装置用基板１を用いた半導体装置７０は、金属部１１（電極部１１ｂ）の裏面に突出部１１ｄを有し、この突出部１１ｄは、金属部１１（電極部１１ｂ）の一部から部分的に突出形成されていることから、突出部１１ｄの高さ寸法分だけ半導体装置７０（封止材１９）の裏面から突出形成された配線逃げ構造が得られることになるので、半導体装置７０（封止材１９）の裏面から電極部１１ｂの裏面全体が突出した形態に比べ、接合を所望する実装基板の電極部分や配線部分以外での電極部１１ｂの接触を避けることができ、信頼性に優れ、実装基板への搭載自由度が増す半導体装置を得ることができる。さらに、突出部１１ｄ表面のみに金属膜２１を形成した構成であるから、はんだによって半導体装置を実装基板へ実装する際に、はんだを突起部１１ｄ表面に留めて金属部１１（電極部１１ｂ）の裏面全体に広がるのが抑えられ、突出部１１ｄ以外の箇所での実装基板上の電極部分や配線部分との接触・接合を可及的に避けることができる。さらに、金属膜２１が形成された突出部１１ｄ表面を除く金属部１１（電極部１１ｂ）の裏面を絶縁材で被覆形成することで、突出部１１ｄ以外での実装基板上の電極部分や配線部分との接触・接合を確実に防ぐことができる。 As described above, the semiconductor device substrate 1 according to the present embodiment and the semiconductor device 70 using this semiconductor device substrate 1 have the protrusion 11d on the back surface of the metal portion 11 (electrode portion 11b), and this protrusion 11d is formed to partially protrude from a part of the metal part 11 (electrode part 11b), and therefore is formed to protrude from the back surface of the semiconductor device 70 (sealing material 19) by the height dimension of the protruding part 11d. Therefore, compared to a configuration in which the entire back surface of the electrode portion 11b protrudes from the back surface of the semiconductor device 70 (sealing material 19), a wire escape structure is obtained in which the entire back surface of the electrode portion 11b is protruded from the back surface of the semiconductor device 70 (sealing material 19). Therefore, it is possible to avoid contact of the electrode portion 11b with the electrode portion 11b, thereby obtaining a semiconductor device with excellent reliability and increased flexibility in mounting onto a mounting board. Furthermore, since the metal film 21 is formed only on the surface of the protrusion 11d, when the semiconductor device is mounted on the mounting board by soldering, the solder is held on the surface of the protrusion 11d and the metal film 21 (electrode portion 11b) is closed. Spreading over the entire back surface is suppressed, and contact/bonding with electrode portions and wiring portions on the mounting board at locations other than the protruding portion 11d can be avoided as much as possible. Furthermore, by coating the back surface of the metal part 11 (electrode part 11b) with an insulating material except for the surface of the protrusion part 11d on which the metal film 21 is formed, the electrode parts and wiring parts on the mounting board other than the protrusion part 11d can be covered. It is possible to reliably prevent contact and bonding with.

また、半導体装置７０内部において、金属部１１の上端周縁を張出部１１ｃとして略庇状に張り出し形成し、封止材１９による封止状態で張出部１１ｃが封止材１９に囲まれて固定されること（アンカー効果）で、樹脂同士で密着し強固に一体化した封止材１９に張出部１１ｃが食込んで、金属部１１に加わる外力に対する抵抗体の役割を果たすこととなり、母型基板１０にステンレス等を用い、半導体装置側から母型基板１０を物理的に引き剥がして除去する場合など、金属部１１裏面側に装置外装から引離そうとする外力が加わっても、該張出部１１ｃが金属部１１の移動を妨げ、金属部１１の他部分に対するズレ等をなくすことができ、製造時における歩留りを向上させられるとともに、半導体装置としての強度を高められ、使用時の耐久性や半導体装置動作の信頼性も高められる。しかも、金属部１１の表面に窪み部１１ｅを有することで、この窪み部１１ｅ内に封止材１９が入り込むことになるので、張出部１１ｃによる食い付き効果と相まって、金属部１１と封止材１９との密着をより強固にでき、半導体装置としての強度を高められ、半導体素子１４の保護をより確実にできる。 Further, inside the semiconductor device 70, the upper end periphery of the metal part 11 is formed to protrude into a substantially eave-like shape as a protruding part 11c, and the protruding part 11c is surrounded by the encapsulant 19 in a sealed state with the encapsulant 19. By being fixed (anchor effect), the overhanging part 11c bites into the sealing material 19, which is tightly integrated with the resins, and plays the role of a resistor against external force applied to the metal part 11. When the mother substrate 10 is made of stainless steel or the like and the mother substrate 10 is physically peeled off and removed from the semiconductor device side, even if an external force is applied to the back side of the metal part 11 to separate it from the device exterior, The projecting portion 11c prevents the movement of the metal portion 11 and eliminates misalignment of the metal portion 11 with respect to other portions, improving the yield during manufacturing, increasing the strength of the semiconductor device, and increasing the strength of the semiconductor device during use. The durability of the semiconductor device and the reliability of the operation of the semiconductor device can also be improved. Moreover, by having the recessed part 11e on the surface of the metal part 11, the sealing material 19 enters into the recessed part 11e, so that, combined with the biting effect of the overhanging part 11c, the sealing material 19 and the metal part 11 are sealed. The adhesion with the material 19 can be made stronger, the strength of the semiconductor device can be increased, and the semiconductor element 14 can be protected more reliably.

上記実施形態において、突出部１１ｄの形状（平面視、断面視含む）としては、丸状、円状、多角状、球体状、半球体状、錐体状、柱体状が挙げられ、突出部１１ｄと金属部１１（裏面）との境はなだらかに連続する面となるように形成されるのが好ましい。また、上記実施形態において、金属部１１（金属膜２１、金属層２２、表面金属層２３）の形成方法としては、電解めっきに限らず、無電解めっき、蒸着、スパッタなどによって形成しても良い。また、上記実施形態において、半導体素子１４を窪み部１１ｅに重なるように載置する、詳しくは、半導体素子１４をフリップチップ方式で接続する場合に、半導体素子１４の電極が窪み部１１ｅの内面にて接続できるように載置しても良く、これにより、窪み部１１ｅの深さ寸法分または半導体素子１４の電極の高さ寸法分を最大に、半導体素子１４の高さ位置を低くでき、パッケージの低背化に寄与できる。なお、半導体素子１４をワイヤボンディング方式で接続する場合に、ワイヤ１５と電極部１１ｂとの接続位置が窪み部１１ｅの内面であっても良い。また、上記実施形態において、半導体素子１４は電極部１１ｂ上に搭載しているが、図７に示すように、金属部１１として半導体素子搭載部１１ａを設け、この半導体素子搭載部１１ａ上に半導体素子１４を搭載するようにしても良い。なお、図７に示す半導体装置において、半導体素子搭載部１１ａの裏面に突出部１１ｄを設けることも可能であり、この突出部１１ｄの表面や半導体素子搭載部１１ａの裏面に金属膜２１を形成しても良い。また、金属部１１（半導体素子搭載部１１ａ、電極部１１ｂ）上に半導体素子１４を搭載するための接着材としては、固体状、粘体状、液体状のものがあり、例えば、はんだ、銀ペースト、樹脂ペースト、ダイアタッチフィルムが挙げられる。 In the above embodiment, the shape of the protrusion 11d (including plan view and cross-sectional view) includes round, circular, polygonal, spherical, hemispherical, conical, and columnar shapes; It is preferable that the boundary between the metal portion 11d and the metal portion 11 (back surface) be formed as a gently continuous surface. Further, in the above embodiment, the method for forming the metal part 11 (metal film 21, metal layer 22, surface metal layer 23) is not limited to electrolytic plating, and may be formed by electroless plating, vapor deposition, sputtering, etc. . Further, in the above embodiment, when the semiconductor element 14 is placed so as to overlap the recess 11e, specifically, when the semiconductor element 14 is connected by a flip-chip method, the electrode of the semiconductor element 14 is placed on the inner surface of the recess 11e. By doing so, the height of the semiconductor element 14 can be lowered by maximizing the depth of the recess 11e or the height of the electrode of the semiconductor element 14, and the package This can contribute to lowering the height of the vehicle. In addition, when connecting the semiconductor element 14 by a wire bonding method, the connection position of the wire 15 and the electrode part 11b may be the inner surface of the recessed part 11e. Further, in the above embodiment, the semiconductor element 14 is mounted on the electrode part 11b, but as shown in FIG. 7, a semiconductor element mounting part 11a is provided as the metal part 11, and the semiconductor The element 14 may also be mounted. In the semiconductor device shown in FIG. 7, it is also possible to provide a protrusion 11d on the back surface of the semiconductor element mounting portion 11a, and the metal film 21 may be formed on the surface of the protrusion 11d or the back surface of the semiconductor element mounting portion 11a. It's okay. Furthermore, adhesive materials for mounting the semiconductor element 14 on the metal part 11 (semiconductor element mounting part 11a, electrode part 11b) include solid, viscous, and liquid materials, such as solder and silver paste. , resin paste, and die attach film.

また、上記実施形態において、図３に示すように、金属部１１（電極部１１ｂ）を直線状に形成することで、半導体装置の底部（封止材１９の裏面）における有効利用面積（金属部１１形成領域を除く領域）を最大限にできるので、実装基板における配線が複雑に配置されていても不具合を起こすおそれを減少させることができる。また、図８に示すように、半導体装置の底部（封止材１９の裏面）において、金属部１１の一端を外周部分に配設し、金属部１１の他端を中心部分に集中するように配設すれば、隣り合う金属部１１の配置間隔を一定にすることができる。係る構成は、半導体素子１４の電極（実装基板の電極）が多数設けられているときに有効である。 In the above embodiment, as shown in FIG. 3, by forming the metal part 11 (electrode part 11b) in a straight line, the effective usable area (metal part 11 (excluding the formation area) can be maximized, so even if the wiring on the mounting board is arranged in a complicated manner, the risk of causing a problem can be reduced. Further, as shown in FIG. 8, at the bottom of the semiconductor device (the back surface of the sealing material 19), one end of the metal part 11 is arranged at the outer peripheral part, and the other end of the metal part 11 is arranged in the central part. If provided, the spacing between adjacent metal parts 11 can be made constant. Such a configuration is effective when a large number of electrodes of the semiconductor element 14 (electrodes of the mounting board) are provided.

１ 半導体装置用基板
１０ 母型基板
１１ 金属部
１１ａ 半導体素子搭載部
１１ｂ 電極部
１１ｃ 張出部
１１ｄ 突出部
１１ｅ 窪み部
１２ 第一レジスト層
１４ 半導体素子
１５ ワイヤ
１６ 第二レジスト層
１９ 封止材
２０ 凹部
２１ 金属膜
２２ 金属層
２３ 表面金属層
７０ 半導体装置 1 Semiconductor device substrate 10 Mother substrate 11 Metal part 11a Semiconductor element mounting part 11b Electrode part 11c Projection part 11d Projection part 11e Recessed part 12 First resist layer 14 Semiconductor element 15 Wire 16 Second resist layer 19 Sealing material 20 Recessed portion 21 Metal film 22 Metal layer 23 Surface metal layer 70 Semiconductor device

Claims (8)

母型基板（１０）上に少なくとも電極部（１１ｂ）となる金属部（１１）が形成されており、前記金属部（１１）の母型基板面側には部分的に突出する突出部（１１ｄ）が設けられ、前記突出部（１１ｄ）の表面のみに金属膜（２１）が形成されてあって、
前記母型基板（１０）上の前記金属部（１１）形成領域に凹部（２０）が形成されており、
前記金属膜（２１）は、前記凹部（２０）内の表面に形成され、
前記突出部（１１ｄ）は、金属で構成され、前記金属膜（２１）上であって前記凹部（２０）内に埋設して形成され、
前記金属部（１１）は、前記母型基板（１０）上および前記突出部（１１ｄ）上に形成されていることを特徴とする半導体装置用基板。 A metal part (11) that becomes at least an electrode part (11b) is formed on the mother board (10), and a protrusion (11d) that partially projects from the mother board surface side of the metal part (11) is formed on the mother board (10). ), and a metal film (21) is formed only on the surface of the protrusion (11d),
A recess (20) is formed in the metal part (11) formation area on the mother substrate (10),
The metal film (21) is formed on the surface inside the recess (20),
The protrusion (11d) is made of metal and is formed on the metal film (21) and embedded in the recess (20),
A substrate for a semiconductor device, wherein the metal portion (11) is formed on the mother substrate (10) and the protrusion (11d). 前記金属部（１１）の母型基板面側とは反対側の面には窪み部（１１ｅ）が設けられていることを特徴とする請求項１に記載の半導体装置用基板。 2. The substrate for a semiconductor device according to claim 1, wherein a recessed portion (11e) is provided on a surface of the metal portion (11) opposite to a mother substrate surface. 前記突出部（１１ｄ）と前記窪み部（１１ｅ）が前記金属部（１１）の厚み方向において重なる位置に設けられていることを特徴とする請求項２に記載の半導体装置用基板。 3. The substrate for a semiconductor device according to claim 2, wherein the protrusion (11d) and the recess (11e) are provided at positions that overlap in the thickness direction of the metal portion (11). 母型基板（１０）上に少なくとも電極部（１１ｂ）となる金属部（１１）が形成されており、前記金属部（１１）の母型基板面側には部分的に突出する突出部（１１ｄ）が設けられ、前記突出部（１１ｄ）の表面のみに金属膜（２１）が形成されてあって、前記母型基板（１０）上の前記金属部（１１）形成領域に凹部（２０）が形成されており、前記金属膜（２１）が前記凹部（２０）内の表面に形成され、前記突出部（１１ｄ）が金属で構成され、前記金属膜（２１）上であって前記凹部（２０）内に埋設して形成され、前記金属部（１１）が前記母型基板（１０）上および前記突出部（１１ｄ）上に形成されている半導体装置用基板の製造方法であって、
前記母型基板（１０）上に、第一レジスト層（１２）を形成する工程と、
前記母型基板（１０）の前記第一レジスト層（１２）で覆われていない露出領域に、凹部（２０）を形成する工程と、
前記凹部（２０）内の表面に、金属膜（２１）を形成する工程と、
前記第一レジスト層（１２）を除去する工程と、
前記母型基板（１０）上に、第二レジスト層（１６）を形成する工程と、
前記凹部（２０）を含む前記母型基板（１０）の前記第二レジスト層（１６）で覆われていない露出領域に、前記金属層（２２）を形成する工程とを有することを特徴とする半導体装置用基板の製造方法。 A metal part (11) that becomes at least an electrode part (11b) is formed on the mother board (10), and a protrusion (11d) that partially projects from the mother board surface side of the metal part (11) is formed on the mother board (10). ), a metal film (21) is formed only on the surface of the protrusion (11d), and a recess (20) is formed in the area where the metal part (11) is formed on the mother substrate (10). The metal film (21) is formed on the surface inside the recess (20), the protrusion (11d) is made of metal, and the metal film (21) is formed on the surface of the recess (20). ), and the metal part (11) is formed on the mother substrate (10) and the protrusion part (11d),
forming a first resist layer (12) on the mother substrate (10);
forming a recess (20) in an exposed area of the mother substrate (10) not covered with the first resist layer (12);
forming a metal film (21) on the surface inside the recess (20);
removing the first resist layer (12);
forming a second resist layer (16) on the mother substrate (10);
forming the metal layer (22) in an exposed area of the mother substrate (10) that is not covered with the second resist layer (16) and includes the recess (20). A method for manufacturing a substrate for a semiconductor device. 前記金属層（２２）を形成する工程において、前記凹部（２０）内に、前記金属層（２２）をめっき成長させることで、前記金属層（２２）の表面に窪み部（１１ｅ）が形成されることを特徴とする請求項４に記載の半導体装置用基板の製造方法。 In the step of forming the metal layer (22), a recess (11e) is formed on the surface of the metal layer (22) by growing the metal layer (22) in the recess (20) by plating. 5. The method of manufacturing a semiconductor device substrate according to claim 4. 請求項１ないし３のいずれかに記載の半導体装置用基板、あるいは請求項４または５に記載の半導体装置用基板の製造方法によって製造された半導体装置用基板を用いて構成される半導体装置であって、
半導体素子（１４）と、前記半導体素子（１４）と電気的に接続する電極部（１１ｂ）となる金属部（１１）とが封止材（１９）によって封止されており、
前記封止材（１９）の底部から露出する前記金属部（１１）の裏面には、金属で構成され、部分的に突出する突出部（１１ｄ）が設けられており、
前記突出部（１１ｄ）を除く金属部（１１）の裏面と前記封止材（１９）の裏面とが略同一平面上に位置し、
前記突出部（１１ｄ）の表面のみに金属膜（２１）が形成されていることを特徴とする半導体装置。 A semiconductor device constructed using a semiconductor device substrate according to any one of claims 1 to 3, or a semiconductor device substrate manufactured by the method for manufacturing a semiconductor device substrate according to claim 4 or 5. hand,
A semiconductor element (14) and a metal part (11) that becomes an electrode part (11b) electrically connected to the semiconductor element (14) are sealed with a sealing material (19),
A protruding part (11d) made of metal and partially protruding is provided on the back surface of the metal part (11) exposed from the bottom of the sealing material (19),
The back surface of the metal part (11) excluding the protruding part (11d) and the back surface of the sealing material (19) are located on substantially the same plane,
A semiconductor device characterized in that a metal film (21) is formed only on the surface of the protrusion (11d). 前記金属部（１１）の表面には窪み部（１１ｅ）が設けられていることを特徴とする請求項６に記載の半導体装置。 7. The semiconductor device according to claim 6, wherein a recessed portion (11e) is provided on the surface of the metal portion (11). 前記突出部（１１ｄ）と前記窪み部（１１ｅ）が前記金属部（１１）の厚み方向において重なる位置に設けられていることを特徴とする請求項７に記載の半導体装置。 8. The semiconductor device according to claim 7, wherein the protruding portion (11d) and the recessed portion (11e) are provided at positions that overlap in the thickness direction of the metal portion (11).
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JP6336298B2 (en) * 2014-03-10 2018-06-06 ローム株式会社 Semiconductor device
JP6806436B2 (en) * 2015-11-19 2021-01-06 マクセルホールディングス株式会社 Substrates for semiconductor devices, their manufacturing methods, and semiconductor devices

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