JP2018046310A - Substrate for semiconductor device, method for manufacturing the substrate, and semiconductor device - Google Patents

Substrate for semiconductor device, method for manufacturing the substrate, and semiconductor device Download PDF

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Publication number
JP2018046310A
JP2018046310A JP2017250422A JP2017250422A JP2018046310A JP 2018046310 A JP2018046310 A JP 2018046310A JP 2017250422 A JP2017250422 A JP 2017250422A JP 2017250422 A JP2017250422 A JP 2017250422A JP 2018046310 A JP2018046310 A JP 2018046310A
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Japan
Prior art keywords
semiconductor device
metal
resist layer
substrate
metal part
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JP2017250422A
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JP6579666B2 (en
Inventor
佑也 五郎丸
Yuya Goromaru
佑也 五郎丸
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Maxell Ltd
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Maxell Holdings Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a substrate for a semiconductor device, in which a recess is disposed in an appropriate position of a metal part so as to optimize structures of various parts of a semiconductor device to be obtained, as well as to efficiently manufacture a semiconductor device.SOLUTION: The substrate for a semiconductor device is to be used for manufacturing a semiconductor device in which a metal part to be at least an electrode part is exposed on a device bottom, and includes a plurality of the metal parts formed on a matrix substrate. As a recess is disposed in at least an electrode part 11b among metal parts 11 formed on a matrix substrate 10, preferable characteristics can be imparted to the structure of a semiconductor device in response to the surface profile of the metal part 11 having a variation by the recess in the manufacture of the semiconductor device using the substrate 1 for a semiconductor device. For example, with an increase in the surface area of the metal part 11 by the recess, a contact area between the metal part 11 and an encapsulation material of the semiconductor device can be increased to enhance the strength in the integration of the metal part 11.SELECTED DRAWING: Figure 8

Description

本発明は、底部に電極等の金属部が露出する形態の半導体装置を製造するのに用いる半
導体装置用基板に関する。 The present invention relates to a semiconductor device substrate used for manufacturing a semiconductor device in which a metal part such as an electrode is exposed at the bottom.

半導体素子支持用の基板上に半導体素子を搭載し、半導体素子と外部導出用の金属端子
とを配線接続した上で、樹脂等の保護材で半導体素子を含む基板全体を被覆した旧来の構
造の半導体装置は、その構造上、小型化には限界があった。これに対し、半導体素子搭載
部分や電極部分となる金属部（リード）を形成し、この金属部上に半導体素子を搭載し配
線等の処理後、半導体素子や配線等のある金属部の表面側を樹脂等の封止材で封止し、金
属部が底部に一部露出した構成とされる半導体装置は、その高さを低くして省スペース化
が図れる他、露出した金属部を通じて半導体素子で生じた熱を外部に放出でき、放熱の面
で優れるといった特長を有しており、チップサイズなど超小型の半導体装置の分野で利用
が進んでいる。 A semiconductor element is mounted on a substrate for supporting a semiconductor element, and the semiconductor element and a metal terminal for lead-out are connected by wiring, and then the entire substrate including the semiconductor element is covered with a protective material such as resin. The semiconductor device has a limit in miniaturization due to its structure. On the other hand, a metal part (lead) to be a semiconductor element mounting part or an electrode part is formed, a semiconductor element is mounted on this metal part, and after processing such as wiring, the surface side of the metal part with the semiconductor element or wiring, etc. The semiconductor device in which the metal portion is partially exposed at the bottom portion can be saved by reducing the height of the semiconductor device and the semiconductor element through the exposed metal portion. The heat generated in the process can be released to the outside, and is excellent in terms of heat dissipation, and is being used in the field of ultra-small semiconductor devices such as chip sizes.

こうした半導体装置は、主に、導電性を有する母型基板上に半導体素子搭載部分や電極
部分となる金属部を、メッキを厚く形成する手法、いわゆる電鋳、により、半導体装置の
所望個数分まとめて形成し、半導体素子が搭載され配線等の処理を経た金属部の表面側を
封止材で封止した後、母型基板のみを除去し、一体にまとまった状態の多数の半導体装置
を個別に切り分ける、といった製造過程を経て製造される。このような半導体装置の製造
方法の一例として、特開２００２−９１９６号公報や特開２００４−２１４２６５号公報
に開示されるものがある。 Such a semiconductor device is mainly composed of a desired number of semiconductor devices by means of so-called electroforming, in which a metal part to be a semiconductor element mounting portion or an electrode portion is formed thickly on a conductive base substrate, so-called electroforming. After forming the semiconductor element and sealing the surface side of the metal part that has undergone processing such as wiring with a sealing material, only the mother board is removed, and a large number of semiconductor devices in an integrated state are individually separated It is manufactured through a manufacturing process such as cutting into two. As an example of a method for manufacturing such a semiconductor device, there are those disclosed in Japanese Patent Application Laid-Open Nos. 2002-9196 and 2004-214265.

特開２００２−９１９６号公報JP 2002-9196 A 特開２００４−２１４２６５号公報JP 2004-214265 A

従来の半導体装置の製造方法は前記特許文献に示される構成となっており、母型基板上
への金属部の形成にあたり、母型基板における金属部の非配置部分にレジスト層をあらか
じめ形成して、金属部が電解メッキの手法により適切な位置に形成されるようにしていた
。この金属部には、メッキによる膜形成に適したニッケル等の金属が使用されており、導
電性や配線用ワイヤの接合性を高めるために、金属部表面には一般に金メッキや銀メッキ
が施されていた。このメッキに対しても、レジスト層が必要箇所以外へのメッキの付着を
防ぐ役割を果していた。そして、このレジスト層を溶剤等で溶解除去した上で、母型基板
とその表面に形成された金属部が、半導体装置用基板として供給された。この半導体装置
用基板を用いて、実際の半導体装置の製造工程において、半導体素子の取付や配線、封止
材による封止等を行うようにしていた。 A conventional method for manufacturing a semiconductor device has a structure shown in the above-mentioned patent document. In forming a metal part on a mother board, a resist layer is formed in advance on a non-arranged part of the metal part on the mother board. The metal part is formed at an appropriate position by the method of electrolytic plating. The metal part is made of a metal such as nickel, which is suitable for film formation by plating. The surface of the metal part is generally plated with gold or silver in order to improve the electrical conductivity or the bonding property of wiring wires. It was. Also for this plating, the resist layer played a role of preventing the adhesion of the plating to portions other than the necessary portions. Then, after the resist layer was dissolved and removed with a solvent or the like, the mother substrate and the metal portion formed on the surface thereof were supplied as a semiconductor device substrate. Using this semiconductor device substrate, in the actual manufacturing process of the semiconductor device, mounting of semiconductor elements, wiring, sealing with a sealing material, and the like are performed.

従来の半導体装置用基板では、母型基板上へのレジスト膜の配置で多様な形状の金属部
を得られるものの、基板上に形成する工程上の関係で、金属部は上面が平面状で一様な厚
さとなる板形状とならざるを得ず、上下方向について立体的な変化に富む形状とすること
が難しいという課題を有していた。 In a conventional semiconductor device substrate, a metal portion having various shapes can be obtained by arranging a resist film on a base substrate. However, the upper surface of the metal portion has a flat surface because of the process of forming on the substrate. It had to have a plate shape with such a thickness, and had a problem that it was difficult to obtain a shape rich in three-dimensional changes in the vertical direction.

また、製造される半導体装置には、これが用いられる電子機器のさらなる小型化を実現
するために、低背化の要求があるが、これまでの構造では、半導体装置からの半導体素子
搭載部分や電極部分の脱落を防止するために、半導体素子搭載部分や電極部分をなす金属
部の薄型化には限界があり、さらに半導体素子自体も所定の強度を与えるために一定の厚
さを確保する必要があり、さらなる薄型化、低背化が困難であるという課題を有していた
。 In addition, semiconductor devices to be manufactured are required to have a low profile in order to realize further downsizing of electronic devices in which they are used. However, in the structure so far, a semiconductor element mounting portion and electrodes from the semiconductor device are required. In order to prevent the parts from falling off, there is a limit to the thinning of the metal part forming the semiconductor element mounting part and the electrode part, and the semiconductor element itself needs to have a certain thickness to give a predetermined strength. In addition, there is a problem that it is difficult to further reduce the thickness and height.

本発明は前記課題を解消するためになされたもので、金属部の適切な箇所に凹部を設け
て、得られる半導体装置各部の構造を最適化できると共に、効率よく半導体装置を製造で
きる、半導体装置用基板と当該基板の製造方法、並びに、この半導体装置用基板を用いて
製造される半導体装置、及びその製造方法を提供することを目的とする。 The present invention has been made to solve the above-described problems. A semiconductor device in which a concave portion is provided at an appropriate location of a metal portion to optimize the structure of each part of the obtained semiconductor device and to efficiently manufacture the semiconductor device. It is an object of the present invention to provide a semiconductor substrate, a method for manufacturing the substrate, a semiconductor device manufactured using the substrate for a semiconductor device, and a method for manufacturing the semiconductor device.

本発明の開示に係る半導体装置用基板は、装置底部に半導体素子搭載部及び電極部とな
る各金属部が露出する半導体装置の製造に用いられ、母型基板上に前記金属部がそれぞれ
形成される半導体装置用基板において、前記金属部が、表面側に凹部を設けられるもので
ある。 The substrate for a semiconductor device according to the disclosure of the present invention is used for manufacturing a semiconductor device in which each metal portion to be a semiconductor element mounting portion and an electrode portion is exposed at the bottom of the device, and the metal portion is formed on a mother substrate. In the semiconductor device substrate, the metal portion is provided with a recess on the surface side.

このように本発明の開示によれば、母型基板上に形成される金属部である半導体素子搭
載部及び／又は電極部に凹部が設けられ、半導体素子搭載部及び／又は電極部における凹
部の下側部分の厚さを小さくすることにより、半導体装置用基板を用いた半導体装置の製
造にあたり、凹部で変化を加えた金属部の表面形状に応じて、半導体装置の構造に好まし
い特長を付与でき、例えば凹部で金属部の表面積が増える分、金属部と半導体装置の封止
材との接触面積を増やして、金属部の一体化の強度を高められる。また、半導体素子搭載
部に凹部を設けるようにすれば、半導体素子の配設位置の設定に柔軟性を与えられ、製造
される半導体装置の構造の自由度を大きくすることができる。さらに、半導体装置同士の
切り離し位置に配置される金属部に凹部を設けるようにすれば、半導体装置の切り離しの
際の金属の切断量を減らすことができ、切断装置の損耗を抑えられる。 Thus, according to the disclosure of the present invention, a recess is provided in the semiconductor element mounting portion and / or the electrode portion, which is a metal portion formed on the matrix substrate, and the recess in the semiconductor element mounting portion and / or the electrode portion is formed. By reducing the thickness of the lower part, it is possible to give favorable features to the structure of the semiconductor device according to the surface shape of the metal part that has been changed in the recess when manufacturing the semiconductor device using the substrate for the semiconductor device. For example, by increasing the surface area of the metal part at the concave part, the contact area between the metal part and the sealing material of the semiconductor device can be increased to increase the strength of the integration of the metal part. Further, if the concave portion is provided in the semiconductor element mounting portion, flexibility in setting the arrangement position of the semiconductor element can be given, and the degree of freedom of the structure of the manufactured semiconductor device can be increased. Furthermore, if the concave portion is provided in the metal portion disposed at the position where the semiconductor devices are separated from each other, the amount of metal cut when the semiconductor device is separated can be reduced, and wear of the cutting device can be suppressed.

また、本発明の開示に係る半導体装置用基板は、必要に応じて、前記凹部が、金属部の
うち少なくとも半導体素子搭載部に、凹部内に半導体素子を挿入し且つ凹部底部に半導体
素子を載置可能な大きさとして設けられるものである。 In the semiconductor device substrate according to the disclosure of the present invention, if necessary, the recess includes at least the semiconductor element mounting portion of the metal portion, the semiconductor element is inserted into the recess, and the semiconductor element is mounted on the bottom of the recess. It is provided as a size that can be placed.

このように本発明の開示によれば、金属部のうち半導体素子搭載部に凹部を設け、この
凹部を半導体装置製造工程で半導体素子を挿入、載置可能な大きさとなるようにすること
により、半導体装置製造の際に、半導体素子を半導体素子搭載部の凹部に挿入配設した場
合、従来のように半導体素子搭載部の上面に搭載される場合と比べて、配設位置を下げる
ことができ、半導体素子上面や、電極部と半導体素子とを接合するワイヤ等の高さも下が
る分、半導体装置の厚さを小さくして製造することができ、半導体装置の低背化を実現で
きる。また、半導体素子の位置が下がって、ワイヤが接合する半導体素子と電極部の各上
面が互いに近付く分、ワイヤ長さも短くすることができ、ワイヤ使用量を削減してコスト
を低減できる。 Thus, according to the disclosure of the present invention, by providing a recess in the semiconductor element mounting portion of the metal portion, and by making the recess into a size capable of inserting and mounting the semiconductor element in the semiconductor device manufacturing process, When a semiconductor device is inserted into the recess of the semiconductor element mounting portion when manufacturing a semiconductor device, the mounting position can be lowered compared to the case where the semiconductor device is mounted on the upper surface of the semiconductor element mounting portion as in the past. Since the height of the upper surface of the semiconductor element and the height of the wire that joins the electrode portion and the semiconductor element also decreases, the thickness of the semiconductor device can be reduced and the semiconductor device can be reduced in height. Further, as the position of the semiconductor element is lowered and the semiconductor element to which the wire is bonded and the upper surfaces of the electrode portions approach each other, the wire length can also be shortened, and the amount of wire used can be reduced and the cost can be reduced.

また、本発明の開示に係る半導体装置用基板は、必要に応じて、前記金属部における電
極部の少なくとも一部が、基板上に設計される半導体装置位置のうち、個々の半導体装置
ごとに切り離す切断加工を経て各半導体装置の側端位置となる切断予定箇所に跨って、前
記切断加工時に切断される配置として基板上に形成され、前記凹部が、切断予定箇所に位
置する電極部に、電極部の切断加工により除去される部位を含んで所定の大きさとして設
けられるものである。 Further, in the semiconductor device substrate according to the disclosure of the present invention, at least a part of the electrode portion in the metal portion is separated for each individual semiconductor device among the positions of the semiconductor device designed on the substrate, as necessary. Formed on the substrate as an arrangement to be cut at the time of the cutting process across the planned cutting position that becomes the side edge position of each semiconductor device through the cutting process, and the recess is formed on the electrode portion located at the planned cutting position. It is provided as a predetermined size including a part to be removed by cutting the part.

このように本発明の開示によれば、金属部のうち、切断予定箇所に位置する電極部に凹
部を設け、半導体装置の製造工程で半導体装置を切り離す切断加工の際に、電極部の凹部
のある位置を切断するようにしていることにより、電極の凹部深さの分、切断位置が下が
り、切断加工における金属の切断量を減らすことができ、切断に伴う切断加工用装置の負
担を減らし、刃部の劣化を抑えられる。また、切断面の近傍で電極部上面は凹部に伴う段
差のある形状となっており、その分電極部上面と半導体装置の封止材とが広く接触するこ
ととなり、半導体装置における電極部の支持強度が向上し、耐久性を高められる。 As described above, according to the disclosure of the present invention, a recess is provided in an electrode portion located in a planned cutting position of a metal portion, and the recess of the electrode portion is cut during the cutting process for separating the semiconductor device in the manufacturing process of the semiconductor device. By cutting a certain position, the cutting position is lowered by the amount of the concave portion of the electrode, the amount of metal cutting in the cutting process can be reduced, and the burden on the cutting processing apparatus accompanying the cutting is reduced. Deterioration of the blade can be suppressed. In addition, the upper surface of the electrode portion has a step with a concave portion in the vicinity of the cut surface, and accordingly, the upper surface of the electrode portion and the sealing material of the semiconductor device are in wide contact with each other, thereby supporting the electrode portion in the semiconductor device. Strength is improved and durability is increased.

また、本発明の開示に係る半導体装置用基板は、必要に応じて、前記金属部が、少なく
とも上側の表面にメッキによる表面金属層を形成される一方、前記凹部に面する表面には
前記表面金属層を形成されないものである。 Further, in the semiconductor device substrate according to the disclosure of the present invention, if necessary, the metal portion is formed with a surface metal layer by plating on at least the upper surface, while the surface facing the recess is the surface. A metal layer is not formed.

このように本発明の開示によれば、金属部の上側の表面に形成する表面金属層を、凹部
周囲には形成しないことにより、凹部下側部分の厚さが、金属部の厚さ以上に厚くならな
いようにして、凹部下側部分の厚さ削減を確実なものとすると共に、半導体装置用基板で
製造された半導体装置の側面に切断に伴って電極部が一部露出する場合でも、凹部のある
位置で切断される電極部の切断面には表面金属層が露出することはなく、表面金属層露出
部を起点とするマイグレーションのような信頼性低下につながる事象の発生を未然に防止
できる。 As described above, according to the disclosure of the present invention, the surface metal layer formed on the upper surface of the metal portion is not formed around the recess, so that the thickness of the lower portion of the recess is greater than the thickness of the metal portion. The thickness of the lower portion of the concave portion is ensured by preventing the thickness from being increased, and the concave portion is formed even if the electrode portion is partially exposed on the side surface of the semiconductor device manufactured by the semiconductor device substrate. The surface metal layer is not exposed on the cut surface of the electrode part cut at a certain position, and it is possible to prevent the occurrence of an event that leads to a decrease in reliability such as migration starting from the surface metal layer exposed part. .

また、本発明の開示に係る半導体装置用基板の製造方法は、母型基板上の所定部位にレ
ジスト層を形成し、レジスト層の非形成部位に、半導体装置の半導体素子搭載部及び電極
部となる各金属部をメッキの手法で形成して、当該金属部が底部に露出する構造の半導体
装置の製造に用いることのできる基板を得る、半導体装置用基板の製造方法において、前
記金属部を、レジスト層を越えない所定高さまで形成する工程と、形成した金属部及び／
又はレジスト層の上側の所定部位に、別のレジスト層を新たに形成する工程と、形成され
た前記別のレジスト層に対し、当該別のレジスト層の非形成部位で金属部の形成を再開し
て、別のレジスト層を越えない所定高さまで金属部を追加で形成する工程と、前記レジス
ト層及び別のレジスト層をそれぞれ除去する工程を備えて、前記別のレジスト層で設定さ
れた所定形状が表面に現れた金属部を得るものである。 Further, in the method for manufacturing a semiconductor device substrate according to the disclosure of the present invention, a resist layer is formed in a predetermined portion on the mother substrate, and a semiconductor element mounting portion and an electrode portion of the semiconductor device are formed in a portion where the resist layer is not formed. In the method for manufacturing a substrate for a semiconductor device, wherein each metal part is formed by a plating method to obtain a substrate that can be used for manufacturing a semiconductor device having a structure in which the metal part is exposed at the bottom. Forming a predetermined height not exceeding the resist layer, the formed metal portion, and / or
Alternatively, a step of newly forming another resist layer at a predetermined portion above the resist layer and the formation of the metal portion at the portion where the other resist layer is not formed with respect to the formed another resist layer are resumed. And a step of additionally forming a metal portion to a predetermined height not exceeding another resist layer, and a step of removing the resist layer and the other resist layer, respectively, and a predetermined shape set by the another resist layer. The metal part which appeared on the surface is obtained.

このように本発明の開示によれば、金属部の形成において別のレジスト層を用いて金属
部の形成領域を一部規制して、レジスト除去後の金属部表面に別のレジスト層に基づく形
状を付与できることにより、金属部の形成範囲をレジスト層だけでなく上側の別のレジス
ト層も併用してより正確に規定して、金属部を基板上により精細な配置とすることができ
ると共に、金属部の構造の自由度が増すこととなり、半導体装置用基板を用いて製造され
る半導体装置を、金属部の構造に基づいて改良できる。 As described above, according to the disclosure of the present invention, the formation of the metal part is partially regulated by using another resist layer, and the shape based on another resist layer is formed on the surface of the metal part after removing the resist. In addition to providing a resist layer as well as another resist layer on the upper side, the metal portion can be more precisely defined, and the metal portion can be arranged more finely on the substrate. The degree of freedom of the structure of the part is increased, and the semiconductor device manufactured using the substrate for a semiconductor device can be improved based on the structure of the metal part.

また、本発明の開示に係る半導体装置用基板の製造方法は、必要に応じて、前記別のレ
ジスト層が、前記中断時点の金属部のうち最終的に半導体素子搭載部となるものの上側所
定部位に形成され、前記別のレジスト層の形成後、金属部の形成再開で、金属部が別のレ
ジスト層の側面に接する部位を伴って形成され、形成終了後、最終的に別のレジスト層を
除去して、金属部の半導体素子搭載部における、別のレジスト層が存在していた部位に、
穴又は溝状の凹部を生じさせるものである。 Also, in the method for manufacturing a substrate for a semiconductor device according to the disclosure of the present invention, if necessary, the other resist layer is an upper predetermined portion of the metal portion at the time of the interruption that finally becomes a semiconductor element mounting portion. After the formation of the another resist layer, the formation of the metal portion is resumed, and the metal portion is formed with a portion in contact with the side surface of the other resist layer. Removed, in the part where another resist layer was present in the semiconductor element mounting part of the metal part,
A hole or a groove-like recess is generated.

このように本発明の開示によれば、別のレジスト層を金属部のうち半導体素子搭載部と
なる部位に配設して、最終的に形成された金属部の半導体素子搭載部に、別のレジスト層
の配置範囲に応じた凹部を生じさせることにより、レジスト形状の設定で自由に凹部を配
置できることに加え、得られた半導体装置用基板を用いて半導体装置を製造する際に、半
導体素子を半導体素子搭載部の凹部に挿入配設した場合、半導体素子の配設位置を下げる
ことができ、半導体素子上面や、電極部と半導体素子とを接合するワイヤ等の高さも下が
る分、半導体装置の厚さを小さくして製造することができ、半導体装置の低背化を実現で
きる。 As described above, according to the disclosure of the present invention, another resist layer is disposed in a portion to be a semiconductor element mounting portion in the metal portion, and the semiconductor element mounting portion of the finally formed metal portion is provided with another resist layer. In addition to being able to freely arrange the recesses by setting the resist shape by generating the recesses according to the arrangement range of the resist layer, when manufacturing the semiconductor device using the obtained semiconductor device substrate, the semiconductor element When the semiconductor element is mounted in the recess of the semiconductor element mounting portion, the placement position of the semiconductor element can be lowered, and the height of the upper surface of the semiconductor element and the wire joining the electrode portion and the semiconductor element are also reduced. The thickness can be reduced and the semiconductor device can be reduced in height.

また、本発明の開示に係る半導体装置用基板の製造方法は、必要に応じて、前記別のレ
ジスト層が、前記中断時点の金属部のうち最終的に電極部となるものの上側所定部位に、
複数の電極部にわたる略線状配置で形成され、前記別のレジスト層の形成後、金属部の形
成再開で、金属部が別のレジスト層の側面に接する部位を伴って形成され、形成終了後、
最終的に別のレジスト層を除去して、金属部の電極部における、別のレジスト層が存在し
ていた部位に、複数の電極部にわたって直列に並ぶ配置となる溝状の凹部をそれぞれ生じ
させるものである。 Further, in the method for manufacturing a substrate for a semiconductor device according to the disclosure of the present invention, if necessary, the another resist layer may be placed on the upper predetermined portion of the metal portion at the time of interruption, which finally becomes the electrode portion.
Formed in a substantially linear arrangement over a plurality of electrode parts, and after the formation of the another resist layer, the formation of the metal part is resumed, and the metal part is formed with a portion in contact with the side surface of the other resist layer. ,
Finally, another resist layer is removed to form groove-like recesses that are arranged in series across the plurality of electrode portions in the portions where the other resist layers existed in the electrode portions of the metal portions. Is.

このように本発明の開示によれば、別のレジスト層を金属部のうち電極部となる部位に
配設して、最終的に形成された金属部の電極部の切断加工対象位置に並んだ凹部を生じさ
せることにより、レジスト形状の設定で所望の凹部を配置できることに加え、得られた半
導体装置用基板を用いて半導体装置を製造する際に、凹部のある電極部を切断するように
して各半導体装置を切り離す場合、電極部の凹部下側の部位が薄くされる分、切断加工の
負荷を小さくすることができ、切断装置の損耗を抑えられる。 As described above, according to the disclosure of the present invention, another resist layer is disposed in a portion to be an electrode portion of the metal portion, and is arranged at a position to be cut in the electrode portion of the finally formed metal portion. In addition to being able to arrange the desired recesses by setting the resist shape by generating the recesses, when manufacturing a semiconductor device using the obtained substrate for a semiconductor device, the electrode part with the recesses is cut. When each semiconductor device is separated, the load on the cutting process can be reduced and the wear of the cutting device can be reduced by reducing the thickness of the portion below the concave portion of the electrode portion.

また、本発明の開示に係る半導体装置は、半導体素子搭載部及び電極部となる各金属部
を有し、当該金属部表面の少なくとも一部にメッキにより表面金属層を形成され、金属部
表面側への半導体素子搭載及び配線、封止材による封止がなされ、装置底部に前記金属部
の裏面側が露出した状態とされる半導体装置において、前記金属部のうち半導体素子搭載
部における表面側に半導体素子より広い大きさの凹部が設けられ、当該凹部に面する表面
には前記表面金属層を形成されない状態とされ、前記凹部が、半導体素子を挿入配置され
、半導体素子ごと封止材により封止されるものである。 In addition, a semiconductor device according to the disclosure of the present invention has a metal part to be a semiconductor element mounting part and an electrode part, and a surface metal layer is formed by plating on at least a part of the surface of the metal part. In the semiconductor device in which the semiconductor element is mounted on the wiring, sealed with a wiring material and a sealing material, and the back side of the metal part is exposed at the bottom of the apparatus, the semiconductor is mounted on the surface side of the semiconductor element mounting part among the metal parts. A recess having a size larger than that of the element is provided, and the surface metal layer is not formed on the surface facing the recess, and the recess is inserted and disposed with the semiconductor element, and the entire semiconductor element is sealed with a sealing material It is what is done.

このように本発明の開示によれば、半導体装置を構成する金属部のうち、半導体素子を
搭載する半導体素子搭載部に凹部が設けられていることで、半導体素子を半導体素子搭載
部の凹部に挿入配設した場合、従来のように半導体素子搭載部の上面に搭載される場合と
比べて、配設位置を下げることができ、半導体素子上面や、電極部と半導体素子とを接合
するワイヤ等の高さも下がる分、半導体装置の厚さを小さくすることができ、半導体装置
の低背化を実現できる。また、半導体素子の位置が下がって、ワイヤが接合する半導体素
子と電極部の各上面が互いに近付く分、ワイヤ長さも短くすることができ、ワイヤ使用量
を削減して半導体装置のコストを低減できる。 As described above, according to the disclosure of the present invention, among the metal portions constituting the semiconductor device, the semiconductor element mounting portion on which the semiconductor element is mounted is provided with the recess, so that the semiconductor element is formed in the recess of the semiconductor element mounting portion. In the case of insertion and arrangement, the arrangement position can be lowered as compared with the case where it is mounted on the upper surface of the semiconductor element mounting portion as in the past, and the upper surface of the semiconductor element, wires for joining the electrode portion and the semiconductor element, etc. Therefore, the thickness of the semiconductor device can be reduced and the height of the semiconductor device can be reduced. In addition, as the position of the semiconductor element is lowered and the semiconductor element to which the wire is joined and the upper surfaces of the electrode portions approach each other, the wire length can be shortened, and the cost of the semiconductor device can be reduced by reducing the amount of wire used. .

また、本発明の開示に係る半導体装置は、半導体素子搭載部及び電極部となる各金属部
を有し、当該金属部表面の少なくとも一部にメッキにより表面金属層を形成され、金属部
表面側への半導体素子搭載及び配線、封止材による封止がなされ、装置底部に前記金属部
の裏面側が露出した状態とされる半導体装置において、少なくともいずれかの側面が、複
数の半導体装置の集合形成状態から個々の半導体装置を切り離す切断加工により生じた切
断面であり、切断加工を受けて切断面の一部として露出した電極部を有し、当該側面に露
出した電極部が、前記切断加工での切断予定箇所に位置する電極部の表面側にあらかじめ
凹部を設けられてなり、当該凹部に面する表面には前記表面金属層を形成されず、前記側
面に露出した電極部の表面が、元の凹部のあった位置の下側部分の断面であり、表面金属
層の断面を一切含まないものである。 In addition, a semiconductor device according to the disclosure of the present invention has a metal part to be a semiconductor element mounting part and an electrode part, and a surface metal layer is formed by plating on at least a part of the surface of the metal part. In the semiconductor device in which the semiconductor element is mounted on the wiring, sealed with a sealing material, and the back side of the metal portion is exposed at the bottom of the device, at least one of the side surfaces is an assembly of a plurality of semiconductor devices It is a cut surface generated by a cutting process for separating individual semiconductor devices from the state, and has an electrode part exposed as a part of the cutting surface after receiving the cutting process, and the electrode part exposed on the side surface is the cutting process. The surface of the electrode part located at the planned cutting position is provided with a recess in advance, the surface facing the recess is not formed with the surface metal layer, the surface of the electrode part exposed on the side surface, A cross section of the lower portion of the position for which the recess is one that does not contain any cross-section of the surface metal layer.

このように本発明の開示によれば、半導体装置を構成する金属部のうち電極部にあらか
じめ凹部が設けられて、凹部を切断加工対象位置とされて個々の半導体装置に切り離され
た際に、端部に電極部の凹部位置の切断面が現れていることにより、電極部の露出部分は
元の凹部の下側にあたる部分となり、表面金属層が現れないこととなり、表面金属層露出
部分を起点とするマイグレーションを未然に防止できる上、切断加工に伴って側端部に位
置する電極部は凹部のある位置とされた分、封止部分との接触面が増えるので強度を高め
られ、半導体装置としての耐久性や信頼性も高められる。 As described above, according to the disclosure of the present invention, when the concave portion is provided in advance in the electrode portion of the metal portion constituting the semiconductor device and the concave portion is set as a cutting processing target position and separated into individual semiconductor devices, Since the cut surface at the concave portion of the electrode portion appears at the end, the exposed portion of the electrode portion becomes a portion below the original concave portion, the surface metal layer does not appear, and the surface metal layer exposed portion is the starting point. In addition to being able to prevent migration, the electrode portion located at the side end portion along with the cutting process has a recessed portion, so that the contact surface with the sealing portion increases, so the strength can be increased, and the semiconductor device As a result, durability and reliability can be improved.

本発明の第１の実施形態に係る半導体装置用基板の要部拡大図である。It is a principal part enlarged view of the board | substrate for semiconductor devices which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置用基板の製造方法におけるレジスト層形成工程説明図である。It is a resist layer formation process explanatory drawing in the manufacturing method of the board | substrate for semiconductor devices which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置用基板の製造方法における最初の金属部形成工程説明図である。FIG. 6 is an explanatory diagram of a first metal part forming step in the method for manufacturing a semiconductor device substrate according to the first embodiment of the present invention. 本発明の第１の実施形態に係る半導体装置用基板の製造方法における第二レジスト層の形成工程説明図である。It is a formation process explanatory view of the 2nd resist layer in the manufacturing method of the substrate for semiconductor devices concerning a 1st embodiment of the present invention. 本発明の第１の実施形態に係る半導体装置用基板の製造方法における後の金属部形成、表面金属層形成、及びレジスト層除去の各工程説明図である。FIG. 5 is an explanatory diagram of each step of subsequent metal part formation, surface metal layer formation, and resist layer removal in the method for manufacturing a semiconductor device substrate according to the first embodiment of the present invention. 本発明の第１の実施形態に係る半導体装置用基板を用いた半導体装置の製造工程説明図である。It is manufacturing process explanatory drawing of the semiconductor device using the board | substrate for semiconductor devices which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の断面図及び底面図である。It is sectional drawing and the bottom view of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置用基板の要部拡大図である。It is a principal part enlarged view of the board | substrate for semiconductor devices which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置用基板の製造方法における最初の金属部形成工程説明図である。It is explanatory drawing of the 1st metal part formation process in the manufacturing method of the board | substrate for semiconductor devices which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置用基板の製造方法における第二レジスト層の形成工程説明図である。It is a formation process explanatory view of the 2nd resist layer in the manufacturing method of the substrate for semiconductor devices concerning a 2nd embodiment of the present invention. 本発明の第２の実施形態に係る半導体装置用基板の製造方法における後の金属部形成、表面金属層形成、及びレジスト層除去の各工程説明図である。It is each process explanatory drawing of the subsequent metal part formation, surface metal layer formation, and resist layer removal in the manufacturing method of the board | substrate for semiconductor devices which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置用基板を用いた半導体装置の製造工程説明図である。It is manufacturing process explanatory drawing of the semiconductor device using the board | substrate for semiconductor devices which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置の底面側斜視図及び断面図である。6A and 6B are a bottom perspective view and a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. 本発明の第３の実施形態に係る半導体装置用基板の製造方法における第二レジスト層の形成工程説明図である。It is a formation process explanatory view of the 2nd resist layer in the manufacturing method of the substrate for semiconductor devices concerning a 3rd embodiment of the present invention. 本発明の第３の実施形態に係る半導体装置用基板の製造方法における後の金属部形成、表面金属層形成、及びレジスト層除去の各工程説明図である。It is each process explanatory drawing of the subsequent metal part formation, surface metal layer formation, and resist layer removal in the manufacturing method of the board | substrate for semiconductor devices which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置用基板による金属部配置間隔の縮小状態説明図である。It is reduction state explanatory drawing of the metal part arrangement | positioning space | interval by the board | substrate for semiconductor devices which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置用基板の他の製造方法における第二レジスト層の形成工程説明図である。It is a formation process explanatory view of the 2nd resist layer in other manufacturing methods of a substrate for semiconductor devices concerning a 3rd embodiment of the present invention. 本発明の第３の実施形態に係る半導体装置用基板の他の製造方法における金属部形成工程説明図である。It is metal part formation process explanatory drawing in the other manufacturing method of the board | substrate for semiconductor devices which concerns on the 3rd Embodiment of this invention. 本発明の第３の実施形態に係る半導体装置用基板の他の製造方法における表面金属層形成及びレジスト層除去の各工程説明図である。It is each process explanatory drawing of surface metal layer formation and the resist layer removal in the other manufacturing method of the board | substrate for semiconductor devices which concerns on the 3rd Embodiment of this invention. 本発明の他の実施形態に係る半導体装置用基板の製造におけるレジスト層除去工程前後の基板状態説明図、及び、半導体装置用基板を用いて得られた半導体装置の概略断面図である。It is the board | substrate state explanatory drawing before and behind the resist layer removal process in manufacture of the board | substrate for semiconductor devices which concerns on other embodiment of this invention, and the schematic sectional drawing of the semiconductor device obtained using the board | substrate for semiconductor devices.

（本発明の第１の実施形態）
以下、本発明の第１の実施形態に係る半導体装置用基板を図１ないし図７に基づいて説
明する。
前記各図において本実施形態に係る半導体装置用基板１は、導電性を有する材質からな
る母型基板１０と、この母型基板１０上に形成され、本基板を用いて製造される半導体装
置７０の半導体素子搭載部１１ａ又は電極部１１ｂとなる金属部１１と、金属部１１表面
にメッキにより形成される表面金属層１３とを備える構成である。 (First embodiment of the present invention)
A semiconductor device substrate according to a first embodiment of the present invention will be described below with reference to FIGS.
In each of the drawings, a semiconductor device substrate 1 according to this embodiment includes a mother substrate 10 made of a conductive material, and a semiconductor device 70 formed on the mother substrate 10 and manufactured using the substrate. The metal part 11 to be the semiconductor element mounting part 11a or the electrode part 11b and the surface metal layer 13 formed by plating on the surface of the metal part 11 are provided.

この半導体装置用基板１を用いて製造される半導体装置７０は、図７に示すように、半
導体装置用基板１から得られる金属部１１及び表面金属層１３に加えて、金属部１１のう
ち半導体素子搭載部１１ａに搭載される半導体素子１４と、この半導体素子１４と金属部
１１のうちの電極部１１ｂとを電気的に接続するワイヤ１５と、半導体素子１４やワイヤ
１５を含む金属部１１の表面側を覆って封止する封止材１９とを備える構成である。 As shown in FIG. 7, the semiconductor device 70 manufactured using the semiconductor device substrate 1 includes a semiconductor portion of the metal portion 11 in addition to the metal portion 11 and the surface metal layer 13 obtained from the semiconductor device substrate 1. The semiconductor element 14 mounted on the element mounting portion 11 a, the wire 15 that electrically connects the semiconductor element 14 and the electrode portion 11 b of the metal portion 11, and the metal portion 11 including the semiconductor element 14 and the wire 15. It is the structure provided with the sealing material 19 which covers and seals the surface side.

この半導体装置７０では、底部に金属部１１の裏面側が電極や放熱パッド等として露出
した状態となり（図７（Ｂ）参照）、この露出する金属部１１の裏面側と、装置外装の一
部として現れる封止材１９の裏面側とが略同一平面上に位置する構成である。半導体装置
７０における底部以外の各面は、装置外装をなす封止材１９のみがそれぞれ現れた状態と
なる。 In this semiconductor device 70, the back surface side of the metal part 11 is exposed as an electrode, a heat dissipation pad or the like at the bottom (see FIG. 7B), and the exposed back surface side of the metal part 11 and a part of the device exterior The back surface side of the sealing material 19 that appears is positioned on substantially the same plane. Each surface other than the bottom of the semiconductor device 70 is in a state where only the sealing material 19 forming the device exterior appears.

前記半導体装置用基板１は、母型基板１０上に金属部１１の非配置部分に対応する第一
レジスト層１２が形成された後、電解メッキで金属部１１を形成され、続いて金属部１１
の凹部に対応する前記レジスト層とは別の第二レジスト層１６が形成された後、電解メッ
キで金属部１１を追加形成され、さらに金属部１１表面にメッキにより表面金属層１３を
形成された後、第一レジスト層１２及び第二レジスト層１６を除去することで製造される
ものである。 In the semiconductor device substrate 1, the first resist layer 12 corresponding to the non-arranged portion of the metal portion 11 is formed on the base substrate 10, and then the metal portion 11 is formed by electrolytic plating.
After the second resist layer 16 different from the resist layer corresponding to the concave portion of the metal layer 11 was formed, the metal part 11 was additionally formed by electrolytic plating, and the surface metal layer 13 was formed on the surface of the metal part 11 by plating. After that, the first resist layer 12 and the second resist layer 16 are removed to manufacture.

また、この半導体装置用基板１を用いた半導体装置製造の際は、この半導体装置用基板
１に対し、金属部１１表面側への半導体素子１４搭載及び配線、封止材１９による封止が
なされ、封止の後、半導体装置部分から母型基板１０を分離除去して半導体装置７０を得
る仕組みである。 Further, when manufacturing the semiconductor device using the semiconductor device substrate 1, the semiconductor device substrate 1 is mounted with the semiconductor element 14 on the surface side of the metal portion 11, wiring, and sealing with the sealing material 19. Then, after the sealing, the mother substrate 10 is separated and removed from the semiconductor device portion to obtain the semiconductor device 70.

前記母型基板１０は、ステンレス材（ＳＵＳ４３０等）やアルミニウム、銅等の導電性
の金属板（厚さ約０．１ｍｍ）で形成され、半導体装置の製造工程で除去されるまで、半
導体装置用基板１の要部をなすものであり、半導体装置用基板製造工程の各段階で、表面
側に第一レジスト層１２、金属部１１が形成され、また裏面側にレジスト層１８が配設さ
れる。金属部１１の形成の際には、この母型基板１０を介した通電がなされることで、母
型基板１０表面の第一レジスト層１２に覆われない通電可能な部分に電解メッキで金属部
１１が形成されることとなる。また、表面金属層１３のメッキの際も、電解メッキとする
場合には、母型基板１０を介して通電がなされる。 The matrix substrate 10 is formed of a conductive metal plate (thickness: about 0.1 mm) such as stainless steel (SUS430, etc.), aluminum, copper, etc., and is used for semiconductor devices until it is removed in the manufacturing process of the semiconductor device. The first resist layer 12 and the metal part 11 are formed on the front surface side, and the resist layer 18 is disposed on the back surface side in each stage of the semiconductor device substrate manufacturing process. . When the metal part 11 is formed, the energization is performed through the matrix substrate 10, so that the energized part that is not covered by the first resist layer 12 on the surface of the matrix substrate 10 is subjected to electrolytic plating. 11 will be formed. In addition, when the surface metal layer 13 is plated, electricity is supplied through the matrix substrate 10 when electrolytic plating is performed.

一方、半導体装置用基板１を用いた半導体装置の製造工程では、母型基板１０上の金属
部１１表面側が封止材１９で覆われ（図６（Ｂ）参照）、母型基板１０で金属部１１及び
封止材１９を支持しなくても十分な強度が得られたら、母型基板１０がこれらから分離除
去される（図６（Ｃ）参照）。母型基板１０がステンレス材の場合には、力を加えて半導
体装置側から物理的に引き剥がして除去する方法が採られ、また、母型基板１０が銅等の
場合、薬液を用いて溶解除去するエッチングの方法が用いられる。エッチングの場合、母
型基板１０は溶解するが金属部１１のニッケル等の材質が冒されないような選択エッチン
グ性を有するエッチング液を用いることとなる。
この母型基板１０が除去されると、半導体装置底部に、金属部１１の半導体素子搭載部
１１ａ及び電極部１１ｂ、並びに封止材１９の各裏面が同一平面上に露出した状態が得ら
れる。 On the other hand, in the manufacturing process of the semiconductor device using the semiconductor device substrate 1, the surface of the metal portion 11 on the mother substrate 10 is covered with the sealing material 19 (see FIG. 6B). If sufficient strength is obtained without supporting the portion 11 and the sealing material 19, the matrix substrate 10 is separated and removed from these (see FIG. 6C). When the mother substrate 10 is made of stainless steel, a method is adopted in which a force is applied to physically remove the substrate 10 from the semiconductor device side, and when the mother substrate 10 is made of copper or the like, it is dissolved using a chemical solution. An etching method for removing is used. In the case of etching, an etching solution having a selective etching property that dissolves the matrix substrate 10 but does not affect the material such as nickel of the metal portion 11 is used.
When the mother substrate 10 is removed, the semiconductor device mounting portion 11a and the electrode portion 11b of the metal portion 11 and the back surfaces of the sealing material 19 are exposed on the same plane at the bottom of the semiconductor device.

前記金属部１１は、電解メッキに適したニッケルや銅、又はニッケル−コバルト等のニ
ッケル合金からなり、母型基板１０上の第一レジスト層１２のない部分に、電解メッキで
形成される構成である。半導体装置用基板１において、金属部１１は、母型基板１０表面
で、半導体素子搭載部１１ａとその近傍に複数配置される電極部１１ｂの組合わせを一つ
の単位として、製造する半導体装置の数だけ前記組合わせが多数整列状態で並べられた形
態で形成されることとなる。 The metal part 11 is made of nickel, copper, or a nickel alloy such as nickel-cobalt suitable for electrolytic plating, and is formed by electrolytic plating on a part of the matrix substrate 10 without the first resist layer 12. is there. In the semiconductor device substrate 1, the metal part 11 is the number of semiconductor devices to be manufactured on the surface of the base substrate 10, with a combination of a semiconductor element mounting part 11 a and a plurality of electrode parts 11 b arranged in the vicinity thereof as one unit. Therefore, the combination is formed in a form in which a large number of the combinations are aligned.

この金属部１１は、第一レジスト層１２の厚さを越える厚さ（例えば、厚さ約６０〜８
０μｍ）で、且つ上端周縁には第一レジスト層１２側に張出した略庇状の張出し部１１ｃ
を有する形状として形成される。張出し部１１ｃは、電解メッキの際、金属部１１を第一
レジスト層１２の厚さまで形成した後も電解メッキを継続して、金属部の成長を厚さ方向
に加えて第一レジスト層１２による制限のない他の向きにも進行させることで、第一レジ
スト層１２を越えた金属部１１上端部から第一レジスト層１２側へ張出した形状として得
られるものである。この張出し部１１ｃは、封止材１９による封止に伴って、封止材１９
で挟まれて固定された状態となる。 The metal portion 11 has a thickness exceeding the thickness of the first resist layer 12 (for example, a thickness of about 60 to 8).
0 [mu] m), and a substantially bowl-shaped protruding portion 11c protruding toward the first resist layer 12 at the upper edge.
It is formed as a shape having During the electrolytic plating, the overhanging portion 11c continues the electrolytic plating after the metal portion 11 is formed to the thickness of the first resist layer 12, and adds the growth of the metal portion in the thickness direction so that the first resist layer 12 By proceeding in another direction without restriction, it is obtained as a shape protruding from the upper end of the metal part 11 beyond the first resist layer 12 to the first resist layer 12 side. The overhanging portion 11 c is sealed with the sealing material 19 along with the sealing with the sealing material 19.
It will be in the state of being pinched and fixed.

この他、金属部１１のうち、半導体素子搭載部１１ａには、半導体装置製造の際に半導
体素子１４を挿入して搭載可能な凹部１１ｅが設けられる。この凹部１１ｅに半導体素子
１４が挿入配設されると、凹部深さの分、従来のように半導体素子搭載部の上面に搭載さ
れる場合と比べて、半導体素子１４の配設位置を下げることができる。凹部１１ｅは、金
属部１１の形成の途中段階で、半導体素子搭載部１１ａにおける凹部１１ｅに対応する箇
所に第二レジスト層１６を配設することで穴又は溝状として生じるものであり、凹部１１
ｅの下側に半導体素子搭載部１１ａが必要な強度を維持する厚さを十分確保可能な程度の
深さとされる。 In addition, in the metal part 11, the semiconductor element mounting part 11a is provided with a concave part 11e into which the semiconductor element 14 can be inserted and mounted when the semiconductor device is manufactured. When the semiconductor element 14 is inserted and disposed in the recess 11e, the position where the semiconductor element 14 is disposed is lowered by an amount corresponding to the depth of the recess as compared with the conventional case where the semiconductor element 14 is mounted on the upper surface of the semiconductor element mounting portion. Can do. The recess 11e is formed as a hole or a groove by disposing the second resist layer 16 at a position corresponding to the recess 11e in the semiconductor element mounting portion 11a in the middle of the formation of the metal portion 11.
The depth is sufficient to ensure a sufficient thickness for the semiconductor element mounting portion 11a to maintain the required strength below e.

金属部１１は、大部分を電解メッキに適したニッケルやニッケル合金等で形成されるが
、金属部１１の裏面側には、半導体装置実装時のハンダ付けを適切に行えるようにするた
めに、ニッケル等の主材質部よりハンダぬれ性の良好な金属、例えば金や錫、パラジウム
、ハンダ等の薄膜１１ｄが配設される構成である。この薄膜１１ｄの厚さは０．０３〜１
μｍ程度とするのが好ましい。 The metal part 11 is mostly formed of nickel or a nickel alloy suitable for electrolytic plating, but on the back side of the metal part 11 in order to appropriately perform soldering when mounting a semiconductor device, A metal having better solder wettability than the main material portion such as nickel, for example, a thin film 11d such as gold, tin, palladium, or solder is disposed. The thickness of this thin film 11d is 0.03-1.
It is preferable to be about μm.

金属部１１形成の際には、あらかじめ薄膜１１ｄが母型基板１０上の第一レジスト層１
２のない部分にメッキ等で形成された後（図３（Ｂ）参照）、この薄膜１１ｄ上にさらに
電解メッキによりニッケル等の主材質部が形成されることとなる。この薄膜１１ｄには、
母型基板１０のエッチングによる除去の際にエッチング液による金属部１１の侵食劣化を
防ぐ機能を与えることもでき、その場合、金や銀、錫などの薄膜を配設するのが好ましい
。 When forming the metal part 11, the thin film 11 d is previously formed on the first resist layer 1 on the matrix substrate 10.
After the portion 2 is formed by plating or the like (see FIG. 3B), a main material portion such as nickel is further formed on the thin film 11d by electrolytic plating. In this thin film 11d,
When removing the matrix substrate 10 by etching, a function of preventing the erosion degradation of the metal portion 11 by the etching solution can be given. In that case, it is preferable to dispose a thin film of gold, silver, tin or the like.

なお、この金属部１１裏面側の薄膜形成は、前記ハンダ付け対策を目的とするものの場
合、電解メッキで金属部１１主材質部を形成する前に限られるものではなく、半導体装置
７０の完成後、メッキにより金属部１１の露出した裏面側に薄膜を形成するようにしても
かまわない。 Note that the thin film formation on the back surface side of the metal part 11 is not limited to the formation of the main material part of the metal part 11 by electrolytic plating in the case of aiming at the soldering countermeasure, but after the semiconductor device 70 is completed. Alternatively, a thin film may be formed on the exposed back side of the metal part 11 by plating.

前記第一レジスト層１２は、金属部１１の電解メッキや表面金属層１３のメッキで使用
するメッキ液に対する耐溶解性を備えた絶縁性材で形成され、母型基板１０上にあらかじ
め設定される金属部１１の非配置部分に対応させて配設され、金属部１１及び表面金属層
１３の形成後には除去されるものである（図５（Ｃ）参照）。 The first resist layer 12 is formed of an insulating material having a resistance to dissolution with respect to a plating solution used for electrolytic plating of the metal part 11 and plating of the surface metal layer 13, and is set on the matrix substrate 10 in advance. The metal portion 11 is disposed corresponding to the non-arranged portion, and is removed after the metal portion 11 and the surface metal layer 13 are formed (see FIG. 5C).

この第一レジスト層１２は、母型基板１０上に金属部１１の形成に先立って配設され、
詳細には、公知の感光性レジスト剤を母型基板１０に所定の厚さ、例えば約５０μｍの厚
さとなるようにして密着配設し、半導体装置７０の金属部１１位置に対応する所定パター
ンのマスクフィルム５０を載せた状態で、紫外線照射による露光での硬化（図２（Ｃ）参
照）、非照射部分の感光性材料を除去する現像等の処理を経て、金属部１１の非配置部分
に対応させた形状で形成される。 The first resist layer 12 is disposed on the matrix substrate 10 prior to the formation of the metal portion 11,
Specifically, a known photosensitive resist agent is placed in close contact with the base substrate 10 so as to have a predetermined thickness, for example, about 50 μm, and a predetermined pattern corresponding to the position of the metal portion 11 of the semiconductor device 70 is formed. With the mask film 50 placed on the non-arranged portion of the metal portion 11 through processing such as curing by exposure by ultraviolet irradiation (see FIG. 2C) and development to remove the photosensitive material in the non-irradiated portion. It is formed in a corresponding shape.

前記第二レジスト層１６は、前記第一レジスト層１２同様にメッキ液に対する耐溶解性
を備えた絶縁性材で形成され、金属部１１の形成の途中段階で、あらかじめ設定される金
属部１１の凹部１１ｅに対応させて配設され、金属部１１及び表面金属層１３の形成後に
は除去されるものである。この第二レジスト層１６としては、第一レジスト層１２の場合
と同様、感光性レジスト剤等を用いることができる。このレジスト剤を金属部１１と第一
レジスト層１２の各表面に所定の厚さ、例えば約６０μｍを超える厚さとなるようにして
コーティングし、金属部１１の凹部１１ｅ位置に対応する所定パターンのマスクフィルム
５１を載せた状態で、紫外線照射による露光で硬化させる処理を経ると、金属部１１上に
固定状態の第二レジスト層１６が形成されることとなる。この金属部１１上の第二レジス
ト層１６により、金属部１１の凹部１１ｅに相当する部分で電解メッキが進行せず、金属
部１１の欠けた部分、すなわち凹部１１ｅを生じさせられる。 Like the first resist layer 12, the second resist layer 16 is formed of an insulating material having resistance to dissolution with respect to a plating solution, and the metal portion 11 is set in advance during the formation of the metal portion 11. It is arranged corresponding to the recess 11e and is removed after the metal part 11 and the surface metal layer 13 are formed. As the second resist layer 16, a photosensitive resist agent or the like can be used as in the case of the first resist layer 12. This resist agent is coated on each surface of the metal portion 11 and the first resist layer 12 so as to have a predetermined thickness, for example, a thickness exceeding about 60 μm, and a mask having a predetermined pattern corresponding to the position of the concave portion 11 e of the metal portion 11. When the film 51 is placed and undergoes a curing process by exposure by ultraviolet irradiation, the fixed second resist layer 16 is formed on the metal part 11. Due to the second resist layer 16 on the metal part 11, the electrolytic plating does not proceed at the part corresponding to the concave part 11 e of the metal part 11, and the part where the metal part 11 is missing, that is, the concave part 11 e is generated.

なお、この第一レジスト層１２や第二レジスト層１６については、感光性レジストに限
られるものではなく、メッキ液に対し変質せず強度の高い塗膜が得られる塗料を、母型基
板１０上における金属部１１の非配置部分や金属部１１の凹部１１ｅ位置に、電着塗装等
により必要な塗膜厚さとなるように塗装して形成することもできる。 The first resist layer 12 and the second resist layer 16 are not limited to the photosensitive resist, and a coating material that does not change the plating solution and can provide a high-strength coating film is formed on the matrix substrate 10. It can also be formed by coating the non-arranged part of the metal part 11 or the concave part 11e position of the metal part 11 so as to have a required coating thickness by electrodeposition coating or the like.

一方、この表面側の第一レジスト層１２や第二レジスト層１６とは別に、母型基板１０
の裏面側にも、レジスト層１８が形成される構成である（図２参照）。裏面側のレジスト
層１８は、硬化状態でメッキ液への耐性のある材質で、且つ不要となったら容易に溶解除
去可能なレジスト材、例えば厚さ約５０μｍのアルカリ現像タイプの感光性フィルムレジ
ストを熱圧着等により配設し、そのままマスクなしに紫外線照射による露光等の処理を経
て、裏面全面にわたり硬化形成されるものとすることができる。 On the other hand, apart from the first resist layer 12 and the second resist layer 16 on the surface side, the mother substrate 10
The resist layer 18 is also formed on the back surface side of (see FIG. 2). The resist layer 18 on the back side is made of a resist material that is resistant to the plating solution in a cured state, and can be easily dissolved and removed when it becomes unnecessary, for example, an alkali development type photosensitive film resist having a thickness of about 50 μm. It can be disposed by thermocompression bonding or the like, and can be cured and formed over the entire back surface through a process such as exposure by ultraviolet irradiation without a mask.

前記表面金属層１３は、配線用のワイヤ１５をなす金線等との接合性に優れる金や銀等
からなるメッキ膜として形成される。
この表面金属層１３は、母型基板１０ごとのメッキ浴により金属部１１の表面に所定の
厚さ、例えば、金メッキの場合は約０．１〜１μｍ、銀メッキの場合は約１〜１０μｍの
厚さのメッキとして形成される。この表面金属層１３のメッキの際、母型基板１０の裏面
側はレジスト層１８で覆われていることから、メッキの付着等は生じない（図５（Ｂ）参
照）。
なお、この表面金属層１３へのメッキに際しては、金属部１１のメッキの場合とはメッ
キ液を異ならせるなど、メッキの金属に対応するメッキ液を使用することとなる。 The surface metal layer 13 is formed as a plating film made of gold, silver, or the like that is excellent in bondability with a gold wire or the like forming the wire 15 for wiring.
The surface metal layer 13 has a predetermined thickness on the surface of the metal portion 11 by a plating bath for each base substrate 10, for example, about 0.1 to 1 μm in the case of gold plating and about 1 to 10 μm in the case of silver plating. It is formed as a thick plating. When the surface metal layer 13 is plated, the back surface side of the matrix substrate 10 is covered with the resist layer 18, so that no plating adhesion occurs (see FIG. 5B).
In the plating on the surface metal layer 13, a plating solution corresponding to the plating metal is used, such as making the plating solution different from the case of plating the metal portion 11.

この表面金属層１３のメッキを形成する際は、金属部１１がニッケルの場合、メッキが
付着しにくいため、通常、表面金属層１３のメッキの前にあらかじめ金属部１１表面に下
地メッキ（銅ストライクや銀ストライク、又は金ストライク）を行い、表面金属層１３の
金属部１１への密着性を高めることが望ましい。 When forming the plating of the surface metal layer 13, if the metal part 11 is nickel, the plating is difficult to adhere. Therefore, usually, before the surface metal layer 13 is plated, the surface of the metal part 11 is preliminarily plated (copper strike). Or silver strike or gold strike) to improve the adhesion of the surface metal layer 13 to the metal portion 11.

前記半導体素子１４は、微細な電子回路が形成されたいわゆるチップであり、金属部１
１のうち半導体素子搭載部１１ａの凹部１１ｅに挿入、接着されて搭載される。そして、
金、銅等の導電性線材からなる配線（ボンディング）用のワイヤ１５が、半導体素子１４
表面に設けられた電極と、金属部１１のうち半導体素子搭載部１１ａと独立させて形成さ
れた電極部１１ｂとにそれぞれ接合され、半導体素子１４と電極部１１ｂとを電気的に接
続することとなる。 The semiconductor element 14 is a so-called chip in which a fine electronic circuit is formed, and the metal part 1
1 is inserted and bonded to the recess 11e of the semiconductor element mounting portion 11a. And
A wire 15 for wiring (bonding) made of a conductive wire material such as gold or copper is used as the semiconductor element 14.
The electrode provided on the surface and the electrode part 11b formed independently of the semiconductor element mounting part 11a of the metal part 11 are respectively joined to electrically connect the semiconductor element 14 and the electrode part 11b; Become.

この半導体素子１４は、半導体素子搭載部１１ａの凹部１１ｅに挿入配設されることか
ら、従来のように半導体素子搭載部の上面に搭載される場合と比べて、配設位置を下げる
ことができ、半導体素子１４上面や接合されるワイヤ１５も下がる分、半導体装置７０の
厚さを小さくして製造することができ、半導体装置７０の低背化を実現できる。また、半
導体素子１４の位置が下がって、ワイヤ１５が接合する半導体素子１４と電極部の各上面
が近付く分、ワイヤ長さも短くすることができ、ワイヤ使用量を削減してコストを低減で
きる。 Since the semiconductor element 14 is inserted and disposed in the recess 11e of the semiconductor element mounting portion 11a, the position of the semiconductor element 14 can be lowered as compared with the conventional case where the semiconductor element 14 is mounted on the upper surface of the semiconductor element mounting portion. Since the upper surface of the semiconductor element 14 and the wire 15 to be joined are also lowered, the semiconductor device 70 can be manufactured with a reduced thickness, and a reduction in the height of the semiconductor device 70 can be realized. Further, as the position of the semiconductor element 14 is lowered and the semiconductor element 14 to which the wire 15 is joined and the upper surfaces of the electrode portions are brought closer, the wire length can be shortened, and the amount of wire used can be reduced and the cost can be reduced.

前記封止材１９は、物理的強度の高い熱硬化性エポキシ樹脂等であり、金属部１１表面
側の半導体素子１４やワイヤ１５を覆った状態で封止し、半導体素子１４やワイヤ１５等
の構造的に弱い部分を外部から隔離した保護状態とするものである。なお、半導体素子１
４がＬＥＤ等の発光素子の場合、透光性の材質が用いられる。 The sealing material 19 is a thermosetting epoxy resin or the like having high physical strength. The sealing material 19 is sealed in a state where the semiconductor element 14 or the wire 15 on the surface side of the metal part 11 is covered. The structurally weak parts are protected from the outside. Semiconductor element 1
When 4 is a light emitting element such as an LED, a translucent material is used.

この封止材１９を用いる封止工程は、半導体装置用基板１に対して行われ、母型基板１
０の表面側における金属部１１等のある半導体装置となる範囲を、上型となる金型で覆っ
た上で、この金型と母型基板１０の間に硬化前の封止材１９を圧入し、封止材１９を硬化
させることで封止が完了となる。ただし、封止工程では、一つの半導体装置となる半導体
素子搭載部１１ａと複数の電極部１１ｂとの組合わせが多数整列状態のままで一様に封止
されるため、半導体装置は封止材１９を介して多数つながった状態となっている。 The sealing process using the sealing material 19 is performed on the semiconductor device substrate 1, and the mother substrate 1
The area to be a semiconductor device such as the metal part 11 on the surface side of 0 is covered with an upper mold, and an unsealed sealing material 19 is press-fitted between the mold and the base substrate 10 Then, the sealing is completed by curing the sealing material 19. However, in the sealing process, since the combination of the semiconductor element mounting portion 11a and the plurality of electrode portions 11b, which are one semiconductor device, is uniformly sealed while being aligned, the semiconductor device is a sealing material. Many are connected through 19.

この封止材１９は、十分な物理的強度を有しており、半導体装置７０の外装の一部とし
て十分に内部を保護する機能を果し、また母型基板１０を半導体装置側から引き剥がすな
ど力を加えて物理的に除去する場合にも、割れ等の破損もなく金属部１１との一体化状態
を維持することとなる。 This sealing material 19 has a sufficient physical strength, functions sufficiently to protect the inside as a part of the exterior of the semiconductor device 70, and peels off the mother substrate 10 from the semiconductor device side. Even when physically removed by applying a force such as the above, the integrated state with the metal part 11 is maintained without breakage or the like.

次に、本実施形態に係る半導体装置用基板の製造及び半導体装置用基板を用いた半導体
装置製造の各工程について説明する。
半導体装置用基板の製造工程として、まず、母型基板１０上にあらかじめ設定される金
属部１１の非配置部分に対応させて母型基板１０に第一レジスト層１２を配設する。具体
的には、母型基板１０の表面側に、感光性レジスト剤１２ａを、形成する金属部１１の高
さに対応する所定厚さ（例えば約５０μｍ）となるようにして密着配設する（図２（Ｂ）
参照）。感光性レジスト剤に対しては、金属部１１の配置位置に対応する所定パターンの
マスクフィルム５０を載せた状態で、紫外線照射による露光での硬化（図２（Ｃ）参照）
、非照射部分のレジスト剤を除去する現像等の公知の処理を行い、金属部１１の非配置部
分に対応させた第一レジスト層１２を硬化形成する（図３（Ａ）参照）。また、母型基板
１０の裏面側にも、感光性レジスト剤を表面側同様に配設し、これに対してはそのまま全
面に対する露光等の処理を経て、裏面全面にわたりレジスト層１８を硬化形成する（図２
（Ｃ）参照）。 Next, each process of manufacturing a semiconductor device substrate and manufacturing a semiconductor device using the semiconductor device substrate according to the present embodiment will be described.
As a manufacturing process of a substrate for a semiconductor device, first, the first resist layer 12 is disposed on the mother substrate 10 so as to correspond to a non-arranged portion of the metal portion 11 set on the mother substrate 10 in advance. Specifically, the photosensitive resist agent 12a is closely attached to the surface side of the mother substrate 10 so as to have a predetermined thickness (for example, about 50 μm) corresponding to the height of the metal part 11 to be formed ( FIG. 2 (B)
reference). For the photosensitive resist agent, curing by exposure by ultraviolet irradiation with a mask film 50 having a predetermined pattern corresponding to the arrangement position of the metal part 11 (see FIG. 2C).
Then, a known process such as development for removing the resist agent in the non-irradiated part is performed to cure and form the first resist layer 12 corresponding to the non-arranged part of the metal part 11 (see FIG. 3A). Further, a photosensitive resist agent is also disposed on the back surface side of the base substrate 10 in the same manner as the front surface side, and the resist layer 18 is cured and formed over the entire back surface through a process such as exposure to the entire surface. (Fig. 2
(See (C)).

こうして、金属部１１のメッキで使用するメッキ液に対する耐溶解性を備えたレジスト
層１２、１８を形成したら、母型基板１０表面の第一レジスト層１２で覆われていない露
出部分に対し、必要に応じて表面酸化被膜除去や表面活性化処理を行う。その後、この露
出部分にメッキ等によりハンダぬれ性改善用の金の薄膜１１ｄを、例えば０．０３〜１μ
ｍ厚で形成する（図３（Ｂ）参照）。そして、この薄膜１１ｄ上に、電解メッキによりニ
ッケルを積層して金属部１１を形成する（図３（Ｃ）参照）。 Thus, when the resist layers 12 and 18 having resistance to the plating solution used for plating of the metal part 11 are formed, it is necessary for the exposed part not covered with the first resist layer 12 on the surface of the mother board 10. Depending on the conditions, surface oxide film removal and surface activation treatment are performed. Thereafter, a gold thin film 11d for improving solder wettability is formed on the exposed portion by plating or the like, for example, 0.03 to 1 μm.
It is formed with a thickness of m (see FIG. 3B). Then, nickel is laminated on the thin film 11d by electrolytic plating to form the metal portion 11 (see FIG. 3C).

この最初の金属部１１の形成工程で、金属部１１は、第一レジスト層１２の厚さを越え
ない所定厚さ（例えば、厚さ５０μｍ未満）として形成される（図３（Ｃ）参照）。金属
部１１は、母型基板１０表面において、半導体素子搭載部１１ａとその近傍に複数配置さ
れる電極部１１ｂの組合わせを一つの単位として、製造する半導体装置の数だけ前記組合
わせが多数整列状態で並べられた形態で形成されることとなる。 In the first metal part 11 formation step, the metal part 11 is formed with a predetermined thickness (for example, less than 50 μm) that does not exceed the thickness of the first resist layer 12 (see FIG. 3C). . The metal part 11 is arranged on the surface of the base substrate 10 in such a number that the number of semiconductor devices mounted is the same as the number of semiconductor devices to be manufactured, with a combination of the semiconductor element mounting part 11a and a plurality of electrode parts 11b arranged in the vicinity thereof as one unit It will be formed in the form arranged in the state.

金属部１１を所定厚さまで形成したら、いったん電解メッキによる金属部形成作業を中
断し、表面を清浄化した後、所定厚さまで形成された金属部１１の上に、金属部１１にお
ける半導体素子搭載部１１ａの凹部１１ｅに対応させて第二レジスト層１６を配設する。
具体的には、金属部１１と第一レジスト層１２の表面側に、感光性レジスト剤１６ａを、
凹部１１ｅの深さより大きい所定厚さ（例えば約５０μｍ）となるようにして密着配設す
る（図４（Ａ）参照）。この感光性レジスト剤に対し、半導体素子搭載部１１ａの凹部１
１ｅの配置位置に対応する所定パターンのマスクフィルム５１を載せた状態で、紫外線照
射による露光での硬化（図４（Ｂ）参照）、非照射部分のレジスト剤を除去する現像等の
公知の処理を行い、凹部１１ｅを生じさせる箇所に対応させた第二レジスト層１６を硬化
形成する（図４（Ｃ）参照）。 Once the metal part 11 is formed to a predetermined thickness, the metal part forming operation by electrolytic plating is interrupted once, the surface is cleaned, and then the semiconductor element mounting part in the metal part 11 is formed on the metal part 11 formed to the predetermined thickness. A second resist layer 16 is disposed corresponding to the recess 11e of 11a.
Specifically, a photosensitive resist agent 16a is provided on the surface side of the metal part 11 and the first resist layer 12,
A predetermined thickness (for example, about 50 μm) larger than the depth of the recess 11e is provided in close contact (see FIG. 4A). The concave portion 1 of the semiconductor element mounting portion 11a is against this photosensitive resist agent.
In a state where a mask film 51 having a predetermined pattern corresponding to the position 1e is placed, known processing such as curing by exposure by ultraviolet irradiation (see FIG. 4B) and development for removing the resist agent in the non-irradiated portion Then, the second resist layer 16 corresponding to the location where the recess 11e is generated is cured (see FIG. 4C).

第二レジスト層１６を形成したら、この第二レジスト層１６で覆われていない金属部１
１の露出部分に対し、必要に応じて公知の表面処理、例えば清浄処理や密着処理等を行っ
た後、電解メッキによりニッケルを積層して金属部１１を形成する工程を再度行い、金属
部１１をあらかじめ設定された所定厚さ（例えば、厚さ約６０μｍ）に形成する（図５（
Ａ）参照）。 When the second resist layer 16 is formed, the metal part 1 not covered with the second resist layer 16 is formed.
After performing a known surface treatment such as a cleaning process or an adhesion process on the exposed part of 1 as necessary, a step of forming a metal part 11 by laminating nickel by electrolytic plating is performed again. Is formed in a predetermined thickness (for example, a thickness of about 60 μm) (see FIG. 5 (
A)).

金属部１１は、第一レジスト層１２の厚さを越える一方、第二レジスト層１６の上面を
越えない厚さとして形成され、第二レジスト層１６の側面に接する部位を伴う一方、第一
レジスト層１２寄りの金属部１１上端周縁には第一レジスト層１２側に張出した略庇状の
張出し部１１ｃが形成される。この新たな電解メッキによる金属部１１の形成工程では、
第二レジスト層１６の配置された箇所に金属部１１は形成されない。 The metal part 11 is formed to have a thickness that does not exceed the thickness of the first resist layer 12 but does not exceed the upper surface of the second resist layer 16, and has a portion that contacts the side surface of the second resist layer 16. A substantially hook-like protruding portion 11c protruding toward the first resist layer 12 is formed at the upper end periphery of the metal portion 11 near the layer 12. In the formation process of the metal part 11 by this new electrolytic plating,
The metal part 11 is not formed at the place where the second resist layer 16 is disposed.

所望の厚さ及び形状の金属部１１が得られたら、母型基板１０ごとのメッキ浴により、
金属部１１の表面に、表面金属層１３を所定の厚さ、例えば銀メッキの場合、厚さ約０．
３〜０．４μｍとなるように形成する（図５（Ｂ）参照）。メッキ浴に用いられるメッキ
液に対し、第一レジスト層１２及び第二レジスト層１６は十分な耐性を有しているため、
変質等が生じることはなく、レジスト層としての機能を維持し、金属部１１等必要箇所以
外へのメッキ付着を防ぐことができる。また、この表面金属層１３のメッキの際、母型基
板１０の裏面側はレジスト層１８で覆われていることから、メッキの付着はない。 When the metal part 11 having a desired thickness and shape is obtained, a plating bath for each matrix substrate 10 is used.
When the surface metal layer 13 is formed on the surface of the metal part 11 with a predetermined thickness, for example, silver plating, the thickness is about 0.
It is formed to be 3 to 0.4 μm (see FIG. 5B). Since the first resist layer 12 and the second resist layer 16 have sufficient resistance to the plating solution used in the plating bath,
No alteration or the like occurs, the function as a resist layer is maintained, and plating adhesion to places other than necessary portions such as the metal portion 11 can be prevented. Further, when the surface metal layer 13 is plated, the back surface side of the matrix substrate 10 is covered with the resist layer 18, so that no plating adheres.

表面金属層１３形成後、母型基板１０表面側の第一レジスト層１２、第二レジスト層１
６、及び裏面側のレジスト層１８を所定の除去剤で溶解させてそれぞれ除去すると（図５
（Ｃ）参照）、半導体装置用基板１が完成する。第二レジスト層１６を除去した後は、金
属部１１の半導体素子搭載部１１ａにおける、第二レジスト層１６が存在していた部位に
、穴又は溝状の凹部１１ｅが生じている。 After the surface metal layer 13 is formed, the first resist layer 12 and the second resist layer 1 on the surface of the mother substrate 10 are formed.
6 and the resist layer 18 on the back side are removed by dissolving them with a predetermined removing agent (FIG. 5).
(See (C)), the semiconductor device substrate 1 is completed. After the second resist layer 16 is removed, a hole or groove-shaped recess 11e is generated at a portion of the semiconductor element mounting portion 11a of the metal portion 11 where the second resist layer 16 was present.

続いて、得られた半導体装置用基板１を用いた半導体装置の製造について説明すると、
まず、半導体装置用基板１における金属部１１のうち半導体素子搭載部１１ａの凹部１１
ｅに、接着剤を介在させた上で半導体素子１４を挿入して搭載し、接着固定状態とし、さ
らに、半導体素子１４表面の電極と、これに対応する各電極部１１ｂとに、金線等のワイ
ヤ１５を接合し、半導体素子１４と各電極部１１ｂとを電気的接続状態とする（図６（Ａ
）参照）。この配線による電気的接続は、公知の超音波ボンディング装置等により実施さ
れる。電極部１１ｂの表面には表面金属層１３が形成されているため、ワイヤ１５との接
合を確実なものとすることができ、接続の信頼性を高められる。 Next, manufacturing of a semiconductor device using the obtained semiconductor device substrate 1 will be described.
First, of the metal part 11 in the semiconductor device substrate 1, the concave part 11 of the semiconductor element mounting part 11 a.
The semiconductor element 14 is inserted and mounted in e with an adhesive interposed therebetween, and is set in an adhesively fixed state. Further, a gold wire or the like is provided on the electrode on the surface of the semiconductor element 14 and each electrode portion 11b corresponding thereto. The wire 15 is bonded, and the semiconductor element 14 and each electrode portion 11b are electrically connected (FIG. 6A).
)reference). The electrical connection by this wiring is performed by a known ultrasonic bonding apparatus or the like. Since the surface metal layer 13 is formed on the surface of the electrode portion 11b, the bonding with the wire 15 can be ensured, and the connection reliability can be improved.

半導体素子１４と各電極部１１ｂとの接続が完了したら、母型基板１０の表面側におけ
る金属部１１等のある半導体装置となる範囲を、熱硬化性エポキシ樹脂等の封止材１９で
封止し、半導体素子１４やワイヤ１５を外部から隔離した保護状態とする（図６（Ｂ）参
照）。詳細には、母型基板１０の表面側を上型となるモールド金型に装着し、母型基板１
０に下型の役割を担わせつつ、モールド金型内に封止材１９となる硬化前のエポキシ樹脂
を圧入するという過程で封止が実行され、母型基板１０上では、一つの半導体装置となる
半導体素子搭載部１１ａと複数の電極部１１ｂとの組合わせが多数整列状態のままで一様
に封止され、半導体装置が多数つながった状態で現れることとなる。 When the connection between the semiconductor element 14 and each electrode portion 11b is completed, the range of the semiconductor device such as the metal portion 11 on the surface side of the base substrate 10 is sealed with a sealing material 19 such as a thermosetting epoxy resin. Then, the semiconductor element 14 and the wires 15 are protected from the outside (see FIG. 6B). In detail, the surface side of the mother board 10 is mounted on the upper mold, and the mother board 1
Sealing is executed in the process of press-fitting an epoxy resin before curing, which becomes the sealing material 19, into the mold die while taking the role of the lower die to 0, and one semiconductor device is formed on the mother substrate 10 The combination of the semiconductor element mounting portion 11a and the plurality of electrode portions 11b is uniformly sealed while being in an aligned state, and appears in a state where a large number of semiconductor devices are connected.

この多数つながった状態の半導体装置が得られたら、母型基板１０を除去し、各半導体
装置の底部に金属部１１の裏面側が露出した状態を得る（図６（Ｃ）参照）。ステンレス
材製である母型基板１０の除去には、半導体装置側から母型基板１０を物理的に引き剥が
して除去する方法を用いる。母型基板１０に強度及び剥離性に優れるステンレス材を用い
ることで、半導体装置側から母型基板１０を引き剥がして速やかに分離除去することがで
きる。 When the semiconductor devices in such a connected state are obtained, the mother substrate 10 is removed to obtain a state in which the back side of the metal portion 11 is exposed at the bottom of each semiconductor device (see FIG. 6C). For removing the mother substrate 10 made of stainless steel, a method of physically peeling the mother substrate 10 from the semiconductor device side and removing it is used. By using a stainless steel material that is excellent in strength and peelability for the mother substrate 10, the mother substrate 10 can be peeled off from the semiconductor device side and quickly removed.

この他、母型基板が他の金属材である場合には、母型基板を除去する方法として、母型
基板をエッチング液に浸漬して溶解させる方法を用いることもできる。このエッチングの
場合、母型基板は溶解するが金属部１１や表面金属層１３の材質が冒されないような選択
エッチング性を有するエッチング液を用いることとなる。溶解させて除去する場合では、
半導体装置側に過大な力が加わらないため、母型基板の除去に伴って悪影響が生じる確率
を小さくできる。 In addition, when the base substrate is another metal material, a method of removing the base substrate by immersing the base substrate in an etchant and dissolving it can be used. In this etching, an etching solution having a selective etching property is used so that the matrix substrate is dissolved but the material of the metal portion 11 and the surface metal layer 13 is not affected. When removing by dissolving,
Since an excessive force is not applied to the semiconductor device side, it is possible to reduce the probability that an adverse effect will occur with the removal of the mother substrate.

母型基板１０を除去された半導体装置の底部では、露出する金属部１１の裏面側と、封
止材１９の裏面側とが同一平面上に位置する状態となっている。母型基板１０の除去後、
多数つながった状態の半導体装置を一つ一つ切り離せば、半導体装置７０としての完成と
なる。 At the bottom of the semiconductor device from which the matrix substrate 10 has been removed, the exposed back side of the metal part 11 and the back side of the sealing material 19 are in the same plane. After removing the matrix substrate 10,
The semiconductor device 70 is completed by separating the semiconductor devices connected in large numbers one by one.

得られた半導体装置７０内部において、金属部１１の上端周縁を張出し部１１ｃとして
略庇状に張り出し形成し、封止材１９による封止状態で、この張出し部１１ｃが硬化した
封止材１９に囲まれて固定されていることから、樹脂同士で密着し強固に一体化した封止
材１９に張出し部１１が食込んで、金属部１１に加わる外力に対する抵抗体の役割を果す
こととなり、母型基板１０にステンレス材等を用い、半導体装置側から母型基板１０を物
理的に引き剥がして除去する場合など、金属部１１裏面側に装置外装から引離そうとする
外力が加わっても、張出し部１１が金属部１１の移動を妨げ、金属部１１の他部分に対す
るずれ等をなくすことができ、製造時における歩留りを向上させられると共に、半導体装
置としての強度を高められ、使用時の耐久性や半導体装置動作の信頼性も高められる。 In the obtained semiconductor device 70, the upper end periphery of the metal portion 11 is formed as a protruding portion 11 c so as to protrude in a substantially bowl shape, and in a sealed state by the sealing material 19, the protruding portion 11 c is cured to the sealing material 19. Since it is surrounded and fixed, the overhanging portion 11 bites into the sealing material 19 that is closely adhered and firmly integrated with the resin, and plays a role of a resistor against an external force applied to the metal portion 11. Even when an external force is applied to the back surface side of the metal part 11 from the exterior of the device, such as when the base substrate 10 is physically removed from the semiconductor device side by using stainless steel or the like for the mold substrate 10, The overhanging portion 11 prevents the movement of the metal portion 11 and can eliminate displacement with respect to other portions of the metal portion 11, thereby improving the yield during manufacturing and increasing the strength as a semiconductor device. Reliability of durability and semiconductor device operations when also enhanced.

このように、本実施形態に係る半導体装置用基板は、母型基板１０上に形成される金属
部１１である半導体素子搭載部１１ａに凹部１１ｅを設け、半導体素子搭載部１１ａにお
ける凹部１１ｅの下側部分の厚さを小さくすると共に、凹部１１ｅを半導体装置製造工程
で半導体素子１４を挿入、載置可能な大きさとなるようにすることから、この半導体装置
用基板１を用いた半導体装置７０の製造にあたり、凹部１１ｅで変化を加えた金属部１１
の表面形状に応じて、半導体装置の構造に好ましい特長を付与でき、例えば、半導体素子
１４を半導体素子搭載部１１ａの凹部１１ｅに挿入配設して、従来のように半導体素子搭
載部の上面に搭載される場合と比べて、配設位置を下げることができ、半導体素子１４上
面や、電極部１１ｂと半導体素子１４とを接合するワイヤ１５等の高さも下がる分、半導
体装置７０の厚さを小さくして製造することができ、半導体装置７０の低背化を実現でき
る。また、半導体素子１４の位置が下がって、ワイヤ１５が接合する半導体素子１４と電
極部１１ｂの各上面が互いに近付く分、ワイヤ長さも短くすることができ、ワイヤ使用量
を削減してコストを低減できる。 As described above, the substrate for a semiconductor device according to the present embodiment is provided with the recess 11e in the semiconductor element mounting portion 11a, which is the metal portion 11 formed on the mother substrate 10, and below the recess 11e in the semiconductor element mounting portion 11a. Since the thickness of the side portion is reduced and the recess 11e is sized so that the semiconductor element 14 can be inserted and placed in the semiconductor device manufacturing process, the semiconductor device 70 using the semiconductor device substrate 1 is provided. In manufacturing, the metal part 11 is changed by the recess 11e.
Depending on the surface shape of the semiconductor device, a preferable feature can be imparted to the structure of the semiconductor device. For example, the semiconductor element 14 is inserted and disposed in the recess 11e of the semiconductor element mounting portion 11a, so that it is formed on the upper surface of the semiconductor element mounting portion. Compared with the case where it is mounted, the arrangement position can be lowered, and the thickness of the semiconductor device 70 is reduced by the height of the upper surface of the semiconductor element 14 and the height of the wire 15 that joins the electrode portion 11b and the semiconductor element 14 and the like. The semiconductor device 70 can be manufactured in a small size, and the height of the semiconductor device 70 can be reduced. In addition, as the position of the semiconductor element 14 is lowered and the upper surfaces of the semiconductor element 14 and the electrode portion 11b to which the wire 15 is joined can approach each other, the length of the wire can be shortened, reducing the amount of wire used and reducing the cost. it can.

（本発明の第２の実施形態）
前記第１の実施形態における半導体装置用基板１においては、金属部１１の半導体素子
搭載部１１ａに凹部１１ｅを設けて、この半導体装置用基板を用いた半導体装置の製造工
程では、凹部１１ｅに半導体素子１４を搭載するようにしているが、この他、第２の実施
形態として、図８に示すように、半導体装置用基板２における金属部１１の電極部１１ｆ
にも凹部１１ｇを設け、半導体装置の製造工程で電極部の凹部位置を切断して、切り分け
られた個々の半導体装置７１を得るものとすることもできる。 (Second embodiment of the present invention)
In the semiconductor device substrate 1 in the first embodiment, the recess 11e is provided in the semiconductor element mounting portion 11a of the metal portion 11, and in the manufacturing process of the semiconductor device using the semiconductor device substrate, the recess 11e has a semiconductor. Although the element 14 is mounted, in addition to this, as a second embodiment, as shown in FIG. 8, the electrode portion 11f of the metal portion 11 in the semiconductor device substrate 2 is provided.
Also, the recess 11g may be provided, and the position of the recess of the electrode portion may be cut in the manufacturing process of the semiconductor device to obtain individual semiconductor devices 71 that are separated.

本実施形態に係る半導体装置用基板２は、前記第１の実施形態同様、母型基板１０と、
金属部１１と、表面金属層１３とを備えるものであり、異なる点として、金属部１１にお
ける電極部１１ｆが、後の半導体装置製造工程で行われる切断加工での切断予定箇所に位
置して、切断加工時に二つに切断される配置として基板上に形成される構成を有するもの
である。そして、この電極部１１ｆには、切断加工の際に除去される部位を含む所定の大
きさとして凹部１１ｇが設けられることとなる。 The semiconductor device substrate 2 according to the present embodiment is similar to the first embodiment in that the mother substrate 10 and
The metal part 11 and the surface metal layer 13 are provided, and the difference is that the electrode part 11f in the metal part 11 is located at a planned cutting position in a cutting process performed in a subsequent semiconductor device manufacturing process. It has the structure formed on a board | substrate as arrangement | positioning cut | disconnected in two at the time of a cutting process. And this electrode part 11f will be provided with the recessed part 11g as a predetermined magnitude | size including the site | part removed in the case of a cutting process.

この半導体装置用基板２を用いて製造される半導体装置７１は、図１３に示すように、
前記第１の実施形態同様に金属部１１と、表面金属層１３と、半導体素子１４と、ワイヤ
１５と、封止材１９とを備える一方、異なる点として、金属部１１のうち電極部１１ｆが
、装置底部だけでなく側面にも露出する配置とされる構成を有するものである。 As shown in FIG. 13, a semiconductor device 71 manufactured using this semiconductor device substrate 2 is
As in the first embodiment, the metal part 11, the surface metal layer 13, the semiconductor element 14, the wire 15, and the sealing material 19 are provided. The arrangement is such that it is exposed not only on the bottom of the apparatus but also on the side surface.

半導体装置７１の各側面は、複数の半導体装置の集合形成状態から個々の半導体装置を
切り離す切断加工により生じた切断面となっている。半導体装置の実装上の必要等から、
電極部を底部だけでなく側面にも露出させる構造を採用する場合、切断面である側面の一
部に位置する関係から、電極部も切断加工を受けることとなる。 Each side surface of the semiconductor device 71 is a cut surface generated by a cutting process that separates the individual semiconductor devices from the aggregated state of the plurality of semiconductor devices. From the necessity for mounting semiconductor devices,
In the case of adopting a structure in which the electrode part is exposed not only on the bottom part but also on the side surface, the electrode part is also subjected to a cutting process because it is located on a part of the side surface which is a cut surface.

よって、半導体装置用基板２では、基板上に設計される半導体装置位置のうち、後の半
導体装置製造の際の切断加工を経て各半導体装置の側端位置となる切断予定箇所Ｙに、隣
り合う二つの半導体装置位置に跨り、切断加工で二つに切断されて、それぞれの半導体の
側端部で電極部をなすような配置及び大きさとして、電極部としての金属部が基板上に形
成される（図８参照）。 Therefore, in the semiconductor device substrate 2, among the semiconductor device positions designed on the substrate, the semiconductor device substrate 2 is adjacent to a planned cutting position Y that becomes a side end position of each semiconductor device through a subsequent cutting process in manufacturing the semiconductor device. A metal part as an electrode part is formed on a substrate so as to be arranged and sized so as to form an electrode part at the side end part of each semiconductor by being cut into two by cutting processing across two semiconductor device positions. (See FIG. 8).

なお、電極部を半導体装置のコーナ部に位置させる場合、電極部となる金属部は、半導
体装置用基板上の直線状の切断位置が交差する箇所で四つに切断されて、各々が問題なく
電極部をなすような大きさ及び配置として形成されることとなる。 In addition, when positioning an electrode part in the corner part of a semiconductor device, the metal part used as an electrode part is cut | disconnected into four in the location where the linear cutting position on the board | substrate for semiconductor devices crosses, and each has no problem. It will be formed as a size and arrangement to form an electrode part.

そして、半導体装置用基板２においては、電極部を形成する金属部形成工程で、電極部
の表面側に、切断予定箇所に位置するように溝状の凹部１１ｇが設けられる。この凹部１
１ｇは、前記第１の実施形態の場合同様、金属部１１の形成の途中段階で、凹部１１ｇに
対応させて第二レジスト層１６を配設し（図１０参照）、金属部１１の形成を再開した時
に第二レジスト層１６位置で金属部１１を形成させないことにより生じるものである。前
記第１の実施形態と同様、表面金属層１３の形成工程でも第二レジスト層１６は存在して
いることで、金属部１１の凹部１１ｇに面する部位には表面金属層は形成されない（図１
１（Ｂ）参照）。 Then, in the semiconductor device substrate 2, in the metal part forming step for forming the electrode part, a groove-like recess 11 g is provided on the surface side of the electrode part so as to be located at a planned cutting position. This recess 1
1g, as in the case of the first embodiment, in the middle of the formation of the metal part 11, a second resist layer 16 is disposed corresponding to the recess 11g (see FIG. 10) to form the metal part 11. This is because the metal part 11 is not formed at the position of the second resist layer 16 when resuming. Similar to the first embodiment, since the second resist layer 16 is present in the step of forming the surface metal layer 13, the surface metal layer is not formed on the portion of the metal portion 11 facing the recess 11 g (see FIG. 1
1 (B)).

半導体装置用基板２上で電極部１１ｆとなる金属部１１における凹部１１ｇの大きさは
、電極部１１ｆの切断予定箇所に重なり、且つ、切断加工において０でない所定の厚さを
有する切断刃の切削作用により少なからず除去される部位Ａが、確実に凹部の範囲に収ま
るように設定される（図１２（Ｃ）参照）。また、凹部１１ｇは、その下側で電極部１１
ｉが半導体装置製造工程における切断加工時まで必要な強度を維持する厚さを十分確保可
能な程度の深さとされる。 The size of the recess 11g in the metal part 11 which becomes the electrode part 11f on the semiconductor device substrate 2 is cut by a cutting blade having a predetermined thickness which is not 0 in the cutting process and overlaps with a planned cutting position of the electrode part 11f. The part A to be removed as a result of the action is set so as to surely fall within the range of the recess (see FIG. 12C). Further, the recess 11g has an electrode portion 11 on the lower side.
i is a depth that can sufficiently secure a thickness that maintains a required strength until the time of cutting in the semiconductor device manufacturing process.

そして、半導体装置製造工程での切断加工を経て各半導体装置７１の側面に露出した電
極部１１ｆの表面は、元の凹部１１ｇのあった位置の下側部分の断面であることから、表
面金属層の断面を一切含まないこととなる（図１３（Ｂ）参照）。 The surface of the electrode portion 11f exposed on the side surface of each semiconductor device 71 through the cutting process in the semiconductor device manufacturing process is a cross section of the lower portion of the position where the original concave portion 11g was present. No cross section is included (see FIG. 13B).

次に、本実施形態に係る半導体装置用基板の製造及び半導体装置用基板を用いた半導体
装置製造の各工程について説明する。
半導体装置用基板の製造工程として、はじめに、母型基板１０の表裏にレジスト層１２
、１８をそれぞれ形成する工程と、母型基板１０表面の第一レジスト層１２で覆われてい
ない部分に金属部１１を所定厚さまで形成する工程とがそれぞれ実行される点は、金属部
１１の形成位置が電極部１１ｆの形状に基づいて一部変化することを除いて前記第１の実
施形態の場合と同様であり、詳細な説明を省略する。 Next, each process of manufacturing a semiconductor device substrate and manufacturing a semiconductor device using the semiconductor device substrate according to the present embodiment will be described.
As a manufacturing process of a substrate for a semiconductor device, first, a resist layer 12 is formed on the front and back of the mother substrate 10.
, 18, and the step of forming the metal part 11 to a predetermined thickness on the surface of the base substrate 10 that is not covered with the first resist layer 12. Except that the formation position is partially changed based on the shape of the electrode portion 11f, it is the same as the case of the first embodiment, and detailed description thereof is omitted.

金属部１１を所定厚さまで形成したら（図９参照）、金属部形成作業を中断し、表面を
清浄化した後、所定厚さまで形成された金属部１１の上に、金属部１１における電極部１
１ｆのあらかじめ設定された凹部１１ｇの位置に対応させて、第二レジスト層１６を配設
する（図１０参照）。第二レジスト層１６は、形成中断時点の金属部１１のうち最終的に
電極部１１ｆとなるものの上側所定部位に、複数の電極部１１ｆにわたる略線状配置で形
成される。 When the metal part 11 is formed to a predetermined thickness (see FIG. 9), the metal part forming operation is interrupted, the surface is cleaned, and then the electrode part 1 in the metal part 11 is formed on the metal part 11 formed to the predetermined thickness.
The second resist layer 16 is disposed so as to correspond to the position of the recessed portion 11g set in advance 1f (see FIG. 10). The second resist layer 16 is formed in a substantially linear arrangement over the plurality of electrode portions 11f at a predetermined upper portion of the metal portion 11 at the time when formation is interrupted, which finally becomes the electrode portion 11f.

第二レジスト層１６を形成した後の、第二レジスト層１６で覆われていない金属部１１
の露出部分に対し、金属部１１を所定厚さまで形成する工程（図１１（Ａ）参照）と、金
属部１１の表面に表面金属層１３を形成する工程（図１１（Ｂ）参照）、並びに、母型基
板１０表面側の第一レジスト層１２、第二レジスト層１６、及び裏面側のレジスト層１８
をそれぞれ除去する工程（図１１（Ｃ）参照）を経て、半導体装置用基板２の完成に至る
点も、前記第１の実施形態同様である。 After the second resist layer 16 is formed, the metal part 11 not covered with the second resist layer 16
Forming the metal portion 11 to a predetermined thickness with respect to the exposed portion (see FIG. 11A), forming the surface metal layer 13 on the surface of the metal portion 11 (see FIG. 11B), and The first resist layer 12 on the surface side of the mother substrate 10, the second resist layer 16, and the resist layer 18 on the back side
In the same manner as in the first embodiment, the semiconductor device substrate 2 is completed through a step of removing each of the substrate 2 (see FIG. 11C).

第二レジスト層１６を除去した後、金属部１１の電極部１１ｆにおける、第二レジスト
層１６が存在していた部位には、複数の電極部１１ｆにわたって直列に並ぶ配置となる溝
状の凹部１１ｇがそれぞれ生じている（図８参照）。 After the second resist layer 16 is removed, a groove-shaped recess 11g that is arranged in series across the plurality of electrode portions 11f is formed in the portion of the electrode portion 11f of the metal portion 11 where the second resist layer 16 is present. (See FIG. 8).

続いて、半導体装置用基板２を用いた半導体装置の製造では、半導体装置用基板２の金
属部１１のうち半導体素子搭載部１１ａに、半導体素子１４を搭載、固定する工程と、半
導体素子１４表面の電極と各電極部１１ｂの表面金属層１３部分とにワイヤ１５を接合し
て電気的接続状態とする工程（図１２（Ａ）参照）と、母型基板１０の表面側における半
導体装置となる範囲を封止材１９で封止する工程（図１２（Ｂ）参照）と、封止で得られ
た多数つながった状態の半導体装置から母型基板１０を除去する工程（図１２（Ｃ）参照
）とが、順次実行される点は、前記第１の実施形態同様であり、詳細な説明を省略する。 Subsequently, in the manufacture of the semiconductor device using the semiconductor device substrate 2, the step of mounting and fixing the semiconductor element 14 on the semiconductor element mounting portion 11 a of the metal portion 11 of the semiconductor device substrate 2, and the surface of the semiconductor element 14 A step of joining the wires 15 to the surface metal layer 13 portions of the electrodes 11b and the surface metal layer 13 portions (see FIG. 12A), and a semiconductor device on the surface side of the mother substrate 10 A step of sealing the area with the sealing material 19 (see FIG. 12B) and a step of removing the mother substrate 10 from the semiconductor devices connected in a large number obtained by the sealing (see FIG. 12C) ) Are sequentially executed in the same manner as in the first embodiment, and detailed description thereof is omitted.

母型基板１０の除去後、多数つながった状態の半導体装置に対し、あらかじめ設定され
た切断位置に沿って切断加工を実行し、半導体装置７１を一つ一つ切り離していく。この
半導体装置を切り分ける工程で、切断位置は電極部１１ｆの凹部１１ｇと重なっており、
切断加工の際、硬化した封止材１９が切断されていくと共に、各電極部１１ｆが凹部１１
ｇの位置で順次切断される。 After the removal of the mother substrate 10, the semiconductor devices 71 connected to each other are cut along predetermined cutting positions to separate the semiconductor devices 71 one by one. In the step of cutting the semiconductor device, the cutting position overlaps with the concave portion 11g of the electrode portion 11f.
During the cutting process, the cured sealing material 19 is cut and each electrode portion 11f is recessed 11
Sequential cutting is performed at the position of g.

凹部１１ｇが切断位置となることで、凹部深さの分、切断位置が下がり、従来のように
一様な高さに電極部を形成した場合と比べて、切断加工における金属の切断量を減らすこ
とができ、切断に伴う切断加工用装置の刃部（ダイシングブレード）の摩耗を軽減可能と
なる。 Since the concave portion 11g becomes the cutting position, the cutting position is lowered by the depth of the concave portion, and the amount of metal cut in the cutting process is reduced compared to the case where the electrode portion is formed at a uniform height as in the prior art. Therefore, it is possible to reduce the wear of the blade portion (dicing blade) of the cutting device accompanying cutting.

また、半導体装置の切り分けの際、封止材１９で覆われた表面側から切断位置の位置決
めを行って切断を実行する場合、封止材１９が透明な材質であれば、封止材１９を介して
電極部１１ｆにおける凹部１１ｇを識別できることから、この凹部１１ｇを切断位置の目
印として利用することもでき、精度よく切断加工を実行できる。 Further, when cutting the semiconductor device by positioning the cutting position from the surface side covered with the sealing material 19 and performing the cutting, if the sealing material 19 is a transparent material, the sealing material 19 Since the concave portion 11g in the electrode portion 11f can be identified through this, the concave portion 11g can be used as a mark for the cutting position, and cutting can be performed with high accuracy.

切断されて得られた半導体装置７１の側面には、切断された電極部１１ｆが露出する（
図１３参照）。この電極部１１ｆの、半導体装置側面に露出した部位は、あらかじめ切断
予定箇所に位置するようにして凹部１１ｇを設けられた箇所の下側部分にあたり、凹部１
１ｇの位置において電極部１１ｆはその表面に表面金属層を形成されていないことから、
表面金属層の断面は含んでいない（図１３（Ｂ）参照）。 The cut electrode portion 11f is exposed on the side surface of the semiconductor device 71 obtained by the cutting (see FIG.
(See FIG. 13). The portion of the electrode portion 11f exposed on the side surface of the semiconductor device is the lower portion of the portion where the recess portion 11g is provided in advance so as to be positioned at the planned cutting location.
Since the electrode portion 11f is not formed with a surface metal layer on the surface at the position of 1g,
The cross section of the surface metal layer is not included (see FIG. 13B).

こうして半導体装置の側面には電極部１１ｆの一部が露出するものの、表面金属層は現
れていないことから、表面金属層が例えば銀メッキ等の場合に、表面金属層露出部を起点
とするマイグレーションのような信頼性低下につながる事象の発生を未然に防止できる。
また、側面における電極部１１ｆの露出部分上側には元は凹部１１ｇがあったことで、そ
の近傍で封止材１９で覆われている電極部１１ｆ上面は段差１１ｈのある形状となってお
り（図１３（Ｂ）参照）、その分電極部上面と封止材１９との接触面が、単純な平面の場
合より増えるので、電極部の支持強度が向上し、半導体装置としての耐久性も高められる
。 Thus, although a part of the electrode portion 11f is exposed on the side surface of the semiconductor device, the surface metal layer does not appear. Therefore, when the surface metal layer is, for example, silver plating, the migration starting from the surface metal layer exposed portion The occurrence of an event that leads to a decrease in reliability can be prevented in advance.
Also, the upper side of the exposed portion of the electrode portion 11f on the side surface originally had a recess 11g, and the upper surface of the electrode portion 11f covered with the sealing material 19 in the vicinity thereof has a shape with a step 11h ( 13B), the contact surface between the upper surface of the electrode portion and the sealing material 19 is increased as compared with a simple flat surface, so that the support strength of the electrode portion is improved and the durability as a semiconductor device is also increased. It is done.

（本発明の第３の実施形態）
前記第１の実施形態に係る半導体装置用基板の製造においては、最初の金属部１１の形
成工程で、金属部１１を第一レジスト層１２の厚さを越えない所定厚さまで形成したら、
金属部形成を中断し、金属部１１の上に凹部位置に対応させて第二レジスト層１６を形成
配設し、さらに、この第二レジスト層１６で覆われていない金属部１１の露出部分に対し
、金属部１１を形成する工程を再度行い、適切に配置した第二レジスト層１６により金属
部１１の形状を制御しつつ金属部１１の最終形状を得るようにしているが、この他、第３
の実施形態として、金属部１１を形成する二つの工程の間で、第一レジスト層１２の上の
所定範囲に第二レジスト層１６を形成し（図１４参照）、後の金属部形成工程で、金属部
の形成範囲を第二レジスト層１６で制限して（図１５参照）、金属部１１の上部をあらか
じめ設定された大きさに調整することもできる。 (Third embodiment of the present invention)
In the manufacture of the semiconductor device substrate according to the first embodiment, when the metal part 11 is formed to a predetermined thickness not exceeding the thickness of the first resist layer 12 in the first metal part 11 formation step,
The metal part formation is interrupted, the second resist layer 16 is formed and disposed on the metal part 11 so as to correspond to the position of the concave part, and further, the exposed part of the metal part 11 not covered with the second resist layer 16 is formed. On the other hand, the process of forming the metal part 11 is performed again, and the final shape of the metal part 11 is obtained while controlling the shape of the metal part 11 by the appropriately arranged second resist layer 16. 3
As an embodiment, the second resist layer 16 is formed in a predetermined range on the first resist layer 12 between the two steps of forming the metal portion 11 (see FIG. 14), and in the subsequent metal portion forming step. The formation range of the metal part can be limited by the second resist layer 16 (see FIG. 15), and the upper part of the metal part 11 can be adjusted to a preset size.

例えば、金属部１１が第一レジスト層１２の厚さを越えて形成されることで、第一レジ
スト層１２寄りの金属部１１上端周縁には第一レジスト層１２側に張出した略庇状の張出
し部１１ｉが形成される（図１５（Ａ）参照）。この時、第一レジスト層１２上に第二レ
ジスト層１６が配設されていることで、張出し部１１ｉは、その形成範囲を第二レジスト
層１６で規制され、第二レジスト層１６の側面に接する部位を伴いつつ形成される。結果
として、張出し部１１ｉの張出し量は、あらかじめ設定された第二レジスト層１６の配置
に基づいた所定量に管理されることとなる。 For example, when the metal part 11 is formed beyond the thickness of the first resist layer 12, a substantially bowl-like shape protruding toward the first resist layer 12 is formed at the upper end periphery of the metal part 11 near the first resist layer 12. Overhang portions 11i are formed (see FIG. 15A). At this time, since the second resist layer 16 is disposed on the first resist layer 12, the overhanging portion 11 i is restricted in its formation range by the second resist layer 16, and on the side surface of the second resist layer 16. It is formed with the part which contacts. As a result, the overhang amount of the overhang portion 11i is managed to a predetermined amount based on the arrangement of the second resist layer 16 set in advance.

この場合、母型基板１０上で隣り合う金属部１１のそれぞれが上部に張出し部１１ｉを
備えつつ、これら張出し部１１ｉ同士があらかじめ設定された適切な間隔をなす状態に調
整できることから、母型基板１０上における金属部の配置間隔を従来より小さくすること
ができる。すなわち、従来の工程では金属部１１上部の張出し部の張出し量を厳密に管理
できないため、張出し部同士の間隔が後のレジスト除去を妨げる狭小なものとならないよ
うに金属部１１の配置間隔を広めにとる必要があったのに対し、本実施形態では張出し部
１１ｉの張出し量を第二レジスト層１６の配置で調整できることから、金属部１１の配置
間隔を詰めた場合でも、張出し部１１ｉの張出し量をレジスト除去を問題なく行える程度
に抑えて、隣り合う金属部１１の最小間隔を適切な量とすることができる。 In this case, each of the metal parts 11 adjacent on the mother board 10 is provided with the overhanging part 11i on the upper side, and these overhanging parts 11i can be adjusted to a state having an appropriate preset interval. The arrangement interval of the metal parts on 10 can be made smaller than before. That is, in the conventional process, the amount of overhang of the overhanging portion on the upper portion of the metal portion 11 cannot be strictly controlled. Therefore, the interval between the overhanging portions is widened so that the interval between the overhanging portions does not become narrow enough to prevent subsequent resist removal. However, in this embodiment, since the amount of overhang of the overhanging portion 11i can be adjusted by the arrangement of the second resist layer 16, the overhang of the overhanging portion 11i can be adjusted even when the arrangement interval of the metal portions 11 is reduced. The amount can be suppressed to an extent that the resist can be removed without any problem, and the minimum distance between the adjacent metal portions 11 can be set to an appropriate amount.

なお、金属部の配置間隔は、張出し部１１ｉで抜けに対する十分な強度を得られる必要
最小限の張出し量を確保でき、且つ金属部間に第一レジスト層１２の除去剤が到達して第
一レジスト層１２が適切に除去できる状態が維持される範囲で、小さくすることができる
（図１６参照）。これにより、半導体装置用基板３上で形成される半導体装置の一層の小
型化が図れると共に、半導体装置用基板３上での半導体装置の形成密度を高められ、半導
体装置の製造を効率化できる。 It should be noted that the arrangement interval of the metal portions can secure the minimum amount of overhang that can obtain sufficient strength against the detachment at the overhang portion 11i, and the first resist layer 12 remover reaches between the metal portions and the first interval. The resist layer 12 can be made small as long as the state in which the resist layer 12 can be properly removed is maintained (see FIG. 16). As a result, the semiconductor device formed on the semiconductor device substrate 3 can be further miniaturized, the formation density of the semiconductor devices on the semiconductor device substrate 3 can be increased, and the manufacturing of the semiconductor device can be made more efficient.

こうして第一レジスト層１２の上に第二レジスト層１６を配設して、第二レジスト層１
６で金属部１１の上部形状を調整制御する場合、上記の他に、図１７に示すように、母型
基板上に第一レジスト層１２を形成するのに続いて、第二レジスト層１６を形成し、その
後、金属部を形成する手順で行うこともでき、金属部の形成を一つの工程で行えることで
、製造の能率をさらに高められる。 Thus, the second resist layer 16 is disposed on the first resist layer 12, and the second resist layer 1
6, in the case of adjusting and controlling the upper shape of the metal part 11, in addition to the above, as shown in FIG. 17, the second resist layer 16 is formed following the formation of the first resist layer 12 on the mother substrate. Then, the metal part can be formed by the procedure of forming the metal part, and the metal part can be formed in one step, thereby further improving the production efficiency.

この場合の半導体装置用基板の製造方法としては、母型基板１０の表裏にレジスト層１
２、１８をそれぞれ形成する工程と、さらに第一レジスト層１２の上側で、張出し部１１
ｉとして形成される金属部１１の形成を抑えたい位置に対応させて、第二レジスト層１６
を配設する工程と、母型基板１０表面の第一レジスト層１２や第二レジスト層１６で覆わ
れていない部分に金属部１１を所定厚さまで形成する工程と、金属部１１の表面に表面金
属層１３を形成する工程と、母型基板１０表面側の第一レジスト層１２、第二レジスト層
１６、及び裏面側のレジスト層１８をそれぞれ除去する工程とを含むものであるといえる
。 In this case, as a method for manufacturing a substrate for a semiconductor device, the resist layer 1 is formed on the front and back of the mother substrate 10.
2 and 18, and further on the upper side of the first resist layer 12, the overhang portion 11 is formed.
The second resist layer 16 is made to correspond to the position where the formation of the metal part 11 formed as i is to be suppressed.
A step of forming the metal part 11 to a predetermined thickness on a portion of the surface of the base substrate 10 that is not covered with the first resist layer 12 or the second resist layer 16, and a surface on the surface of the metal part 11 It can be said that the method includes a step of forming the metal layer 13 and a step of removing the first resist layer 12, the second resist layer 16, and the resist layer 18 on the back surface side of the mother substrate 10 respectively.

これらの半導体装置用基板製造の各工程について具体的に説明すると、はじめに、母型
基板１０の表裏にレジスト層１２、１８をそれぞれ形成する工程が実行される点は、前記
第１の実施形態同様であり、詳細な説明を省略する。 The steps of manufacturing the semiconductor device substrate will be described in detail. First, the steps of forming the resist layers 12 and 18 on the front and back surfaces of the mother substrate 10 are executed as in the first embodiment. Therefore, detailed description is omitted.

続いて、第二レジスト層１６を形成する工程では、最初に形成された第一レジスト層１
２の上に、金属部１１の形成を抑えたい範囲に対応させて第二レジスト層１６を配設する
。具体的には、母型基板１０と第一レジスト層１２の表面側に、感光性レジスト剤１６ａ
を、所定厚さ（例えば約５０μｍ）となるようにして密着配設する（図１７（Ｂ）参照）
。この感光性レジスト剤に対し、張出し部１１ｉとしての金属部１１の形成を抑えたい位
置に対応する所定パターンのマスクフィルム５１を載せた状態で、紫外線照射による露光
での硬化（図１７（Ｃ）参照）、非照射部分のレジスト剤を除去する現像等の公知の処理
を行い、金属部１１を形成させない箇所に対応させた第二レジスト層１６を硬化形成する
（図１８（Ａ）参照）。 Subsequently, in the step of forming the second resist layer 16, the first resist layer 1 formed first.
A second resist layer 16 is disposed on 2 in correspondence with a range in which formation of the metal part 11 is desired to be suppressed. Specifically, the photosensitive resist agent 16a is formed on the surface side of the matrix substrate 10 and the first resist layer 12.
Are closely attached so as to have a predetermined thickness (for example, about 50 μm) (see FIG. 17B).
. The photosensitive resist agent is cured by exposure by ultraviolet irradiation with a mask film 51 having a predetermined pattern corresponding to a position where the formation of the metal part 11 as the overhanging part 11i is desired to be suppressed (FIG. 17C). And a known process such as development for removing the resist agent in the non-irradiated part is performed to cure and form the second resist layer 16 corresponding to the part where the metal part 11 is not formed (see FIG. 18A).

第二レジスト層１６を形成したら、母型基板１０表面の第一レジスト層１２並びに第二
レジスト層１６で覆われていない露出部分に対し、必要に応じて公知の表面酸化被膜除去
や表面活性化処理を行う。その後、この露出部分にメッキ等によりハンダぬれ性改善用の
金の薄膜１１ｄを、例えば０．０５〜１μｍ厚で形成する（図１８（Ｂ）参照）。そして
、この薄膜１１ｄ上に、電解メッキによりニッケルを積層して金属部１１を形成する（図
１８（Ｃ）参照） Once the second resist layer 16 is formed, known surface oxide film removal and surface activation are performed on the first resist layer 12 on the surface of the base substrate 10 and the exposed portions not covered with the second resist layer 16 as necessary. Process. Thereafter, a gold thin film 11d for improving solder wettability is formed on the exposed portion by plating or the like with a thickness of, for example, 0.05 to 1 μm (see FIG. 18B). Then, nickel is laminated on the thin film 11d by electrolytic plating to form the metal part 11 (see FIG. 18C).

この金属部１１の形成工程で、金属部１１は、第一レジスト層１２の厚さを越える一方
、第二レジスト層１６の上面を越えない所定厚さ（例えば、厚さ約６０μｍ）として形成
され、第一レジスト層１２寄りの金属部１１上端周縁には、第一レジスト層１２側に張出
した略庇状の張出し部１１ｉが、第二レジスト層１６の側面に接する部位を伴いつつ形成
される（図１８（Ｃ）参照）。この張出し部１１ｉの形成範囲は、金属部１１が形成され
ないように配置された第二レジスト層１６で規制されることから、張出し部１１ｉの張出
し量はあらかじめ設定されたものとなる。また、金属部１１は、前記第１の実施形態同様
、母型基板１０表面において、半導体素子搭載部１１ａとその近傍に複数配置される電極
部１１ｂの組合わせを一つの単位として、製造する半導体装置の数だけ前記組合わせが多
数整列状態で並べられた形態で形成されることとなる。 In the formation process of the metal part 11, the metal part 11 is formed to have a predetermined thickness (for example, a thickness of about 60 μm) that exceeds the thickness of the first resist layer 12 but does not exceed the upper surface of the second resist layer 16. A substantially bowl-shaped protruding portion 11 i that protrudes toward the first resist layer 12 is formed on the periphery of the upper end of the metal portion 11 near the first resist layer 12 with a portion that contacts the side surface of the second resist layer 16. (See FIG. 18C). The formation range of the overhang portion 11i is regulated by the second resist layer 16 disposed so that the metal portion 11 is not formed, and thus the overhang amount of the overhang portion 11i is set in advance. Further, as in the first embodiment, the metal part 11 is a semiconductor that is manufactured on the surface of the base substrate 10 with a combination of the semiconductor element mounting part 11a and a plurality of electrode parts 11b arranged in the vicinity thereof as one unit. As many combinations as the number of devices are formed in an aligned state.

金属部１１を所定厚さまで形成した後の、金属部１１の表面に表面金属層１３を形成す
る工程（図１９（Ａ）参照）、並びに、母型基板１０表面側の第一レジスト層１２、第二
レジスト層１６、及び裏面側のレジスト層１８をそれぞれ除去する工程（図１９（Ｂ）参
照）を経て、半導体装置用基板４の完成に至る点は、前記第１の実施形態同様である。 A step of forming a surface metal layer 13 on the surface of the metal part 11 after the metal part 11 is formed to a predetermined thickness (see FIG. 19A), and a first resist layer 12 on the surface of the mother substrate 10; Similar to the first embodiment, the second resist layer 16 and the resist layer 18 on the back side are removed (see FIG. 19B) and the semiconductor device substrate 4 is completed. .

このように、母型基板１０上に第一レジスト層１２を形成する工程に続いて、第二レジ
スト層１６を形成し、その後に金属部１１を形成するようにすることで、前記同様に第一
レジスト層１２上側に達する金属部１１（張出し部１１ｉ）の形成範囲を制御できること
に加え、各レジスト層を先にまとめて形成し、金属部１１の形成を一工程で行うことで、
第二レジスト層１６形成後の、既存の金属部１１に対し清浄化等の処理を行った上で金属
部の形成を再開する工程を省略できるなど、生産効率の向上が図れることとなる。 In this manner, following the step of forming the first resist layer 12 on the base substrate 10, the second resist layer 16 is formed, and then the metal portion 11 is formed. In addition to being able to control the formation range of the metal part 11 (overhanging part 11i) reaching the upper side of one resist layer 12, by forming each resist layer together first and forming the metal part 11 in one step,
After the second resist layer 16 is formed, the process of cleaning the existing metal part 11 and the process of restarting the formation of the metal part can be omitted. For example, production efficiency can be improved.

なお、母型基板１０上に第一レジスト層１２を形成する工程に続いて、第二レジスト層
１６を形成し、その後に金属部１１を形成する前記一連の工程を、半導体素子搭載部や電
極部となる金属部の一部に適用して、金属部に貫通孔を生じさせることもできる。具体的
には、金属部における貫通孔を設けたい箇所に第一レジスト層１２を形成し、さらにその
上に第二レジスト層１６を配設し、金属部の形成工程で、各レジスト層の周囲に金属部を
形成するようにすれば、適切に配置した第二レジスト層１６により上部開口形状を調整さ
れた貫通孔が、レジスト除去後に生じることとなる。孔の大きさが金属部１１の第一レジ
スト層１２側への張出しの量に比べて十分大きい場合には、第二レジスト層１６を設けず
第一レジスト層１２のみ孔位置に形成して、孔を生じさせるようにしてもよい。 In addition, following the process of forming the first resist layer 12 on the base substrate 10, the series of processes of forming the second resist layer 16 and then forming the metal part 11 are performed by the semiconductor element mounting part and the electrode. By applying to a part of the metal part to be a part, a through hole can be formed in the metal part. Specifically, the first resist layer 12 is formed at a location where the through hole is to be provided in the metal portion, and the second resist layer 16 is further disposed thereon, and in the metal portion forming step, the periphery of each resist layer is formed. If the metal portion is formed in the through hole, a through hole whose upper opening shape is adjusted by the appropriately arranged second resist layer 16 is formed after the resist is removed. When the size of the hole is sufficiently larger than the amount of protrusion of the metal part 11 to the first resist layer 12 side, only the first resist layer 12 is formed at the hole position without providing the second resist layer 16; You may make it produce a hole.

この他、金属部の凹部を設ける箇所と重なるように貫通孔を設けるようにしてもよく、
例として、隣り合う半導体装置の各電極部となる金属部間に貫通孔を設ける場合を説明す
ると、まず母型基板１０上に第一レジスト層１２を形成した後、金属部１１を所定厚さま
で形成し、凹部及び貫通孔としたい箇所に第二レジスト層１６を形成する。凹部と貫通孔
の両方を生じさせる箇所では、第二レジスト層は金属部と第一レジスト層とに跨るように
形成されることとなる。 In addition, a through hole may be provided so as to overlap with a place where the concave portion of the metal part is provided,
As an example, a case where a through hole is provided between metal parts serving as electrode parts of adjacent semiconductor devices will be described. First, after the first resist layer 12 is formed on the matrix substrate 10, the metal part 11 is made to a predetermined thickness. The second resist layer 16 is formed at the locations where the recesses and through holes are to be formed. At the location where both the recess and the through hole are generated, the second resist layer is formed so as to straddle the metal portion and the first resist layer.

その後、さらに金属部の追加形成、表面金属層形成の各工程を実行し（図２０（Ａ）参
照）、最終的に各レジスト層を除去すると、凹部１１ｊ及び貫通孔１１ｋの生じた半導体
装置用基板５が得られる（図２０（Ｂ）参照）。図２０に示した例では、半導体装置の製
造工程で、封止後に個々の半導体装置を切り分ける際の切断加工で電極部１１ｌ間の除去
される部位に、ちょうど貫通孔１１ｋが位置するようにされており、切断の際に、貫通孔
部分に存在する封止材１９が除去される結果、切断されて得られた半導体装置７２の側面
に電極部１１ｌの一部が露出する（図２０（Ｃ）参照）。貫通孔１１ｋが切断位置となる
ことで、前記第２の実施形態と同様に半導体装置の側面に電極部を露出させる構成を得る
場合でも、切断加工において金属の切断を行わずに済むこととなり、切断に伴う切断加工
用装置の刃部（ダイシングブレード）の摩耗を軽減できる。 Thereafter, further steps of additional formation of the metal portion and formation of the surface metal layer are performed (see FIG. 20A). Finally, when each resist layer is removed, for the semiconductor device in which the recess 11j and the through hole 11k are generated. A substrate 5 is obtained (see FIG. 20B). In the example shown in FIG. 20, in the semiconductor device manufacturing process, the through-hole 11k is positioned exactly at a portion that is removed between the electrode portions 11l by cutting processing when individual semiconductor devices are cut after sealing. As a result of removal of the sealing material 19 present in the through-hole portion at the time of cutting, a part of the electrode portion 11l is exposed on the side surface of the semiconductor device 72 obtained by cutting (FIG. 20C )reference). When the through hole 11k is at the cutting position, even when a configuration in which the electrode portion is exposed on the side surface of the semiconductor device as in the second embodiment is obtained, it is not necessary to cut the metal in the cutting process. Wear of the blade portion (dicing blade) of the cutting device accompanying cutting can be reduced.

１、２、３、４ 半導体装置用基板
１０ 母型基板
１１ 金属部
１１ａ 半導体素子搭載部
１１ｂ、１１ｆ 電極部
１１ｃ、１１ｉ 張出し部
１１ｄ 薄膜
１１ｅ、１１ｇ 凹部
１１ｈ 段差
１１ｊ 凹部
１１ｋ 貫通孔
１１ｌ 電極部
１２ 第一レジスト層
１２ａ レジスト剤
１３ 表面金属層
１４ 半導体素子
１５ ワイヤ
１６ 第二レジスト層
１６ａ レジスト剤
１８ レジスト層
１９ 封止材
５０、５１ マスクフィルム
７０、７１、７２ 半導体装置 1, 2, 3, 4 Semiconductor device substrate 10 Mother substrate 11 Metal portion 11a Semiconductor element mounting portion 11b, 11f Electrode portion 11c, 11i Overhang portion 11d Thin film 11e, 11g Recess 11h Step 11j Recess 11k Through hole 11l Electrode portion 12 First resist layer 12a Resist agent 13 Surface metal layer 14 Semiconductor element 15 Wire 16 Second resist layer 16a Resist agent 18 Resist layer 19 Sealant 50, 51 Mask film 70, 71, 72 Semiconductor device

本発明の開示に係る半導体装置用基板は、半導体素子搭載部及び／又は電極部となる金属部を備える半導体装置の製造に用いられ、母型基板上に前記金属部が形成される半導体装置用基板において、前記金属部の表面側に凹部が設けられるものである。詳しくは、母型基板上に少なくとも前記金属部における前記電極部が形成される半導体装置用基板であって、電極部の表面側に凹部が設けられており、電極部の表面側には、凹部に面する表面を除いて、表面金属層が形成されているものである。さらに、金属部における電極部の少なくとも一部が、個々の半導体装置ごとに切り離す切断加工での切断予定箇所に跨って位置し、切断加工時に切断される配置として母型基板上に形成されており、電極部の凹部が切断予定箇所に位置し、切断加工時に除去される部位を含んで所定の大きさとして設けられているものである。 The semiconductor device substrate according to the disclosure of the present invention is used in the manufacture of a semiconductor device including a Rukin genus portions such as semi-conductor element mounting portion and / or the electrode portion, the metal portion is made form a matrix on a substrate In the semiconductor device substrate, a concave portion is provided on the surface side of the metal portion. Specifically, the substrate for a semiconductor device has at least the electrode part of the metal part formed on a matrix substrate, and a recess is provided on the surface side of the electrode part, and a recess is provided on the surface side of the electrode part. The surface metal layer is formed except for the surface facing the surface. Further, at least a part of the electrode part in the metal part is located over the planned cutting position in the cutting process for each individual semiconductor device, and is formed on the mother board as an arrangement to be cut during the cutting process. The concave portion of the electrode portion is located at a planned cutting location, and is provided in a predetermined size including a portion to be removed during the cutting process.

このように本発明の開示によれば、母型基板上に形成される金属部である半導体素子搭載部及び／又は電極部に凹部が設けられ、半導体素子搭載部及び／又は電極部における凹部の下側部分の厚さを小さくすることにより、半導体装置用基板を用いた半導体装置の製造にあたり、凹部で変化を加えた金属部の表面形状に応じて、半導体装置の構造に好ましい特長を付与でき、例えば凹部で金属部の表面積が増える分、金属部と半導体装置の封止材との接触面積を増やして、金属部の一体化の強度を高められる。また、半導体素子搭載部に凹部を設けるようにすれば、半導体素子の配設位置の設定に柔軟性を与えられ、製造される半導体装置の構造の自由度を大きくすることができる。さらに、半導体装置同士の切り離し位置に配置される金属部に凹部を設けるようにすれば、半導体装置の切り離しの際の金属の切断量を減らすことができ、切断装置の損耗を抑えられる。そして、電極部の表面側に凹部を設け、この電極部の表面側には、凹部に面する表面を除いて、表面金属層を形成することにより、凹部下側部分の厚さが、金属部の厚さ以上に厚くならないようにして、凹部下側部分の厚さ削減を確実なものとすると共に、半導体装置用基板で製造された半導体装置の側面に切断に伴って電極部が一部露出する場合でも、凹部のある位置で切断される電極部の切断面には表面金属層が露出することはなく、表面金属層露出部を起点とするマイグレーションのような信頼性低下につながる事象の発生を未然に防止できる。また、金属部における電極部の少なくとも一部が、個々の半導体装置ごとに切り離す切断加工での切断予定箇所に跨って位置し、切断加工時に切断される配置として母型基板上に形成され、電極部の凹部が切断予定箇所に位置し、切断加工時に除去される部位を含んで所定の大きさとして設けられていることにより、電極部の凹部深さの分、切断位置が下がり、しかも、この電極部の凹部に面する表面には表面金属層が形成されていないため、切断加工における金属の切断量を減らすことができ、切断に伴う切断加工用装置の負担を減らし、刃部の劣化を抑えられる。加えて、切断面の近傍で電極部上面は凹部に伴う段差のある形状となっており、その分電極部上面と半導体装置の封止材とが広く接触することとなり、半導体装置における電極部の支持強度が向上し、耐久性を高められる。 Thus, according to the disclosure of the present invention, a recess is provided in the semiconductor element mounting portion and / or the electrode portion, which is a metal portion formed on the matrix substrate, and the recess in the semiconductor element mounting portion and / or the electrode portion is formed. By reducing the thickness of the lower part, it is possible to give favorable features to the structure of the semiconductor device according to the surface shape of the metal part that has been changed in the recess when manufacturing the semiconductor device using the substrate for the semiconductor device. For example, by increasing the surface area of the metal part at the concave part, the contact area between the metal part and the sealing material of the semiconductor device can be increased to increase the strength of the integration of the metal part. Further, if the concave portion is provided in the semiconductor element mounting portion, flexibility in setting the arrangement position of the semiconductor element can be given, and the degree of freedom of the structure of the manufactured semiconductor device can be increased. Furthermore, if the concave portion is provided in the metal portion disposed at the position where the semiconductor devices are separated from each other, the amount of metal cut when the semiconductor device is separated can be reduced, and wear of the cutting device can be suppressed. Then, a concave portion is provided on the surface side of the electrode portion, and a surface metal layer is formed on the surface side of the electrode portion excluding the surface facing the concave portion, whereby the thickness of the lower portion of the concave portion is reduced to the metal portion. The thickness of the lower part of the recess is surely reduced and the electrode part is partially exposed on the side surface of the semiconductor device manufactured by the semiconductor device substrate. Even if it is, the surface metal layer is not exposed on the cut surface of the electrode part that is cut at the position where there is a recess, and the occurrence of an event that leads to reliability degradation such as migration starting from the exposed surface metal layer part Can be prevented. Further, at least a part of the electrode part in the metal part is located over the planned cutting position in the cutting process for separating each individual semiconductor device, and is formed on the matrix substrate as an arrangement to be cut at the time of the cutting process. The concave portion of the part is located at the planned cutting position, and is provided as a predetermined size including the part to be removed at the time of cutting, so that the cutting position is lowered by the amount of the concave part of the electrode part, and this Since the surface metal layer is not formed on the surface facing the recess of the electrode part, it is possible to reduce the amount of metal cutting in the cutting process, reduce the burden on the cutting apparatus accompanying the cutting, and reduce the deterioration of the blade part. It can be suppressed. In addition, in the vicinity of the cut surface, the upper surface of the electrode portion has a stepped shape associated with the recess, and the upper surface of the electrode portion and the sealing material of the semiconductor device are in wide contact with each other. Support strength is improved and durability is increased.

この他、本発明の開示に係る半導体装置用基板は、必要に応じて、前記凹部が、金属部のうち少なくとも半導体素子搭載部に、凹部内に半導体素子を挿入し且つ凹部底部に半導体素子を載置可能な大きさとして設けられるものである。 In addition, in the semiconductor device substrate according to the disclosure of the present invention, if necessary, the recess includes at least the semiconductor element mounting portion of the metal portion, the semiconductor element is inserted into the recess, and the semiconductor element is disposed at the bottom of the recess. It is provided as a size that can be placed.

また、本発明の開示に係る半導体装置用基板の製造方法は、半導体素子搭載部及び／又は電極部となる金属部を備える半導体装置の製造に用いられ、母型基板上に少なくとも前記金属部における前記電極部が形成されており、前記電極部の表面側に、凹部が設けられ、前記電極部の表面側には、前記凹部に面する表面を除いて、表面金属層が形成されてあって、母型基板上に、少なくとも金属部における電極部の非配置部分に対応させた第一レジスト層を形成する工程と、母型基板の第一レジスト層で覆われていない露出部分に対し、金属部を形成する工程と、金属部上に凹部を生じさせる箇所に対応させた第二レジスト層を形成する工程と、第二レジスト層で覆われていない金属部の露出部分に対し、金属部を積層形成する工程と、第二レジスト層で覆われていない金属部の露出部分に対し、表面金属層を形成する工程とを備えるものである。さらに、第二レジスト層は、中断時点の金属部のうち最終的に電極部となるものの上側所定部位に、複数の電極部にわたる略線状配置で形成されているものである。 A method of manufacturing a substrate for a semiconductor device according to the disclosure of the present invention is used in the manufacture of a semiconductor device including a Rukin genus portions such as semi-conductor element mounting portion and / or the electrode portion, at least the the matrix substrate the electrode portions of the metal part is formed, on the surface side of the electrode portion, the recess is provided on the surface side of the electrode portion, with the exception of the surface facing the recess, the surface metal layer is formed Therefore, a step of forming a first resist layer corresponding to at least a non-arranged portion of the electrode portion in the metal portion on the mother substrate, and an exposed portion not covered with the first resist layer of the mother substrate. On the other hand, with respect to the step of forming the metal part, the step of forming the second resist layer corresponding to the location where the recess is formed on the metal part, and the exposed part of the metal part not covered with the second resist layer, A step of laminating and forming a metal part; To the exposed portion of the metal part which is not covered by the strike layer, in which and forming a surface metal layer. Further, the second resist layer is formed in a substantially linear arrangement over a plurality of electrode portions at a predetermined upper portion of the metal portion at the time of interruption that finally becomes the electrode portion.

このように本発明の開示によれば、金属部の形成において別のレジスト層（第二レジスト層）を用いて金属部の形成領域を一部規制して、レジスト除去後の金属部表面に別のレジスト層に基づく形状を付与できることにより、金属部の形成範囲をレジスト層（第一レジスト層）だけでなく上側の別のレジスト層も併用してより正確に規定して、金属部を母型基板上により精細な配置とすることができると共に、金属部の構造の自由度が増すこととなり、半導体装置用基板を用いて製造される半導体装置を、金属部の構造に基づいて改良できる。さらに、別のレジスト層を金属部のうち電極部となる部位に配設して、最終的に形成された金属部の電極部の切断加工対象位置に並んだ凹部を生じさせることにより、レジスト形状の設定で所望の凹部を配置できることに加え、得られた半導体装置用基板を用いて半導体装置を製造する際に、凹部のある電極部を切断するようにして各半導体装置を切り離す場合、電極部の凹部下側の部位が薄くされる分、切断加工の負荷を小さくすることができ、切断装置の損耗を抑えられる。 Thus, according to the disclosure of the present invention, in forming the metal part, a part of the metal part forming region is regulated by using another resist layer (second resist layer), and the metal part surface after the resist removal is separated. The shape based on the resist layer can be given, so that the formation range of the metal part can be defined more precisely by using not only the resist layer (first resist layer) but also another resist layer on the upper side, and the metal part can be used as a matrix A finer arrangement can be achieved on the substrate, and the degree of freedom of the structure of the metal portion is increased, so that a semiconductor device manufactured using the substrate for a semiconductor device can be improved based on the structure of the metal portion. Furthermore, another resist layer is disposed in the portion to be the electrode portion of the metal portion, thereby forming a concave portion aligned with the position to be cut of the electrode portion of the finally formed metal portion. In addition to being able to arrange the desired recesses in the setting of, when manufacturing a semiconductor device using the obtained substrate for a semiconductor device, when separating each semiconductor device by cutting the electrode portion having the recesses, the electrode portion Since the portion below the concave portion is made thinner, the cutting processing load can be reduced, and the wear of the cutting device can be suppressed.

この他、本発明の開示に係る半導体装置用基板の製造方法は、必要に応じて、前記別のレジスト層が、前記中断時点の金属部のうち最終的に半導体素子搭載部となるものの上側所定部位に形成され、前記別のレジスト層の形成後、金属部の形成再開で、金属部が別のレジスト層の側面に接する部位を伴って形成され、形成終了後、最終的に別のレジスト層を除去して、金属部の半導体素子搭載部における、別のレジスト層が存在していた部位に、穴又は溝状の凹部を生じさせるものである。 In addition, in the method for manufacturing a substrate for a semiconductor device according to the disclosure of the present invention, if necessary, the another resist layer may be a predetermined upper side of the metal part at the time of the interruption that eventually becomes a semiconductor element mounting part. After the formation of the another resist layer, the formation of the metal part is resumed, and the metal part is formed with the part in contact with the side surface of the other resist layer. Is removed, and a hole or a groove-like recess is formed in a portion where another resist layer is present in the semiconductor element mounting portion of the metal portion.

また、本発明の開示に係る半導体装置は、半導体素子搭載部及び／又は電極部となる金属部を有し、少なくとも当該金属部における電極部表面に表面金属層が形成され、金属部表面側への半導体素子搭載及び配線、封止材による封止がなされる半導体装置において、電極部の表面側に凹部が設けられ、電極部の表面には、凹部に面する表面を除いて、表面金属層が形成されているものである。さらに、封止材のいずれかの側面から電極部の端面が露出しており、電極部の凹部が個々の半導体装置ごとに切り離す切断加工での切断予定箇所に位置し、電極部の端面が凹部のあった位置の下側部分の断面であり、表面金属層の断面を含まないものである。 The semiconductor device according to the disclosure of the present invention, has a Rukin genus portion such as a semiconductor element mounting portion and / or the electrode portion, the surface metal layer is formed on the electrode portion surface in at least the metal part, the metal part surface the semiconductor element mounting and wiring to the side, in the semiconductor device sealing with sealing material is done, the recess is provided on the surface side of the electrode portion on the surface of the electrode portion, with the exception of the surface facing the recess, A surface metal layer is formed . Furthermore, the end surface of the electrode part is exposed from one of the side surfaces of the sealing material, and the recessed part of the electrode part is located at the planned cutting position in the cutting process for separating each individual semiconductor device, and the end surface of the electrode part is recessed. This is a cross-section of the lower portion of the position where there is a defect, and does not include the cross-section of the surface metal layer.

このように本発明の開示によれば、半導体装置を構成する金属部のうち電極部にあらかじめ凹部が設けられて、凹部を切断加工対象位置とされて個々の半導体装置に切り離された際に、端部に電極部の凹部位置の切断面が現れていることにより、電極部の露出部分は元の凹部の下側にあたる部分となり、表面金属層が現れないこととなり、表面金属層露出部分を起点とするマイグレーションを未然に防止できる上、切断加工に伴って側端部に位置する電極部は凹部のある位置とされた分、封止部分との接触面が増えるので強度を高められ、半導体装置としての耐久性や信頼性も高められる。 As described above, according to the disclosure of the present invention, when the concave portion is provided in advance in the electrode portion of the metal portion constituting the semiconductor device and the concave portion is set as a cutting processing target position and separated into individual semiconductor devices, Since the cut surface at the concave portion of the electrode portion appears at the end, the exposed portion of the electrode portion becomes a portion below the original concave portion, the surface metal layer does not appear, and the surface metal layer exposed portion is the starting point. In addition to being able to prevent migration, the electrode portion located at the side end portion along with the cutting process has a recessed portion, so that the contact surface with the sealing portion increases, so the strength can be increased, and the semiconductor device As a result, durability and reliability can be improved.

この他、本発明の開示に係る半導体装置は、半導体素子搭載部及び電極部となる各金属部を有し、当該金属部表面の少なくとも一部にメッキにより表面金属層を形成され、金属部表面側への半導体素子搭載及び配線、封止材による封止がなされ、装置底部に前記金属部の裏面側が露出した状態とされる半導体装置において、前記金属部のうち半導体素子搭載部における表面側に半導体素子より広い大きさの凹部が設けられ、当該凹部に面する表面には前記表面金属層を形成されない状態とされ、前記凹部が、半導体素子を挿入配置され、半導体素子ごと封止材により封止されるものである。In addition, the semiconductor device according to the disclosure of the present invention has a metal part to be a semiconductor element mounting part and an electrode part, and a surface metal layer is formed by plating on at least a part of the surface of the metal part. In a semiconductor device in which the semiconductor element is mounted on the side and sealed with a wiring and a sealing material, and the back side of the metal part is exposed at the bottom of the apparatus, the metal part has a surface on the surface side in the semiconductor element mounting part. A recess having a size larger than that of the semiconductor element is provided, and the surface metal layer is not formed on the surface facing the recess. The recess is inserted and disposed in the recess, and the entire semiconductor element is sealed with a sealing material. It will be stopped.

このように本発明の開示によれば、半導体装置を構成する金属部のうち、半導体素子を搭載する半導体素子搭載部に凹部が設けられていることで、半導体素子を半導体素子搭載部の凹部に挿入配設した場合、従来のように半導体素子搭載部の上面に搭載される場合と比べて、配設位置を下げることができ、半導体素子上面や、電極部と半導体素子とを接合するワイヤ等の高さも下がる分、半導体装置の厚さを小さくすることができ、半導体装置の低背化を実現できる。また、半導体素子の位置が下がって、ワイヤが接合する半導体素子と電極部の各上面が互いに近付く分、ワイヤ長さも短くすることができ、ワイヤ使用量を削減して半導体装置のコストを低減できる。 As described above, according to the disclosure of the present invention, among the metal portions constituting the semiconductor device, the semiconductor element mounting portion on which the semiconductor element is mounted is provided with the recess, so that the semiconductor element is formed in the recess of the semiconductor element mounting portion. In the case of insertion and arrangement, the arrangement position can be lowered as compared with the case where it is mounted on the upper surface of the semiconductor element mounting portion as in the past, and the upper surface of the semiconductor element, wires for joining the electrode portion and the semiconductor element, etc. Therefore, the thickness of the semiconductor device can be reduced and the height of the semiconductor device can be reduced. In addition, as the position of the semiconductor element is lowered and the semiconductor element to which the wire is joined and the upper surfaces of the electrode portions approach each other, the wire length can be shortened, and the cost of the semiconductor device can be reduced by reducing the amount of wire used. .

Claims (10)

装置底部に半導体素子搭載部及び電極部となる各金属部が露出する半導体装置の製造に
用いられ、母型基板上に前記金属部がそれぞれ形成される半導体装置用基板において、
前記金属部が、表面側に凹部を設けられることを
特徴とする半導体装置用基板。 In a semiconductor device substrate used for manufacturing a semiconductor device in which each metal portion to be a semiconductor element mounting portion and an electrode portion is exposed at the bottom of the device, and the metal portion is formed on a mother substrate, respectively.
A substrate for a semiconductor device, wherein the metal part is provided with a concave part on the surface side. 前記請求項１に記載の半導体装置用基板において、
前記凹部が、金属部のうち少なくとも半導体素子搭載部に、凹部内に半導体素子を挿入
し且つ凹部底部に半導体素子を載置可能な大きさとして設けられることを
特徴とする半導体装置用基板。 The semiconductor device substrate according to claim 1,
The substrate for a semiconductor device, wherein the recess is provided in at least a semiconductor element mounting portion of the metal portion so that the semiconductor element can be inserted into the recess and the semiconductor element can be placed on the bottom of the recess. 前記請求項１に記載の半導体装置用基板において、
前記金属部における電極部の少なくとも一部が、基板上に設計される半導体装置位置の
うち、個々の半導体装置ごとに切り離す切断加工を経て各半導体装置の側端位置となる切
断予定箇所に跨って、前記切断加工時に切断される配置として基板上に形成され、
前記凹部が、切断予定箇所に位置する電極部に、電極部の切断加工により除去される部
位を含んで所定の大きさとして設けられることを
特徴とする半導体装置用基板。 The semiconductor device substrate according to claim 1,
At least a part of the electrode part in the metal part straddles a planned cutting position to be a side end position of each semiconductor device through a cutting process for cutting each semiconductor device among semiconductor device positions designed on the substrate. , Formed on the substrate as an arrangement to be cut during the cutting process,
A substrate for a semiconductor device, wherein the concave portion is provided in a predetermined size in an electrode portion located at a planned cutting location, including a portion that is removed by cutting the electrode portion. 前記請求項１ないし３のいずれかに記載の半導体装置用基板において、
前記金属部が、少なくとも上側の表面にメッキによる表面金属層を形成される一方、前
記凹部に面する表面には前記表面金属層を形成されないことを
特徴とする半導体装置用基板。 The substrate for a semiconductor device according to any one of claims 1 to 3,
The semiconductor device substrate, wherein the metal portion is formed with a surface metal layer by plating on at least the upper surface, and the surface metal layer is not formed on the surface facing the recess. 母型基板上の所定部位にレジスト層を形成し、レジスト層の非形成部位に、半導体装置
の半導体素子搭載部及び電極部となる各金属部をメッキの手法で形成して、当該金属部が
底部に露出する構造の半導体装置の製造に用いることのできる基板を得る、半導体装置用
基板の製造方法において、
前記金属部を、レジスト層を越えない所定高さまで形成する工程と、
形成した金属部及び／又はレジスト層の上側の所定部位に、別のレジスト層を新たに形
成する工程と、
形成された前記別のレジスト層に対し、当該別のレジスト層の非形成部位で金属部の形
成を再開して、別のレジスト層を越えない所定高さまで金属部を追加で形成する工程と、
前記レジスト層及び別のレジスト層をそれぞれ除去する工程を備えて、
前記別のレジスト層で設定された所定形状が表面に現れた金属部を得ることを
特徴とする半導体装置用基板の製造方法。 A resist layer is formed in a predetermined part on the base substrate, and each metal part to be a semiconductor element mounting part and an electrode part of the semiconductor device is formed in a part where the resist layer is not formed by a plating method. In a method for manufacturing a substrate for a semiconductor device, a substrate that can be used for manufacturing a semiconductor device having a structure exposed at the bottom is obtained.
Forming the metal part to a predetermined height not exceeding the resist layer;
A step of newly forming another resist layer in a predetermined portion above the formed metal part and / or resist layer;
For the formed another resist layer, restarting the formation of the metal part at the non-formation site of the other resist layer, and additionally forming the metal part to a predetermined height not exceeding the other resist layer;
A step of removing each of the resist layer and another resist layer,
A method for producing a substrate for a semiconductor device, comprising: obtaining a metal portion having a predetermined shape set on the other resist layer appearing on a surface thereof. 前記請求項５に記載の半導体装置用基板の製造方法において、
前記別のレジスト層が、前記中断時点の金属部のうち最終的に半導体素子搭載部となる
ものの上側所定部位に形成され、
前記別のレジスト層の形成後、金属部の形成再開で、金属部が別のレジスト層の側面に
接する部位を伴って形成され、形成終了後、最終的に別のレジスト層を除去して、金属部
の半導体素子搭載部における、別のレジスト層が存在していた部位に、穴又は溝状の凹部
を生じさせることを
特徴とする半導体装置用基板の製造方法。 In the manufacturing method of the board | substrate for semiconductor devices of the said Claim 5,
The another resist layer is formed at a predetermined upper portion of the metal portion at the time of the interruption and finally becomes a semiconductor element mounting portion,
After the formation of the other resist layer, the formation of the metal part is resumed, and the metal part is formed with a portion in contact with the side surface of the other resist layer.After the formation is completed, the other resist layer is finally removed, A method for manufacturing a substrate for a semiconductor device, wherein a hole or a groove-like recess is formed in a portion where another resist layer is present in a semiconductor element mounting portion of a metal portion. 前記請求項５に記載の半導体装置用基板の製造方法において、
前記別のレジスト層が、前記中断時点の金属部のうち最終的に電極部となるものの上側
所定部位に、複数の電極部にわたる略線状配置で形成され、
前記別のレジスト層の形成後、金属部の形成再開で、金属部が別のレジスト層の側面に
接する部位を伴って形成され、形成終了後、最終的に別のレジスト層を除去して、金属部
の電極部における、別のレジスト層が存在していた部位に、複数の電極部にわたって直列
に並ぶ配置となる溝状の凹部をそれぞれ生じさせることを
特徴とする半導体装置用基板の製造方法。 In the manufacturing method of the board | substrate for semiconductor devices of the said Claim 5,
The another resist layer is formed in a substantially linear arrangement over a plurality of electrode portions on the upper predetermined portion of the metal portion at the time of interruption, which finally becomes the electrode portion,
After the formation of the other resist layer, the formation of the metal part is resumed, and the metal part is formed with a portion in contact with the side surface of the other resist layer.After the formation is completed, the other resist layer is finally removed, A method of manufacturing a substrate for a semiconductor device, characterized in that a groove-like recess that is arranged in series across a plurality of electrode portions is formed in a portion where another resist layer is present in an electrode portion of a metal portion. . 半導体素子搭載部及び電極部となる各金属部を有し、当該金属部表面の少なくとも一部
にメッキにより表面金属層を形成され、金属部表面側への半導体素子搭載及び配線、封止
材による封止がなされ、装置底部に前記金属部の裏面側が露出した状態とされる半導体装
置において、
前記金属部のうち半導体素子搭載部における表面側に半導体素子より広い大きさの凹部
が設けられ、当該凹部に面する表面には前記表面金属層を形成されない状態とされ、
前記凹部が、半導体素子を挿入配置され、半導体素子ごと封止材により封止されること
を
特徴とする半導体装置。 It has each metal part which becomes a semiconductor element mounting part and an electrode part, and a surface metal layer is formed by plating on at least a part of the surface of the metal part. In the semiconductor device in which sealing is made and the back side of the metal part is exposed at the bottom of the device,
A recess having a size larger than that of the semiconductor element is provided on the surface side of the semiconductor element mounting portion of the metal portion, and the surface metal layer is not formed on the surface facing the recess,
A semiconductor device, wherein the recess is inserted and disposed with a semiconductor element, and the semiconductor element is sealed with a sealing material. 半導体素子搭載部及び電極部となる各金属部を有し、当該金属部表面の少なくとも一部
にメッキにより表面金属層を形成され、金属部表面側への半導体素子搭載及び配線、封止
材による封止がなされ、装置底部に前記金属部の裏面側が露出した状態とされる半導体装
置において、
少なくともいずれかの側面が、複数の半導体装置の集合形成状態から個々の半導体装置
を切り離す切断加工により生じた切断面であり、切断加工を受けて切断面の一部として露
出した電極部を有し、
当該側面に露出した電極部が、前記切断加工での切断予定箇所に位置する電極部の表面
側にあらかじめ凹部を設けられてなり、当該凹部に面する表面には前記表面金属層を形成
されず、
前記側面に露出した電極部の表面が、元の凹部のあった位置の下側部分の断面であり、
表面金属層の断面を一切含まないことを
特徴とする半導体装置。 It has each metal part which becomes a semiconductor element mounting part and an electrode part, and a surface metal layer is formed by plating on at least a part of the surface of the metal part. In the semiconductor device in which sealing is made and the back side of the metal part is exposed at the bottom of the device,
At least one of the side surfaces is a cut surface generated by a cutting process that separates the individual semiconductor devices from the aggregated formation state of the plurality of semiconductor devices, and has an electrode portion that is exposed as part of the cut surface after receiving the cutting process ,
The electrode part exposed on the side surface is provided with a recess in advance on the surface side of the electrode part located at the planned cutting position in the cutting process, and the surface metal layer is not formed on the surface facing the recess. ,
The surface of the electrode part exposed on the side surface is a cross section of the lower part of the position where the original concave portion was,
A semiconductor device characterized by not including any cross section of the surface metal layer. 前記請求項１ないし４のいずれかに記載の半導体装置用基板に対し、金属部上への半導
体素子搭載及び配線、封止材による封止を行い、
封止材による封止を行った後で、前記金属部の裏面側を覆う母型基板を除去して、底部
に前記金属部の裏面側が露出した状態の半導体装置の集合体を得ることを
特徴とする半導体装置の製造方法。 The semiconductor device substrate according to any one of claims 1 to 4 is mounted with a semiconductor element on a metal portion and wiring, and sealed with a sealing material,
After sealing with a sealing material, the matrix substrate covering the back side of the metal part is removed to obtain an assembly of semiconductor devices in a state where the back side of the metal part is exposed at the bottom. A method for manufacturing a semiconductor device.
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US20110267789A1 (en) * 2010-04-28 2011-11-03 Advanpack Solutions Pte Ltd. Etch-back type semiconductor package, substrate and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7270867B1 (en) * 1998-06-10 2007-09-18 Asat Ltd. Leadless plastic chip carrier
US20020024147A1 (en) * 2000-01-05 2002-02-28 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
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