JP2002184927A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JP2002184927A
JP2002184927A JP2000385832A JP2000385832A JP2002184927A JP 2002184927 A JP2002184927 A JP 2002184927A JP 2000385832 A JP2000385832 A JP 2000385832A JP 2000385832 A JP2000385832 A JP 2000385832A JP 2002184927 A JP2002184927 A JP 2002184927A
Authority
JP
Japan
Prior art keywords
semiconductor chip
chip mounting
lead
semiconductor device
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000385832A
Other languages
Japanese (ja)
Inventor
Yuichi Michiyoshi
裕一 道喜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP2000385832A priority Critical patent/JP2002184927A/en
Publication of JP2002184927A publication Critical patent/JP2002184927A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device whose cost can be reduced and manufacture time can be shortened, by stabilizing the flatness of a lead and a pad and saving a work process for removing resin stuck to an exposure face. SOLUTION: A semiconductor chip loading part and the lead of a lead frame are formed on a substrate by using a non-through groove. A semiconductor chip and the like are arranged and are resin-sealed. Then, the non-through groove is pierced and the semiconductor device is formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
方法に関し、特に、リードの露出面に樹脂バリが形成さ
れることを防止することが可能な半導体装置の製造方法
に関する。
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device capable of preventing resin burrs from being formed on exposed surfaces of leads.

【0002】[0002]

【従来の技術】近年、半導体装置の小型化および薄型化
に伴い、半導体チップ搭載部(パッド)およびリードが
パッケージの下面に露出した構造の半導体装置(図6参
照)が提案されている。
2. Description of the Related Art In recent years, as semiconductor devices have become smaller and thinner, semiconductor devices having a structure in which a semiconductor chip mounting portion (pad) and leads are exposed on the lower surface of a package have been proposed (see FIG. 6).

【0003】この構造の半導体装置は、図5に示すよう
な以下に説明する方法を用いて、従来は形成されてい
た。
A semiconductor device having this structure has been conventionally formed by using a method described below as shown in FIG.

【0004】まず、金属製の基板にパターニングを施
し、図5(a)に示すように、リードフレームのリード
3および半導体チップ搭載部(パッド)4を形成する。
First, a metal substrate is patterned to form leads 3 of a lead frame and semiconductor chip mounting portions (pads) 4 as shown in FIG.

【0005】そして、図5(b)に示すように、半導体
チップ搭載部4上に、Agペーストなどの接着剤を介し
て半導体チップ5を搭載し、半導体チップ5の電極6と
リード3のボンディング部7とを、Au、Al等からな
るボンディングワイヤ8を用いてボンディングを行い、
半導体チップ5とリード3とを電気的に接続する。
[0005] Then, as shown in FIG. 5 (b), the semiconductor chip 5 is mounted on the semiconductor chip mounting portion 4 via an adhesive such as Ag paste, and the bonding between the electrode 6 of the semiconductor chip 5 and the lead 3 is performed. Bonding with the part 7 using a bonding wire 8 made of Au, Al, or the like;
The semiconductor chip 5 and the leads 3 are electrically connected.

【0006】ここで、図5(c)に示すように、半導体
チップ搭載部4およびリード3の半導体チップ搭載面9
をエポキシ樹脂等を用いて樹脂封止し、パッケージ10
を形成する。その後、樹脂封止の際に、各リード間等か
ら裏面11に漏れた樹脂により、リード3および半導体
チップ搭載部4の露出面に形成された樹脂バリ16をブ
ラスト等を用いて除去する。
Here, as shown in FIG. 5C, the semiconductor chip mounting portion 4 and the semiconductor chip mounting surface 9 of the leads 3 are formed.
Is sealed with an epoxy resin or the like, and the package 10
To form Thereafter, at the time of resin sealing, the resin burrs 16 formed on the exposed surfaces of the leads 3 and the semiconductor chip mounting portion 4 are removed by blasting or the like by the resin leaking from between the leads or the like to the back surface 11.

【0007】そして、図5(d)に示すように、半導体
チップ搭載部4およびリード3の露出面を露出させ、こ
の露出面に貴金属等を用いてめっきを施し、図6に示す
ように、半導体チップ搭載部およびリードフレームがパ
ッケージの下面に露出した構造の半導体装置を製造して
いた。
Then, as shown in FIG. 5D, the exposed surfaces of the semiconductor chip mounting portion 4 and the leads 3 are exposed, and the exposed surfaces are plated with a noble metal or the like, as shown in FIG. A semiconductor device having a structure in which a semiconductor chip mounting portion and a lead frame are exposed on a lower surface of a package has been manufactured.

【0008】[0008]

【発明が解決しようとする課題】しかし、従来の方法に
よれば、リードおよびパッドの形成を行った後に、一連
の組立工程を行なうため、リードおよびパッドの平坦度
が不安定であった。
However, according to the conventional method, a series of assembling steps are performed after the formation of the leads and pads, so that the flatness of the leads and pads is unstable.

【0009】また、リード及び半導体チップ搭載部の形
状形成を樹脂封止工程の前に行うので、樹脂封止工程の
際に、各リード間等から漏れた樹脂がリードおよびパッ
ドの露出面に付着し、露出面にめっきを施すことが困難
となるという問題が発生していた(図7参照)。
Further, since the shapes of the leads and the semiconductor chip mounting portion are formed before the resin sealing step, during the resin sealing step, the resin leaked from between the leads and the like adheres to the exposed surfaces of the leads and pads. However, there has been a problem that it is difficult to perform plating on the exposed surface (see FIG. 7).

【0010】このため、樹脂封止を行う際にリードの露
出面をマスキングテープ等で覆い、樹脂バリの形成を防
止する工程や、ブラスト等を用いて露出面に付着した樹
脂バリを除去する工程など、樹脂バリの形成防止や除去
を行うための工程が必要となり、半導体装置の製造コス
トや製造時間を抑えることが困難であった。
For this reason, when performing resin sealing, the exposed surface of the lead is covered with a masking tape or the like to prevent the formation of resin burrs, or the step of removing resin burrs attached to the exposed surface using blasting or the like. For example, a process for preventing or removing resin burrs is required, and it has been difficult to reduce the manufacturing cost and the manufacturing time of the semiconductor device.

【0011】そこで本発明では、リードおよびパッドの
平坦度の安定を図ると共に、露出面に付着した樹脂を除
去するための作業工程を省略することにより、コストの
低減および製造時間の短縮を図ることが可能な半導体装
置の製造方法を提供することを目的とする。
Therefore, in the present invention, the flatness of the leads and the pads is stabilized, and the operation step for removing the resin adhering to the exposed surface is omitted, thereby reducing the cost and the manufacturing time. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of performing the following.

【0012】[0012]

【課題を解決するための手段】本発明の半導体装置製造
方法では、基板の両面から該基板の所定の位置を所定量
除去し、非貫通溝で囲まれたリード及び半導体チップ搭
載部を形成する工程と、前記半導体チップ搭載部に半導
体チップを搭載し、かつ前記リードと該半導体チップと
を電気的に接続する工程と、前記基板の半導体チップ搭
載面を樹脂を用いて樹脂封止する工程と、前記樹脂封止
の後、前記非貫通溝を貫通させて前記リード及び前記半
導体チップ搭載部を形成する工程とを有する。
According to the method of manufacturing a semiconductor device of the present invention, a predetermined position of a substrate is removed from both surfaces of the substrate by a predetermined amount to form a lead and a semiconductor chip mounting portion surrounded by a non-through groove. Mounting a semiconductor chip on the semiconductor chip mounting portion, and electrically connecting the lead and the semiconductor chip, and sealing the semiconductor chip mounting surface of the substrate with a resin. Forming the leads and the semiconductor chip mounting portion through the non-through grooves after the resin sealing.

【0013】この構成では、樹脂封止の後に非貫通溝を
貫通させるため、リード及び半導体チップ搭載部の平坦
度が安定すると共に、樹脂バリの形成を防止することが
できる。
In this configuration, since the non-penetrating groove is made to penetrate after the resin sealing, the flatness of the lead and the semiconductor chip mounting portion is stabilized, and the formation of resin burrs can be prevented.

【0014】また、請求項2記載の発明では、基板の両
面から該基板の所定の位置を所定量除去し、非貫通溝で
囲まれたリードを形成する工程と、前記リード上に半導
体チップを搭載し、かつ前記リードと該半導体チップと
を電気的に接続する工程と、前記基板の半導体チップ搭
載面を樹脂を用いて樹脂封止する工程と、前記樹脂封止
の後、前記非貫通溝を貫通させて前記リードを形成する
工程とを有する。
According to the second aspect of the invention, a predetermined position of the substrate is removed from both sides of the substrate by a predetermined amount to form a lead surrounded by a non-through groove, and a semiconductor chip is mounted on the lead. Mounting, and electrically connecting the leads to the semiconductor chip, sealing the semiconductor chip mounting surface of the substrate with a resin, and forming the non-through groove after the resin sealing. And forming the lead by penetrating through.

【0015】この構成では、樹脂封止の後に非貫通溝を
貫通させるため、リード間からの樹脂漏れによる樹脂バ
リの形成を防止すると共に、リードの平坦度が安定する
ため、リード上に半導体チップを安定して搭載すること
ができる。
In this configuration, since the non-through groove is penetrated after resin sealing, formation of resin burrs due to resin leakage from between the leads is prevented, and the flatness of the leads is stabilized. Can be mounted stably.

【0016】なお、レーザーを用いて前記非貫通溝を貫
通させることにより、基板裏面にレジストを形成、除去
する工程を省くことができる。
By using a laser to penetrate the non-penetrating groove, a step of forming and removing a resist on the back surface of the substrate can be omitted.

【0017】[0017]

【発明の実施の形態】以下、本発明に係わる半導体装置
の製造方法を図面を参照して詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings.

【0018】図1は、第1の実施の形態における半導体
装置の製造工程を示す断面図である。
FIG. 1 is a sectional view showing a manufacturing process of the semiconductor device according to the first embodiment.

【0019】まず、図1(a)に示すように、銅からな
る導電性基板1の半導体チップ搭載面9および半導体チ
ップ搭載面9の裏面11にハーフエッチングを施し、非
貫通溝2を用いてリードフレームのリード3および半導
体チップ搭載部4を形状加工する。
First, as shown in FIG. 1A, the semiconductor chip mounting surface 9 of the conductive substrate 1 made of copper and the back surface 11 of the semiconductor chip mounting surface 9 are subjected to half etching, and the non-through grooves 2 are used. The lead 3 of the lead frame and the semiconductor chip mounting portion 4 are processed.

【0020】そして、図1(b)に示すように、半導体
チップ搭載部4にAgペーストなどの接着剤を介して半
導体チップ5を搭載し、半導体チップ5の電極6とリー
ド3のボンディング部7とをAu、Al等からなるボン
ディングワイヤ8を介して電気的に接続する。
Then, as shown in FIG. 1B, the semiconductor chip 5 is mounted on the semiconductor chip mounting portion 4 via an adhesive such as Ag paste, and the bonding portion 7 between the electrode 6 of the semiconductor chip 5 and the lead 3 is mounted. Are electrically connected via a bonding wire 8 made of Au, Al or the like.

【0021】ここで、図1(c)に示すように、基板1
の半導体チップ搭載面9をエポキシ樹脂等を用いて樹脂
封止し、パッケージ10を形成する。
Here, as shown in FIG.
The semiconductor chip mounting surface 9 is resin-encapsulated using an epoxy resin or the like to form a package 10.

【0022】樹脂封止の後、図1(d)に示すように、
半導体チップ搭載面9の裏面11の非貫通溝2を除いた
領域にレジスト12を形成する。
After resin sealing, as shown in FIG.
A resist 12 is formed in a region of the back surface 11 of the semiconductor chip mounting surface 9 except for the non-through groove 2.

【0023】そして、図1(e)に示すように、非貫通
溝2を裏面11からエッチングして貫通溝13を形成
し、リード3と半導体チップ搭載部4を分断すると共
に、図示ししない各リードを形成する。
Then, as shown in FIG. 1E, the non-through groove 2 is etched from the back surface 11 to form a through groove 13, and the lead 3 and the semiconductor chip mounting portion 4 are separated from each other. Form the leads.

【0024】その後、図1(f)に示すように、レジス
ト12を除去して、半導体装置が製造される。
Thereafter, as shown in FIG. 1F, the resist 12 is removed, and a semiconductor device is manufactured.

【0025】なお、本実施の形態では、レジストを形成
した後にエッチングを施して貫通溝を形成しているが、
例えばレーザー等を用いて選択的に非貫通溝を貫通させ
る方法を用いることもできる。
In this embodiment, a through groove is formed by etching after forming a resist.
For example, a method of selectively penetrating the non-penetrating groove using a laser or the like can be used.

【0026】また、この構成ではレジストの形成および
除去の工程を省略することができるため、一層のコスト
の低減および製造時間の短縮を図ることができる。
Further, in this structure, the steps of forming and removing the resist can be omitted, so that the cost and the manufacturing time can be further reduced.

【0027】図2は、本発明に係わる半導体装置製造方
法における第2の実施の形態の半導体装置の製造工程を
示す断面図である。
FIG. 2 is a sectional view showing a semiconductor device manufacturing process according to a second embodiment of the present invention.

【0028】まず、図2(a)に示すように、導電性基
板1の半導体チップ搭載面9および半導体チップ搭載面
9の裏面11にハーフエッチングを施し、非貫通溝2を
用いてリード3および半導体チップ搭載部4を形状加工
する。
First, as shown in FIG. 2A, the semiconductor chip mounting surface 9 of the conductive substrate 1 and the back surface 11 of the semiconductor chip mounting surface 9 are half-etched, and the leads 3 and The semiconductor chip mounting part 4 is shaped.

【0029】そして、図2(b)に示すように、半導体
チップ搭載部4に接着剤を介して半導体チップ5を搭載
し、半導体チップ5の電極6とリード3のボンディング
部7とをボンディングワイヤ8を介して電気的に接続す
る。
Then, as shown in FIG. 2B, the semiconductor chip 5 is mounted on the semiconductor chip mounting portion 4 via an adhesive, and the electrodes 6 of the semiconductor chip 5 and the bonding portions 7 of the leads 3 are bonded with bonding wires. 8 for electrical connection.

【0030】ここで、図2(c)に示すように、基板1
の半導体チップ搭載面9を樹脂封止し、パッケージ10
を形成する。
Here, as shown in FIG.
Of the semiconductor chip mounting surface 9 of the package
To form

【0031】樹脂封止の後、図2(d)に示すように、
半導体チップ搭載面9の裏面11から基板1の全面をエ
ッチングして、図2(e)に示すように、貫通溝13を
形成し、リード3と半導体チップ搭載部4を分断すると
共に、図示ししない各リードを形成する。
After resin sealing, as shown in FIG.
The entire surface of the substrate 1 is etched from the back surface 11 of the semiconductor chip mounting surface 9 to form a through groove 13 as shown in FIG. 2E, and the lead 3 and the semiconductor chip mounting portion 4 are separated and shown in FIG. Not forming each lead.

【0032】なお、本実施の形態では、基板裏面全面を
エッチングして貫通溝を形成しているが、例えばレーザ
ー等を用いて選択的に非貫通溝を貫通させるなどの方法
を用いることもできる。
In this embodiment, the through-groove is formed by etching the entire back surface of the substrate. However, a method of selectively penetrating the non-groove by using a laser or the like may be used. .

【0033】図3は、本発明に係わる半導体装置製造方
法における第3の実施の形態の半導体装置の製造工程を
示す断面図である。
FIG. 3 is a sectional view showing a semiconductor device manufacturing process according to a third embodiment in a semiconductor device manufacturing method according to the present invention.

【0034】まず、図3(a)に示すように、銅からな
る薄板14の半導体チップ搭載面9の半導体チップ搭載
部4となる所定の位置に接着剤を介して半導体チップ5
を搭載し、半導体チップ5の電極6とリード3のボンデ
ィング部7となる所定の位置とをボンディングワイヤ8
を介して電気的に接続する。
First, as shown in FIG. 3A, the semiconductor chip 5 is placed at a predetermined position on the semiconductor chip mounting surface 9 of the thin plate 14 made of copper to be the semiconductor chip mounting portion 4 with an adhesive.
And bonding wires 6 of electrodes 6 of semiconductor chip 5 and predetermined positions of bonding portions 7 of leads 3 to bonding wires 8
To make electrical connection.

【0035】そして、図3(b)に示すように、薄板1
4の半導体チップ搭載面9を樹脂封止して、パッケージ
10を形成し、図3(c)に示すように、半導体チップ
搭載面9の裏面11から、リード3及び半導体チップ搭
載部4を導電性接着剤15を介して薄板14に接着す
る。
Then, as shown in FIG.
4 is sealed with a resin to form a package 10. As shown in FIG. 3C, the leads 3 and the semiconductor chip mounting portion 4 are electrically conductive from the back surface 11 of the semiconductor chip mounting surface 9. It adheres to the thin plate 14 via the conductive adhesive 15.

【0036】この後、図3(d)に示すように、リード
3および半導体チップ搭載部4に沿って裏面11から薄
板14をエッチングして、半導体装置を形成する。
Thereafter, as shown in FIG. 3D, the thin plate 14 is etched from the back surface 11 along the leads 3 and the semiconductor chip mounting portion 4 to form a semiconductor device.

【0037】ここで、エッチングに代えてレーザー等を
用いて非貫通溝を貫通させるように構成することもでき
る。
Here, it is also possible to use a laser or the like instead of etching to penetrate the non-through groove.

【0038】なお、上記各実施の形態では基板及び薄板
の材料として銅を用いているが、例えばNi−Fe合金
など、エッチング可能な導電性材料を用いることができ
る。
In each of the above embodiments, copper is used as the material of the substrate and the thin plate, but an etchable conductive material such as a Ni—Fe alloy can be used.

【0039】また、図4に示すように、半導体チップ搭
載部を設けず、リードフレームのリード3の上に半導体
チップ5を搭載する構造の半導体装置に用いることもで
きる。
Further, as shown in FIG. 4, a semiconductor device having a structure in which a semiconductor chip 5 is mounted on a lead 3 of a lead frame without providing a semiconductor chip mounting portion can also be used.

【0040】[0040]

【発明の効果】本発明では、配線パターン及び半導体チ
ップ搭載部を最後に分離するため、リード及び半導体チ
ップ搭載部の平坦度が安定すると共に、樹脂バリの形成
を防止することができる。
According to the present invention, since the wiring pattern and the semiconductor chip mounting portion are finally separated, the flatness of the lead and the semiconductor chip mounting portion can be stabilized, and the formation of resin burrs can be prevented.

【0041】また、リード及び半導体チップ搭載部の形
成は、非貫通溝を分断するだけでよいため、生産性が良
好であり、さらに、リードが封止樹脂の下面から突出し
て形成できるため、実装性が良好である。
Further, the formation of the lead and the semiconductor chip mounting portion only requires dividing the non-penetrating groove, so that the productivity is good. Further, since the lead can be formed to protrude from the lower surface of the sealing resin, the mounting can be performed. The properties are good.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の実施の形態における半導体装置の製造工
程を示す断面図
FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to a first embodiment.

【図2】第2の実施の形態における半導体装置の製造工
程を示す断面図
FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device according to the second embodiment;

【図3】第3の実施の形態における半導体装置の製造工
程を示す断面図
FIG. 3 is a sectional view showing a manufacturing process of a semiconductor device according to a third embodiment;

【図4】本発明における半導体装置の構造の一例を示す
断面図
FIG. 4 is a cross-sectional view illustrating an example of the structure of a semiconductor device according to the present invention.

【図5】従来技術における半導体装置の製造工程を示す
断面図
FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a conventional technique.

【図6】従来技術における半導体装置を示す断面図FIG. 6 is a cross-sectional view showing a semiconductor device according to a conventional technique.

【図7】従来技術における半導体装置の裏面を示す平面
FIG. 7 is a plan view showing a back surface of a semiconductor device according to a conventional technique.

【符号の説明】[Explanation of symbols]

1…導電性基板 2…非貫通溝 3…リード 4…半導体チップ搭載部 5…半導体チップ 6…電極 7…ボンディング部 8…ボンディングワイヤ 9…半導体チップ搭載面 10…パッケージ 11…裏面 12…レジスト 13…貫通溝 14…薄板 15…導電性接着剤 16…樹脂バリ DESCRIPTION OF SYMBOLS 1 ... Conductive board 2 ... Non-through-groove 3 ... Lead 4 ... Semiconductor chip mounting part 5 ... Semiconductor chip 6 ... Electrode 7 ... Bonding part 8 ... Bonding wire 9 ... Semiconductor chip mounting surface 10 ... Package 11 ... Back surface 12 ... Resist 13 ... Through groove 14 ... Thin plate 15 ... Conductive adhesive 16 ... Resin burr

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板の両面から該基板の所定の位置を所
定量除去し、非貫通溝で囲まれたリード及び半導体チッ
プ搭載部を形成する工程と、 前記半導体チップ搭載部に半導体チップを搭載し、かつ
前記リードと該半導体チップとを電気的に接続する工程
と、 前記基板の半導体チップ搭載面を樹脂を用いて樹脂封止
する工程と、 前記樹脂封止の後、前記非貫通溝を貫通させて前記リー
ド及び前記半導体チップ搭載部を形成する工程とを有す
る半導体装置製造方法。
A step of removing a predetermined amount of a predetermined position of the substrate from both surfaces of the substrate to form a lead and a semiconductor chip mounting portion surrounded by a non-through groove; and mounting a semiconductor chip on the semiconductor chip mounting portion. And electrically connecting the lead and the semiconductor chip; sealing the semiconductor chip mounting surface of the substrate with a resin; and sealing the non-through groove after the resin sealing. Forming the lead and the semiconductor chip mounting portion by penetrating the semiconductor device.
【請求項2】 基板の両面から該基板の所定の位置を所
定量除去し、非貫通溝で囲まれたリードを形成する工程
と、 前記リード上に半導体チップを搭載し、かつ前記リード
と該半導体チップとを電気的に接続する工程と、 前記基板の半導体チップ搭載面を樹脂を用いて樹脂封止
する工程と、 前記樹脂封止の後、前記非貫通溝を貫通させて前記リー
ドを形成する工程とを有する半導体装置製造方法。
A step of removing a predetermined position of the substrate from both sides of the substrate by a predetermined amount to form a lead surrounded by a non-through groove; mounting a semiconductor chip on the lead; A step of electrically connecting to a semiconductor chip; a step of resin sealing the semiconductor chip mounting surface of the substrate using a resin; and after the resin sealing, forming the leads by penetrating the non-through groove. Semiconductor device manufacturing method.
JP2000385832A 2000-12-19 2000-12-19 Method of manufacturing semiconductor device Pending JP2002184927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000385832A JP2002184927A (en) 2000-12-19 2000-12-19 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000385832A JP2002184927A (en) 2000-12-19 2000-12-19 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2002184927A true JP2002184927A (en) 2002-06-28

Family

ID=18853035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000385832A Pending JP2002184927A (en) 2000-12-19 2000-12-19 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2002184927A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005276890A (en) * 2004-03-23 2005-10-06 Renesas Technology Corp Semiconductor device and its manufacturing method
US7525184B2 (en) 2002-07-01 2009-04-28 Renesas Technology Corp. Semiconductor device and its manufacturing method
JP2009246395A (en) * 2009-07-27 2009-10-22 Renesas Technology Corp Method of manufacturing semiconductor device
JP2010135718A (en) * 2008-11-07 2010-06-17 Toppan Printing Co Ltd Leadframe for led light emitting element, method of manufacturing the leadframe, and led light emitting element using the leadframe
JP2010272565A (en) * 2009-05-19 2010-12-02 Toppan Printing Co Ltd Leadframe, method of manufacturing the leadframe, and semiconductor light emitting device using the leadframe
JP2015177080A (en) * 2014-03-15 2015-10-05 新日本無線株式会社 Circuit package with built-in lead and manufacturing method therefor
JP2016025120A (en) * 2014-07-16 2016-02-08 大日本印刷株式会社 Lead frame member and method for manufacturing the same, and semiconductor device and method for manufacturing the same
CN108257938A (en) * 2018-01-31 2018-07-06 江苏长电科技股份有限公司 For the jig of lead frame and the engraving method of lead frame

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7525184B2 (en) 2002-07-01 2009-04-28 Renesas Technology Corp. Semiconductor device and its manufacturing method
KR100975692B1 (en) * 2002-07-01 2010-08-12 가부시끼가이샤 르네사스 테크놀로지 Semiconductor device
US7843049B2 (en) 2002-07-01 2010-11-30 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US8222720B2 (en) 2002-07-01 2012-07-17 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US8390133B2 (en) 2002-07-01 2013-03-05 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
JP2005276890A (en) * 2004-03-23 2005-10-06 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2010135718A (en) * 2008-11-07 2010-06-17 Toppan Printing Co Ltd Leadframe for led light emitting element, method of manufacturing the leadframe, and led light emitting element using the leadframe
JP2010272565A (en) * 2009-05-19 2010-12-02 Toppan Printing Co Ltd Leadframe, method of manufacturing the leadframe, and semiconductor light emitting device using the leadframe
JP2009246395A (en) * 2009-07-27 2009-10-22 Renesas Technology Corp Method of manufacturing semiconductor device
JP2015177080A (en) * 2014-03-15 2015-10-05 新日本無線株式会社 Circuit package with built-in lead and manufacturing method therefor
JP2016025120A (en) * 2014-07-16 2016-02-08 大日本印刷株式会社 Lead frame member and method for manufacturing the same, and semiconductor device and method for manufacturing the same
CN108257938A (en) * 2018-01-31 2018-07-06 江苏长电科技股份有限公司 For the jig of lead frame and the engraving method of lead frame

Similar Documents

Publication Publication Date Title
JP3285815B2 (en) Lead frame, resin-encapsulated semiconductor device and method of manufacturing the same
US7459347B2 (en) Manufacturing method of a semiconductor device
CN105185752B (en) Semiconductor devices and its manufacturing method
JP4091050B2 (en) Manufacturing method of semiconductor device
JPH11340409A (en) Lead frame and its manufacture and resin encapsulated semiconductor device and its manufacture
JP3436159B2 (en) Method for manufacturing resin-encapsulated semiconductor device
JP3046024B1 (en) Lead frame and method of manufacturing resin-encapsulated semiconductor device using the same
JP3072291B1 (en) Lead frame, resin-encapsulated semiconductor device using the same and method of manufacturing the same
JP2000195984A (en) Semiconductor device, its manufacture carrier substrate therefor and its manufacture
JP2002184927A (en) Method of manufacturing semiconductor device
JP3786339B2 (en) Manufacturing method of semiconductor device
JP3292082B2 (en) Terminal land frame and method of manufacturing resin-encapsulated semiconductor device using the same
JP2000114426A (en) Single-sided resin sealing type semiconductor device
JP3427492B2 (en) Semiconductor device with convex heat sink and method of manufacturing the convex heat sink
JPH11260990A (en) Lead frame, resin-sealed semiconductor device and its manufacture
JP3445930B2 (en) Resin-sealed semiconductor device
JP3618316B2 (en) Manufacturing method of semiconductor device
JP2002134654A (en) Resin sealing type semiconductor device and its manufacturing method
JP2001077285A (en) Lead frame and manufacture of resin-sealed semiconductor device using the same
JP3503502B2 (en) Resin-sealed semiconductor device and method of manufacturing the same
WO2022202242A1 (en) Semiconductor device and manufacturing method for semiconductor device
JP3569642B2 (en) Semiconductor device carrier substrate, method of manufacturing the same, and method of manufacturing a semiconductor device
JP2877122B2 (en) Semiconductor device and lead frame
JPH08250545A (en) Semiconductor device and manufacture thereof
JP2001077263A (en) Manufacture of resin sealed semiconductor device