JP2005268442A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005268442A
JP2005268442A JP2004076833A JP2004076833A JP2005268442A JP 2005268442 A JP2005268442 A JP 2005268442A JP 2004076833 A JP2004076833 A JP 2004076833A JP 2004076833 A JP2004076833 A JP 2004076833A JP 2005268442 A JP2005268442 A JP 2005268442A
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metal layer
film
solder
electrode
semiconductor device
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Kazuto Higuchi
和人 樋口
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Toshiba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a barrier metal layer can be prevented from being peeled off by a stress generating at a bump connector in a heating/cooling cycle after a flip chip is mounted. <P>SOLUTION: An electrode pad on a semiconductor chip 1A is made of a laminated body formed of a plurality of metallic layers that are comprised of a connection electrode 4 and barrier metal layers 6, 7 and 9. Among the metallic layers, the metallic layers 6 and 7 formed near the surface of the semiconductor chip are made larger in dimension in the radial direction than the metallic layer 9 in contact with the bump electrode 11. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置およびその製造方法に関し、特に半導体チップ上にバンプ電極が形成された半導体装置の信頼性を有利に向上させることのできる構造とその有利な製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure that can advantageously improve the reliability of a semiconductor device in which bump electrodes are formed on a semiconductor chip and an advantageous manufacturing method thereof.

近年、情報処理技術の発達、普及により電子機器の小型化、薄型化、高性能化が進められており、これに伴って半導体チップも小型化、高集積化の方向にある。特に、数ＧＨｚの周波数で動作し演算処理を行うようなマイクロプロセッサ等のＬＳＩチップでは、ムーア則に従い、チップに集積されるトランジスタ数が年々増加するとともに、デザインルールが微細化されており、近年では０．２５μｍ以下のデザインルールで５０００万個以上のトランジスタが集積化された半導体チップが製造されている。   In recent years, with the development and spread of information processing technology, electronic devices have been reduced in size, thickness, and performance, and semiconductor chips are also becoming smaller and more integrated. In particular, in an LSI chip such as a microprocessor that operates at a frequency of several GHz and performs arithmetic processing, the number of transistors integrated on the chip increases year by year according to Moore's rule, and the design rule is miniaturized. Then, a semiconductor chip in which 50 million transistors or more are integrated with a design rule of 0.25 μm or less is manufactured.

このような半導体チップでは、集積化されるトランジスタ数の増大に伴う、電源容量の増加、入出力数の増加、入出力信号の高速化に対応すべく、半導体チップとパッケージ基板との接続には、フリップチップ接続技術が採用されつつある。これは、フリップチップ接続技術が、ワイヤボンディング法、ＴＡＢ法では困難であった、半導体素子上に格子状に配置された電極パッドと基板上の電極との接続が可能な接続法であるため、多端子の半導体チップの接続に適した実装技術だからである。かかるフリップチップ実装は、半導体素子と回路基板を対向させてバンプ電極により接続する方法の総称であり、接続方法の違いにより、はんだバンプ接続、導電性樹脂接続、圧接接続、超音波接続に分類される。   In such a semiconductor chip, the connection between the semiconductor chip and the package substrate is required in order to cope with an increase in power supply capacity, an increase in the number of input / outputs, and an increase in input / output signal speed as the number of integrated transistors increases. Flip chip connection technology is being adopted. This is because the flip-chip connection technique is a connection method that can connect the electrode pads arranged in a lattice pattern on the semiconductor element and the electrodes on the substrate, which has been difficult with the wire bonding method and the TAB method. This is because the mounting technology is suitable for connecting multi-terminal semiconductor chips. Such flip-chip mounting is a general term for a method of connecting a semiconductor element and a circuit board with a bump electrode facing each other, and is classified into solder bump connection, conductive resin connection, pressure connection, and ultrasonic connection depending on the connection method. The

中でも、はんだバンプを用いる方式は、溶融接続であるため接合強度が高く、また、はんだバンプが塑性変形を起こし接続部に発生する応力が緩和され、高信頼性化が可能となる等の長所を持っているためフリップチップ実装の主流となっている。   Among them, the method using solder bumps has high bonding strength because it is a fusion connection, and the solder bumps are plastically deformed to relieve the stress generated in the connection part, thereby enabling high reliability. It has become the mainstream of flip chip mounting.

はんだ材料としては、優れた機械的特性を有するＳｎ（錫）と鉛（Ｐｂ）の合金が最も多く用いられているが、近年では、Ｐｂの環境に及ぼす影響が懸念されるようになってきたため、Ｐｂを基本的に含有しない、ＳｎとＡｇ（銀）の合金やＳｎとＣｕ（銅）の合金等の、いわゆるＰｂフリーはんだ材料を用いたフリップチップ実装が開発されつつあり、将来、主流になると考えられる。Ｐｂフリー材料は、一般的にはＳｎを主体とする合金である。   As a solder material, an alloy of Sn (tin) and lead (Pb) having excellent mechanical properties is most often used. However, in recent years, the influence of Pb on the environment has become a concern. Flip chip mounting using a so-called Pb-free solder material, such as an alloy of Sn and Ag (silver) or an alloy of Sn and Cu (copper), which does not contain Pb basically, is being developed. It is considered to be. The Pb-free material is generally an alloy mainly composed of Sn.

ところで、微細なメモリデバイスを有する半導体チップ上に、前述したフリップチップ実装のためのはんだバンプを形成したとき、はんだ材料にＰｂを含む合金を用いた場合には、このはんだを構成するＰｂ中に含まれたＵ（ウラン）、Ｔｈ（トリウム）等の放射性物質からα線が発生し、このα線が半導体チップ表面に向かい、更には半導体チップ内部へ突入することがある。突入したα線はＳｉ（シリコン）基板に作用し、電子−正孔対を生成するため、メモリセルに蓄積された電荷による情報を書き換える、いわゆるソフトエラーを引き起こす場合がある。   By the way, when the above-described solder bump for flip chip mounting is formed on a semiconductor chip having a fine memory device, when an alloy containing Pb is used as a solder material, Α-rays are generated from radioactive substances such as U (uranium) and Th (thorium) contained therein, and the α-rays may be directed toward the surface of the semiconductor chip and further enter the semiconductor chip. The rushed α-rays act on the Si (silicon) substrate and generate electron-hole pairs, which may cause a so-called soft error that rewrites information due to charges accumulated in the memory cell.

はんだバンプを形成した半導体チップにおいて、ソフトエラーを回避する方法として、Ｐｂ含有はんだ中の放射性不純物量を低減することが考えられるが、ソフトエラーを起こすことのない程度にまで高純度に精錬して放射性不純物量を低減するにはコストが嵩む。そのため、そのような放射性不純物量を低減したはんだを使用した半導体装置は高価になってしまう。   As a method of avoiding soft errors in semiconductor chips on which solder bumps are formed, it is conceivable to reduce the amount of radioactive impurities in the Pb-containing solder, but it is refined to a high purity to the extent that soft errors do not occur. Cost is increased to reduce the amount of radioactive impurities. For this reason, a semiconductor device using such solder with a reduced amount of radioactive impurities becomes expensive.

また、ソフトエラーを回避する方法として、はんだバンプの材料にＰｂフリー材料であるＳｎとＣｕの合金、ＳｎとＡｇの合金を用いる方法が考えられる。Ｐｂフリー材料を用いることは、前述した環境影響の観点にも沿う。このようなＰｂフリー材料を用いてソフトエラーを回避する方法については、特許文献１に開示されている。しかし、Ｐｂフリー材料をはんだ材料として用いれば、理論上はα線によるソフトエラーを回避できる可能性があるが、現実にはＳｎの原料となる酸化錫中には不純物としてＰｂが含まれる場合が多く、その結果、Ｓｎ合金はんだからもα線が発生する場合がある。実際、特許文献２では、ＰｂフリーはんだであるＳｎ−Ａｇ−Ｃｕ合金から発生するα線量を測定しているが、０．０３ｃｏｕｎｔ／ｃｍ２・ｈ以上のα線が検出されたとしている。 Further, as a method of avoiding soft errors, a method of using an alloy of Sn and Cu, which is a Pb-free material, and an alloy of Sn and Ag, as a material of the solder bump can be considered. The use of the Pb-free material is in line with the above-described viewpoint of environmental influence. A method for avoiding a soft error using such a Pb-free material is disclosed in Patent Document 1. However, if a Pb-free material is used as a solder material, there is a possibility that a soft error due to α rays can be avoided in theory. However, in reality, tin oxide as a raw material of Sn may contain Pb as an impurity. As a result, α rays may also be generated from the Sn alloy solder. Actually, in Patent Document 2, the α dose generated from the Sn—Ag—Cu alloy that is Pb-free solder is measured, but it is assumed that α rays of 0.03 count / cm 2 · h or more are detected.

そこで、上掲特許文献２では、はんだバンプを形成した半導体チップにおいて、ソフトエラーを回避する別の方法として、はんだバンプ下の電極（バンプランド）層の厚さを厚くして、α線のＳｉ基板への突入を遮蔽する方法を開示している。この特許文献２においてバンプランド層を構成するＣｕ膜やＮｉ膜は、同一膜厚の絶縁材料に比べ、α線遮蔽能が高く、この膜を３ないし９μｍの厚みとすることにより、高い遮蔽効果を得るものである。なお、特許文献２では、Ｓｉチップ上のＡｌパッド電極よりＣｕ配線を介してバンプランドを形成した、いわゆるパッドの再配列を行った場合について記載しているが、パッド電極数が極めて多いチップの場合では、再配列を行う領域が少なくなるため、パッド電極の直上にはんだバンプを形成せざるを得ない。このような場合は、パッド電極の一部を構成しはんだバンプに接して形成される、いわゆるバリアメタル層を厚く形成することで、同様に高いα線遮蔽効果が期待できる。   Therefore, in the above-mentioned Patent Document 2, as another method for avoiding a soft error in a semiconductor chip on which solder bumps are formed, the thickness of the electrode (bump land) layer under the solder bumps is increased, and the α-ray Si A method for shielding entry into the substrate is disclosed. In this Patent Document 2, the Cu film or Ni film constituting the bump land layer has a higher α-ray shielding ability than an insulating material having the same film thickness. By making this film 3 to 9 μm thick, a high shielding effect is obtained. Is what you get. Note that Patent Document 2 describes a case where a so-called pad rearrangement in which bump lands are formed from an Al pad electrode on a Si chip via a Cu wiring, but a chip having a very large number of pad electrodes is described. In some cases, the area to be rearranged is reduced, so a solder bump must be formed immediately above the pad electrode. In such a case, a high α-ray shielding effect can be expected by forming a thick so-called barrier metal layer that forms part of the pad electrode and is in contact with the solder bump.

バリアメタルは、半導体素子と接続する接続電極を構成するＡｌと密着性の良い金属、はんだ中のＳｎの拡散が比較的遅い金属、はんだと濡れ性の良い金属等から構成されている。更に、バリアメタルは、コスト低減、工程削減の為に、前述した効果を合わせ持った金属を使用することにより、２層、もしくは３層で構成されることが一般的である。はんだに対するバリアメタルとしては、Ｔｉ（チタン）／Ｃｕの積層膜やＣｒ（クロム）／Ｎｉ（ニッケル）の積層膜等が使用されている。ＣｕやＮｉを用いる場合に、バリアメタル本来の機能であるＳｎの拡散を防止する目的に対しては、通常、１μｍ程度の厚みで十分であるが、α線の遮蔽を目的とした場合には、Ｃｕ層やＮｉ層の厚さをさらに厚くすることが最も効果的である。   The barrier metal is composed of a metal having good adhesion with Al constituting the connection electrode connected to the semiconductor element, a metal having relatively slow diffusion of Sn in the solder, a metal having good wettability with the solder, and the like. Furthermore, the barrier metal is generally composed of two or three layers by using a metal having the above-described effects in order to reduce cost and process. As a barrier metal for solder, a Ti (titanium) / Cu laminated film, a Cr (chromium) / Ni (nickel) laminated film, or the like is used. When using Cu or Ni, a thickness of about 1 μm is usually sufficient for the purpose of preventing the diffusion of Sn, which is the original function of the barrier metal, but for the purpose of shielding α rays. It is most effective to further increase the thickness of the Cu layer or Ni layer.

Ｃｕ層やＮｉ層を厚くするには、半導体装置の製造工程において、電気めっきにより形成されるこれらの層厚を厚くすることが考えられる。   In order to increase the thickness of the Cu layer or Ni layer, it is conceivable to increase the thickness of these layers formed by electroplating in the manufacturing process of the semiconductor device.

また、一般に、はんだバンプの形成は、半導体装置の製造工程において高い生産性を得るため、ウェハ状態で一括してバンプ形成が可能でしかも成膜速さが高速な電気めっき法による形成が主流である。従来の電気めっき法によるバンプ形成の要素技術としては、電気めっきによりバンプ電極を形成した後、このバンプをマスクにしてバリアメタルをエッチング除去する技術（特許文献３）が用いられる。この方法により形成される半導体装置を、図１４に示す。従来法によるはんだバンプ付き半導体ウェハは、図９〜１４に示すような製造工程で作製される。   In general, the formation of solder bumps is mainly performed by electroplating, which allows bump formation at the same time in the wafer state and high film formation speed in order to obtain high productivity in the manufacturing process of semiconductor devices. is there. As a conventional element technology for bump formation by electroplating, a technique (Patent Document 3) is used in which a bump electrode is formed by electroplating and then the barrier metal is removed by etching using the bump as a mask. A semiconductor device formed by this method is shown in FIG. A conventional semiconductor wafer with solder bumps is manufactured by a manufacturing process as shown in FIGS.

先ず、図９に断面図で示すような半導体ウェハ１０１を準備する。半導体チップの能動素子と電気的に接続する接続電極１０２はＡｌよりなり、この接続電極１０２以外の半導体ウェハ１０１表面は、ポリイミド膜１０３およびＳｉＯ２膜／ＳｉＮ膜の積層膜１１０からなるパッシベーション膜に被覆されている。次に、図１０に示すように接続電極１０２およびパッシベーション膜が形成された半導体ウェハ１０１上にＴｉ膜１０４、Ｃｕ膜１０７を順にスパッタし、バリアメタル層の第一の層を形成する。次に、図１１に示すように、その上にめっき用レジスト１０５を選択的に形成してから、図１２に示すように、めっき用レジスト１０５の開口部にバリアメタルの第二の層となるＮｉ膜１０６を電気めっきで形成し、続けてはんだめっきを行いはんだ膜１０８を形成する。ここで、Ｎｉ膜の厚さを５μｍ程度とすることで、はんだ膜１０８から発生するα線を遮蔽する効果が得られる。 First, a semiconductor wafer 101 as shown in a sectional view in FIG. 9 is prepared. The connection electrode 102 electrically connected to the active element of the semiconductor chip is made of Al, and the surface of the semiconductor wafer 101 other than the connection electrode 102 is a passivation film made of a polyimide film 103 and a laminated film 110 of SiO 2 film / SiN film. It is covered. Next, as shown in FIG. 10, a Ti film 104 and a Cu film 107 are sequentially sputtered on a semiconductor wafer 101 on which a connection electrode 102 and a passivation film are formed, thereby forming a first layer of a barrier metal layer. Next, as shown in FIG. 11, a plating resist 105 is selectively formed thereon, and then, as shown in FIG. 12, a second layer of barrier metal is formed in the opening of the plating resist 105. A Ni film 106 is formed by electroplating, followed by solder plating to form a solder film 108. Here, by setting the thickness of the Ni film to about 5 μm, an effect of shielding α rays generated from the solder film 108 can be obtained.

次に、図１３に示すように、はんだめっき用レジスト１０５を剥離し、はんだ膜１０８をエッチングレジストとしてバリアメタル層の第一の層である、Ｃｕ膜１０７、Ｔｉ膜１０４を順次エッチング除去する。その後、図１４に示すように、はんだ膜１０８をリフローしてはんだバンプ電極１０９を得ることができる。この方法で形成されたバリアメタル層は、はんだバンプの最大径よりも径方向のサイズが小さくなっている。
特開２００２−４３３５２号公報 特開２００２−１７０８２６号公報 特開平２−２２３４３６号公報 Next, as shown in FIG. 13, the solder plating resist 105 is peeled off, and the Cu film 107 and the Ti film 104 which are the first layers of the barrier metal layer are sequentially removed by etching using the solder film 108 as an etching resist. Thereafter, as shown in FIG. 14, the solder film 108 can be reflowed to obtain a solder bump electrode 109. The barrier metal layer formed by this method has a size in the radial direction smaller than the maximum diameter of the solder bump.
JP 2002-43352 A JP 2002-170826 A JP-A-2-223436

以上、説明したように、はんだバンプを用いたフリップチップ接続では、はんだ材料から発生したα線によるソフトエラーを回避するために、バリアメタル層の厚みを厚くすることが必須である。これは、はんだ材料がＰｂフリー材料であっても不純物中からα線が発生する場合があり、ソフトエラーが生ずるおそれがあるため、同様である。   As described above, in flip chip connection using solder bumps, it is essential to increase the thickness of the barrier metal layer in order to avoid soft errors due to α rays generated from the solder material. This is the same because α-rays may be generated from impurities even if the solder material is a Pb-free material, and a soft error may occur.

しかしながら、α線の遮蔽能力を高めるため、厚いバリアメタル層を形成し、Ｐｂフリー材料によるはんだバンプを形成した後、この半導体チップを樹脂基板上にフリップチップ実装した半導体装置においては、半導体チップと基板間の熱膨張差に起因する応力がバンプ接続部に生じ、バリアメタルが剥離してしまうという問題が生じてしまう。これは、特に、チップサイズが大きく、バリアメタル寸法が小さい場合には顕著である。   However, in a semiconductor device in which a thick barrier metal layer is formed and solder bumps made of a Pb-free material are formed in order to increase the α-ray shielding ability, and then this semiconductor chip is flip-chip mounted on a resin substrate, The stress resulting from the difference in thermal expansion between the substrates is generated in the bump connection portion, causing a problem that the barrier metal is peeled off. This is particularly noticeable when the chip size is large and the barrier metal dimension is small.

この問題は、Ｐｂフリーはんだ材料の多くが、Ｐｂ含有はんだに比べ、弾性率が大きく、塑性変形に至る応力緩和時間が長いためである。すなわち、半導体パッケージの基板として多用される樹脂基板の熱膨張係数は、少なくとも１０ｐｐｍ／Ｋ以上はあり、Ｓｉの３．８倍以上熱膨張することになる。したがって、加熱工程で膨張した基板が冷却時に収縮するに伴い、熱膨張差によりバンプには剪断方向に応力が生じる。バンプに応力が生じた場合に、従来のＰｂ含有はんだでは、バンプ自体の弾塑性変形によりその応力が大きく緩和されるが、Ｐｂフリーはんだにおいては応力が長時間残留することになる。   This problem is because many Pb-free solder materials have a higher elastic modulus and a longer stress relaxation time to plastic deformation than Pb-containing solder. That is, the thermal expansion coefficient of a resin substrate frequently used as a substrate of a semiconductor package is at least 10 ppm / K or more, and the thermal expansion coefficient is 3.8 times or more that of Si. Therefore, as the substrate expanded in the heating process contracts during cooling, stress is generated in the shear direction on the bump due to the difference in thermal expansion. When stress is generated in the bump, the stress is greatly relieved in the conventional Pb-containing solder due to the elastic-plastic deformation of the bump itself, but in the Pb-free solder, the stress remains for a long time.

さらに、バリアメタル層には引張り方向に内部応力が生じている場合が多く、その大きさは厚みが増加するに伴い大きくなる。引張り応力は、膜間の密着力を低下させる要因の一つであり、はんだバンプに過大な応力が加わった場合に、かかる内部応力により密着力が低下した部分で容易に剥離を生じる可能性がある。   Furthermore, the barrier metal layer often has an internal stress in the tensile direction, and the magnitude increases as the thickness increases. Tensile stress is one of the factors that reduce the adhesion between films, and when excessive stress is applied to the solder bumps, there is a possibility that peeling will occur easily at the part where the adhesion is reduced by the internal stress. is there.

また、バリアメタル層が薄い場合には、熱膨張差に起因する応力はバンプ部に集中するところ、バリアメタル層を厚くするに伴い、バリアメタル層を引き剥がす様にバリアメタル層の端部に応力が集中してしまう。本発明者が、有限要素法によるシミュレーションで、シリコンチップと樹脂基板とのフリップチップ接続後にはんだバンプ接続部に生じる応力を調べた結果、バリアメタル層のＮｉ厚さを１μｍとしたバンプ接続部では約３ＧＰａの応力がバンプ部に生じているのに対し、Ｎｉを５μｍとした場合は、バリアメタル層の端部に１０ＧＰａ以上の応力が生じていた。このシミュレーションでは、はんだ材料はＳｎ−３．５％Ａｇ合金、バリアメタル層は、０．０５μｍ厚のＴｉ／０．５μｍ厚のＣｕ／Ｎｉの３層構造とした。   In addition, when the barrier metal layer is thin, the stress due to the difference in thermal expansion concentrates on the bump part. As the barrier metal layer becomes thicker, the barrier metal layer is peeled off at the end of the barrier metal layer. Stress is concentrated. As a result of investigating the stress generated in the solder bump connection portion after flip chip connection between the silicon chip and the resin substrate by the simulation by the finite element method, the present inventor found that the bump connection portion in which the Ni thickness of the barrier metal layer is 1 μm While a stress of about 3 GPa is generated in the bump portion, when Ni is 5 μm, a stress of 10 GPa or more is generated in the end portion of the barrier metal layer. In this simulation, the solder material is a Sn-3.5% Ag alloy, and the barrier metal layer is a 0.05 μm thick Ti / 0.5 μm thick Cu / Ni three-layer structure.

図１４に示したように、従来のバリアメタル構造では、各層の径方向端部が同一位置になる。このような構造の場合、バリアメタル端部に集中した応力は、バリアメタルをピールするように（引き剥がすように）作用する。本発明者がバリアメタルを構成する各層間のピール強度を測定した結果、バリアメタルの第二の層であるＮｉ膜１０６と、第一の層を構成するＣｕ膜１０７とのピール強度は約２ｋｇｆ／ｃｍであり、Ｃｕ膜１０７とＴｉ膜１０４との密着力も２ｋｇｆ／ｃｍ以上であった。一方、Ｔｉ膜１０４とパッシベーション膜のポリイミド膜１０３とのピール強度は約０．４ｋｇｆ／ｃｍと他より低い。このため、ピール方向の応力が作用した場合には、最も弱いＴｉ膜１０４とポリイミド膜１０３との界面で剥離する。   As shown in FIG. 14, in the conventional barrier metal structure, the radial ends of the respective layers are at the same position. In the case of such a structure, the stress concentrated on the end of the barrier metal acts to peel (peel off) the barrier metal. As a result of measuring the peel strength between the layers constituting the barrier metal by the present inventor, the peel strength between the Ni film 106 as the second layer of the barrier metal and the Cu film 107 constituting the first layer is about 2 kgf. / Cm, and the adhesion between the Cu film 107 and the Ti film 104 was also 2 kgf / cm or more. On the other hand, the peel strength between the Ti film 104 and the polyimide film 103 of the passivation film is about 0.4 kgf / cm, which is lower than the others. For this reason, when the stress in the peel direction acts, the peeling occurs at the interface between the weakest Ti film 104 and the polyimide film 103.

このように、バリアメタル層を厚くした場合は、フリップチップ実装による加熱工程だけでも、比較的大きな応力がバリアメタル層端部に加わるため、極めて剥離が生じ易い状態となっている。たとえ実装工程で剥離が生じなくとも、その後の熱サイクルによって発生する応力で剥離が生じる可能性は非常に高く、長期的な接続信頼性が著しく低くなってしまう。   In this way, when the barrier metal layer is thickened, a relatively large stress is applied to the end of the barrier metal layer only in the heating process by flip chip mounting, so that peeling is very likely to occur. Even if peeling does not occur in the mounting process, the possibility of peeling due to the stress generated by the subsequent thermal cycle is very high, and the long-term connection reliability is significantly reduced.

本発明は、以上の問題を鑑みてなされたものであり、半導体チップ上にＰｂフリー材料によるはんだバンプを形成し、且つ、はんだ材料から発生したα線によるソフトエラーを回避するために、バリアメタル層の厚みを厚くした場合であっても、フリップチップ実装後の加熱冷却サイクルでバンプ接続部に発生する応力に由来したバリアメタル層の剥離を防止することのできる半導体装置およびその製造方法を提供することを目的とする。   The present invention has been made in view of the above problems, and in order to form a solder bump made of a Pb-free material on a semiconductor chip and to avoid a soft error due to α rays generated from the solder material, a barrier metal is provided. Provided is a semiconductor device capable of preventing peeling of a barrier metal layer caused by stress generated in a bump connection portion in a heating / cooling cycle after flip chip mounting even when the thickness of the layer is increased, and a manufacturing method thereof The purpose is to do.

上記目的を達成する、本発明は、半導体素子が形成された半導体チップと、この半導体チップの表面に形成されて前記半導体素子と電気的に接続する電極パッドと、この電極パッド上に形成されたバンプ電極とを備え、前記電極パッドが複数の金属層で構成された積層体からなり、この金属層のうち、バンプ電極と接して形成されている金属層に比べて、半導体チップの表面寄りに形成されている金属層はα線遮蔽能が高く、かつ径方向の寸法が大きいことを特徴とする半導体装置である。   To achieve the above object, the present invention provides a semiconductor chip on which a semiconductor element is formed, an electrode pad formed on the surface of the semiconductor chip and electrically connected to the semiconductor element, and formed on the electrode pad. A bump electrode, and the electrode pad is composed of a laminate composed of a plurality of metal layers, and the metal layer is closer to the surface of the semiconductor chip than the metal layer formed in contact with the bump electrode. The formed metal layer is a semiconductor device characterized in that the α-ray shielding ability is high and the radial dimension is large.

また、本発明の半導体装置においては、前記バンプ電極と接して形成されている金属層の径方向端部に比べて、前記半導体チップの表面寄りに形成されている金属層の径方向端部は、５μｍ以上外側に位置することが好ましい。   Further, in the semiconductor device of the present invention, the radial end of the metal layer formed closer to the surface of the semiconductor chip than the radial end of the metal layer formed in contact with the bump electrode is It is preferable to be located outside by 5 μm or more.

また、本発明の半導体装置においては、前記バンプ電極と接して形成されている金属層の側方で、かつこの金属層より下側の金属層上に、樹脂からなる永久レジスト層が形成されていることが好ましい。   In the semiconductor device of the present invention, a permanent resist layer made of a resin is formed on the side of the metal layer formed in contact with the bump electrode and on the metal layer below the metal layer. Preferably it is.

また、本発明の半導体装置においては、前記永久レジスト層の外周端が、はんだバンプ電極の最大径部における径方向端部よりも外側に配されていることが好ましい。   In the semiconductor device of the present invention, it is preferable that the outer peripheral end of the permanent resist layer is disposed outside the radial end portion of the maximum diameter portion of the solder bump electrode.

また、本発明の半導体装置の製造方法は、導電金属体である接続電極と、この接続電極の上方が開口された絶縁性保護膜とが表面に形成された半導体チップに対し、前記半導体チップ表面の全面にわたり、１層または２層以上の第一の金属層を形成する工程と、前記金属層上に、樹脂からなる永久レジスト層を、前記接続電極の上方に当たる部分を開口したリング状に形成する工程と、前記永久レジスト層および第一の金属層上に、前記接続電極の上方に当たる部分を開口しためっきレジストを形成する工程と、前記第一の金属層を陰極として、この第一の金属層上に第二の金属層を電気っきにより形成する工程と、前記第二の金属層を陰極として、この第二の金属層上にはんだ膜を電気めっきにより形成する工程と、前記めっきレジストを除去する工程と、前記はんだ膜および永久レジスト層をレジストとして、第一の金属層をエッチング除去する工程と、はんだ膜にフラックスを塗布し、はんだの溶融温度以上に加熱し冷却することにより、はんだ膜が半球状に固化したパンプ電極を形成するする工程とを具備することを特徴とする。   The method for manufacturing a semiconductor device according to the present invention provides a semiconductor chip surface with respect to a semiconductor chip in which a connection electrode which is a conductive metal body and an insulating protective film having an opening above the connection electrode are formed on the surface. Forming a first metal layer of one layer or two or more layers over the entire surface, and forming a permanent resist layer made of resin on the metal layer in a ring shape with an opening corresponding to the upper side of the connection electrode A step of forming a plating resist on the permanent resist layer and the first metal layer, wherein the portion corresponding to the upper side of the connection electrode is opened, and the first metal layer as a cathode. Forming a second metal layer on the layer by electroplating, forming a solder film on the second metal layer by electroplating using the second metal layer as a cathode, and the plating resist The Removing the first metal layer by using the solder film and the permanent resist layer as a resist, applying a flux to the solder film, and heating and cooling to a temperature higher than the melting temperature of the solder, Forming a pump electrode in which the film is solidified into a hemisphere.

または、本発明の半導体装置の製造方法においては、前記めっきレジストの開口端が、前記の永久レジスト層の開口端よりも径方向の外側に位置することが好ましい。   Or in the manufacturing method of the semiconductor device of this invention, it is preferable that the opening end of the said plating resist is located in the radial direction outer side rather than the opening end of the said permanent resist layer.

本発明によれば、フリップチップ実装後の加熱冷却サイクルでバンプ接続部に発生する応力によるバリアメタル層の剥離を防止できる半導体素子を提供することを可能とする。   ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the semiconductor element which can prevent peeling of the barrier metal layer by the stress which generate | occur | produces in a bump connection part in the heating / cooling cycle after flip chip mounting.

以下に本発明の実施の形態を示す。なお、本発明は以下の実施形態に限定されることなく、種々変更して用いることができる。   Embodiments of the present invention will be described below. The present invention is not limited to the following embodiments and can be used with various modifications.

図１は本発明によるはんだバンプ電極が形成された半導体チップ断面の概略図を示している。半導体チップ１ＡはＳｉ上に形成されたトランジスタやメモリセル等の能動領域２と、絶縁層と金属配線とからなる多層配線層３の領域から構成される。また、多層配線層３上にはＡｌやＣｕを主体とする接続電極４が形成され、さらに、チップ表面全体はＳｉＯ２膜、ＳｉＮ膜の積層膜８とポリイミド膜５を積層したパッシベーション膜によりコーティングされており、このパッシベーション膜は前記接続電極４部のみが開口された構造となっている。接続電極４の厚さは約０．３μｍである。また、パッシベーション膜の表面のポリイミド膜５の厚さは約３μｍであり、α線の遮蔽膜としても機能する。 FIG. 1 is a schematic view of a cross section of a semiconductor chip on which solder bump electrodes according to the present invention are formed. The semiconductor chip 1A includes an active region 2 such as a transistor or a memory cell formed on Si, and a region of a multilayer wiring layer 3 including an insulating layer and a metal wiring. Further, a connection electrode 4 mainly composed of Al or Cu is formed on the multilayer wiring layer 3, and the entire chip surface is coated with a passivation film in which a laminated film 8 of a SiO 2 film, a SiN film and a polyimide film 5 are laminated. The passivation film has a structure in which only the connection electrode 4 is opened. The thickness of the connection electrode 4 is about 0.3 μm. Further, the polyimide film 5 on the surface of the passivation film has a thickness of about 3 μm, and functions as an α-ray shielding film.

接続電極４上には、複数の金属層からなるバリアメタル層が形成されていて、本実施形態においては、このバリアメタル層と接続電極４とで、バンプ電極（はんだパンプ）と接続する電極パッドを構成している。バリアメタル層のうち、接続電極４の直上には、第一の金属層が形成されている。この第一の金属層はＴｉ膜６とＣｕ膜７の積層膜であり、接続電極４ないしポリイミド膜５に接する部分はＴｉ膜６で形成されている。Ｔｉ膜６の厚さは約０．０５μｍであり、Ｃｕ膜７の厚さは約１μｍである。このＴｉ膜６とＣｕ膜７の積層膜からなる第一の金属層の径方向端部は、はんだバンプ電極１１の最大径部での径方向端部（はんだバンプを直上より第一の金属層表面に投影した場合の投影像の端部）よりも外側に位置している。   A barrier metal layer composed of a plurality of metal layers is formed on the connection electrode 4. In this embodiment, an electrode pad that is connected to a bump electrode (solder bump) with this barrier metal layer and the connection electrode 4. Is configured. Of the barrier metal layer, a first metal layer is formed immediately above the connection electrode 4. The first metal layer is a laminated film of a Ti film 6 and a Cu film 7, and a portion in contact with the connection electrode 4 or the polyimide film 5 is formed of the Ti film 6. The thickness of the Ti film 6 is about 0.05 μm, and the thickness of the Cu film 7 is about 1 μm. The radial end portion of the first metal layer formed of the laminated film of the Ti film 6 and the Cu film 7 is the radial end portion at the maximum diameter portion of the solder bump electrode 11 (the first metal layer is directly above the solder bump). It is located outside the edge of the projected image when projected onto the surface.

第一の金属層上には、第一の金属層より厚い第二の金属層が形成されており、この第二の金属層は、はんだバンプ電極１１と接している。この第二の金属層は、本実施形態ではＮｉ膜９で構成されており、その厚さは約５μｍである。Ｎｉ及びＣｕは、α線遮蔽能が高い材料であり、第二の金属層であるＮｉ膜９と第一の金属層のＣｕ膜７とを合わせると約６μｍの厚さとなるため、はんだバンプから発生するα線に対する遮蔽能力は十分高い。   A second metal layer thicker than the first metal layer is formed on the first metal layer, and the second metal layer is in contact with the solder bump electrode 11. This second metal layer is composed of the Ni film 9 in the present embodiment, and its thickness is about 5 μm. Ni and Cu are materials having high α-ray shielding ability, and when the Ni film 9 as the second metal layer and the Cu film 7 as the first metal layer are combined, the thickness becomes about 6 μm. The shielding ability against the generated α rays is sufficiently high.

バンプ電極と接して形成されている第二の金属層（Ｎｉ膜９）に比べて、前述した半導体チップの表面寄りに形成されている第一の金属層は径方向の寸法が大きくなっており、好ましくは、第一の金属層の径方向端部が第二の金属層の径方向端部よりも、５μｍ以上外側に位置するようにする。   Compared to the second metal layer (Ni film 9) formed in contact with the bump electrode, the first metal layer formed closer to the surface of the semiconductor chip has a larger dimension in the radial direction. Preferably, the radial end of the first metal layer is positioned 5 μm or more outside the radial end of the second metal layer.

また、バリアメタル層を構成する第二の金属層（Ｎｉ膜９）の側方でかつ第一の金属層の表面上には、永久レジスト層として機能するポリイミド膜１０が形成されている。このポリイミド膜１０の厚みは約５μｍであり、はんだバンプから発生するα線の遮蔽膜としても機能する。   A polyimide film 10 that functions as a permanent resist layer is formed on the side of the second metal layer (Ni film 9) constituting the barrier metal layer and on the surface of the first metal layer. The polyimide film 10 has a thickness of about 5 μm and functions as a shielding film for α rays generated from the solder bumps.

さらに、第二の金属層であるＮｉ膜９上には、電気めっき法とその後のリフロー工程により形成された半球状のはんだバンプ電極１１が配置されている。はんだ材料は、ＰｂフリーはんだであるＳｎとＡｇからなる合金であり、その組成はＳｎが９６．５重量％、Ａｇが３．５重量％である。   Furthermore, a hemispherical solder bump electrode 11 formed by an electroplating method and a subsequent reflow process is disposed on the Ni film 9 which is the second metal layer. The solder material is an alloy composed of Sn and Ag, which is a Pb-free solder, and the composition thereof is 96.5% by weight of Sn and 3.5% by weight of Ag.

以上述べたような本発明に従う電極パッドの構造であれば、フリップチップ実装後に、熱膨張差に起因した応力が、電極パッドを構成しているバリアメタルの第二の金属層であるＮｉ膜９端部に集中しても、下地Ｃｕ膜７に対するＮｉ膜９のピール強度は約２ｋｇｆ／ｃｍと大きいため、その界面でＮｉ膜９が剥離することはない。一方、第一の金属層であるＴｉ膜６とパッシベーション膜のポリイミド膜５との密着力は、既に述べたとおりＮｉ膜９とＣｕ膜７との密着力よりも低いが、本発明の構成では、第一の金属層は第二の金属層よりも径方向の寸法が大きく、好ましくは、第一の金属層の径方向端部が第二の金属層（Ｎｉ膜９）の径方向端部よりも、５μｍ以上外側に位置していることから、仮に第二の層の端部に応力が集中しても、その応力は第一の層の端部にはほとんど加わらず、第一の層の端部に作用する応力すなわちピール力は僅かである。したがって、Ｃｕ膜７とＴｉ膜６からなる第一の層がポリイミド膜５との界面においても剥離することはない。   In the electrode pad structure according to the present invention as described above, after flip chip mounting, the stress due to the difference in thermal expansion causes the Ni film 9 which is the second metal layer of the barrier metal constituting the electrode pad. Even if concentrated on the edge, the peel strength of the Ni film 9 relative to the underlying Cu film 7 is as large as about 2 kgf / cm, so the Ni film 9 does not peel off at the interface. On the other hand, the adhesion force between the Ti film 6 as the first metal layer and the polyimide film 5 as the passivation film is lower than the adhesion force between the Ni film 9 and the Cu film 7 as described above. The first metal layer has a larger dimension in the radial direction than the second metal layer. Preferably, the radial end of the first metal layer is the radial end of the second metal layer (Ni film 9). Than the first layer, even if stress is concentrated on the end of the second layer, the stress is hardly applied to the end of the first layer. The stress acting on the end of the film, that is, the peel force, is slight. Therefore, the first layer composed of the Cu film 7 and the Ti film 6 is not peeled even at the interface with the polyimide film 5.

以上のことから、本発明の半導体装置は、パンプ電極として鉛含有量が２０００ｐｐｍ以下で含まれている合金よりなる、いわゆるＰｂフリーはんだを材料として用いた場合であっても、剥離が生じることを防止することができ、信頼性の高い半導体装置を得ることができるのである。   From the above, the semiconductor device of the present invention shows that peeling occurs even when a so-called Pb-free solder made of an alloy containing a lead content of 2000 ppm or less is used as a pump electrode. Therefore, a highly reliable semiconductor device can be obtained.

本発明の半導体装置において、バンプ電極と接して形成されている金属層は、α線遮蔽能が高い材料であることが好ましく、そのため、図１においては、Ｎｉを材料としている。本発明は、このＮｉに限らず、例えば、Ｃｕもα線遮蔽能が高いので用いることができる。また、純金属に限らず、Ｃｕを８０重量％以上含む合金、または、Ｎｉを８０重量％以上含む合金の少なくとも一つを用いることもできる。また、その金属層の厚みは、α線遮蔽の観点からは、厚いほうが好ましいが、少なくとも２μｍより厚ければ所望のα線遮蔽効果が得られる。   In the semiconductor device of the present invention, the metal layer formed in contact with the bump electrode is preferably a material having a high α-ray shielding ability, and therefore Ni is used as the material in FIG. The present invention is not limited to this Ni. For example, Cu can also be used because it has a high α-ray shielding ability. Moreover, not only a pure metal but at least one of the alloy containing 80 weight% or more of Cu or the alloy containing 80 weight% or more of Ni can also be used. The thickness of the metal layer is preferably thicker from the viewpoint of α-ray shielding, but if it is thicker than at least 2 μm, a desired α-ray shielding effect can be obtained.

図２〜図７に、本発明の半導体装置の製造方法に従う半導体チップ上へのバンプ電極の製造工程の実施例を時系列的に断面図で示す。   FIG. 2 to FIG. 7 show, in a sectional view, time-series examples of manufacturing steps of bump electrodes on a semiconductor chip according to the method of manufacturing a semiconductor device of the present invention.

先ず、図２に示すような半導体素子が形成された半導体ウェハ１を準備する。半導体ウェハ１はシリコンに限らず、ガリウム砒素、インジュウム燐等の化合物半導体のウェハでも良い。半導体ウェハ１は前記したように、能動領域２と多層配線層３を含んでいる。半導体ウェハ１上には能動素子と接続する接続電極４が形成されていると共に、この接続電極４の上方が円形に開口されたパッシベーション膜で半導体ウェハ１表面が覆われている。このパッシベーション膜は前記したように、ＳｉＯ２膜、ＳｉＮ膜の積層膜８とポリイミド膜５の積層膜であり、表層はポリイミド膜５である。なお、半導体素子のサイズ、パッド電極の数、寸法、及びピッチは、任意とすることができ、適宜選択することができる。 First, a semiconductor wafer 1 on which a semiconductor element as shown in FIG. 2 is formed is prepared. The semiconductor wafer 1 is not limited to silicon, but may be a compound semiconductor wafer such as gallium arsenide or indium phosphorus. As described above, the semiconductor wafer 1 includes the active region 2 and the multilayer wiring layer 3. A connection electrode 4 connected to an active element is formed on the semiconductor wafer 1, and the surface of the semiconductor wafer 1 is covered with a passivation film having a circular opening above the connection electrode 4. As described above, the passivation film is a laminated film of the laminated film 8 of the SiO 2 film and the SiN film and the polyimide film 5, and the surface layer is the polyimide film 5. The size of the semiconductor element, the number of pad electrodes, the dimensions, and the pitch can be arbitrarily selected and can be appropriately selected.

次に、図３に示すように、接続電極４およびパッシベーション膜が形成された半導体ウェハ１上にバリアメタルとしての第一の金属層となるＴｉ膜６、Ｃｕ膜７をスパッタリング法等により連続的に積層する。ここで、Ｔｉ膜６の成膜に先立ち、ポリイミド膜５および接続電極４の表面を逆スパッタすることにより、Ｔｉ膜６とポリイミド膜５との密着力を高めることができる。   Next, as shown in FIG. 3, a Ti film 6 and a Cu film 7 serving as a first metal layer as a barrier metal are continuously formed on the semiconductor wafer 1 on which the connection electrode 4 and the passivation film are formed by a sputtering method or the like. Laminate to. Here, the adhesion between the Ti film 6 and the polyimide film 5 can be increased by reverse sputtering the surfaces of the polyimide film 5 and the connection electrode 4 prior to the formation of the Ti film 6.

第一の金属層のうち、Ｃｕ膜７は、後述する電気めっき工程時に陰極として作用するものであり、そのシート抵抗は、その後に成膜されるめっき膜の膜厚分布に影響を及ぼす。例えば、直径２００ｍｍのシリコンウェハに対しては、Ｃｕ膜は１μｍの厚さで実用上問題の無い膜厚分布が得られる。   Of the first metal layer, the Cu film 7 acts as a cathode during an electroplating process described later, and its sheet resistance affects the film thickness distribution of the plating film formed thereafter. For example, for a silicon wafer having a diameter of 200 mm, the Cu film has a thickness of 1 μm, and a film thickness distribution having no practical problem can be obtained.

Ｔｉ膜６は、Ｃｕ膜７と接続電極４およびポリイミド膜５との密着性を高める接着層として作用する。したがって、Ｔｉ膜６の膜厚は薄くてもよく、０．０５μｍ程度で十分である。パッシベーション膜として用いるポリイミド膜５に直接Ｃｕ膜を成膜した場合、高い密着力を得ることは困難であるが、前記Ｔｉ膜６を接着層として介在させることにより、Ｃｕ膜７の剥離を防止することができる。なお、これらの積層膜は、膜界面に酸化膜が介在すると著しく密着力が低下するため、自然酸化膜の介在を防止する目的で真空状態を破ることなく連続的に形成することが好ましい。   The Ti film 6 acts as an adhesive layer that improves the adhesion between the Cu film 7, the connection electrode 4, and the polyimide film 5. Therefore, the thickness of the Ti film 6 may be thin, and about 0.05 μm is sufficient. When a Cu film is directly formed on the polyimide film 5 used as a passivation film, it is difficult to obtain a high adhesion force, but the Cu film 7 is prevented from peeling by interposing the Ti film 6 as an adhesive layer. be able to. Note that these laminated films are preferably formed continuously without breaking the vacuum state in order to prevent the natural oxide film from intervening because the adhesion is remarkably lowered when the oxide film is present at the film interface.

この後、図４に示すように、Ｔｉ／Ｃｕ積層膜上に永久レジスト層としてのポリイミド膜１０を選択的に形成する。この永久レジスト層には、感光性（ネガ型）のポリイミド膜を用いた。永久レジスト層の形成には、まず、ポリイミド前駆体であるワニスをスピンコート法によりＴｉ／Ｃｕ積層膜が形成されたウェハ全面に形成し、ベークを行い、次いで、パッシベーション膜に形成された開口周辺を取り囲む様なリング状のパタ−ンを形成すべく、同形状にパターンが開口した遮光ガラスマスクを用い、露光・現像工程を行って当該形状を選択的に形成する。その後、キュアを行いポリイミドパターンを形成する。この永久レジスト層のリングパターンの開口端は、パッシベーション膜の開口端よりも外側のパッシベーション膜上に設けるのが信頼性上好ましい。また、ポリイミド膜の厚みはキュア後５μｍであり、リングの幅は１５μｍとした。本実施例では永久レジスト層（ポリイミド膜１０）を円形のリング形状としたが、開口部の形状や外形の形状は任意であり、また、特に対称形でなくても構わない。この永久レジスト層は、後のＣｕ膜７およびＴｉ膜６のエッチング時におけるエッチングレジストとして作用し、また、はんだバンプ溶融時のソルダレジストとしても作用する。さらに、α線の遮蔽作用も有する。   Thereafter, as shown in FIG. 4, a polyimide film 10 as a permanent resist layer is selectively formed on the Ti / Cu laminated film. For this permanent resist layer, a photosensitive (negative type) polyimide film was used. For the formation of the permanent resist layer, first, a varnish, which is a polyimide precursor, is formed on the entire surface of the wafer on which the Ti / Cu laminated film is formed by spin coating, baked, and then the periphery of the opening formed in the passivation film In order to form a ring-shaped pattern that surrounds, a light-shielding glass mask having a pattern opened in the same shape is used, and the shape is selectively formed by performing an exposure / development process. Thereafter, curing is performed to form a polyimide pattern. It is preferable from the viewpoint of reliability that the opening end of the ring pattern of the permanent resist layer is provided on the passivation film outside the opening end of the passivation film. The thickness of the polyimide film was 5 μm after curing, and the ring width was 15 μm. In this embodiment, the permanent resist layer (polyimide film 10) has a circular ring shape. However, the shape of the opening and the shape of the outer shape are arbitrary, and may not be particularly symmetric. This permanent resist layer acts as an etching resist when the Cu film 7 and Ti film 6 are etched later, and also acts as a solder resist when melting the solder bumps. Furthermore, it also has an α ray shielding function.

この後、図５に示すように、半導体ウェハ１上にめっきレジスト１２を形成し、パターニングを行う。めっきレジスト１２には、厚膜形成可能な高粘度なポジ型レジストを使用し、レジストの厚さは約６０μｍとした。レジストパターンは、まずスピンコート法によりレジストを塗布後、プリベークを行い、露光・現像により形成する。この際、めっきレジスト１２の開口端は、永久レジスト層（ポリイミド膜１０）の開口端よりも外側の、永久レジスト層上になるようにパターニングした。   Thereafter, as shown in FIG. 5, a plating resist 12 is formed on the semiconductor wafer 1 and patterned. As the plating resist 12, a high-viscosity positive resist capable of forming a thick film was used, and the thickness of the resist was about 60 μm. The resist pattern is formed by first applying a resist by a spin coating method, pre-baking, and then exposing and developing. At this time, the opening end of the plating resist 12 was patterned on the permanent resist layer outside the opening end of the permanent resist layer (polyimide film 10).

次に、めっきレジスト１２を形成したウェハにＮｉめっきを行う。Ｎｉめっきは、成膜速さが無電解めっきに比べ高速で、めっき液管理が容易な電気めっき法により形成する。電気めっき装置には、めっき液の濃度がウェハ表面で均一になるような噴流式めっき装置（図示せず）を用いる。また、Ｎｉめっき液には、硫酸ニッケル、塩化ニッケル、ホウ酸の混合溶液に、界面活性剤とサッカリンを微量添加しためっき液を用いた。Ｎｉめっき膜と下地のＣｕ膜７との密着性を高めるため、Ｎｉめっきの直前にウェハをクエン酸の希釈溶液に浸漬し、Ｃｕ表面をライトエッチングした。その後、直流電流供給源の負極を、陰極となるＣｕ膜７に接触させ、陽極にＮｉ板を用いめっき液中で通電することにより、めっきレジスト１２の開口部にＮｉ膜９を形成した。このＮｉ膜の厚さが５μｍとなる間通電し、その後水洗し、続けてはんだ膜を電気めっきにより形成する。   Next, Ni plating is performed on the wafer on which the plating resist 12 is formed. Ni plating is formed by an electroplating method in which the deposition rate is higher than that of electroless plating and the plating solution is easily managed. As the electroplating apparatus, a jet type plating apparatus (not shown) that makes the concentration of the plating solution uniform on the wafer surface is used. As the Ni plating solution, a plating solution obtained by adding a trace amount of a surfactant and saccharin to a mixed solution of nickel sulfate, nickel chloride, and boric acid was used. In order to improve the adhesion between the Ni plating film and the underlying Cu film 7, the wafer was immersed in a diluted solution of citric acid immediately before Ni plating, and the Cu surface was light-etched. Thereafter, the negative electrode of the direct current supply source was brought into contact with the Cu film 7 serving as the cathode, and a Ni plate 9 was used as the anode to energize in the plating solution, thereby forming the Ni film 9 in the opening of the plating resist 12. Energization is performed while the thickness of the Ni film becomes 5 μm, and then the substrate is washed with water. Subsequently, a solder film is formed by electroplating.

はんだ膜を形成する際に、はんだめっき液にはスルホン酸系のめっき液を用いた。めっき後の膜中のＳｎ、Ａｇの組成比が９６．５対３．５となる様にＳｎイオン、Ａｇイオンの量を調節する。陽極に同組成のＳｎＡｇ合金板を用い、Ｎｉめっきと同様に電流供給源を接続し、所定の時間通電することにより、図６に示すように、めっきレジスト１２の開口部のＮｉ膜９上に、はんだ膜１３が形成される。はんだ膜１３の厚さは約５０μｍとした。Ｃｕ膜７、Ｔｉ膜６からなる積層膜はめっきにおける下地電極となるが、Ｔｉに比べ抵抗率が低いＣｕ膜７が約１μmの厚さでウェハ全面にわたり形成されているため、下地電極のシート抵抗は低く、給電部周囲への電流集中が緩和されるから、ウェハ内でのＮｉ膜９とはんだめっき膜１３との合計膜厚分布は±１０％以内（２００ｍｍ径ウェハにおいて）であった。   When forming the solder film, a sulfonic acid-based plating solution was used as the solder plating solution. The amounts of Sn ions and Ag ions are adjusted so that the composition ratio of Sn and Ag in the film after plating is 96.5 to 3.5. Using a SnAg alloy plate of the same composition as the anode, connecting a current supply source in the same manner as Ni plating, and energizing for a predetermined time, as shown in FIG. 6, on the Ni film 9 in the opening of the plating resist 12 The solder film 13 is formed. The thickness of the solder film 13 was about 50 μm. The laminated film composed of the Cu film 7 and the Ti film 6 serves as a base electrode in plating. However, since the Cu film 7 having a resistivity lower than that of Ti is formed over the entire surface of the wafer with a thickness of about 1 μm, the base electrode sheet Since the resistance is low and current concentration around the power feeding portion is relaxed, the total film thickness distribution of the Ni film 9 and the solder plating film 13 within the wafer is within ± 10% (in a 200 mm diameter wafer).

続いて、めっきレジスト１２を剥離液により溶解除去する。さらに、図７に示すように、はんだ膜１３および永久レジスト層をエッチングレジストとして、永久レジスト層（ポリイミド膜）１０外側のＣｕ膜７、Ｔｉ膜６からなる積層膜を除去する。この際、Ｃｕのエッチングには、塩化銅と塩酸の混合溶液を用い、Ｔｉのエッチングには、アンモニア水、過酸化水素水、エチレンジアミン四酢酸（ＥＤＴＡ）の混合溶液を用いた。この後、ウェハ１を高圧水洗する。   Subsequently, the plating resist 12 is removed by dissolution with a stripping solution. Further, as shown in FIG. 7, the laminated film composed of the Cu film 7 and the Ti film 6 outside the permanent resist layer (polyimide film) 10 is removed using the solder film 13 and the permanent resist layer as an etching resist. At this time, a mixed solution of copper chloride and hydrochloric acid was used for etching Cu, and a mixed solution of aqueous ammonia, hydrogen peroxide, and ethylenediaminetetraacetic acid (EDTA) was used for etching Ti. Thereafter, the wafer 1 is washed with high pressure water.

このようにして出来たバンプ電極付きウェハ１の表面に、ロジン変性誘導体を主体としたフラックスを塗布する（図示せず）。その後、気相リフロー炉に通し、２５０℃程度で加熱し、はんだ膜１３を溶融冷却することにより、図８に示すように半球状のはんだバンプ電極１１が形成された半導体装置を得ることができる。   A flux mainly composed of a rosin-modified derivative is applied to the surface of the wafer 1 with bump electrodes thus formed (not shown). Thereafter, it is passed through a vapor phase reflow furnace, heated at about 250 ° C., and the solder film 13 is melted and cooled to obtain a semiconductor device in which hemispherical solder bump electrodes 11 are formed as shown in FIG. .

以上のようにして形成した本発明に従うバンプ付き半導体ウェハ１と、図９〜１４に示した従来法で形成したバンプ付きウェハ１０１とを、それぞれチップ状にダイシングし、樹脂基板に対しフリップチップ実装した。図１５には、フリップチップ実装後の外観概略を示した。樹脂基板４３には、ガラスエポキシ基板をコアとして表層に絶縁層４２と配線層４１を積層したビルドアップ配線基板を用いた。基板上におけるはんだバンプ電極４５の対極となる電極パッド４４表面には、はんだバンプ電極４５と同組成のＳｎＡｇ合金めっきを施した。フリップチップ実装においては、半導体チップ４６のバンプ形成面および基板の電極面にフラックスを塗布し、フリップチップボンダー等を用いて、はんだバンプ電極４５と基板上の電極パッド４４を位置合わせし仮固定した後、ピーク温度２５０℃程度の気相リフロー炉に通し接続を行った。半導体チップ４６と基板４３間の熱膨張係数の相違により接続部に生じる応力を緩和する目的で、半導体チップ４６と基板４３間は樹脂４７で封止した。封止樹脂としてはビスフェノール系エポキシとイミダゾール硬化触媒、酸無水物硬化材と球状の石英フィラーを含有するエポキシ樹脂を用いた。   The bumped semiconductor wafer 1 according to the present invention formed as described above and the bumped wafer 101 formed by the conventional method shown in FIGS. 9 to 14 are each diced into chips and mounted on a resin substrate by flip chip mounting. did. FIG. 15 shows an outline of the appearance after flip chip mounting. As the resin substrate 43, a build-up wiring substrate in which a glass epoxy substrate is used as a core and an insulating layer 42 and a wiring layer 41 are laminated on the surface layer is used. The surface of the electrode pad 44 that is the counter electrode of the solder bump electrode 45 on the substrate was plated with SnAg alloy having the same composition as the solder bump electrode 45. In flip chip mounting, flux is applied to the bump forming surface of the semiconductor chip 46 and the electrode surface of the substrate, and the solder bump electrode 45 and the electrode pad 44 on the substrate are aligned and temporarily fixed using a flip chip bonder or the like. Thereafter, connection was made through a gas phase reflow furnace having a peak temperature of about 250 ° C. The resin chip 47 was sealed between the semiconductor chip 46 and the substrate 43 in order to relieve stress generated in the connection portion due to the difference in thermal expansion coefficient between the semiconductor chip 46 and the substrate 43. As the sealing resin, an epoxy resin containing a bisphenol-based epoxy and an imidazole curing catalyst, an acid anhydride curing material and a spherical quartz filler was used.

図１６は、上述したフリップチップ実装後の接続信頼性試験の結果を示している。図中の試料ａは本発明の半導体チップ、ｂは従来法による半導体チップを用いた試料を示している。   FIG. 16 shows the result of the connection reliability test after the flip-chip mounting described above. In the figure, sample a is a semiconductor chip of the present invention, and b is a sample using a conventional semiconductor chip.

試験は１２ｍｍ×１２ｍｍ大のチップを用い、チップ上の配線と基板上の配線を１００μｍ径のバンプで接続したチェーン（バンプ数：２５６個）を作製し、温度サイクル試験を行った。試験条件は−５５℃（３０分）〜２５℃（５分）〜１２５℃（３０分）〜２５℃（５分）で行い、２００サイクル毎に回路端の抵抗を測定し、２５６ピンの中で１箇所でも接続がオープンになった場合を不良として累積不良率を調べた。   In the test, a 12 mm × 12 mm chip was used, a chain (the number of bumps: 256) in which the wiring on the chip and the wiring on the substrate were connected by bumps having a diameter of 100 μm was prepared, and a temperature cycle test was performed. The test conditions are -55 ° C (30 minutes) to 25 ° C (5 minutes) to 125 ° C (30 minutes) to 25 ° C (5 minutes), and the resistance of the circuit end is measured every 200 cycles. Thus, the cumulative failure rate was examined by assuming that the connection was open even at one location.

試料は、a、ｂともに３０個作製したが、実装後の段階で、試料ａでは不良は見られなかったのに対し、試料ｂでは接続不良が４個の試料で見られた。図１６は、累積不良率の温度サイクル依存性を示している。図に示されるように、試料ｂは約８００サイクルで不良率が１００％に達した。一方、試料ａは１６００サイクル付近まで不良は発生せず、高い接続信頼性を示した。また、試験後の試料断面を観察した結果、試料ｂでは全てバリアメタル層の剥離に起因するチップ配線の断線であったのに対し、試料ａの不良モードははんだバンプの疲労破壊であった。   30 samples were prepared for both a and b. At the stage after mounting, no failure was found in sample a, whereas in sample b, connection failure was seen in 4 samples. FIG. 16 shows the temperature cycle dependency of the cumulative defect rate. As shown in the figure, the defect rate of sample b reached 100% in about 800 cycles. On the other hand, the sample a showed no defect until around 1600 cycles, and showed high connection reliability. Moreover, as a result of observing the cross section of the sample after the test, in sample b, all of the chip wirings were disconnected due to the peeling of the barrier metal layer, whereas in the sample a, the failure mode was fatigue failure of the solder bumps.

以上、図面を用いて本発明の実施形態を説明したが、本発明は前記実施形態に限定されるものでなく、その要旨を逸脱しない範囲で変更して実施し得る。例えば、はんだのめっき方法として、合金膜を一度にめっきする代わりに、合金を構成する金属を異なるめっき液で逐次めっきし、積層膜として形成する方法を用いても良い。この場合、リフロー工程でのはんだ溶融時に、積層膜は相互拡散し合金化する。   As mentioned above, although embodiment of this invention was described using drawing, this invention is not limited to the said embodiment, It can change and implement in the range which does not deviate from the summary. For example, as a solder plating method, instead of plating an alloy film at a time, a method of sequentially plating metals constituting the alloy with different plating solutions to form a laminated film may be used. In this case, when the solder is melted in the reflow process, the laminated film is interdiffused and alloyed.

また、ウェハ、バリアメタル、永久レジスト、はんだバンプ、レジストはその材質、組成、寸法などに関して種々変更して用いることができ、めっき液の組成やめっきを行う際の諸条件も前記例示に限定されないことはむろんである。さらに、はんだ膜の形成方法は、特にめっき法に限定されるものではなく、印刷法、ディスペンス法、転写法等も用いることができる。   In addition, wafers, barrier metals, permanent resists, solder bumps, resists can be used with various changes in materials, compositions, dimensions, etc., and the composition of the plating solution and various conditions for plating are not limited to the above examples. That is of course. Furthermore, the method for forming the solder film is not particularly limited to the plating method, and a printing method, a dispensing method, a transfer method, and the like can also be used.

本発明の半導体装置の断面概略図。1 is a schematic cross-sectional view of a semiconductor device of the present invention. 本発明の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the semiconductor device of this invention. 従来の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を説明する断面図。Sectional drawing explaining the manufacturing method of the conventional semiconductor device. フリップチップ実装した半導体装置の断面概略図。FIG. 6 is a schematic cross-sectional view of a flip-chip mounted semiconductor device. 本発明による半導体装置と従来法による半導体装置の信頼性試験結果を示す図。The figure which shows the reliability test result of the semiconductor device by this invention, and the semiconductor device by a conventional method.

符号の説明Explanation of symbols

１…半導体ウェハ、１Ａ…半導体チップ、４…接続電極、５…ポリイミド膜（パッシベーション膜）、６…Ｔｉ膜、７…Ｃｕ膜、９…Ｎｉ膜、１０…ポリイミド膜（永久レジスト）、１１…はんだバンプ電極、１２…めっきレジスト、１３…はんだ膜、４１…基板上配線、４２…基板上絶縁層、４３…基板、４４…基板上電極パッド、４５…はんだバンプ電極、４６…半導体チップ、４７…封止樹脂、４８…ポリイミド膜（パッシベーション膜）、４９…電極パッド、１０１…半導体ウェハ、１０２…接続電極、１０３…ポリイミド膜（パッシベーション膜）１０４…Ｔｉ膜、１０５…めっきレジスト、１０６…Ｎｉ膜、１０７…Ｃｕ膜、１０８…はんだ膜、１０９…はんだバンプ電極 DESCRIPTION OF SYMBOLS 1 ... Semiconductor wafer, 1A ... Semiconductor chip, 4 ... Connection electrode, 5 ... Polyimide film (passivation film), 6 ... Ti film, 7 ... Cu film, 9 ... Ni film, 10 ... Polyimide film (permanent resist), 11 ... Solder bump electrode, 12 ... plating resist, 13 ... solder film, 41 ... wiring on substrate, 42 ... insulating layer on substrate, 43 ... substrate, 44 ... electrode pad on substrate, 45 ... solder bump electrode, 46 ... semiconductor chip, 47 ... sealing resin, 48 ... polyimide film (passivation film), 49 ... electrode pad, 101 ... semiconductor wafer, 102 ... connection electrode, 103 ... polyimide film (passivation film) 104 ... Ti film, 105 ... plating resist, 106 ... Ni Film 107, Cu film 108, Solder film 109, Solder bump electrode

Claims (7)

半導体素子が形成された半導体チップと、この半導体チップの表面に形成されて前記半導体素子と電気的に接続する電極パッドと、この電極パッド上に形成されたバンプ電極とを備え、
前記電極パッドが複数の金属層で構成された積層体からなり、この金属層のうち、バンプ電極と接して形成されている金属層に比べて、半導体チップの表面寄りに形成されている金属層はα線遮蔽能が高く、かつ径方向の寸法が大きいことを特徴とする半導体装置。 A semiconductor chip on which a semiconductor element is formed, an electrode pad formed on the surface of the semiconductor chip and electrically connected to the semiconductor element, and a bump electrode formed on the electrode pad;
The electrode pad is composed of a laminate composed of a plurality of metal layers, and among these metal layers, the metal layer formed closer to the surface of the semiconductor chip than the metal layer formed in contact with the bump electrode Is a semiconductor device characterized by having a high α-ray shielding ability and a large radial dimension. 前記バンプ電極と接して形成されている金属層の径方向端部に比べて、前記半導体チップの表面寄りに形成されている金属層の径方向端部は、５μｍ以上外側に位置することを特徴とする請求項１に記載の半導体装置。   Compared to the radial end of the metal layer formed in contact with the bump electrode, the radial end of the metal layer formed closer to the surface of the semiconductor chip is located outside by 5 μm or more. The semiconductor device according to claim 1. 前記バンプ電極と接して形成されている金属層の側方で、かつこの金属層より下側の金属層上に、樹脂からなる永久レジスト層が形成されていることを特徴とする請求項１又は２に記載の半導体装置。   2. A permanent resist layer made of a resin is formed on a side of the metal layer formed in contact with the bump electrode and on a metal layer below the metal layer. 2. The semiconductor device according to 2. 前記永久レジスト層の外周端が、はんだバンプ電極の最大径部における径方向端部よりも外側に配されていることを特徴とする請求項３に記載の半導体装置。   4. The semiconductor device according to claim 3, wherein an outer peripheral end of the permanent resist layer is disposed outside a radial end portion of a maximum diameter portion of the solder bump electrode. 前記バンプ電極が、錫を主体とし鉛含有量が２０００ｐｐｍ以下で含まれている合金よりなることを特徴とする請求項１ないし４のいずれか１項に記載の半導体装置。   5. The semiconductor device according to claim 1, wherein the bump electrode is made of an alloy containing tin as a main component and having a lead content of 2000 ppm or less. 導電金属体である接続電極と、この接続電極の上方が開口された絶縁性保護膜とが表面に形成された半導体チップに対し、
前記半導体チップ表面の全面にわたり、１層または２層以上の第一の金属層を形成する工程と、
前記金属層上に、樹脂からなる永久レジスト層を、前記接続電極の上方に当たる部分を開口したリング状に形成する工程と、
前記永久レジスト層および第一の金属層上に、前記接続電極の上方に当たる部分を開口しためっきレジストを形成する工程と、
前記第一の金属層を陰極として、この第一の金属層上に第二の金属層を電気めっきにより形成する工程と、
前記第二の金属層を陰極として、この第二の金属層上にはんだ膜を電気めっきにより形成する工程と、
前記めっきレジストを除去する工程と、
前記はんだ膜および永久レジスト層をレジストとして、第一の金属層をエッチング除去する工程と、
はんだ膜にフラックスを塗布し、はんだの溶融温度以上に加熱し冷却することにより、はんだ膜が半球状に固化したパンプ電極を形成するする工程と
を具備することを特徴とする半導体装置の製造方法。 For a semiconductor chip in which a connection electrode that is a conductive metal body and an insulating protective film having an opening above the connection electrode are formed on the surface,
Forming one or more first metal layers over the entire surface of the semiconductor chip;
On the metal layer, forming a permanent resist layer made of a resin in a ring shape with an opening at a portion corresponding to the connection electrode; and
On the permanent resist layer and the first metal layer, a step of forming a plating resist having an opening at a portion corresponding to the upper side of the connection electrode;
Forming the second metal layer on the first metal layer by electroplating using the first metal layer as a cathode;
Forming the solder film on the second metal layer by electroplating using the second metal layer as a cathode;
Removing the plating resist;
Using the solder film and the permanent resist layer as a resist, etching the first metal layer,
Forming a bump electrode in which the solder film is solidified into a hemisphere by applying a flux to the solder film and heating and cooling to a temperature equal to or higher than the melting temperature of the solder. . 前記めっきレジストの開口端が、前記の永久レジスト層の開口端よりも径方向の外側に位置することを特徴とする請求項６に記載の半導体装置の製造方法。

The method for manufacturing a semiconductor device according to claim 6, wherein an opening end of the plating resist is positioned on a radially outer side than an opening end of the permanent resist layer.

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JP2010508673A (en) * 2006-10-31 2010-03-18 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Metallization layer stack without terminal aluminum metal layer
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JP2010531066A (en) * 2007-06-20 2010-09-16 フリップチップ インターナショナル エルエルシー Under bump metallization structure with seed layer for electroless nickel deposition
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