JPH08250551A - Flip-chip and manufacture and mounting thereof and burn-in inspection substrate - Google Patents

Flip-chip and manufacture and mounting thereof and burn-in inspection substrate

Info

Publication number
JPH08250551A
JPH08250551A JP5114695A JP5114695A JPH08250551A JP H08250551 A JPH08250551 A JP H08250551A JP 5114695 A JP5114695 A JP 5114695A JP 5114695 A JP5114695 A JP 5114695A JP H08250551 A JPH08250551 A JP H08250551A
Authority
JP
Japan
Prior art keywords
bump
burn
chip
flip
flip chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5114695A
Other languages
Japanese (ja)
Inventor
Teruhito Matsui
輝仁 松井
Mika Oonada
美香 大内田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5114695A priority Critical patent/JPH08250551A/en
Publication of JPH08250551A publication Critical patent/JPH08250551A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To obtain the flip-chip, which can sufficiently protect the surface at the mounting on a printed board, and can improve the yield rate. CONSTITUTION: A semiconductor chip 1, on which a pad 2 is formed at the specified position of the surface, is provided. An insulating resin layer 11 is formed so as to cover the surface of the semiconductor chip 1 and has an opening 11a reaching the upper surface of the pad 2 at the position corresponding to the pad 2. A bump is formed of a cream solder 12, which is filled in the opening 11a and formed so that the upper surface is protruding from the insularing resin layer 11. These pars parts are provided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、電極上に形成される
バンプをプリント基板のパッド部に接合することによっ
て、プリント基板上に直接搭載するフリップチップおよ
びその製造方法ならびに実装方法、そして、このフリッ
プチップの実装工程中に実施されるバーンイン検査に適
用されるバーンイン検査基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip directly mounted on a printed circuit board by bonding a bump formed on an electrode to a pad portion of the printed circuit board, a method of manufacturing the same and a method of mounting the same. The present invention relates to a burn-in test board applied to a burn-in test performed during a flip chip mounting process.

【０００２】[0002]

【従来の技術】図１１は、例えばKubota T. et al., ”
COG (Chip-On-Glass) Mounting of Siand GaAs Device
s”, 1991 JAPAN IEMT SYMPOSIUM (TOKYO) p.188に示さ
れたこの種従来のフリップチップの製造方法を示す断面
図である。図において、１は半導体チップ、２はこの半
導体チップ１上に配設されたパッド、３は燐珪酸ガラス
（ＰＳＧ）、４は導電膜、５はパッド１の上部に形成さ
れたバリアメタル層、６はめっき用レジスト、７は鉛
（Ｐｂ）層、８は錫（Ｓｎ）層、９ははんだバンプであ
る。そして、これら１〜９でフリップチップ１０が構成
される。2. Description of the Related Art FIG. 11 shows, for example, Kubota T. et al., "
COG (Chip-On-Glass) Mounting of Siand GaAs Device
s ", 1991 JAPAN IEMT SYMPOSIUM (TOKYO) p.188 is a cross-sectional view showing a method for manufacturing a conventional flip chip of this kind. In the figure, 1 is a semiconductor chip and 2 is a semiconductor chip on the semiconductor chip 1. Pads 3 are provided, 3 is phosphosilicate glass (PSG), 4 is a conductive film, 5 is a barrier metal layer formed on the pad 1, 6 is a plating resist, 7 is a lead (Pb) layer, and 8 is tin. The (Sn) layer 9 is a solder bump, and the flip chip 10 is composed of these 1 to 9.

【０００３】そして、従来のフリップチップ１０は以下
に説明するような工程を経て製造され実装されている。
まず、図１１（Ａ）に示すように、半導体チップ１上に
チップ表面を保護するために燐珪酸ガラス（ＰＳＧ）３
を塗布し、写真製版によりパッド２に対応する部分を開
口し、次いで図１１（Ｂ）に示すように、電気めっき時
の電流供給用の導電膜４を全面に形成する。フォトレジ
スト（図示せず）を塗布し写真製版によりパッド２と対
応する部分のフォトレジストを取り除く、その後バリア
メタル層５を蒸着等より形成し、このレジストを除去す
ることによりパッド２と対応する部分にのみ、バリアメ
タル層５を残す、次に図１１（Ｃ）に示すように、めっ
き用のレジスト６を形成し、同様に写真製版を用いて、
パッド２部分のレジストを除去する。そして、電気めっ
きにより鉛（Ｐｂ）層７、錫（Ｓｎ）層８を順次積層形
成する。最後に図１１（Ｄ）に示すように、めっき用レ
ジスト６及び導電膜４を除去した後、加熱することによ
って、鉛（Ｐｂ）層７および錫（Ｓｎ）層８を溶融合金
化させ、はんだ形状を球形にしてはんだバンプ９を形成
してフリップチップ１０は完成する。この後、プリント
基板（図示せず）のパッド２部にフラックスを塗布し、
フリップチップ１０のはんだバンプ９がこのパッド２上
に来るよう位置合わせし、加熱溶融して接合することに
よって、フリップチップ１０を直接プリント基板上にフ
リップチップ実装を行う。The conventional flip chip 10 is manufactured and mounted through the steps described below.
First, as shown in FIG. 11A, phosphosilicate glass (PSG) 3 is provided on the semiconductor chip 1 to protect the chip surface.
Is applied, the portion corresponding to the pad 2 is opened by photolithography, and then, as shown in FIG. 11B, a conductive film 4 for current supply during electroplating is formed on the entire surface. A photoresist (not shown) is applied and the photoresist corresponding to the pad 2 is removed by photolithography. After that, a barrier metal layer 5 is formed by vapor deposition or the like, and the resist is removed to remove the photoresist corresponding to the pad 2. Only, the barrier metal layer 5 is left, and then a resist 6 for plating is formed as shown in FIG.
The resist on the pad 2 portion is removed. Then, a lead (Pb) layer 7 and a tin (Sn) layer 8 are sequentially laminated by electroplating. Finally, as shown in FIG. 11D, after removing the plating resist 6 and the conductive film 4, by heating, the lead (Pb) layer 7 and the tin (Sn) layer 8 are melt-alloyed and the solder is applied. The flip chip 10 is completed by forming the solder bumps 9 into a spherical shape. After that, flux is applied to the pad 2 of the printed circuit board (not shown),
The flip chip 10 is flip chip mounted directly on the printed circuit board by aligning the solder bumps 9 of the flip chip 10 so as to be on the pad 2, heating and melting and joining.

【０００４】[0004]

【発明が解決しようとする課題】従来のフリップチップ
は以上のように構成され、又、製造されており、半導体
チップ１の表面には電子回路のパターンが形成されてい
て凹凸があるので、燐珪酸ガラス（ＰＳＧ）３で表面を
保護しているとは言っても、例えば３０００オングスト
ロームというように非常に薄いため十分ではなく、プリ
ント基板への実装時に半導体チップ１の表面に傷をつけ
る恐れがあり、不良を発生させて歩留まりの低下を招く
という問題点があった。The conventional flip chip is constructed and manufactured as described above, and since the surface of the semiconductor chip 1 is provided with an electronic circuit pattern and has irregularities, the phosphorus chip is Even though the surface is protected by silicate glass (PSG) 3, it is not enough because it is very thin, for example, 3000 angstrom, and there is a risk that the surface of the semiconductor chip 1 will be scratched when it is mounted on a printed circuit board. Therefore, there is a problem in that a defect is caused and a yield is reduced.

【０００５】又、実装時におけるフリップチップ１０の
良否を判定するためのバーンイン検査をどのように実施
するかという問題点も残されている。例えば、検査のた
めに別の基板に一度仮接合し、検査後に接合部のはんだ
を剥すという従来行われている方法では、バンプ９のは
んだ量が減少したり、又、バンプ９が取れたり形状が変
わることによって、再度はんだを供給しなければならな
い等といった問題点があった。Further, there remains a problem of how to carry out a burn-in test for judging the quality of the flip chip 10 at the time of mounting. For example, in a conventional method of temporarily joining another substrate for inspection and peeling the solder at the joint after the inspection, the amount of solder in the bump 9 is reduced, or the bump 9 is removed or the shape of the bump 9 is removed. However, there was a problem that the solder had to be supplied again due to the change.

【０００６】この発明は上記のような問題点を解消する
ためになされたもので、プリント基板への実装時に表面
を十分に保護して歩留まりの向上を図り、又、バンプの
状態を変化させることなくバーンイン検査を実施するこ
とが可能なフリップチップおよびその製造方法ならびに
実装方法、バーンイン検査基板を提供することを目的と
するものである。The present invention has been made in order to solve the above problems, and it is possible to sufficiently protect the surface during mounting on a printed circuit board to improve the yield and to change the state of bumps. It is an object of the present invention to provide a flip chip capable of performing a burn-in inspection without any need, a manufacturing method and a mounting method thereof, and a burn-in inspection board.

【０００７】[0007]

【課題を解決するための手段】この発明の請求項１に係
るフリップチップは、表面の所定の位置にパッドが形成
された半導体チップと、半導体チップの表面を覆うよう
に形成されパッドと対応する位置にパッドの上面まで達
する開口を有する緩衝層と、開口に充填され上面が緩衝
層より上方に突出して形成された導電性部材でなるバン
プとを備えたものである。A flip chip according to a first aspect of the present invention corresponds to a semiconductor chip having a pad formed at a predetermined position on the surface and a pad formed so as to cover the surface of the semiconductor chip. A buffer layer having an opening reaching the upper surface of the pad at a position, and a bump made of a conductive member formed in the opening and having an upper surface protruding above the buffer layer are provided.

【０００８】又、この発明の請求項２に係るフリップチ
ップは、請求項１において、緩衝層を絶縁樹脂で形成す
るようにしたものである。A flip chip according to a second aspect of the present invention is the flip chip according to the first aspect, wherein the buffer layer is formed of an insulating resin.

【０００９】又、この発明の請求項３に係るフリップチ
ップは、請求項２において、弾性を有する絶縁樹脂で形
成するようにしたものである。A flip chip according to a third aspect of the present invention is the flip chip according to the second aspect, which is formed of an insulating resin having elasticity.

【００１０】又、この発明の請求項４に係るフリップチ
ップは、請求項１において、バンプ上面の径を半導体チ
ップのパッドと接する下面の径より大に形成するように
したものである。A flip chip according to a fourth aspect of the present invention is the flip chip according to the first aspect, wherein the diameter of the upper surface of the bump is larger than the diameter of the lower surface in contact with the pad of the semiconductor chip.

【００１１】又、この発明の請求項５に係るフリップチ
ップは、請求項４において、バンプは下面から上面に向
けて径を階段状に順次拡大させるようにしたものであ
る。A flip chip according to a fifth aspect of the present invention is the flip chip according to the fourth aspect, wherein the diameter of the bump is gradually increased from the lower surface to the upper surface in a stepwise manner.

【００１２】又、この発明の請求項６に係るフリップチ
ップは、請求項１において、バンプを金属粒子が添加さ
れた樹脂で形成するようにしたものである。A flip chip according to a sixth aspect of the present invention is the flip chip according to the first aspect, wherein the bump is formed of a resin to which metal particles are added.

【００１３】又、この発明の請求項７に係るフリップチ
ップの製造方法は、半導体チップの表面に絶縁樹脂層を
形成する工程と、絶縁樹脂層の半導体チップのパッドと
対応する部分を除去して開口を形成する工程と、開口に
バンプ部材を充填して加熱溶融し上面を所定の形状に形
成する工程とを包含したものである。According to a seventh aspect of the present invention, in the method of manufacturing a flip chip, the step of forming an insulating resin layer on the surface of the semiconductor chip and the portion of the insulating resin layer corresponding to the pad of the semiconductor chip are removed. It includes a step of forming an opening and a step of filling the opening with a bump member and heating and melting it to form the upper surface into a predetermined shape.

【００１４】又、この発明の請求項８に係るフリップチ
ップの製造方法は、半導体チップの表面に絶縁樹脂層を
形成する工程と、絶縁樹脂層の半導体チップのパッドと
対応する部分を除去して開口を形成する工程と、開口の
内壁に金属膜を形成する工程と、開口にクリームはんだ
を充填し加熱溶融してバンプを形成する工程とを包含し
たものである。According to the eighth aspect of the present invention, in the method of manufacturing a flip chip, the step of forming an insulating resin layer on the surface of the semiconductor chip and the portion of the insulating resin layer corresponding to the pad of the semiconductor chip are removed. It includes a step of forming an opening, a step of forming a metal film on the inner wall of the opening, and a step of filling the opening with cream solder and heating and melting to form bumps.

【００１５】又、この発明の請求項９に係るフリップチ
ップの製造方法は、半導体チップの表面に絶縁樹脂層を
形成する工程と、絶縁樹脂層の半導体チップのパッドと
対応する部分を除去して開口を形成する工程と、開口の
内壁に金属膜を形成する工程と、開口に電気めっきによ
りはんだ部材を充填し加熱溶融してバンプを形成する工
程とを包含したものである。According to a ninth aspect of the present invention, in the method of manufacturing a flip chip, the step of forming an insulating resin layer on the surface of the semiconductor chip and the portion of the insulating resin layer corresponding to the pad of the semiconductor chip are removed. It includes a step of forming an opening, a step of forming a metal film on the inner wall of the opening, and a step of filling the opening with a solder member by electroplating and heating and melting to form a bump.

【００１６】又、この発明の請求項１０に係るバーンイ
ン検査基板は、可溶性部材でなる基材と、この基材の表
面に所定のパターンで形成された配線層とを備えたもの
である。A burn-in test board according to a tenth aspect of the present invention comprises a base material made of a fusible material and a wiring layer formed in a predetermined pattern on the surface of the base material.

【００１７】又、この発明の請求項１１に係るバーンイ
ン検査基板は、請求項１０において、可溶性のバインダ
に導電性部材の粒子を混合して配線層を形成するように
したものである。The burn-in test substrate according to an eleventh aspect of the present invention is the burn-in inspection substrate according to the tenth aspect, wherein a soluble binder is mixed with particles of a conductive member to form a wiring layer.

【００１８】又、この発明の請求項１２に係るバーンイ
ン検査基板は、請求項１０において、低融点金属膜で配
線層を形成するようにしたものである。A burn-in test board according to a twelfth aspect of the present invention is the burn-in test board according to the tenth aspect, wherein the wiring layer is formed of a low melting point metal film.

【００１９】又、この発明の請求項１３に係るフリップ
チップの実装方法は、可溶性部材でなる基材の表面に所
定のパターンの配線層を施してバーンイン検査基板を形
成する工程と、バーンイン検査基板の配線層にフリップ
チップのバンプ部を接合してバーンイン検査を行う工程
と、基材を溶剤にて溶解し除去する工程と、フリップチ
ップのバンプ部を加熱溶融してプリント基板のパッド部
に接合する工程とを包含したものである。In a flip-chip mounting method according to a thirteenth aspect of the present invention, a step of forming a burn-in test board by forming a wiring layer having a predetermined pattern on the surface of a base material made of a soluble member, and a burn-in test board. Of the bump part of the flip chip to the wiring layer for the burn-in test, the step of dissolving and removing the base material with a solvent, and the bump part of the flip chip being heated and melted to be bonded to the pad part of the printed circuit board. And the step of performing.

【００２０】又、この発明の請求項１４に係るフリップ
チップの実装方法は、可溶性部材でなる基材の表面に所
定のパターンの配線層を施してバーンイン検査基板を形
成する工程と、バーンイン検査基板の配線層にフリップ
チップのバンプ部を接合してバーンイン検査を行う工程
と、基材を溶剤にて溶解し除去する工程と、フリップチ
ップの表面にバンプ部を除いて封止剤を塗布する工程
と、フリップチップのバンプ部を加熱溶融してプリント
基板のパッド部に接合する工程とを包含したものであ
る。According to a fourteenth aspect of the present invention, in the flip-chip mounting method, a step of forming a burn-in test board by forming a wiring layer having a predetermined pattern on the surface of a base material made of a fusible material, and a burn-in test board. Step of joining the bump part of the flip chip to the wiring layer of the above, performing a burn-in test, dissolving the base material with a solvent and removing it, and applying a sealant on the surface of the flip chip excluding the bump part And a step of bonding the bump portion of the flip chip to the pad portion of the printed board by heating and melting the bump portion.

【００２１】又、この発明の請求項１５に係るフリップ
チップの実装方法は、可溶性部材でなる基材の表面に所
定パターンの配線層を施してなるバーンイン検査基板の
配線層上の所定の位置にバンプ部材を装着する工程と、
半導体チップの表面を覆う緩衝層の開口にバンプ部材の
位置を対応させるとともに開口にバンプ部材を嵌入し加
熱溶融して接合しバーンイン検査を行う工程と、基材を
溶剤にて溶解して除去しフリップチップを形成する工程
と、フリップチップのバンプ部を加熱溶融してプリント
基板のパッド部に接合する工程とを包含したものであ
る。According to a fifteenth aspect of the present invention, in a flip-chip mounting method, a wiring layer having a predetermined pattern is formed on a surface of a base material made of a fusible material at a predetermined position on a wiring layer of a burn-in test board. A step of mounting the bump member,
The step of matching the position of the bump member with the opening of the buffer layer covering the surface of the semiconductor chip, inserting the bump member into the opening, heating and melting and joining and performing burn-in inspection, and dissolving and removing the base material with a solvent It includes a step of forming a flip chip and a step of heating and melting the bump portion of the flip chip to bond it to the pad portion of the printed board.

【００２２】又、この発明の請求項１６に係るフリップ
チップの実装方法は、可溶性部材でなる基材の表面に所
定パターンの配線層を施してなるバーンイン検査基板の
表面に緩衝層を形成するとともに緩衝層の半導体チップ
のパッドと対応する位置に開口を形成する工程と、緩衝
層の開口にバンプ部材を充填する工程と、緩衝層の表面
に接着剤を塗布し半導体チップに接着する工程と、開口
に充填されたバンプ部材を加熱溶融して半導体チップの
パッド部に接合しバーンイン検査を行う工程と、基材を
溶剤にて溶解して除去しフリップチップを形成する工程
と、フリップチップのバンプ部を加熱溶融してプリント
基板のパッド部に接合する工程とを包含したものであ
る。In the flip-chip mounting method according to the sixteenth aspect of the present invention, the buffer layer is formed on the surface of the burn-in test board in which the wiring layer having a predetermined pattern is formed on the surface of the base material made of the soluble material. A step of forming an opening in the buffer layer at a position corresponding to the pad of the semiconductor chip, a step of filling the opening of the buffer layer with a bump member, a step of applying an adhesive to the surface of the buffer layer and adhering it to the semiconductor chip, A step of heating and melting the bump member filled in the opening to bond it to the pad portion of the semiconductor chip and performing a burn-in test; a step of dissolving and removing the base material with a solvent to form a flip chip; and a bump of the flip chip The step of heating and melting the parts to bond them to the pad parts of the printed circuit board is included.

【００２３】[0023]

【作用】この発明の請求項１におけるフリップチップの
緩衝層は、半導体チップの表面を保護し傷等による不良
の発生を防止する。The buffer layer of the flip chip according to the first aspect of the present invention protects the surface of the semiconductor chip and prevents defects due to scratches or the like.

【００２４】又、この発明の請求項２におけるフリップ
チップは、絶縁樹脂で形成された緩衝層によって半導体
チップの表面を保護し、傷等による不良の発生を防止す
る。Further, in the flip chip according to the second aspect of the present invention, the surface of the semiconductor chip is protected by the buffer layer formed of the insulating resin, and the occurrence of defects due to scratches or the like is prevented.

【００２５】又、この発明の請求項３におけるフリップ
チップは、弾性を有する絶縁樹脂で形成された緩衝層に
よって半導体チップの表面を保護し、傷等による不良の
発生を防止する。Further, in the flip chip according to the third aspect of the present invention, the surface of the semiconductor chip is protected by the buffer layer formed of the elastic insulating resin to prevent the occurrence of defects due to scratches or the like.

【００２６】又、この発明の請求項４におけるフリップ
チップは、バンプ上面の径を下面の径より大にすること
により、プリント基板のパッドとの接合を容易にする。Further, in the flip chip according to the fourth aspect of the present invention, the diameter of the upper surface of the bump is made larger than the diameter of the lower surface to facilitate bonding with the pad of the printed board.

【００２７】又、この発明の請求項５におけるフリップ
チップは、バンプの下面から上面に向けて径を階段状に
順次拡大させ、バンプ上面の径を大にすることによりプ
リント基板のパッドとの接合を容易にする。According to a fifth aspect of the present invention, in the flip chip, the diameter is increased stepwise from the lower surface to the upper surface of the bump, and the diameter of the upper surface of the bump is increased to bond it to the pad of the printed circuit board. To facilitate.

【００２８】又、この発明の請求項６におけるフリップ
チップは、バンプを金属粒子が添加された樹脂で形成す
ることにより、バンプの形成を容易にする。Further, in the flip chip according to the sixth aspect of the present invention, the bump is formed easily by forming the bump with a resin to which metal particles are added.

【００２９】又、この発明の請求項７におけるフリップ
チップの製造方法は、半導体チップの表面に絶縁樹脂層
を形成するとともに、この絶縁樹脂層の半導体チップの
パッドと対応する部分に形成された開口にバンプ部材を
充填してバンプを形成することにより、半導体チップの
配線に影響を与えることなくバンプを形成することを可
能にする。According to a seventh aspect of the present invention, in the method of manufacturing a flip chip, an insulating resin layer is formed on the surface of the semiconductor chip, and an opening formed in a portion of the insulating resin layer corresponding to the pad of the semiconductor chip. By forming the bump by filling the bump member with the bump member, it is possible to form the bump without affecting the wiring of the semiconductor chip.

【００３０】又、この発明の請求項８におけるフリップ
チップの製造方法は、半導体チップの表面に絶縁樹脂層
を形成するとともに、この絶縁樹脂層の半導体チップの
パッドと対応する部分に形成された開口の内壁に金属膜
を形成した後、クリームはんだを充填してバンプを形成
することにより、半導体チップの配線に影響を与えるこ
となくバンプを形成することを可能にする。Further, in the flip chip manufacturing method according to the eighth aspect of the present invention, the insulating resin layer is formed on the surface of the semiconductor chip, and the opening formed in the portion of the insulating resin layer corresponding to the pad of the semiconductor chip. By forming a metal film on the inner wall of the substrate and then filling it with cream solder to form bumps, it is possible to form bumps without affecting the wiring of the semiconductor chip.

【００３１】又、この発明の請求項９におけるフリップ
チップの製造方法は、半導体チップの表面に絶縁樹脂層
を形成するとともに、この絶縁樹脂層の半導体チップの
パッドと対応する部分に形成された開口の内壁に金属膜
を形成した後、電気めっきによりはんだ部材を充填して
バンプを形成することにより、半導体チップの配線に影
響を与えることなくバンプを形成することを可能にす
る。According to a ninth aspect of the present invention, in the method of manufacturing a flip chip, an insulating resin layer is formed on the surface of the semiconductor chip, and an opening formed in a portion of the insulating resin layer corresponding to the pad of the semiconductor chip. After the metal film is formed on the inner wall of the substrate, the solder member is filled by electroplating to form the bumps, which makes it possible to form the bumps without affecting the wiring of the semiconductor chip.

【００３２】又、この発明の請求項１０におけるバーン
イン検査基板の基材は、溶剤により溶解除去される。The base material of the burn-in test substrate according to the tenth aspect of the present invention is dissolved and removed by a solvent.

【００３３】又、この発明の請求項１１におけるバーン
イン検査基板の配線層は、基材と共に溶剤により溶解除
去される。The wiring layer of the burn-in test substrate according to the eleventh aspect of the present invention is dissolved and removed by the solvent together with the base material.

【００３４】又、この発明の請求項１２におけるバーン
イン検査基板の配線層は、バンプに影響を与えない程度
の加熱で溶解除去される。In the twelfth aspect of the present invention, the wiring layer of the burn-in test substrate is dissolved and removed by heating to the extent that it does not affect the bumps.

【００３５】又、この発明の請求項１３におけるフリッ
プチップの実装方法は、フリップチップのバンプ部をバ
ーンイン検査基板配線層に接合してバーンイン検査を行
った後、バーンイン検査基板の基材を溶剤により溶解除
去することにより、フリップチップのバンプ部に影響を
与えることなくバーンイン検査の実施を可能にする。Further, in the flip-chip mounting method according to the thirteenth aspect of the present invention, the bump portion of the flip-chip is bonded to the burn-in inspection substrate wiring layer to perform the burn-in inspection, and then the base material of the burn-in inspection substrate is removed by a solvent. By melting and removing, the burn-in inspection can be performed without affecting the bump portion of the flip chip.

【００３６】又、この発明の請求項１４におけるフリッ
プチップの実装方法は、フリップチップのバンプ部をバ
ーンイン検査基板配線層に接合してバーンイン検査を行
った後、バーンイン検査基板の基材を溶剤により溶解除
去し、フリップチップの表面にバンプ部を除いて封止剤
を塗布して、バンプ部をプリント基板のパッド部に接合
することにより、フリップチップのバンプ部に影響を与
えることなくバーンイン検査の実施を可能にするととも
に、半導体チップ表面の配線の腐食を防止する。According to a fourteenth aspect of the present invention, in the flip-chip mounting method, the bump portion of the flip-chip is bonded to the burn-in inspection board wiring layer to carry out a burn-in inspection, and then the base material of the burn-in inspection board is made of a solvent. It is melted and removed, the sealant is applied to the surface of the flip chip excluding the bump part, and the bump part is bonded to the pad part of the printed circuit board so that the burn-in inspection can be performed without affecting the bump part of the flip chip. In addition to enabling implementation, it also prevents corrosion of the wiring on the surface of the semiconductor chip.

【００３７】又、この発明の請求項１５におけるフリッ
プチップの実装方法は、バーンイン検査基板の配線層上
の所定の位置にバンプ部材を装着し、このバンプ部材の
位置を半導体チップの表面を覆う緩衝層の開口に対応さ
せるとともに、開口にバンプ部材を嵌入し加熱溶融させ
て接合しバーンイン検査を行うことにより、フリップチ
ップのバンプを形成する工程と、半導体チップとバーン
イン検査基板とを接合する工程とを同時に行うことがで
き、工程の省力化を可能にする。In the flip-chip mounting method according to the fifteenth aspect of the present invention, a bump member is mounted at a predetermined position on the wiring layer of the burn-in test board, and the bump member is covered with a buffer for covering the surface of the semiconductor chip. A step of forming bumps of a flip chip by fitting a bump member into the opening, heating and melting and joining the layers to perform a burn-in test, and a step of joining the semiconductor chip and the burn-in test substrate. Can be performed at the same time, which enables labor saving in the process.

【００３８】又、この発明の請求項１６におけるフリッ
プチップの実装方法は、バーンイン検査基板の表面に緩
衝層を形成するとともに、この緩衝層の半導体チップの
パッド部と対応する位置に開口を形成してバンプ部材を
充填した後、緩衝層の表面に接着剤を塗布して半導体チ
ップに接着し、半導体チップのパッド部に開口内のバン
プ部材を加熱溶融して接合しバーンイン検査を行うこと
により、フリップチップのバンプを形成する工程と、半
導体チップとバーンイン検査基板とを接合する工程とを
同時に行うことができ、工程の省力化を可能にする。According to a sixteenth aspect of the present invention, in the flip-chip mounting method, a buffer layer is formed on the surface of the burn-in test substrate, and an opening is formed in the buffer layer at a position corresponding to the pad portion of the semiconductor chip. After filling the bump member with adhesive, apply an adhesive to the surface of the buffer layer to adhere to the semiconductor chip, and heat-melt and bond the bump member in the opening to the pad portion of the semiconductor chip to perform a burn-in test. The step of forming the bumps of the flip chip and the step of joining the semiconductor chip and the burn-in inspection substrate can be performed at the same time, which enables labor saving in the steps.

【００３９】[0039]

【実施例】【Example】

実施例１．以下、この発明の実施例を図について説明す
る。図１はこの発明の実施例１におけるフリップチップ
の製造方法を示す断面図、図２は図１におけるフリップ
チップのプリント基板への実装方法を示す断面図であ
る。図において、半導体チップ１およびパッド２は図１
１に示す従来のものと同様である。１１は緩衝層として
の例えばエポキシ樹脂でなる絶縁樹脂層で、各パッド２
と対応する位置に開口１１ａが形成されている。１２は
この開口１１ａに充填されたクリームはんだ、１３はこ
のクリームはんだ１２の上面を球面に加工して得られた
はんだバンプで、これら１、２、１１〜１３でフリップ
チップ１４が構成される。１５は可溶性部材でなる基
材、１６はこの基材１５の表面に所定のパターンで形成
された配線層で、これら１５、１６でバーンイン検査基
板１７が構成される。１８は配線層１６の端部に接続さ
れたリード線、１９はフリップチップ１４が実装される
プリント基板、２０はこのプリント基板１９のパッド部
である。Example 1. Embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view showing a method of manufacturing a flip chip according to a first embodiment of the present invention, and FIG. 2 is a sectional view showing a method of mounting the flip chip on a printed circuit board shown in FIG. In the figure, the semiconductor chip 1 and the pad 2 are shown in FIG.
This is the same as the conventional one shown in FIG. Reference numeral 11 denotes an insulating resin layer made of, for example, epoxy resin as a buffer layer, and each pad 2
The opening 11a is formed at a position corresponding to. Reference numeral 12 is a cream solder filled in the opening 11a, 13 is a solder bump obtained by processing the upper surface of the cream solder 12 into a spherical surface, and the flip chip 14 is constituted by these 1, 2, 11 to 13. Reference numeral 15 is a base material made of a fusible material, 16 is a wiring layer formed on the surface of the base material 15 in a predetermined pattern, and these 15 and 16 constitute a burn-in inspection board 17. Reference numeral 18 is a lead wire connected to an end of the wiring layer 16, 19 is a printed circuit board on which the flip chip 14 is mounted, and 20 is a pad portion of the printed circuit board 19.

【００４０】次に、上記のように構成されるフリップチ
ップ１４の製造方法を図１に基づいて説明する。まず、
図１（Ａ）に示すように半導体チップ１の表面に、感光
性を有する液状のエポキシ樹脂を塗布し、半硬化させて
例えば１００μｍ程度の厚みの絶縁樹脂層１１を形成し
た後、写真製版法で露光、現像処理を行って絶縁樹脂層
１１の各パッド２と対応する位置にそれぞれ開口１１ａ
を形成し、加熱処理により絶縁樹脂層１１を完全に硬化
させる。次いで、図１（Ｂ）に示すようにスクリーン印
刷によりクリームはんだ１２を開口１１ａに充填し、図
１（Ｃ）に示すようにクリームはんだ１２を加熱溶融し
て上面を球形に加工してはんだバンプ１３を形成しフリ
ップチップ１４は完成する。Next, a method of manufacturing the flip chip 14 configured as described above will be described with reference to FIG. First,
As shown in FIG. 1 (A), a liquid epoxy resin having photosensitivity is applied to the surface of the semiconductor chip 1 and semi-cured to form an insulating resin layer 11 having a thickness of, for example, about 100 μm. Are exposed and developed to form openings 11a at positions corresponding to the respective pads 2 of the insulating resin layer 11.
And the insulating resin layer 11 is completely cured by heat treatment. Next, as shown in FIG. 1 (B), the cream solder 12 is filled in the opening 11a by screen printing, and the cream solder 12 is heated and melted as shown in FIG. 13 is formed, and the flip chip 14 is completed.

【００４１】さらに、上記のようにして製造されたフリ
ップチップ１４をプリント基板へ実装する方法について
図２に基づき説明する。まず、図２（Ａ）に示すように
可溶性部材でなる基材１５上に、所定のパターンで配線
層１６を形成してバーンイン検査基板１７を完成させ
る。次いで、図２（Ｂ）に示すようにフリップチップ１
４のはんだバンプ１３を、バーンイン検査基板１７の配
線層１６上の所定の位置に接合した後、配線層１６の端
部にリード線１８を接続してバーンイン検査を実施す
る。そして、検査の結果、良品であることが確認される
と、図２（Ｃ）に示すように溶剤を用いて基材１７を溶
解して配線層１６と共に除去する。最後に、フリップチ
ップ１４のはんだバンプ１３を所望のプリント基板１９
のパッド部２０に合わせ、加熱溶融して接合することに
より実装は完了する。Further, a method of mounting the flip chip 14 manufactured as described above on a printed board will be described with reference to FIG. First, as shown in FIG. 2A, a wiring layer 16 is formed in a predetermined pattern on a base material 15 made of a fusible material to complete a burn-in test board 17. Next, as shown in FIG. 2B, the flip chip 1
After the solder bump 13 of No. 4 is bonded to a predetermined position on the wiring layer 16 of the burn-in inspection substrate 17, the lead wire 18 is connected to the end of the wiring layer 16 to perform the burn-in inspection. Then, when it is confirmed that the product is a non-defective product as a result of the inspection, the base material 17 is dissolved by using a solvent and is removed together with the wiring layer 16 as shown in FIG. Finally, the solder bumps 13 of the flip chip 14 are connected to the desired printed circuit board 19
The mounting is completed by aligning with the pad portion 20 and heating, melting, and joining.

【００４２】このように上記実施例１によれば、半導体
チップ１の表面を比較的厚い絶縁樹脂層１１で覆って、
この絶縁樹脂層１１に形成された開口１１ａ内にはんだ
バンプ１３を形成しているので、フリップチップ１４の
表面の機械的強度が増大し、プリント基板１９への実装
時に半導体チップ１の表面に傷を付けることもなくなる
ため、不良の発生が防止されて歩留まりが向上する。As described above, according to the first embodiment, the surface of the semiconductor chip 1 is covered with the relatively thick insulating resin layer 11,
Since the solder bumps 13 are formed in the openings 11a formed in the insulating resin layer 11, the mechanical strength of the surface of the flip chip 14 increases, and the surface of the semiconductor chip 1 is scratched when mounted on the printed board 19. Since it does not need to be attached, the occurrence of defects is prevented and the yield is improved.

【００４３】又、クリームはんだ１２に含まれるフラッ
クス等の活性剤が半導体チップ１の表面に流れたり、周
囲の雰囲気に触れて配線を腐食させることもなくなる。
さらに又、バーンイン検査基板１７の基材１５に可溶性
部材を用いて、バーンイン検査後に溶解して除去するよ
うにしているので、検査後にはんだバンプ１３が取れた
り形状が変わったりすることもなく、正常な状態でプリ
ント基板１９への実装が可能になる等、作業性、信頼性
が向上する。Further, the activator such as the flux contained in the cream solder 12 does not flow to the surface of the semiconductor chip 1 and does not corrode the wiring due to the contact with the surrounding atmosphere.
Furthermore, since a fusible member is used as the base material 15 of the burn-in inspection board 17 so as to be melted and removed after the burn-in inspection, the solder bumps 13 are not removed or their shape is changed after the inspection, and the The workability and the reliability are improved because it can be mounted on the printed circuit board 19 in such a state.

【００４４】実施例２．尚、上記実施例１では、絶縁樹
脂層１１をエポキシ樹脂で形成した場合について説明し
たが、例えば、ウレタン樹脂、シリコン樹脂等のように
弾性を有する絶縁樹脂を適用するようにすれば、フリッ
プチップ１４の表面の機械的強度が増大するのは勿論の
こと、周囲雰囲気の温度変動による、半導体チップ１と
プリント基板１９との間の膨張係数差によって発生する
応力を緩和することができ、より信頼性の向上を図るこ
とが可能になる。Example 2. In the first embodiment described above, the case where the insulating resin layer 11 is formed of the epoxy resin has been described. However, if an insulating resin having elasticity such as urethane resin and silicon resin is applied, the flip chip is applied. In addition to increasing the mechanical strength of the surface of 14, the stress generated by the difference in expansion coefficient between the semiconductor chip 1 and the printed circuit board 19 due to the temperature fluctuation of the ambient atmosphere can be relieved, and the reliability is improved. It is possible to improve the property.

【００４５】実施例３．又、上記実施例１では、バーン
イン検査基板１７の基材１５に適用される可溶性部材お
よび溶剤については何ら説明しなかったが、可溶性部材
として、例えばセルロースアセテート系フィルムを適用
した場合にはケトン類、エステル類の溶剤で、又、ポリ
塩化ビニル樹脂を適用した場合にはケトン類の溶剤で、
さらに又、ポリビニルアルコール系フィルムを適用した
場合には水によってそれぞれ溶解することができる。Example 3. Further, in the above-mentioned Example 1, the soluble member and the solvent applied to the base material 15 of the burn-in inspection substrate 17 were not described at all, but when the soluble member is, for example, a cellulose acetate film, ketones are used. , A solvent of esters, or a solvent of ketones when a polyvinyl chloride resin is applied,
Furthermore, when a polyvinyl alcohol film is applied, it can be dissolved in water.

【００４６】実施例４．図３はこの発明の実施例４にお
けるフリップチップの実装方法の工程の一部を示す断面
図である。尚、本実施例は、バーンイン検査を実施して
バーンイン検査基板１７を溶解除去するまでの工程は、
図２（Ａ）〜（Ｃ）で示す実施例１における工程と同様
なので説明を省略する。まず、バーンイン検査が終了し
てバーンイン検査基板１７が除去されると、図３（Ａ）
に示すように絶縁樹脂層１１の表面に、はんだバンプ１
３を除いて封止剤２１を塗布する。次いで、図３（Ｂ）
に示すようにフリップチップ１４のはんだバンプ１３を
プリント基板１９のパッド部に合わせ、加熱溶融して接
合することにより実装は完了する。Example 4. FIG. 3 is a cross-sectional view showing a part of the process of the flip-chip mounting method according to the fourth embodiment of the present invention. In this embodiment, the steps from performing the burn-in inspection to melting and removing the burn-in inspection substrate 17 are
The description is omitted because it is the same as the process in the first embodiment shown in FIGS. First, when the burn-in inspection substrate is removed after the burn-in inspection is completed, FIG.
As shown in, solder bumps 1 are formed on the surface of the insulating resin layer 11.
The sealant 21 is applied except for 3. Then, FIG. 3 (B)
The mounting is completed by aligning the solder bumps 13 of the flip chip 14 with the pads of the printed board 19 as shown in FIG.

【００４７】このように上記実施例４によれば、フリッ
プチップ１４がプリント基板１９に実装された状態で
は、フリップチップ１４の絶縁樹脂層１１とプリント基
板１９のパッド部２０との間に封止剤２１の層が介在
し、且つこの封止剤２１の層は、はんだバンプ１３の周
囲を取り囲むように配置されているので、はんだバンプ
１３とパッド部２０との接合部が周囲の雰囲気に触れ
て、腐食の原因になることもなく信頼性の向上を図るこ
とが可能になる。As described above, according to the fourth embodiment, in the state where the flip chip 14 is mounted on the printed circuit board 19, sealing is performed between the insulating resin layer 11 of the flip chip 14 and the pad portion 20 of the printed circuit board 19. Since the layer of the sealing agent 21 is interposed and the layer of the sealing agent 21 is arranged so as to surround the periphery of the solder bump 13, the joint portion between the solder bump 13 and the pad portion 20 is exposed to the ambient atmosphere. Thus, it becomes possible to improve reliability without causing corrosion.

【００４８】実施例５．図４はこの発明の実施例５にお
けるフリップチップの製造方法を示す断面図である。以
下、図４に基づいて実施例５におけるフリップチップの
製造方法を説明する。まず、図４（Ａ）に示すように半
導体チップ１の表面に、実施例１の場合と同様に感光性
を有するエポキシ樹脂を塗布し、半硬化させて例えば１
００μｍ程度の厚みの絶縁樹脂層２２を形成した後、写
真製版法で露光、現像処理を行って絶縁樹脂層２２の各
パッド２と対応する位置に下方から上方に向けて内径が
階段状に順次拡大された開口２２ａをそれぞれ形成し、
加熱処理により絶縁樹脂層２２を完全に硬化させる。次
いで、図４（Ｂ）に示すように各開口２２ａ内に金属膜
２３を形成するとともに、図４（Ｃ）に示すようにクリ
ームはんだ２４を各開口２２ａ内の金属膜２３の上部に
充填し、図４（Ｄ）に示すようにクリームはんだ２４を
加熱溶融して球状のはんだバンプ２５を形成しフリップ
チップ２６は完成する。Example 5. FIG. 4 is a sectional view showing a method of manufacturing a flip chip according to a fifth embodiment of the present invention. Hereinafter, a method of manufacturing a flip chip according to the fifth embodiment will be described with reference to FIG. First, as shown in FIG. 4A, an epoxy resin having photosensitivity is applied to the surface of the semiconductor chip 1 as in the case of the first embodiment and semi-cured to form, for example, 1
After the insulating resin layer 22 having a thickness of about 00 μm is formed, the insulating resin layer 22 is exposed and developed by a photoengraving method, and the inner diameter is sequentially stepped from the bottom to the top at a position corresponding to each pad 2 of the insulating resin layer 22. Forming each of the enlarged openings 22a,
The insulating resin layer 22 is completely cured by the heat treatment. Next, the metal film 23 is formed in each opening 22a as shown in FIG. 4B, and the cream solder 24 is filled in the upper portion of the metal film 23 in each opening 22a as shown in FIG. 4C. As shown in FIG. 4D, the cream solder 24 is heated and melted to form spherical solder bumps 25, and the flip chip 26 is completed.

【００４９】このように上記実施例５によれば、はんだ
バンプ２５の上面の径を半導体チップ１のパッド２と接
する下面の径より大に形成しているので、プリント基板
に実装する際の接合面積を大きくすることが可能となり
信頼性が向上する。又、開口２２ａを階段状にして順次
拡大させているので、はんだバンプ２５と絶縁樹脂層２
２との接合面積も大きくとることができるため、バーン
イン検査時等にはんだバンプ２５が取れたりする恐れも
なくなり、さらに信頼性は向上する。As described above, according to the fifth embodiment, the diameter of the upper surface of the solder bump 25 is formed larger than the diameter of the lower surface of the semiconductor chip 1 which is in contact with the pad 2. The area can be increased and the reliability is improved. Further, since the opening 22a is formed in a stepwise shape and is enlarged in sequence, the solder bump 25 and the insulating resin layer 2
Since it is possible to make a large bonding area with 2, the risk of the solder bumps 25 coming off during burn-in inspection is eliminated, and reliability is further improved.

【００５０】実施例６．図５はこの発明の実施例６にお
けるフリップチップの製造方法を示す断面図である。以
下、図５に基づいて実施例６におけるフリップチップの
製造方法を説明する。まず、上記各実施例と同様、図５
（Ａ）に示すように半導体チップ１の表面に、エポキシ
樹脂を塗布して絶縁樹脂層１１を形成し、この絶縁樹脂
層１１の各パッド２と対応する位置に開口１１ａをそれ
ぞれ形成する。次いで、図５（Ｂ）に示すように絶縁樹
脂層１１の表面に電気めっき時の電流供給用の導電膜２
７を形成する。そして、図５（Ｃ）に示すように導電膜
２７の上からはんだ部材２９を、フォトレジスト２８を
マスクにして電気めっきにより充填する。最後に、図５
（Ｄ）に示すようにフォトレジスト２８を除去し、はん
だ部材２９を加熱溶融して球状のはんだバンプ３０を形
成しフリップチップ３１は完成する。Example 6. FIG. 5 is a sectional view showing a method of manufacturing a flip chip according to a sixth embodiment of the present invention. Hereinafter, a method of manufacturing a flip chip according to the sixth embodiment will be described with reference to FIG. First, as in each of the above embodiments, FIG.
As shown in (A), epoxy resin is applied to the surface of the semiconductor chip 1 to form an insulating resin layer 11, and openings 11a are formed in the insulating resin layer 11 at positions corresponding to the respective pads 2. Next, as shown in FIG. 5B, a conductive film 2 for supplying a current to the surface of the insulating resin layer 11 during electroplating.
Form 7. Then, as shown in FIG. 5C, a solder member 29 is filled from above the conductive film 27 by electroplating using the photoresist 28 as a mask. Finally, FIG.
As shown in (D), the photoresist 28 is removed, the solder member 29 is heated and melted to form spherical solder bumps 30, and the flip chip 31 is completed.

【００５１】このように上記実施例６によれば、はんだ
部材２９の開口１１ａへの充填を電気めっきによって行
っているので、上記各実施例と同様の効果を発揮し得る
ことは勿論のこと、はんだバンプ３０の絶縁樹脂層１１
との接合性が良くなり、信頼性はさらに向上する。As described above, according to the sixth embodiment, since the opening 11a of the solder member 29 is filled by the electroplating, it goes without saying that the same effects as those of the respective embodiments can be exhibited. Insulating resin layer 11 of solder bump 30
The bondability with and is improved, and the reliability is further improved.

【００５２】実施例７．図６はこの発明の実施例７にお
けるフリップチップの製造方法を示す断面図である。以
下、図６に基づいて実施例７におけるフリップチップの
製造方法を説明する。まず、上記各実施例と同様、図６
（Ａ）に示すように半導体チップ１の表面に、エポキシ
樹脂を塗布して絶縁樹脂層１１を形成し、この絶縁樹脂
層１１の各パッド２と対応する位置に開口１１ａをそれ
ぞれ形成する。次いで、図６（Ｂ）に示すように開口１
１ａに液状の導電性樹脂３２、例えば熱硬化性フェノー
ル樹脂をバインダとして銀粒子を添加したＬＳ−５０４
Ｊ、エポキシ樹脂をバインダとして銅粒子を添加したＡ
ＣＰ−１０５（株式会社アサヒ化学研究所製）を充填し
た後、図６（Ｃ）に示すように熱硬化させてバンプ３３
を形成しフリップチップ３４は完成する。Example 7. 6 is a sectional view showing a method of manufacturing a flip chip according to a seventh embodiment of the present invention. Hereinafter, a method of manufacturing a flip chip according to the seventh embodiment will be described with reference to FIG. First, as in each of the above embodiments, FIG.
As shown in (A), epoxy resin is applied to the surface of the semiconductor chip 1 to form an insulating resin layer 11, and openings 11a are formed in the insulating resin layer 11 at positions corresponding to the respective pads 2. Then, as shown in FIG.
LS-504 in which silver particles are added to 1a using a liquid conductive resin 32, for example, a thermosetting phenol resin as a binder.
J, A in which copper particles were added using epoxy resin as a binder
After being filled with CP-105 (manufactured by Asahi Chemical Laboratory Co., Ltd.), it is thermally cured as shown in FIG.
And the flip chip 34 is completed.

【００５３】このように上記実施例７によれば、開口１
１ａに液状の導電性樹脂３２を充填し、熱硬化すること
によってバンプ３３を形成するようにしているので、は
んだ部材を用いる場合と比較して加熱温度を低く抑える
ことができるため、他の配線等に悪影響を与えることも
少なくなり、信頼性の向上を図ることができる。As described above, according to the seventh embodiment, the opening 1
Since the bumps 33 are formed by filling the liquid conductive resin 32 in 1a and thermally curing it, the heating temperature can be suppressed to a low level as compared with the case where a solder member is used. It is less likely to adversely affect the above, and reliability can be improved.

【００５４】実施例８．図７はこの発明の実施例８にお
けるフリップチップの実装方法の工程の一部を示す断面
図である。本実施例では、まず、実施例１において図１
（Ａ）で示すように絶縁樹脂層１１に各開口１１ａが形
成された段階のものを用意する。次いで、図２（Ａ）で
示すバーンイン検査基板１７を用意するとともに、図７
（Ａ）に示すようにバーンイン検査基板１７の配線層１
６上の各開口１１ａと対応する位置に、バンプ部材３５
をそれぞれ装着する。Example 8. FIG. 7 is a sectional view showing a part of the process of the flip-chip mounting method according to the eighth embodiment of the present invention. In this embodiment, first, in FIG.
As shown in (A), an insulating resin layer 11 having openings 11a formed therein is prepared. Next, the burn-in inspection board 17 shown in FIG.
As shown in (A), the wiring layer 1 of the burn-in inspection board 17
Bump member 35 at a position corresponding to each opening 11a on
Put on each.

【００５５】そして、各開口１１ａと各バンプ部材３５
との位置合わせを行った後、図７（Ｂ）に示すように各
バンプ部材３５を各開口１１ａ内に嵌入し、加熱溶融し
て接合することによってバンプ３６を形成するととも
に、配線層１６の端部にリード線１８を接続してバーン
イン検査を実施する。その後、図７（Ｃ）に示すように
溶剤を用いて基材１５を溶解し、配線層１６と共に除去
することによりフリップチップ３７が完成する。以下、
図示はしないがこのフリップチップ３７のバンプ３６を
プリント基板のパッド部に合わせ、加熱溶融して接合す
ることにより実装は完了する。Then, each opening 11a and each bump member 35.
7B, each bump member 35 is fitted into each opening 11a, heated and melted to be bonded to form the bump 36, and the wiring layer 16 is formed. The lead wire 18 is connected to the end portion and a burn-in test is performed. After that, as shown in FIG. 7C, the base material 15 is dissolved with a solvent and removed together with the wiring layer 16 to complete the flip chip 37. Less than,
Although not shown, mounting is completed by aligning the bumps 36 of the flip chip 37 with the pads of the printed circuit board, heating and melting, and joining.

【００５６】このように上記実施例８によれば、バーン
イン検査基板１７にフリップチップ３７を接続する作業
と同時に、フリップチップ３７にバンプ部材３５を形成
するようにしているので、作業時間の短縮が可能とな
り、生産性の向上を図ることができる。As described above, according to the eighth embodiment, since the bump member 35 is formed on the flip chip 37 at the same time as the work for connecting the flip chip 37 to the burn-in test substrate 17, the working time can be shortened. It becomes possible and productivity can be improved.

【００５７】実施例９．図８はこの発明の実施例９にお
けるフリップチップの実装方法の工程の一部を示す断面
図である。本実施例では、まず、図８（Ａ）に示すよう
にバーンイン検査基板１７の表面に、エポキシ樹脂を塗
布して絶縁樹脂層３８を形成し、この絶縁樹脂層３８の
半導体チップ１表面上の各パッド２と対応する位置に開
口３８ａをそれぞれ形成するとともに、各開口３８ａに
バンプ部材３９を充填し、絶縁樹脂層３８の表面に接着
剤４０を塗布する。Example 9. FIG. 8 is a cross-sectional view showing a part of the process of the flip-chip mounting method according to the ninth embodiment of the present invention. In this embodiment, first, as shown in FIG. 8A, an epoxy resin is applied to the surface of the burn-in test substrate 17 to form an insulating resin layer 38, and the insulating resin layer 38 is formed on the surface of the semiconductor chip 1. The openings 38a are formed at the positions corresponding to the pads 2, respectively, the bump members 39 are filled in the openings 38a, and the adhesive 40 is applied to the surface of the insulating resin layer 38.

【００５８】次いで、図８（Ｂ）に示すように半導体チ
ップ１の各パッド２と、絶縁樹脂層３８内の各バンプ部
材３９との位置合わせを行った後、接着剤４０で固定し
加熱溶融して各パッド２と各バンプ部材３９とを接合す
る。そして、配線層１６の端部にリード線１８を接続し
てバーンイン検査を実施する。その後、図８（Ｃ）に示
すように溶剤を用いて基材１５を溶解し、配線層１６と
共に除去することにより半導体チップ１の表面には絶縁
樹脂層３８と共にバンプ４１が形成されフリップチップ
４２が完成する。以下、図示はしないがこのフリップチ
ップ４２のバンプ４１をプリント基板のパッド部に合わ
せ、加熱溶融して接合することにより実装は完了する。Next, as shown in FIG. 8B, after aligning the respective pads 2 of the semiconductor chip 1 with the respective bump members 39 in the insulating resin layer 38, they are fixed with an adhesive 40 and heated and melted. Then, each pad 2 and each bump member 39 are joined. Then, the lead wire 18 is connected to the end portion of the wiring layer 16 and the burn-in inspection is performed. Thereafter, as shown in FIG. 8C, the base material 15 is dissolved by using a solvent and is removed together with the wiring layer 16, whereby bumps 41 are formed on the surface of the semiconductor chip 1 together with the insulating resin layer 38 and the flip chip 42. Is completed. Although not shown, the bump 41 of the flip chip 42 is aligned with the pad portion of the printed board, heated, melted, and joined to complete the mounting.

【００５９】このように上記実施例９によれば、まず、
バーンイン検査基板上に絶縁樹脂層３８を形成し、この
絶縁樹脂層３８に開口３８ａを形成するようにしている
ので、半導体チップ１上で絶縁樹脂層３８に開口３８ａ
を形成する場合と比較し、開口３８ａを形成する際に半
導体チップ１の表面に傷を付けて、半導体チップ１が損
傷するようなこともなくなり、歩留まりの向上を図るこ
とが可能になる。As described above, according to the ninth embodiment, first,
Since the insulating resin layer 38 is formed on the burn-in test substrate and the opening 38a is formed in the insulating resin layer 38, the opening 38a is formed in the insulating resin layer 38 on the semiconductor chip 1.
As compared with the case where the openings 38a are formed, the surface of the semiconductor chip 1 is not scratched when the openings 38a are formed, and the semiconductor chips 1 are not damaged, so that the yield can be improved.

【００６０】実施例１０．図９はこの発明の実施例１０
におけるバーンイン検査基板の概略構成を示す断面図で
ある。本実施例におけるバーンイン検査基板４５は、可
溶性部材でなる基材４３の表面に、可溶性部材でなるバ
インダ４４ａに導電性粒子４４ｂを混合したペスト状の
ものを、印刷等の方法で形成することにより配線層４４
を構成するようにしたものである。Example 10. FIG. 9 shows a tenth embodiment of the present invention.
3 is a cross-sectional view showing a schematic configuration of a burn-in inspection board in FIG. The burn-in test substrate 45 in this embodiment is formed by forming a pestle-like mixture of conductive particles 44b in a binder 44a made of a soluble material on the surface of a base material 43 made of a soluble material by a method such as printing. Wiring layer 44
Is configured.

【００６１】このように上記実施例１０によれば、配線
層４４を可溶性部材でなるバインダ４４ａに導電性粒子
４４ｂを混合したペースト状のもので形成するようにし
ているので、バーンイン検査後、基材４３を溶解して除
去する段階で配線層４４も一緒に溶解除去されるので、
配線層４４を取りはずしたりする作業が省けるため、生
産性の向上を図ることが可能になる。As described above, according to the tenth embodiment, the wiring layer 44 is formed of a paste in which the binder 44a made of a soluble material is mixed with the conductive particles 44b. Since the wiring layer 44 is also dissolved and removed at the stage of melting and removing the material 43,
Since the work of removing the wiring layer 44 can be omitted, the productivity can be improved.

【００６２】実施例１１．図１０はこの発明の実施例１
１におけるバーンイン検査基板の概略構成を示す断面図
である。本実施例におけるバーンイン検査基板４８は、
可溶性部材でなる基材４６の表面に低融点金属膜を形成
することにより、配線層４７を構成するようにしたもの
である。Example 11. FIG. 10 is a first embodiment of the present invention.
2 is a cross-sectional view showing a schematic configuration of a burn-in inspection board in FIG. The burn-in inspection board 48 in this embodiment is
The wiring layer 47 is configured by forming a low melting point metal film on the surface of the base material 46 which is a soluble member.

【００６３】このように上記実施例１１によれば、配線
層４７を低融点金属膜で形成するようにしているので、
バーンイン検査後、バンプが溶解しない程度の温度で溶
解して除去することができるため、配線層４７の取りは
ずしの際にバンプがはずれたりすることもなくなり、歩
留まりの向上を図ることが可能になる。As described above, according to the eleventh embodiment, since the wiring layer 47 is formed of the low melting point metal film,
After the burn-in test, the bumps can be melted and removed at a temperature at which the bumps are not melted. Therefore, the bumps are not detached when the wiring layer 47 is removed, and the yield can be improved.

【００６４】実施例１２．尚、上記各実施例では、感光
性を有する液状のエポキシ樹脂を用いた場合について説
明したが、非感光性のエポキシ樹脂を用いて、その上に
フォトレジストを形成しこれをマスクとして、エッチン
グにより開口を形成するようにしても良く、又、液状の
エポキシ樹脂に代えてフィルム状のエポキシ樹脂を使用
しても同様の効果が期待できることは言うまでもない。Example 12 In each of the above-mentioned examples, the case where the liquid epoxy resin having photosensitivity is used is explained. However, by using the non-photosensitive epoxy resin, a photoresist is formed thereon, and this is used as a mask to perform etching. It goes without saying that the opening may be formed, and the same effect can be expected by using a film-shaped epoxy resin instead of the liquid epoxy resin.

【００６５】実施例１３．又、絶縁樹脂層を形成する材
料としては、エポキシ樹脂に限定されるものではなく、
例えばポリイミド樹脂等の他の樹脂を用いても良く、上
記各実施例と同様の効果が期待できる。Example 13 The material for forming the insulating resin layer is not limited to epoxy resin,
For example, another resin such as a polyimide resin may be used, and the same effect as that of each of the above embodiments can be expected.

【００６６】実施例１４．又、上記各実施例では、バー
ンイン検査基板の配線層の先端にリード線を接続して、
バーンイン検査を行う場合について説明したが、配線層
上に直接検査のためのプローブを接触させてバーンイン
検査を行うようにしても良く、上記各実施例と同様の効
果が期待できる。Example 14 In each of the above embodiments, a lead wire is connected to the tip of the wiring layer of the burn-in test board,
Although the case of performing the burn-in test has been described, the burn-in test may be performed by directly contacting the probe for the test on the wiring layer, and the same effect as each of the above-described embodiments can be expected.

【００６７】[0067]

【発明の効果】以上のように、この発明の請求項１によ
れば、表面の所定の位置にパッドが形成された半導体チ
ップと、半導体チップの表面を覆うように形成されパッ
ドと対応する位置にパッドの上面まで達する開口を有す
る緩衝層と、開口に充填され上面が緩衝層より上方に突
出して形成された導電性部材でなるバンプとを備えたの
で、プリント基板への実装時に表面が十分に保護され、
歩留まりの向上を図ることが可能なフリップチップを提
供することができる。As described above, according to claim 1 of the present invention, a semiconductor chip having a pad formed at a predetermined position on the surface and a position corresponding to the pad formed so as to cover the surface of the semiconductor chip. In addition, the buffer layer having an opening reaching the upper surface of the pad and the bump made of a conductive member which is filled in the opening and the upper surface of which protrudes above the buffer layer are provided. Protected by
A flip chip capable of improving the yield can be provided.

【００６８】又、この発明の請求項２によれば、請求項
１において、緩衝層を絶縁樹脂で形成するようにしたの
で、プリント基板への実装時に表面が十分に保護され、
歩留まりの向上を図ることが可能なフリップチップを提
供することができる。According to a second aspect of the present invention, in the first aspect, since the buffer layer is formed of the insulating resin, the surface is sufficiently protected when mounted on the printed circuit board,
A flip chip capable of improving the yield can be provided.

【００６９】又、この発明の請求項３によれば、請求項
２において、弾性を有する絶縁樹脂で形成するようにし
たので、プリント基板への実装時に表面が十分に保護さ
れ、歩留まりの向上を図ることが可能なフリップチップ
を提供することができる。According to the third aspect of the present invention, since the insulating resin having elasticity is used in the second aspect, the surface is sufficiently protected at the time of mounting on the printed circuit board, and the yield is improved. A flip chip that can be manufactured can be provided.

【００７０】又、この発明の請求項４によれば、請求項
１において、バンプ上面の径を半導体チップのパッドと
接する下面の径より大に形成するようにしたので、プリ
ント基板への実装時に表面が十分に保護され、歩留まり
の向上を図ることが可能であり、且つ実装時における接
合面積を大にし信頼性の向上を図ることが可能なフリッ
プチップを提供することができる。According to a fourth aspect of the present invention, in the first aspect, the diameter of the upper surface of the bump is larger than the diameter of the lower surface in contact with the pad of the semiconductor chip. It is possible to provide a flip chip in which the surface is sufficiently protected, the yield can be improved, and the bonding area at the time of mounting can be increased to improve the reliability.

【００７１】又、この発明の請求項５によれば、請求項
４において、バンプは下面から上面に向けて径を階段状
に順次拡大させるようにしたので、実装時における接合
面積を大にし信頼性の向上を図ることが可能なフリップ
チップを提供することができる。According to a fifth aspect of the present invention, in the fourth aspect, the diameter of the bump is increased stepwise from the lower surface to the upper surface, so that the bonding area at the time of mounting is increased and reliability is improved. It is possible to provide a flip chip capable of improving the property.

【００７２】又、この発明の請求項６によれば、請求項
１において、バンプを金属粒子が添加された樹脂で形成
するようにしたので、他の配線等の熱による悪影響を与
えることが少なく、信頼性の向上を図ることが可能なフ
リップチップを提供することができる。According to the sixth aspect of the present invention, in the first aspect, since the bump is formed of the resin to which the metal particles are added, it is less likely that other wiring or the like is adversely affected by heat. Thus, it is possible to provide a flip chip capable of improving reliability.

【００７３】又、この発明の請求項７によれば、半導体
チップの表面に絶縁樹脂層を形成する工程と、絶縁樹脂
層の半導体チップのパッドと対応する部分を除去して開
口を形成する工程と、開口にバンプ部材を充填して加熱
溶融し上面を所定の形状に形成する工程とを包含したの
で、歩留まりの向上を図ることが可能なフリップチップ
が得られるフリップチップの製造方法を提供することが
できる。According to a seventh aspect of the present invention, the step of forming an insulating resin layer on the surface of the semiconductor chip and the step of removing the portion of the insulating resin layer corresponding to the pad of the semiconductor chip to form an opening. And a step of filling the opening with a bump member and heating and melting the same to form the upper surface into a predetermined shape. Therefore, a method of manufacturing a flip chip, which can obtain a flip chip capable of improving the yield, is provided. be able to.

【００７４】又、この発明の請求項８によれば、半導体
チップの表面に絶縁樹脂層を形成する工程と、絶縁樹脂
層の半導体チップのパッドと対応する部分を除去して開
口を形成する工程と、開口の内壁に金属膜を形成する工
程と、開口にクリームはんだを充填し加熱溶融してバン
プを形成する工程とを包含したので、信頼性の向上を図
ることが可能なフリップチップが得られるフリップチッ
プの製造方法を提供することができる。According to claim 8 of the present invention, the step of forming an insulating resin layer on the surface of the semiconductor chip, and the step of removing the portion of the insulating resin layer corresponding to the pad of the semiconductor chip to form an opening. And a step of forming a metal film on the inner wall of the opening and a step of filling the opening with cream solder and heating and melting to form bumps, a flip chip capable of improving reliability is obtained. It is possible to provide a method of manufacturing the flip chip.

【００７５】又、この発明の請求項９によれば、半導体
チップの表面に絶縁樹脂層を形成する工程と、絶縁樹脂
層の半導体チップのパッドと対応する部分を除去して開
口を形成する工程と、開口の内壁に金属膜を形成する工
程と、開口に電気めっきによりはんだ部材を充填し加熱
溶融してバンプを形成する工程とを包含したので、信頼
性の向上を図ることが可能なフリップチップが得られる
フリップチップの製造方法を提供することができる。According to claim 9 of the present invention, the step of forming an insulating resin layer on the surface of the semiconductor chip, and the step of removing the portion of the insulating resin layer corresponding to the pad of the semiconductor chip to form an opening. And a step of forming a metal film on the inner wall of the opening and a step of filling the opening with a solder member and heating and melting to form bumps, so that it is possible to improve reliability. A method of manufacturing a flip chip from which a chip is obtained can be provided.

【００７６】又、この発明の請求項１０によれば、可溶
性部材でなる基材と、この基材の表面に所定のパターン
で形成された配線層とを備えたので、バンプに影響を与
えることなく半導体チップから取りはずし可能なバーン
イン検査基板を提供することができる。According to the tenth aspect of the present invention, since the base material made of a fusible material and the wiring layer formed in a predetermined pattern on the surface of the base material are provided, the bumps are affected. It is possible to provide a burn-in test board that can be detached from a semiconductor chip without the need.

【００７７】又、この発明の請求項１１によれば、請求
項１０において、可溶性のバインダに導電性部材の粒子
を混合して配線層を形成するようにしたので、生産性の
向上を図ることが可能なバーンイン検査基板を提供する
ことができる。According to the eleventh aspect of the present invention, in the tenth aspect, the soluble binder is mixed with the particles of the conductive member to form the wiring layer, so that the productivity is improved. It is possible to provide a burn-in test board capable of performing the above.

【００７８】又、この発明の請求項１２によれば、請求
項１０において、低融点金属膜で配線層を形成するよう
にしたので、歩留まりの向上を図ることが可能なバーン
イン検査基板を提供することができる。According to the twelfth aspect of the present invention, in the tenth aspect, since the wiring layer is formed of the low melting point metal film, the burn-in inspection substrate capable of improving the yield is provided. be able to.

【００７９】又、この発明の請求項１３によれば、可溶
性部材でなる基材の表面に所定のパターンの配線層を施
してバーンイン検査基板を形成する工程と、バーンイン
検査基板の配線層にフリップチップのバンプ部を接合し
てバーンイン検査を行う工程と、基材を溶剤にて溶解し
除去する工程と、フリップチップのバンプ部を加熱溶融
してプリント基板のパッド部に接合する工程とを包含し
たので、バンプに影響を与えることなくプリント基板へ
の実装ができ、信頼性の向上が可能なフリップチップの
実装方法を提供することができる。According to a thirteenth aspect of the present invention, a step of forming a burn-in test board by forming a wiring layer having a predetermined pattern on the surface of the base material made of a soluble member, and flipping the burn-in test board wiring layer. Includes the steps of bonding the bumps of the chip and performing a burn-in test, dissolving the base material with a solvent and removing it, and heating and melting the bumps of the flip chip to bond them to the pads of the printed circuit board. Therefore, it is possible to provide a flip-chip mounting method capable of mounting on a printed circuit board without affecting bumps and improving reliability.

【００８０】又、この発明の請求項１４によれば、可溶
性部材でなる基材の表面に所定のパターンの配線層を施
してバーンイン検査基板を形成する工程と、バーンイン
検査基板の配線層にフリップチップのバンプ部を接合し
てバーンイン検査を行う工程と、基材を溶剤にて溶解し
除去する工程と、フリップチップの表面にバンプ部を除
いて封止剤を塗布する工程と、フリップチップのバンプ
部を加熱溶融してプリント基板のパッド部に接合する工
程とを包含したので、プリント基板との接合部に影響を
与えることなくプリント基板への実装ができ、信頼性の
向上が可能なフリップチップの実装方法を提供すること
ができる。According to a fourteenth aspect of the present invention, a step of forming a burn-in test substrate by forming a wiring layer having a predetermined pattern on the surface of the base material made of a soluble member, and flipping the burn-in test substrate wiring layer. A step of joining the bumps of the chip and performing a burn-in test; a step of dissolving and removing the base material with a solvent; a step of applying a sealant on the surface of the flip chip excluding the bumps; Since it includes the step of heating and melting the bump portion and joining it to the pad portion of the printed circuit board, it is possible to mount it on the printed circuit board without affecting the joint part with the printed circuit board and to improve the reliability. A chip mounting method can be provided.

【００８１】又、この発明の請求項１５によれば、可溶
性部材でなる基材の表面に所定パターンの配線層を施し
てなるバーンイン検査基板の配線層上の所定の位置にバ
ンプ部材を装着する工程と、半導体チップの表面を覆う
緩衝層の開口にバンプ部材の位置を対応させるとともに
開口にバンプ部材を嵌入し加熱溶融して接合しバーンイ
ン検査を行う工程と、基材を溶剤にて溶解して除去しフ
リップチップを形成する工程と、フリップチップのバン
プ部を加熱溶融してプリント基板のパッド部に接合する
工程とを包含したので、配線層を取りはずしたりする作
業を省け生産性の向上が可能なフリップチップの実装方
法を提供することができる。According to the fifteenth aspect of the present invention, the bump member is mounted at a predetermined position on the wiring layer of the burn-in test board in which the wiring layer having a predetermined pattern is formed on the surface of the base material made of the soluble material. The step, the step of associating the position of the bump member with the opening of the buffer layer covering the surface of the semiconductor chip, the step of fitting the bump member into the opening, heating and melting and joining to perform burn-in inspection, and melting the base material with a solvent. Since it includes a step of removing the wiring layer to form a flip chip and a step of heating and melting the bump portion of the flip chip to bond it to the pad portion of the printed circuit board, the work of removing the wiring layer is omitted and the productivity is improved. A possible flip chip mounting method can be provided.

【００８２】又、この発明の請求項１６によれば、可溶
性部材でなる基材の表面に所定パターンの配線層を施し
てなるバーンイン検査基板の表面に緩衝層を形成すると
ともに緩衝層の半導体チップのパッドと対応する位置に
開口を形成する工程と、緩衝層の開口にバンプ部材を充
填する工程と、緩衝層の表面に接着剤を塗布し半導体チ
ップに接着する工程と、開口に充填されたバンプ部材を
加熱溶融して半導体チップのパッド部に接合しバーンイ
ン検査を行う工程と、基材を溶剤にて溶解して除去しフ
リップチップを形成する工程と、フリップチップのバン
プ部を加熱溶融してプリント基板のパッド部に接合する
工程とを包含したので、配線層の取りはずしの際にバン
プがはずれたりすることもなく歩留まりの向上が可能な
フリップチップの実装方法を提供することができる。According to a sixteenth aspect of the present invention, a buffer layer is formed on the surface of a burn-in test substrate in which a wiring layer having a predetermined pattern is formed on the surface of a base material made of a soluble member, and the semiconductor chip of the buffer layer is formed. The step of forming an opening at a position corresponding to the pad, the step of filling the opening of the buffer layer with a bump member, the step of applying an adhesive to the surface of the buffer layer and adhering it to the semiconductor chip, and the step of filling the opening. A step of heating and melting the bump member to bond it to the pad portion of the semiconductor chip and performing a burn-in test; a step of dissolving and removing the base material with a solvent to form a flip chip; and a step of heating and melting the bump portion of the flip chip. The process of bonding to the pad part of the printed circuit board is included, so that the yield can be improved without the bumps coming off when the wiring layer is removed. It is possible to provide a instrumentation methods.

【図面の簡単な説明】[Brief description of drawings]

【図１】 この発明の実施例１におけるフリップチップ
の製造方法を示す断面図である。FIG. 1 is a cross-sectional view showing a method of manufacturing a flip chip according to a first embodiment of the present invention.

【図２】 図１におけるフリップチップのプリント基板
への実装方法を示す断面図である。FIG. 2 is a cross-sectional view showing a method of mounting the flip chip in FIG. 1 on a printed board.

【図３】 この発明の実施例４におけるフリップチップ
の実装方法の工程の一部を示す断面図である。FIG. 3 is a cross-sectional view showing a part of the process of the flip-chip mounting method according to the fourth embodiment of the present invention.

【図４】 この発明の実施例５におけるフリップチップ
の製造方法を示す断面図である。FIG. 4 is a sectional view showing a method of manufacturing a flip chip according to a fifth embodiment of the present invention.

【図５】 この発明の実施例６におけるフリップチップ
の製造方法を示す断面図である。FIG. 5 is a sectional view showing a method of manufacturing a flip chip according to a sixth embodiment of the present invention.

【図６】 この発明の実施例７におけるフリップチップ
の製造方法を示す断面図である。FIG. 6 is a cross-sectional view showing a method of manufacturing a flip chip in Example 7 of the present invention.

【図７】 この発明の実施例８におけるフリップチップ
の実装方法の工程の一部を示す断面図である。FIG. 7 is a cross-sectional view showing a part of the process of the flip-chip mounting method according to the eighth embodiment of the present invention.

【図８】 この発明の実施例９におけるフリップチップ
の実装方法の工程の一部を示す断面図である。FIG. 8 is a sectional view showing a part of the process of the flip-chip mounting method according to the ninth embodiment of the present invention.

【図９】 この発明の実施例１０におけるバーンイン検
査基板の概略構成を示す断面図である。FIG. 9 is a sectional view showing a schematic configuration of a burn-in inspection board in Embodiment 10 of the present invention.

【図１０】 この発明の実施例１１におけるバーンイン
検査基板の概略構成を示す断面図である。FIG. 10 is a sectional view showing a schematic configuration of a burn-in inspection board according to an eleventh embodiment of the present invention.

【図１１】 従来のフリップチップの製造方法を示す断
面図である。FIG. 11 is a cross-sectional view showing a conventional flip-chip manufacturing method.

【符号の説明】[Explanation of symbols]

１ 半導体チップ、２ パッド、１１，２２，３８ 絶
縁樹脂層（緩衝層）、１１ａ，２２ａ，３８ａ 開口、
１２，２４ クリームはんだ、１３，２５，３０ はん
だバンプ、１４，２６，３１，３４，３７，４２ フリ
ップチップ、１５，４３，４６ 基材、１６，４４，４
７ 配線層、１７，４５，４８ バーンイン検査基板、
１９ プリント基板、２０ パッド部、２１ 封止剤、
２３ 金属膜、２７ 導電膜、２８ フォトレジスト、
２９ はんだ部材、３２ 導電性樹脂、３３，３６，４
１ バンプ、３５，３９ バンプ部材、４４ａ バイン
ダ、４４ｂ 導電性粒子。1 semiconductor chip, 2 pads, 11, 22, 38 insulating resin layers (buffer layers), 11a, 22a, 38a openings,
12,24 Cream solder, 13,25,30 Solder bump, 14,26,31,34,37,42 Flip chip, 15,43,46 Base material, 16,44,4
7 wiring layers, 17, 45, 48 burn-in test board,
19 printed circuit board, 20 pad section, 21 sealant,
23 metal film, 27 conductive film, 28 photoresist,
29 Solder member, 32 Conductive resin, 33, 36, 4
1 bump, 35, 39 bump member, 44a binder, 44b conductive particles.

Claims (16)

【特許請求の範囲】[Claims] 【請求項１】 表面の所定の位置にパッドが形成された
半導体チップと、上記半導体チップの表面を覆うように
形成され上記パッドと対応する位置に上記パッドの上面
まで達する開口を有する緩衝層と、上記開口に充填され
上面が上記緩衝層より上方に突出して形成された導電性
部材でなるバンプとを備えたことを特徴とするフリップ
チップ。1. A semiconductor chip in which a pad is formed at a predetermined position on the surface, and a buffer layer having an opening reaching the upper surface of the pad at a position corresponding to the pad and covering the surface of the semiconductor chip. A flip chip, comprising: a bump formed of a conductive member, the bump being filled in the opening and having an upper surface protruding above the buffer layer. 【請求項２】 緩衝層は絶縁樹脂で形成されていること
を特徴とする請求項１記載のフリップチップ。2. The flip chip according to claim 1, wherein the buffer layer is formed of an insulating resin. 【請求項３】 絶縁樹脂は弾性を有していることを特徴
とする請求項２記載のフリップチップ。3. The flip chip according to claim 2, wherein the insulating resin has elasticity. 【請求項４】 バンプ上面の径が半導体チップのパッド
と接する下面の径より大に形成されていることを特徴と
する請求項１記載のフリップチップ。4. The flip chip according to claim 1, wherein the diameter of the upper surface of the bump is larger than the diameter of the lower surface of the bump contacting the pad of the semiconductor chip. 【請求項５】 バンプは下面から上面に向けて径が階段
状に順次拡大されていることを特徴とする請求項４記載
のフリップチップ。5. The flip chip according to claim 4, wherein the bump has a diameter which is sequentially increased in a stepwise manner from the lower surface to the upper surface. 【請求項６】 バンプは金属粒子が添加された樹脂で形
成されていることを特徴とする請求項１記載のフリップ
チップ。6. The flip chip according to claim 1, wherein the bump is formed of a resin to which metal particles are added. 【請求項７】 半導体チップの表面に絶縁樹脂層を形成
する工程と、上記絶縁樹脂層の上記半導体チップのパッ
ドと対応する部分を除去して開口を形成する工程と、上
記開口にバンプ部材を充填して加熱溶融し上面を所定の
形状に形成する工程とを包含したことを特徴とするフリ
ップチップの製造方法。7. A step of forming an insulating resin layer on a surface of a semiconductor chip, a step of removing a portion of the insulating resin layer corresponding to a pad of the semiconductor chip to form an opening, and a bump member being provided in the opening. A method of manufacturing a flip chip, comprising the steps of filling, heating and melting, and forming the upper surface into a predetermined shape. 【請求項８】 半導体チップの表面に絶縁樹脂層を形成
する工程と、上記絶縁樹脂層の上記半導体チップのパッ
ドと対応する部分を除去して開口を形成する工程と、上
記開口の内壁に金属膜を形成する工程と、上記開口にク
リームはんだを充填し加熱溶融してバンプを形成する工
程とを包含したことを特徴とするフリップチップの製造
方法。8. A step of forming an insulating resin layer on a surface of a semiconductor chip, a step of removing a portion of the insulating resin layer corresponding to a pad of the semiconductor chip to form an opening, and a metal on an inner wall of the opening. A method of manufacturing a flip chip, comprising: a step of forming a film; and a step of filling the openings with cream solder and heating and melting to form bumps. 【請求項９】 半導体チップの表面に絶縁樹脂層を形成
する工程と、上記絶縁樹脂層の上記半導体チップのパッ
ドと対応する部分を除去して開口を形成する工程と、上
記開口の内壁に金属膜を形成する工程と、上記開口に電
気めっきによりはんだ部材を充填し加熱溶融してバンプ
を形成する工程とを包含したことを特徴とするフリップ
チップの製造方法。9. A step of forming an insulating resin layer on a surface of a semiconductor chip, a step of removing a portion of the insulating resin layer corresponding to a pad of the semiconductor chip to form an opening, and a metal on an inner wall of the opening. A method of manufacturing a flip chip, comprising: a step of forming a film; and a step of filling a solder member in the opening by electroplating and heating and melting to form a bump. 【請求項１０】 可溶性部材でなる基材と、この基材の
表面に所定のパターンで形成された配線層とを備えたこ
とを特徴とするバーンイン検査基板。10. A burn-in test board comprising a base material made of a soluble material and a wiring layer formed on the surface of the base material in a predetermined pattern. 【請求項１１】 配線層は可溶性のバインダに導電性部
材の粒子を混合して形成されていることを特徴とする請
求項１０記載のバーンイン検査基板。11. The burn-in test board according to claim 10, wherein the wiring layer is formed by mixing particles of a conductive member with a soluble binder. 【請求項１２】 配線層は低融点金属膜で形成されてい
ることを特徴とする請求項１０記載のバーンイン検査基
板。12. The burn-in test board according to claim 10, wherein the wiring layer is formed of a low melting point metal film. 【請求項１３】 可溶性部材でなる基材の表面に所定の
パターンの配線層を施してバーンイン検査基板を形成す
る工程と、上記バーンイン検査基板の配線層にフリップ
チップのバンプ部を接合してバーンイン検査を行う工程
と、上記基材を溶剤にて溶解し除去する工程と、上記フ
リップチップのバンプ部を加熱溶融してプリント基板の
パッド部に接合する工程とを包含したことを特徴とする
フリップチップの実装方法。13. A step of forming a burn-in inspection substrate by applying a wiring layer having a predetermined pattern on a surface of a base material made of a soluble material, and a bump portion of a flip chip being bonded to the wiring layer of the burn-in inspection substrate to burn-in. A flip characterized by including an inspection step, a step of dissolving and removing the base material with a solvent, and a step of heating and melting the bump part of the flip chip to bond it to a pad part of a printed circuit board. Chip mounting method. 【請求項１４】 可溶性部材でなる基材の表面に所定の
パターンの配線層を施してバーンイン検査基板を形成す
る工程と、上記バーンイン検査基板の配線層にフリップ
チップのバンプ部を接合してバーンイン検査を行う工程
と、上記基材を溶剤にて溶解し除去する工程と、上記フ
リップチップの表面に上記バンプ部を除いて封止剤を塗
布する工程と、上記フリップチップのバンプ部を加熱溶
融してプリント基板のパッド部に接合する工程とを包含
したことを特徴とするフリップチップの実装方法。14. A step of forming a burn-in inspection board by forming a wiring layer having a predetermined pattern on a surface of a base material made of a soluble material, and a bump portion of a flip chip being bonded to the wiring layer of the burn-in inspection board to burn-in. Step of inspecting, step of dissolving and removing the base material with a solvent, step of applying sealant on the surface of the flip chip except the bump portion, heating and melting the bump portion of the flip chip And a step of bonding to a pad portion of the printed circuit board. 【請求項１５】 可溶性部材でなる基材の表面に所定パ
ターンの配線層を施してなるバーンイン検査基板の上記
配線層上の所定の位置にバンプ部材を装着する工程と、
半導体チップの表面を覆う緩衝層の開口に上記バンプ部
材の位置を対応させるとともに上記開口に上記バンプ部
材を嵌入し加熱溶融して接合しバーンイン検査を行う工
程と、上記基材を溶剤にて溶解して除去しフリップチッ
プを形成する工程と、上記フリップチップのバンプ部を
加熱溶融してプリント基板のパッド部に接合する工程と
を包含したことを特徴とするフリップチップの実装方
法。15. A step of mounting a bump member at a predetermined position on the wiring layer of a burn-in test substrate, which is formed by applying a wiring layer having a predetermined pattern on a surface of a base material made of a soluble material,
A step of matching the position of the bump member with the opening of the buffer layer covering the surface of the semiconductor chip, inserting the bump member into the opening, heating and melting and joining to perform burn-in inspection, and melting the base material with a solvent A flip-chip mounting method comprising: a step of removing and removing the flip-chip to form a flip-chip; and a step of heating and melting the bump part of the flip-chip to bond it to the pad part of the printed board. 【請求項１６】 可溶性部材でなる基材の表面に所定パ
ターンの配線層を施してなるバーンイン検査基板の表面
に緩衝層を形成するとともに上記緩衝層の半導体チップ
のパッドと対応する位置に開口を形成する工程と、上記
緩衝層の開口にバンプ部材を充填する工程と、上記緩衝
層の表面に接着剤を塗布し上記半導体チップに接着する
工程と、上記開口に充填されたバンプ部材を加熱溶融し
て上記半導体チップのパッド部に接合しバーンイン検査
を行う工程と、上記基材を溶剤にて溶解して除去しフリ
ップチップを形成する工程と、上記フリップチップのバ
ンプ部を加熱溶融してプリント基板のパッド部に接合す
る工程とを包含したことを特徴とするフリップチップの
実装方法。16. A buffer layer is formed on the surface of a burn-in test substrate formed by applying a wiring layer having a predetermined pattern on the surface of a base material made of a soluble material, and an opening is formed in the buffer layer at a position corresponding to a pad of a semiconductor chip. A step of forming, a step of filling a bump member in the opening of the buffer layer, a step of applying an adhesive to the surface of the buffer layer and adhering it to the semiconductor chip, and heating and melting the bump member filled in the opening Then, a step of performing a burn-in test by bonding to the pad portion of the semiconductor chip, a step of dissolving and removing the base material with a solvent to form a flip chip, and a step of heating and melting the bump portion of the flip chip to print A flip-chip mounting method comprising a step of bonding to a pad portion of a substrate.
JP5114695A 1995-03-10 1995-03-10 Flip-chip and manufacture and mounting thereof and burn-in inspection substrate Pending JPH08250551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5114695A JPH08250551A (en) 1995-03-10 1995-03-10 Flip-chip and manufacture and mounting thereof and burn-in inspection substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5114695A JPH08250551A (en) 1995-03-10 1995-03-10 Flip-chip and manufacture and mounting thereof and burn-in inspection substrate

Publications (1)

Publication Number Publication Date
JPH08250551A true JPH08250551A (en) 1996-09-27

Family

ID=12878692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5114695A Pending JPH08250551A (en) 1995-03-10 1995-03-10 Flip-chip and manufacture and mounting thereof and burn-in inspection substrate

Country Status (1)

Country Link
JP (1) JPH08250551A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100253323B1 (en) * 1997-09-27 2000-04-15 김영환 Semiconductor package and fabricating method thereof
EP1022774A2 (en) 1999-01-21 2000-07-26 Lucent Technologies Inc. Flip chip assembly of semiconductor IC chips
WO2001073856A3 (en) * 2000-03-27 2002-05-23 Aegis Semiconductor A semitransparent optical detector on a flexible substrate and method of making
US6670599B2 (en) 2000-03-27 2003-12-30 Aegis Semiconductor, Inc. Semitransparent optical detector on a flexible substrate and method of making
US6879014B2 (en) 2000-03-20 2005-04-12 Aegis Semiconductor, Inc. Semitransparent optical detector including a polycrystalline layer and method of making
US7002697B2 (en) 2001-08-02 2006-02-21 Aegis Semiconductor, Inc. Tunable optical instruments
CN1294635C (en) * 2000-05-01 2007-01-10 精工爱普生株式会社 Protsusion forming method, semiconductor device and its mfg. method, circuit board and electronic machine
US7221827B2 (en) 2003-09-08 2007-05-22 Aegis Semiconductor, Inc. Tunable dispersion compensator
CN1321320C (en) * 2005-03-23 2007-06-13 北京青鸟元芯微系统科技有限责任公司 Chip degree aging method of thermal diffusion pressure drag type MEMS pressure sensor
JP2009049055A (en) * 2007-08-14 2009-03-05 Enrei Yu Method of forming metal bump on semiconductor coupling sheet
JP2011134770A (en) * 2009-12-22 2011-07-07 Sumitomo Electric Ind Ltd Detector, light-receiving element array, and method of manufacturing the detector
CN109257872A (en) * 2018-10-23 2019-01-22 广东晶科电子股份有限公司 A kind of Mini LED module and preparation method thereof

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100253323B1 (en) * 1997-09-27 2000-04-15 김영환 Semiconductor package and fabricating method thereof
EP1022774A2 (en) 1999-01-21 2000-07-26 Lucent Technologies Inc. Flip chip assembly of semiconductor IC chips
EP1022774A3 (en) * 1999-01-21 2003-08-06 Lucent Technologies Inc. Flip chip assembly of semiconductor IC chips
US6879014B2 (en) 2000-03-20 2005-04-12 Aegis Semiconductor, Inc. Semitransparent optical detector including a polycrystalline layer and method of making
WO2001073856A3 (en) * 2000-03-27 2002-05-23 Aegis Semiconductor A semitransparent optical detector on a flexible substrate and method of making
US6670599B2 (en) 2000-03-27 2003-12-30 Aegis Semiconductor, Inc. Semitransparent optical detector on a flexible substrate and method of making
CN1294635C (en) * 2000-05-01 2007-01-10 精工爱普生株式会社 Protsusion forming method, semiconductor device and its mfg. method, circuit board and electronic machine
US7002697B2 (en) 2001-08-02 2006-02-21 Aegis Semiconductor, Inc. Tunable optical instruments
US7221827B2 (en) 2003-09-08 2007-05-22 Aegis Semiconductor, Inc. Tunable dispersion compensator
CN1321320C (en) * 2005-03-23 2007-06-13 北京青鸟元芯微系统科技有限责任公司 Chip degree aging method of thermal diffusion pressure drag type MEMS pressure sensor
JP2009049055A (en) * 2007-08-14 2009-03-05 Enrei Yu Method of forming metal bump on semiconductor coupling sheet
JP2011134770A (en) * 2009-12-22 2011-07-07 Sumitomo Electric Ind Ltd Detector, light-receiving element array, and method of manufacturing the detector
CN109257872A (en) * 2018-10-23 2019-01-22 广东晶科电子股份有限公司 A kind of Mini LED module and preparation method thereof
CN109257872B (en) * 2018-10-23 2024-03-26 广东晶科电子股份有限公司 Mini LED module and manufacturing method thereof

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