KR960000219B1 - Package and manufacture method - Google Patents

Abstract

a substrate where multiple penetration hole is formulated; the first many leads which is installed at a confronting position with a electrode pad of a semiconductor chip to be bonded; the second multiple leads which is electrically connected to one side of the leads through the penetration hole and which is formulated beneath the substrate; a semiconductor chip which is flip chip bonded to a different leads with the first leads formulated below the substrate.

Description

Semiconductor package and manufacturing method

1 is a cross-sectional view showing an example of a semiconductor chip mounting method according to the prior art.

2 is a partially cutaway perspective view showing one embodiment of a semiconductor package according to the present invention.

3 is a manufacturing process diagram showing the manufacturing method of the semiconductor package of FIG.

4 is a cross-sectional view showing a state in which a semiconductor package according to the present invention is mounted on a liquid crystal display panel.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same. More particularly, when mounting a liquid crystal display (LCD) panel, the semiconductor chip is micro-packaged so as to facilitate rework and repair, and the semiconductor chip is packaged into a liquid crystal display panel. It is related with the semiconductor package to be mounted, and its manufacturing method.

Various methods have been proposed for bonding a semiconductor chip, for example, an integrated circuit for driving a liquid crystal display panel (hereinafter referred to as an LCD panel) on a wiring board.

Currently, one method that is attracting attention as a technology for mounting a LCD panel using a glass substrate is a tab automated tape (TAB) method. This tap method was conceived because of the necessity of multi-terminal connection according to the large-capacity display of the LCD panel. The tab method is based on the semiconductor film on the base film having inner and outer leads formed by patterning copper foil, not by conventional wire bonding. A method of collectively connecting electrodes and corresponding internal leads and connecting the external leads to wiring on an LCD panel.

Recently, there has been a demand for changing the mounting method of LCD panels of 4 inches or less due to the simplification of the process, the high pitch of the pins, and the cost reduction. Accordingly, a so-called chip on glass (COG) technology has been developed, which is a method of directly bonding a driving semiconductor chip on a glass substrate of an LCD panel in a bare chip state. Most of the COG technology uses a flip chip mounting method for bonding, and is particularly advantageous for high density mounting. However, glass substrates are not as strong as ceramics, and have a much larger thermal expansion coefficient than that of semiconductor chips (coefficient of thermal expansion of glass substrates is 80∽100 × 10 ^-7 / ℃, and that of semiconductor chips is 30∽10 ^-7 / ℃). Have This difference in thermal expansion coefficient causes cracks in the glass substrate, damages the semiconductor chip, and adversely affects reliability. In particular, since the heat resistance temperature of the color filter is about 150 ° C., when the semiconductor chip is bonded onto the color LCD panel employing the color filter, there is a problem that the temperature is limited. As a technique for overcoming these problems, low temperature bonding technology has been actively discussed.

As an example of a flip chip mounting method, for example, US Pat. No. 4,661,192 forms a solder bump 14 on an electrode pad of a semiconductor chip 13, as shown in FIG. 1, and solder bumps of the semiconductor chip 13. Paste (14) is applied to the metal wiring terminal 12 on the glass substrate 10 after the paste (Paste). Reference numeral 15 denotes an insulating bonding material, such as epoxy resin, silicone resin, or the like, for reinforcing a weak bond due to a difference in thermal expansion coefficient between the glass substrate 10 and the semiconductor chip 13.

Such a semiconductor chip mounting method has an advantage of being relatively simple and easy to mount, but has difficulty in controlling flatness of a paste buried on a bump. In addition, the mounting method undergoes various tests such as burn-in test to test whether the semiconductor chip is a defect-free semiconductor chip, that is, a known good die (KGD) before mounting. Since there is a need to handle in a bare chip state, there is a problem in that it is not easy to secure KGD.

As another example of a conventional semiconductor chip mounting method, the Republic of Korea Patent Publication No. 91-17615 is a method of forming a conductive particle on a semiconductor chip electrode pad using the characteristics of the optical setting adhesive, and bonding to a substrate using UV epoxy, fine Although it is advantageous for pitch application, there is a problem in that the manufacturing process is very complicated and KGD is not easy to secure.

In addition, after apply | coating conductive particle on a board | substrate, a semiconductor chip may be face-down bonded and a molding and a ceramic cap may be covered. In addition, there is a method of flip-chip mounting a semiconductor chip having a solder bump formed on a substrate, and encapsulating for improved reliability. However, these methods are also difficult to secure KGD, and since the semiconductor chip having the fine pitch electrode pads are directly mounted, it is difficult to design the substrate according to the installation of the fine metal wiring corresponding to each electrode pad. In addition, there is a problem in that a process of removing and replacing an encapsulated defective semiconductor chip, that is, rework and repair is difficult, and a low temperature bonding process is difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor package and a method of manufacturing the same, which propose a new structure for mounting a semiconductor chip on an LCD panel.

Another object of the present invention is to provide a semiconductor package and a method for manufacturing the same, which enable a low temperature bonding process when mounting a semiconductor chip on an LCD panel.

It is still another object of the present invention to provide a semiconductor package and a method of manufacturing the same, which facilitate KGD securing when mounting a semiconductor chip in an LCD panel.

Another object of the present invention is to provide a semiconductor package and a method of manufacturing the same that are easy to rework and repair when mounting an LCD panel.

A feature of the semiconductor package according to the present invention for achieving the above object is that the semiconductor chip is formed on a substrate having a plurality of through holes and an upper surface of the substrate, one end of which is in contact with the through hole, and the other end of which is to be bonded. A plurality of first leads installed at positions corresponding to the electrode pads; A plurality of second leads formed on a bottom surface of the substrate and electrically connected to one end of the lead through the through hole; A semiconductor chip flip-chip bonded to different ends of the plurality of first leads formed on the upper surface of the substrate; It is made of a molding resin for molding the semiconductor chip.

A feature of the method for manufacturing a semiconductor package of the present invention for achieving the above-mentioned woodwork includes: a first step of forming a through hole in a substrate; A second step of forming a plurality of first and second leads electrically connected to each other through the through holes by using a metal material on the upper and lower surfaces of the substrate on which the through holes are formed; A third step of flip chip bonding a semiconductor device and a fourth step of encapsulating the flip chip bonded semiconductor chip are provided at one end of a plurality of first electrodes formed on an upper surface of the substrate.

Hereinafter, one preferred embodiment of a semiconductor package and a mounting method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a partially cutaway perspective view of a semiconductor package according to the present invention. As shown here, the thin film substrate 30 such as ceramic, glass ceramic, polyimide, or printed circuit board (PCB), such as alumina, and the image of the substrate 30 A plurality of leads 21, 25 are formed on the lower surface which are electrically connected to each other through the through holes.

The lead 21 formed on the upper surface of the substrate 30 has an inner lead 21a and an outer lead 21b. The lead 25 formed on the lower surface of the substrate 30 is electrically connected to one end of the outer lead 21b through a connection portion 28 of a conductive material filled in the through hole. The lid 25 on the lower surface is designed in consideration of the position of the metal wiring of the LCD panel and the like. The semiconductor chip 40 is collectively connected on the inner lead 21a formed on the upper surface of the substrate 30 via the solder bumps 42. The flip chip bonded semiconductor chip 40 is molded by the molding resin 44.

4 is a cross-sectional view showing a state in which a semiconductor package according to the present invention is mounted on an LCD panel. As shown in the drawing, the semiconductor package 50 according to the present invention includes two glass substrates 60 and 66 of the LCD panel in which two glass substrates 60 and 66 are arranged in parallel at regular intervals with the liquid crystal 64 therebetween. 66 is mounted on at least one substrate 66. Here, the semiconductor package includes a driving semiconductor chip for driving the LCD which has been burned-in, that is, found to be KGD. In the semiconductor package 50, a pad 27 of a lead formed on a bottom surface of the substrate 30 and a metal wiring pad (not shown) of an LCD panel corresponding thereto are electrically connected to each other by an anisotropic conductive adhesive. The anisotropic conductive adhesive is an ultraviolet curable anisotropic conductive material can be obtained at the same time electrical conductivity and sealability.

As described above, the semiconductor package of the present invention, unlike the conventional method of mounting the semiconductor chip in the LCD panel mounting, enables a method of micro-packaging the semiconductor chip first and mounting it secondly. Flip-chip technology can be applied to color LCD panels, reliability is improved, electrical / environmental testing is possible on the packaged chip, and rework is easy. This effect of this invention will be more clearly understood in the production method described below.

One embodiment of a method of manufacturing a semiconductor package according to the present invention as described above will be described.

As shown in FIG. 3A, a thin alumina green sheet is prepared as the substrate 30, and a through hole is formed along the periphery of the package to be formed in the substrate 30. 26) is formed as many as the number of leads. Instead of alumina, the substrate 30 may be made of ceramic, glass ceramic, polyimide, or printed circuit board (PCB) as it is, and may be formed of a thin film. It is safe to use. In addition, the substrate 30 uses a long strip shape so that a plurality of packages can be formed at the same time. In the following description, one package will be described.

Next, in order to form the leads connected to the electrodes of the semiconductor chip, the lead pattern layout is precisely designed in consideration of the electrode position of the semiconductor chip, the position of the LCD panel, and the like. Scrreen printing the conductive materials 24a and 24b on each of the plurality of leads 21 and 25 on the upper and lower surfaces of the substrate 30 as shown in FIGS. 3C and 3D, respectively. To form. Here, FIG. 3 (c) shows the lead 21 formed on the upper surface of the substrate 30, and FIG. 3 (d) shows the lead 25 formed on the lower surface of the substrate 30. At this time, the conductive material is also filled in the through hole 26 so that the conductive materials 24a and 24b on the upper and lower surfaces of the substrate 30 are electrically connected through the connection portion 28 of the conductive material on the inner surface of the through hole 26. To be connected.

FIG. 3B shows a cross section in which the conductive materials 24a and 24b of the upper and lower surfaces of the substrate 30 are electrically interconnected through the connecting portion 28 in the through hole 26. Here, tungsten (W), molybdenum-manganese alloy (Mo-Mn), or the like may be used as the connection portion 28 of the conductive material 24a or 24b to be screen printed or the conductive material filled in the through hole 26. When using a glass ceramic, which is a low-temperature sintered body instead of alumina as the material of the substrate 30, aluminum (Al), copper (Cu), gold (Au), or the like may be used as the conductive material.

As described above, in forming the leads 21 and 25 formed on the upper and lower surfaces of the substrate 30 and interconnected through the connecting portions 28, the lead pitch at the place where the solder bumps of the semiconductor chip to be mounted is to be placed is very narrow. In the case (100 micrometers or less), it patterns by the photolithographic method. That is, as shown in FIG. 3A, the substrate 30 is immersed in a liquid metal material to form a metal thin film on the upper and lower surfaces of the commercially available 30. Then, photolithography is performed to form a plurality of independent leads 21 and 25 respectively on the upper and lower surfaces of the substrate 20, as shown in FIGS. 3C and 3D.

Next, as shown in FIG. 3E, the semiconductor chip 40 is bonded onto the plurality of internal leads 21a formed on the upper surface of the substrate 30. Bonding of the semiconductor chip 40 is performed by the flip chip bonding method using the flip chip in which the solder bump 42 was formed. After bonding the semiconductor chip 40, the semiconductor chip 40 is encapsulated in an upper surface of the semiconductor chip 40 and a gap between the semiconductor chip 40 and the substrate 30.

After the semiconductor chip package is completed, they are separated into individual packages. KGD is obtained by electrical / environmental test and burn-in test of the separated micro package. As described above, the semiconductor package manufactured as described above may be mounted on a LCD panel by a conventional flip chip bonding method using solder bumps.

As described above, according to the semiconductor package and the manufacturing method thereof according to the present invention, it is mounted in the same manner as bare chip mounting, but can be formed in the KGD in the package state, so that the yield is improved and the internal design of the semiconductor chip is changed. It can be applied by changing the design of the board without mounting, and it can be mounted by flip chip bonding technology using solder bumper when mounting LCD panel, and there is no thermal limitation during mounting work, and it is easy to rework and repair by using anisotropic conductive adhesive. Reliability is greatly improved.

Claims (11)

A substrate on which a plurality of through holes are formed; A plurality of first leads formed on an upper surface of the substrate, the one end being in contact with the through hole and the other end being disposed at a position corresponding to the electrode pad of the semiconductor chip to be bonded; A plurality of second leads formed on a bottom surface of the substrate and electrically connected to one end of the lead through the through hole; A semiconductor chip flip-chip bonded to different ends of the plurality of first leads formed on the upper surface of the substrate; A semiconductor package comprising a molding resin for molding the semiconductor chip. The semiconductor package of claim 1, wherein the substrate is formed of any one of ceramic, glass ceramic, polyimide, and printed circuit board (PCB). The semiconductor package of claim 1, wherein the first lead comprises an internal lead connected to the electrode pad of the semiconductor chip to be bonded and an external lead connected to the internal lead. The semiconductor package of claim 1, wherein the second lead is electrically connected to the first lead by a conductive material filled in a through hole formed in a substrate. The semiconductor package of claim 4, wherein the conductive material is formed of any one of tungsten (W), molybdenum-manganese alloy (Mo-Mn), aluminum (Al), copper (Cu), and gold (Au). A first step of forming a through hole in the substrate; A second step of forming a plurality of first and second leads electrically connected to each other through the through holes by using a metal material on the upper and lower surfaces of the substrate on which the through holes are formed; A third process of flip chip bonding a semiconductor package to one end of a plurality of first electrodes formed on an upper surface of the substrate; And a fourth step of encapsulating the flip chip bonded semiconductor chip. The method of claim 6, wherein the substrate comprises any one of alumina, ceramic, glass ceramic, polyimide, and printed circuit board (PCB). The method of claim 6, wherein the second process comprises screen printing a conductive material on the upper and lower surfaces of the substrate on which the through-holes are formed to form a plurality of leads on the upper and lower surfaces of the substrate, respectively. Semiconductor package manufacturing method comprising a. The method of claim 6, wherein the second step comprises the steps of: forming a metal thin film on the upper and lower surfaces of the substrate by immersing the substrate on which the through hole is formed in a liquid conductive material; A semiconductor package manufacturing method comprising the step of forming a plurality of independent leads each. The method of claim 6, wherein the first and second leads are formed of the same conductive material. The method of claim 10, wherein the conductive material is formed of any one of tungsten (W), molybdenum-manganese alloy (Mo-Mn), aluminum (Al), copper (Cu), and gold (Au).