CN107256848A - Semiconductor package assembly and a manufacturing method thereof - Google Patents
Semiconductor package assembly and a manufacturing method thereof Download PDFInfo
- Publication number
- CN107256848A CN107256848A CN201710377401.2A CN201710377401A CN107256848A CN 107256848 A CN107256848 A CN 107256848A CN 201710377401 A CN201710377401 A CN 201710377401A CN 107256848 A CN107256848 A CN 107256848A
- Authority
- CN
- China
- Prior art keywords
- semiconductor package
- integrated circuit
- circuit die
- functional surfaces
- carrier plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000004806 packaging method and process Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000009413 insulation Methods 0.000 claims abstract description 11
- 239000011345 viscous material Substances 0.000 claims description 29
- 238000005538 encapsulation Methods 0.000 claims description 18
- 239000000084 colloidal system Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 239000002390 adhesive tape Substances 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000001746 injection moulding Methods 0.000 description 9
- 238000005498 polishing Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000011218 segmentation Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011505 plaster Substances 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention is on semiconductor package assembly and a manufacturing method thereof.Semiconductor package part according to an embodiment of the invention is included：Integrated circuit die and the insulation shell for covering the integrated circuit die.The integrated circuit die has functional surfaces and the pad face relative with the functional surfaces, and the pad face is provided with some pads.Wherein the functional surfaces are both exposed to outside insulation shell with some pads.Semiconductor package assembly and a manufacturing method thereof provided in an embodiment of the present invention, simply high-quality ultra-thin semiconductor packaging part can be obtained by processing procedure compared to prior art, and production cost is low.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to semiconductor package assembly and a manufacturing method thereof.
Background technology
With electronic product small, in the industry to the size requirement of semiconductor package part also more and more thinner, for example, have
The thickness of the semiconductor package part of required by electronic product is even only 0.3+/- 0.03mm.In this case, if still used
Traditional package substrate and the encapsulation mode of injection molding have two kinds of situations:One kind is to use more thin substrate, for example, 0.1mm
The thick substrate injection-moulded housing thick with 0.2mm；It is another, be use thinner injection-moulded housing, for example 0.2mm thick substrates with
Injection-moulded housing thick 0.1mm.And in actual production, both of which haves the shortcomings that certain and inferior position, if using thin
Substrate, then thin substrate process is complex and high cost；On the other hand, as used thin injection-moulded housing, then because needed for injection
Die cap (mold cap) is very thin and causes injection difficult, and overall thickness is difficult control.
To sum up, be adapt to electronic market lightening demand, existing semiconductor packaging still need to constantly improve and
Innovation.
The content of the invention
An object of the present invention is to provide a kind of semiconductor package assembly and a manufacturing method thereof, and it can realize very thin half
Semiconductor package part after conductor packaging part, such as 0.3+/- 0.03mm.
Semiconductor package part according to an embodiment of the invention is included：Integrated circuit die and cover the integrated circuit die
Insulation shell.The integrated circuit die has functional surfaces and the pad face relative with the functional surfaces, if the pad face is provided with
Dry pad.Wherein the functional surfaces are both exposed to outside insulation shell with some pads.
In another embodiment of the invention, the functional surfaces can be a sensing face.The semiconductor package part does not include lead,
Package substrate or lead frame are not included yet.The semiconductor package part can be Background Grid array packages.
One embodiment of the invention additionally provides the manufacture method of semiconductor package part, and it is included：One encapsulating carrier plate is provided；
In setting a viscous material layer on encapsulating carrier plate, the viscous material layer has the encapsulation position for being configured to paste integrated circuit die
Put；The functional surfaces of integrated circuit die or pad face are pasted on package position；Integrated circuit die is carried out plastic packaging to be formed
Cover the plastic packaging colloid of integrated circuit die；And the plastic packaging colloid of polishing is until expose weldering when functional surfaces are pasted on package position
Pad in card, exposes functional surfaces when pad face is pasted on package position.
According to still another embodiment of the invention, the encapsulating carrier plate can be package substrate or metallic plate, the semiconductor packages
The manufacture method of part further comprises planting tin ball on pad.The package position is by the upper surface through encapsulating carrier plate to lower surface
Encapsulation groove define, the viscous material layer is pasted on encapsulation trench bottom.The viscous material layer can be one side glue.And according to the present invention
Another embodiment, the viscous material layer can be the double faced adhesive tape on the surface for being pasted on the encapsulating carrier plate, and the package position is provided
In the Free Surface of viscous material layer, the Free Surface is relative with the surface for being pasted on encapsulating carrier plate.The semiconductor package part
Manufacture method further comprises heating encapsulating carrier plate Free Surface and integrated circuit die and plastic packaging so that the viscous material layer
Colloid is separated.
Semiconductor package assembly and a manufacturing method thereof provided in an embodiment of the present invention, can obtain high-quality compared to prior art
Ultra-thin semiconductor packaging part, and processing procedure is simple, and production cost is low.
Brief description of the drawings
It is the top view of semiconductor package part according to an embodiment of the invention shown in Fig. 1
Fig. 2 is the upward view of semiconductor package part in Fig. 1
Fig. 3 is the side sectional view of semiconductor package part in Fig. 1
It is the schematic flow sheet of the manufacture method of semiconductor package part according to an embodiment of the invention shown in Fig. 4 a-4d
It is the schematic flow sheet of the manufacture method of semiconductor package part according to another embodiment of the present invention shown in Fig. 5 a-5c
Embodiment
Spirit for a better understanding of the present invention, makees furtherly below in conjunction with the part preferred embodiment of the present invention to it
It is bright.
It is the top view of semiconductor package part 100 according to an embodiment of the invention shown in Fig. 1, Fig. 2 is semiconductor in Fig. 1
The upward view of packaging part 100, and Fig. 3 is then the side sectional view of semiconductor package part 100 in Fig. 1.
As Figure 1-3, semiconductor package part 100 according to an embodiment of the invention can be a LGA (Land Grid
Array, Background Grid array packages) packaging part, it includes an at least integrated circuit die 12 and coats the integrated circuit die 12
Insulation shell 14.The integrated circuit die 12 has functional surfaces 120 and the pad face 122 relative with the functional surfaces 120.The function
Face 120 is exposed to the upper surface 140 of insulation shell 14, and has different work(according to the purposes difference of integrated circuit die 12
Can, it can for example be to provide the sensing face of sensing function.Pad face 122 is provided with some pads 124 being arranged in array, if should
Dry pad 124 is exposed to the lower surface 142 of insulation shell 14.Some pads 124 can further be planted upper tin ball (diagram), with
The semiconductor package part 100 is attached on related circuit plate (not shown), so as to realize integrated circuit die 12 and external electrical
Circuit connection configuration between road.Different from traditional semiconductor package part, the semiconductor package part 100 is without any lead, envelope
Substrate or lead frame are filled, the input/output connection of its integrated circuit die 12 can be provided by pad 124.
It can be seen that, semiconductor package part 100 provided in an embodiment of the present invention can be such that functional surfaces 120 are both exposed to pad 124
Outside insulation shell 14, the thickness of whole semiconductor package part 100 is mainly determined by the thickness of integrated circuit die 12, so as to the greatest extent
The thickness of semiconductor package part 100 may be reduced, very thin semiconductor package part 100, for example, 0.3+/- 0.03mm is obtained.
The embodiment of the present invention additionally provides the manufacture method of semiconductor package part 100, and it can manufacture above-mentioned very thin partly lead
Body packaging part 100.According to one embodiment of the invention, the manufacture method of the semiconductor package part 100 mainly includes：One envelope is provided
Loading plate 20；In setting a viscous material layer 24 on encapsulating carrier plate 20, the viscous material layer 24, which has, to be configured to paste integrated
The package position 22 of circuit die 12；One of the functional surfaces 120 of integrated circuit die 12 and pad face 122 are pasted on this
Package position 22；Then the integrated circuit die 12 is carried out plastic packaging to form the plastic packaging colloid of the masking integrated circuit die 12
26；And the plastic packaging colloid 12 of polishing is until expose the pad 124 or functional surfaces 120 of integrated circuit die 12.Specific manufacture
Process can make further demonstration by following different embodiment.
It is the flow signal of the manufacture method of semiconductor package part 100 according to an embodiment of the invention shown in Fig. 4 a-4d
Figure.Understand herein for the sake of, Fig. 4 c and 4d shows semiconductor package part 100 more lesser amount of than Fig. 4 a, 4b.
With reference to Fig. 4 a, the encapsulating carrier plate 20 can be a strip-shaped packaging substrate in the present embodiment, on the encapsulating carrier plate 20
Provided with some package positions 22, each package position 22 through its upper surface 200 to the encapsulation groove of lower surface (not shown) by defining.
These package positions 22 can be into array arrangement.The size for encapsulating groove is suitable or bigger with the integrated circuit die 12 to be encapsulated,
Depth should be less than the thickness of corresponding integrated circuit nude film 12 so that its pad 124 when integrated circuit die 12 is contained in wherein can be convex
Stretch outside encapsulation groove.
As shown in Figure 4 b, the bottom of some encapsulation grooves 22 is covered by viscous material layer 24.For example, in the encapsulating carrier plate
A viscous material layer 24 can be laid in 20 one side, such as lower surface, for example, pastes one layer of adhesive plaster.Specifically, in the present embodiment,
The upper surface 200 of encapsulating carrier plate 20 can be made to be put into upward in laminator (not shown), viscous material layer 24 is pasted by laminator
In the lower surface of encapsulating carrier plate 20, the viscous material layer 24 can be one side glue, so as to subsequently can be directly from being torn on encapsulating carrier plate 20
Under.Viscous material layer 24 exposes its glued portion in encapsulation trench bottom accordingly, so as to provide Pasting integrated circuit die
12 package position.
Hereafter, as illustrated in fig. 4 c, some integrated circuit dies 12 to be packaged are placed respectively according to flag bit (not shown)
Package position 22 in encapsulation groove accordingly, make its functional surfaces 120 for the cementation of viscous material layer 24 and pad face 122 upward
So that pad 124 is convexedly stretched in outside encapsulation groove, it can then carry out the PROCESS FOR TREATMENT of injection molding and be formed and cover the integrated circuit
The insulation shell 14 of the plastic packaging colloid 26 of nude film 12, i.e. single semiconductor package part 100 of later stage.In the encapsulation larger-size feelings of groove
Under condition, it is preferred that the integrated circuit die 12 housed is arranged at the centre position of encapsulation groove.
The technique of the injection molding can be traditional injection molding process, and it can will include some integrated circuit dies 12
Cover the upper surface 200 of whole encapsulating carrier plate 20 inside.As shown in figure 4d, after injection molding terminates, plastic packaging is encapsulated and carried
The plastic packaging colloid 26 of the upper surface 200 of plate 20 carries out polishing until exposing the pad 124 of each integrated circuit die 12, then
It can carry out planting the operation such as tin ball, segmentation, finishing on pad 124 obtaining the semiconductor package part 100 of single.Cohesive material
Layer 24 can be removed when injection is completed or segmentation is repaired, and there is no particular limitation.
It can be seen that, the manufacture method of semiconductor package part 100 according to an embodiment of the invention is without routing, and encapsulating carrier plate
20 are removed after encapsulation terminates, so that the thickness of semiconductor package part 100 is completely by the thickness of integrated circuit die 12
Determine, thus can accomplish very thin.In other embodiments, encapsulating carrier plate 20 can be other materials, for example, gold such as steel plate
Belong to plate, it is not limited to package substrate, so that recycling can be realized.
The manufacture method of semiconductor package part 100 provided in an embodiment of the present invention can also be real by more easy method
It is existing, the Free Surface that integrated circuit die 12 is set directly at viscous material layer 24 (is contacted with encapsulating carrier plate 20
The relative another surface in surface), so as to save the trouble slotted on encapsulating carrier plate 20.
It is that the flow of the manufacture method of semiconductor package part 100 according to another embodiment of the present invention is shown shown in Fig. 5 a-5c
It is intended to.
With reference to Fig. 5 a, the encapsulating carrier plate 20 can be the smooth package substrate or steel plate of a strip in the present embodiment, no
Encapsulation groove 22 with hollow out.The cohesive material of a double faced adhesive tape can be laid in the one side of the encapsulating carrier plate 20, such as upper surface 200
Layer 24.Specifically, in the present embodiment, the upper surface 200 of encapsulating carrier plate 200 can be upward put into laminator (not shown),
Viscous material layer 24 can be pasted onto the upper surface 200 of encapsulating carrier plate 20 by laminator.In the Free Surface of the viscous material layer 24
Some package positions 22 are marked out on 240, four ends angle of a package position 22 can be such as marked with cross.The Free Surface
240 is relative with the face that encapsulating carrier plate 20 is bonded with the viscous material layer 24.
Then, as shown in Figure 5 b, some integrated circuit dies 12 to be packaged can be individually positioned in corresponding encapsulation position
Put 22, and make its functional surfaces 120 be 24 cementations of the viscous material layer, can then carry out injection molding PROCESS FOR TREATMENT and shape
Into the insulation shell 14 for covering the integrated circuit die 12.It is preferred that, the center of integrated circuit die 12 is correspondingly arranged in encapsulation
The centre position of groove 22.
The technique of the injection molding can be traditional injection molding process, and it can will include some integrated circuit dies 12
Cover the upper surface 200 of whole encapsulating carrier plate 20 inside.As shown in Figure 5 c, after injection molding terminates, plastic packaging is encapsulated and carried
The plastic packaging colloid 26 of the upper surface 200 of plate 20 carries out polishing until exposing the pad 124 of each integrated circuit die 12.May be used also
Encapsulating carrier plate 20 is heated so that the Free Surface 240 of viscous material layer 24 can be with each integrated circuit die 12 and plastic packaging colloid
26 separation, and one side can be still bonded on encapsulating carrier plate 20 in addition.Then it can carry out planting tin ball, segmentation, finishing etc. on pad 124
Operation is so as to obtain the semiconductor package part 100 of single.Viscous material layer 24 can completely be gone when injection is completed or segmentation is repaired
Remove, there is no particular limitation.
Although above-described embodiment is only demonstrated is pasted on viscous material layer 24 by the functional surfaces 120 of integrated circuit die 12
On, the situation for the exposed pad 124 of plastic packaging colloid 26 of then polishing.Those skilled in the art are complete based on above-mentioned disclosure and enlightenment
It is appreciated that and grasps in other embodiments entirely, also the pad face 122 of integrated circuit die 12 can be pasted on cohesive material
On layer 24, plastic packaging colloid 26 of then polishing exposes functional surfaces 120.Because concrete technology is similar, here is omitted.
The technology contents and technical characterstic of the present invention have revealed that as above, but those skilled in the art still may base
Make a variety of replacements and modification without departing substantially from spirit of the present invention in teachings of the present invention and announcement.Therefore, protection model of the invention
The content disclosed in embodiment should be not limited to by enclosing, and should include various replacements and modification without departing substantially from the present invention, and be this patent
Application claims are covered.
Claims (12)
1. a kind of semiconductor package part, it is included：
Integrated circuit die, has：
Functional surfaces；And
Pad face, it is relative with the functional surfaces, and the pad face is provided with some pads；And
Insulation shell, covers the integrated circuit die；Wherein described functional surfaces are both exposed to described exhausted with some pads
Outside edge housing.
2. semiconductor package part as claimed in claim 1, wherein the functional surfaces are a sensing face.
3. semiconductor package part as claimed in claim 1, wherein the semiconductor package part does not include lead.
4. semiconductor package part as claimed in claim 1, wherein the semiconductor package part does not include package substrate or lead
Framework.
5. semiconductor package part as claimed in claim 1, wherein the semiconductor package part is Background Grid array packages.
6. a kind of manufacture method of semiconductor package part, it is included：
One encapsulating carrier plate is provided；
In setting a viscous material layer on the encapsulating carrier plate, the viscous material layer, which has, to be configured to paste integrated circuit die
Package position；The integrated circuit die has functional surfaces and the pad face relative with the functional surfaces；
One in the functional surfaces of the integrated circuit die and pad face is pasted on the package position；
Plastic packaging is carried out to the integrated circuit die and covers the plastic packaging colloid of the integrated circuit die to be formed；And
Polish the plastic packaging colloid until：Expose the weldering on the pad face when the functional surfaces are pasted on the package position
Disk；Expose the functional surfaces when the pad face is pasted on the package position.
7. manufacture method as claimed in claim 6, wherein the encapsulating carrier plate is package substrate or metallic plate.
8. manufacture method as claimed in claim 6, wherein the package position by the upper surface through the encapsulating carrier plate extremely
The encapsulation groove of lower surface is defined, and the viscous material layer is pasted on the encapsulation trench bottom.
9. manufacture method as claimed in claim 8, wherein the viscous material layer is one side glue.
10. manufacture method as claimed in claim 6, wherein the viscous material layer is the table for being pasted on the encapsulating carrier plate
The double faced adhesive tape in face, the package position is provided in the Free Surface of the viscous material layer, and the Free Surface is pasted with described
It is relative in the surface of the encapsulating carrier plate.
11. manufacture method as claimed in claim 10, it further comprises heating the encapsulating carrier plate so that the sticky material
The Free Surface of the bed of material is separated with the integrated circuit die and the plastic packaging colloid.
12. manufacture method as claimed in claim 6, it further comprises planting tin ball on the pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710377401.2A CN107256848A (en) | 2017-05-25 | 2017-05-25 | Semiconductor package assembly and a manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710377401.2A CN107256848A (en) | 2017-05-25 | 2017-05-25 | Semiconductor package assembly and a manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107256848A true CN107256848A (en) | 2017-10-17 |
Family
ID=60027384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710377401.2A Pending CN107256848A (en) | 2017-05-25 | 2017-05-25 | Semiconductor package assembly and a manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107256848A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1535479A (en) * | 2000-08-16 | 2004-10-06 | ض� | Direct build-up layer on encapsulated die package |
| JP2009252859A (en) * | 2008-04-03 | 2009-10-29 | Shinko Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| CN102074514A (en) * | 2009-11-23 | 2011-05-25 | 三星半导体(中国)研究开发有限公司 | Encapsulation element and manufacturing method thereof |
| US20130175686A1 (en) * | 2012-01-10 | 2013-07-11 | Intel Mobile Communications GmbH | Enhanced Flip Chip Package |
| US20140357020A1 (en) * | 2013-06-03 | 2014-12-04 | Aleksandar Aleksov | Methods for high precision microelectronic die integration |
| US20160211214A1 (en) * | 2015-01-20 | 2016-07-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Power amplifier package and method thereof |
| CN105957836A (en) * | 2016-06-01 | 2016-09-21 | 格科微电子（上海）有限公司 | Fan-out type wafer-level packaging method for semiconductor device |
| CN206864454U (en) * | 2017-05-25 | 2018-01-09 | 日月光封装测试(上海)有限公司 | Semiconductor package part |
-
2017
- 2017-05-25 CN CN201710377401.2A patent/CN107256848A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1535479A (en) * | 2000-08-16 | 2004-10-06 | ض� | Direct build-up layer on encapsulated die package |
| JP2009252859A (en) * | 2008-04-03 | 2009-10-29 | Shinko Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| CN102074514A (en) * | 2009-11-23 | 2011-05-25 | 三星半导体(中国)研究开发有限公司 | Encapsulation element and manufacturing method thereof |
| US20130175686A1 (en) * | 2012-01-10 | 2013-07-11 | Intel Mobile Communications GmbH | Enhanced Flip Chip Package |
| US20140357020A1 (en) * | 2013-06-03 | 2014-12-04 | Aleksandar Aleksov | Methods for high precision microelectronic die integration |
| US20160211214A1 (en) * | 2015-01-20 | 2016-07-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Power amplifier package and method thereof |
| CN105957836A (en) * | 2016-06-01 | 2016-09-21 | 格科微电子（上海）有限公司 | Fan-out type wafer-level packaging method for semiconductor device |
| CN206864454U (en) * | 2017-05-25 | 2018-01-09 | 日月光封装测试(上海)有限公司 | Semiconductor package part |
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Effective date of registration: 20201229 Address after: No. 669, GuoShouJing Road, Pudong New Area pilot Free Trade Zone, Shanghai, 201203 Applicant after: Rirong semiconductor (Shanghai) Co.,Ltd. Address before: 6th floor, no.669 GuoShouJing Road, Pudong New Area pilot Free Trade Zone, Shanghai 201203 Applicant before: ASE ASSEMBLY & TEST (SHANGHAI) Ltd. |