CN105895540A - Die back surface silicone printing encapsulation method - Google Patents

Die back surface silicone printing encapsulation method Download PDF

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Publication number
CN105895540A
CN105895540A CN201510015031.9A CN201510015031A CN105895540A CN 105895540 A CN105895540 A CN 105895540A CN 201510015031 A CN201510015031 A CN 201510015031A CN 105895540 A CN105895540 A CN 105895540A
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China
Prior art keywords
wafer
die
full
cutting
glue
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CN201510015031.9A
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Chinese (zh)
Inventor
凡会建
李文化
彭志文
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Te Ke Core Co Ltd
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Te Ke Core Co Ltd
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Priority to CN201510015031.9A priority Critical patent/CN105895540A/en
Publication of CN105895540A publication Critical patent/CN105895540A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a die back surface silicone printing encapsulation method, which adopts a die, a silicone layer and a substrate, and is used for carrying out thinning, silicone brushing, blue film adhering, cutting, die attaching and baking processes on the whole die. The die back surface silicone printing encapsulation method comprises the steps of thinning the back surface of the die, brushing the silicone on the back surface of the die, adhering the blue film on the back surface of the die, cutting the die, attaching the die and baking. The die back surface silicone printing encapsulation method is characterized in that: the die which is subjected to silicone brushing and blue film adhering on the back surface is cut into single die particles, the dependence of the die on the DAF film is changed, and direct material cost of die bonding is greatly reduced; and silicone layer cavities formed by uneven silicone dispersing process are avoided, reliability of the encapsulation technology is improved, and chip flatness after die bonding is increased, thereby being conductive to stabilizing a wire bonding process, reducing cost without increasing complexity of the processes, and improving bonding quality of the die and the substrate.

Description

The method for packing of wafer rear print glue
Technical field
The present invention relates to integrated antenna package technical field, particularly disclose the method for packing of wafer rear print glue.
Background technology
Currently, in integrated antenna package, conventional IC, i.e. integrated circuit are to use semiconductor fabrication process, at one piece of less list Many transistors and the components and parts such as resistor, capacitor, and the method connected up according to multilayer wiring or tunnel is made on crystal silicon chip, Components and parts are combined into complete electronic circuit.Due to the difference of technique, the mode of integrated antenna package also has a variety of, wherein Bonding method used by die bond technique in packaging technology includes two kinds: a kind of technique is the DAF film (Die utilizing wafer rear to paste Attach Film), heated by DAF film, make wafer and base plate bonding (as shown in Figure 1), wafer is fixed on substrate; And another kind technique is to use glue, usually elargol or red glue first to put glue on substrate, namely glue, it is common that add The white glue of silver particles or the red glue without silver ion, squeeze on substrate by sebific duct, the most again by wafer (die) Press on glue-line, allow wafer (die) and substrate combine (as shown in Figure 2).Wherein, DAF used in the first technique Film is expensive because of complex manufacturing technology and raw material, holds at high price.Gluing process used in the second technique is it cannot be guaranteed that glue Layer uniformly easily produces cavity, and particularly with big chip, the probability that cavity produces is higher, and cyst areas is bigger, to follow-up Processing procedure interfere, cause great risk to the stay in grade system of product, so needing to be weeded out the old and bring forth the new.
Summary of the invention
Expensive in order to solve complex manufacturing technology and raw material in prior art, the problem held at high price, the invention discloses One reduces material cost and overcomes problem produced by a glue, by the back side brush silica gel at wafer so that it is be combined with substrate The method for packing of close a kind of wafer rear print glue.
The invention discloses the method for packing of wafer rear print glue, including wafer, glue-line and substrate, described wafer is full wafer wafer, Described glue-line is layer of silica gel, described full wafer wafer is performed reduction process, brush coating technique, the blue membrane process of patch, cutting technique, on Blade technolgy, baking process, comprising:
Step one, reduction process: thinning back side of silicon wafer, by wafer rear upward, with emery wheel wafer is carried out polishing, thinning, Full wafer wafer after thinning is placed on ceramic vacuum absorption platform;
Step 2, brush coating technique: wafer rear brush silica gel, by silk screen steel plate cover at the back side of full wafer wafer, silk screen steel plate and Full wafer wafer carries out para-position placement, coats silica gel on silk screen steel plate, prints to whole with scraper uniformly by the silica gel on silk screen steel plate The wafer back side;
The blue membrane process of step 3, patch: the blue film of wafer rear patch, the wafer paster processing procedure being packaged in technique, at full wafer wafer Above the silica gel at the back side, patch adds blue film, is attached on iron hoop at its edge;
Step 4, cutting technique: wafer cuts, cut full wafer wafer together with the pellosil covering its back side is placed on cutting machine Cutting, become single the wafer granule being backed with pellosil after cutting, the back side of single wafer granule is formed for one layer of uniform silica gel Film;
Step 5, upper blade technolgy: single wafer granule of well cutting by die bond technique, be fixed on substrate;
Step 6, baking process: make to solidify further between single wafer granule and substrate.
Limit ground further as the present invention, reduction process can be used wafer stripping apparatus, the function of wire mark can be attached to pad pasting mould It is automatically performed inside block.
Limit ground further as the present invention, described silk screen steel plate is provided with the rectangle opening of multiple homalographic.
Limit ground further as the present invention, described blue film is that wafer cuts film.
Limit ground further as the present invention, described blue film is more than single wafer area.
Limit ground further as the present invention, described thinning and pad pasting can be used wafer stripping apparatus, can the function of wire mark be attached to It is automatically performed inside pad pasting module.
Limit ground further as the present invention, described iron hoop is when cutting, fixes the chase of single wafer for supporting blue film.
Compared with prior art, the medicine have the advantages that the method is passed through at full wafer wafer rear by silk screen web plate brush silica gel, Stick on blue film again and be cut into single wafer granule, thus change the wafer dependence to DAF film, reduce the direct material of die bond greatly Material cost;Also avoid the glue-line cavity that problem of non-uniform in gluing process causes, that improves integrated antenna package packaging technology can By property, after the most also improving die bond, chip flatness is beneficial to stablizing of bonding wire processing procedure, in the case of not increasing complex process, and fall Low cost, improves chip and substrate combines quality.
Accompanying drawing explanation
Fig. 1 and Fig. 2 is existing wafer packaging method schematic diagram.
Fig. 3 is the step block diagram of the method for packing of wafer rear print glue in the present invention.
Fig. 4 is method for packing step one schematic diagram of wafer rear print glue in the present invention.
Fig. 5 is the method for packing step 2 schematic diagram of wafer rear print glue in the present invention.
Fig. 6 is the method for packing step 3 schematic diagram of wafer rear print glue in the present invention.
Fig. 7 is the method for packing step 4 schematic diagram of wafer rear print glue in the present invention.
Fig. 8 is the method for packing step 5 schematic diagram of wafer rear print glue in the present invention.
Fig. 9 is the method for packing step 6 schematic diagram of wafer rear print glue in the present invention.
In figure, full wafer wafer 1, single wafer 11, silica gel 2, blue film 3, silk screen steel plate 4, rectangle opening 41, after cutting Wafer 5, substrate 6, sucker 7, emery wheel 8.
Detailed description of the invention
The present invention will be further described below in conjunction with the accompanying drawings, it will be appreciated that specific embodiment described herein is only used for explaining The present invention, is not intended to limit the present invention.
As depicted in figs. 1 and 2, existing wafer is in the method for integrated antenna package, including two kinds of conventional processes, The first technique: wafer is pasted by DAF film, because complex manufacturing technology and raw material are expensive, holds at high price;And second Planting technique, wafer is pasted by gluing process, because of gluing process it cannot be guaranteed that glue-line is uniform, easily produces cavity, particularly with Big chip, the probability that cavity produces is higher, and cyst areas is bigger, interferes to follow-up processing procedure, to the quality of product Stability series cause great risk.
As shown in Fig. 3 to Fig. 7, the method for packing of wafer rear disclosed by the invention print glue, including the wafer 1 for encapsulation, Glue-line and substrate 6, described wafer is full wafer wafer, and namely the wafer without processing is overall, and described glue-line is silica gel 2, this Sample arranges and is because silica gel is a kind of epoxy resin, and low price, after heating, bond effect is good, without cavity.Brilliant to described full wafer Circle 1 execution reduction process, brush coating technique, the blue membrane process of patch, cutting technique, upper blade technolgy, baking process, comprising:
Step S200, reduction process: thinning back side of silicon wafer: by full wafer wafer 1 back side upward, with 8 full wafer wafers 1 of emery wheel Carry out polishing, thinning, be placed on ceramic vacuum absorption platform;
Above-mentioned steps S200, as shown in Figure 4 and Figure 5, described thinning after full wafer wafer be that packaging technology is ground to required thickness The full wafer wafer 1 of degree.The described wafer 1 silicon used by silicon semiconductor production of integrated circuits, owing to it is generally circular in shape. And wafer 1 is the carrier producing used in integrated circuits, it is mostly monocrystal silicon circle.At chip wafer 1, its conventional diameter divides It is 4 inches, 5 inches, 6 inches, 8 inches of equal-specifications, also includes that bigger specification such as 12 inch is with first-class.Wafer is the biggest, On same disk, producible integrated circuit is the most, it is possible to decrease cost;Step S201, brush coating technique: wafer 1 back side brush silicon Glue: silk screen steel plate 4 is covered the upper surface at full wafer wafer 1, silk screen steel plate 41 and full wafer wafer 4 and carries out para-position placement, Coat silica gel on silk screen steel plate 4, with scraper, the silica gel on silk screen steel plate printed to uniformly full wafer wafer 1 back side.
Above-mentioned steps S201, as shown in Figure 6, the silica gel on described silk screen steel plate includes the NC7720M, Henkel of Yiztech 6202C, described silk screen steel plate 4 is provided with the rectangle opening 41 of multiple homalographic, so arranges, it is simple in rectangle opening It is uniformly coated with silica gel;It addition, at present, most companies are thinning and pad pasting is equipment integrally, and it is wafer stripping apparatus, its Including the all-in-one that the DFG8761 (wafer is thinning) and DFM2800 (wafer pad pasting) of disco form, DFG8560 is (brilliant Unit is thinning) and the all-in-one that forms of LTD2500 (wafer pad pasting), the thinning pad pasting all-in-one of Tokyo precision: PG300RM, PG200RM, PG300RM etc., the function of wire mark can be attached to inside pad pasting module by it, and the function of wire mark can be attached to patch It is automatically performed inside film module.
The blue membrane process of step S202, patch: the blue film of wafer rear patch, the wafer paster processing procedure being packaged in technique, at wafer core Stick blue film 3 above the silica gel 2 at sheet 1 back side, its edge is attached on iron hoop;
Above-mentioned steps S202, as it is shown in fig. 7, the one that described blue film 3 is semiconducting binder thing, it is wafer cutting film, its For a kind of adhesive tape, wafer cutting and upper slice during, play carrying transmitting effect, it include many days enterprise and Korea Spro's film of looking forward to producing The D-175 of Lintec, D-176 etc.;And described blue film is more than wafer area, described iron hoop be when cutting, is used for supporting indigo plant film The chase of fixing chip wafer;
Step S203, cutting technique: wafer cuts, and is placed on cutting machine and is cut together with silica gel by chip wafer, becomes after cutting Being backed with single wafer of pellosil, single wafer rear is formed for one layer of uniform pellosil;
Step S204, upper blade technolgy: single wafer by die bond technique, be fixed on substrate;
Step S205, baking process: make to solidify further between single wafer granule and substrate.
Above-mentioned steps S205, as it is shown in figure 9, when die bond operation, single wafer (die) 11 reaches well to paste with substrate 6 Close effect, by the load process of die bond, the silica gel of single wafer rear is bonded in the appointment region of substrate.
Present invention wafer rear print glue replaces the DAF film in existing die bond technique and some glue, and the present invention is in specifically used process In, design according to wafer level packaging, the thickness of required layer of silica gel, with the silk screen steel plate of respective thickness, layer of silica gel is printed uniformly At the back side of full wafer wafer, then stick on blueing film, the layer of silica gel at full wafer wafer and the back side thereof is cut together with blue film, cuts into Single wafer granule so that the back side of single wafer granule forms one layer of glued membrane being made up of uniformly silica gel, so makees in die bond During industry so that the sucker of single wafer and substrate reaches well to fit effect.
In sum, the method for packing of the wafer rear of present invention print glue, 1, by wafer rear by silk screen web plate brush silicon Glue, then stick on blue film cutting single wafer of formation, change the ultra-thin wafers dependence to DAF film, reduce die bond greatly direct Material cost;2, avoid the glue-line cavity that in gluing process, problem of non-uniform causes, improve the reliable of technique of integrated circuit packaging Property, 3, simultaneously, after also improving die bond, wafer flatness, beneficially bonding wire processing procedure stablizes, in the feelings not increasing complex process Under condition, reduce cost, improve wafer and substrate combines quality.It is pointed out that above-mentioned better embodiment only illustrates this The technology design of invention and feature, its object is to allow person skilled in the art will appreciate that present disclosure reality according to this Execute, can not limit the scope of the invention with this.All Significant Changes made according to spirit of the invention or modification, all Should contain within protection scope of the present invention.

Claims (7)

1. the method for packing of wafer rear print glue, including wafer, glue-line and substrate, it is characterised in that: described wafer is that full wafer is brilliant Circle, described glue-line is layer of silica gel, described full wafer wafer is performed reduction process, brush coating technique, the blue membrane process of patch, cutting technique, Upper blade technolgy, baking process, comprising:
Step one, reduction process: thinning back side of silicon wafer, by wafer rear upward, with emery wheel wafer is carried out polishing, thinning, Full wafer wafer after thinning is placed on ceramic vacuum absorption platform;
Step 2, brush coating technique: wafer rear brush silica gel, cover silk screen steel plate at the back side of full wafer wafer, silk screen steel plate Carry out para-position placement with full wafer wafer, silica gel coated by silk screen steel plate, with cutter, the silica gel on silk screen steel plate is printed uniformly Glued membrane is formed to full wafer wafer rear;
The blue membrane process of step 3, patch: the blue film of wafer rear patch, patch adds blue film on the silica gel of full wafer wafer rear, by it Edge is attached on iron hoop;
Step 4, cutting technique: wafer cuts, by full wafer wafer together with the pellosil covering its back side is placed on cutting machine Cutting, becomes single the wafer being backed with pellosil after cutting, the back side of single wafer is formed for one layer of uniform pellosil;
Step 5, upper blade technolgy: single wafer of well cutting by die bond technique, be fixed on substrate;
Step 6, baking process: make to solidify further between single wafer granule and substrate.
Wafer rear the most according to claim 1 print glue method for packing, it is characterised in that: described thinning after full wafer Wafer is the full wafer wafer being ground to desired thickness in packaging technology.
The method for packing of wafer rear the most according to claim 1 print glue, it is characterised in that: set on described silk screen steel plate There is the rectangle opening of multiple homalographic.
The method for packing of wafer rear the most according to claim 1 print glue, it is characterised in that: described blue film is that wafer is cut Cut film.
The method for packing of wafer rear the most according to claim 1 print glue, it is characterised in that: described blue film is more than wafer Area.
The method for packing of wafer rear the most according to claim 1 print glue, it is characterised in that: described reduction process can be used Wafer stripping apparatus, can be attached to the function of wire mark inside pad pasting module be automatically performed.
The method for packing of wafer rear the most according to claim 1 print glue, it is characterised in that: described iron hoop is in cutting Time, the chase of single wafer is fixed for supporting blue film.
CN201510015031.9A 2015-01-09 2015-01-09 Die back surface silicone printing encapsulation method Pending CN105895540A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107393840A (en) * 2017-06-15 2017-11-24 江苏长电科技股份有限公司 A kind of cutting method of ceramic substrate encapsulation
CN108767101A (en) * 2018-05-25 2018-11-06 苏州市汇涌进光电有限公司 A kind of LED die-bonding methods
CN108767089A (en) * 2018-05-22 2018-11-06 江苏欧密格光电科技股份有限公司 A kind of LED chip adhesion technique
CN109920752A (en) * 2019-02-28 2019-06-21 厦门信达光电物联科技研究院有限公司 A kind of cutting technique
CN111524815A (en) * 2020-03-26 2020-08-11 江苏长电科技股份有限公司 Glue brushing process method for semiconductor wafer
CN112018272A (en) * 2020-09-10 2020-12-01 紫旸升光电科技(苏州)有限公司 Wafer laminating and packaging method of silicon-based OLED
CN113035720A (en) * 2021-03-01 2021-06-25 紫光宏茂微电子(上海)有限公司 Chip mounting method
WO2021185002A1 (en) * 2020-03-19 2021-09-23 深圳纽迪瑞科技开发有限公司 Preparation method for strain sensitive film, strain sensitive film, and pressure sensor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184872A (en) * 2011-04-08 2011-09-14 嘉盛半导体(苏州)有限公司 Semiconductor packaging bonding process
CN102842511A (en) * 2012-08-20 2012-12-26 上海凯虹科技电子有限公司 Chip packaging method and wafer manufactured through chip packaging method
CN202855801U (en) * 2012-06-08 2013-04-03 杨勇平 Eutectic substrate
CN104157775A (en) * 2014-06-17 2014-11-19 京东方光科技有限公司 LED lighting device and packaging method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184872A (en) * 2011-04-08 2011-09-14 嘉盛半导体(苏州)有限公司 Semiconductor packaging bonding process
CN202855801U (en) * 2012-06-08 2013-04-03 杨勇平 Eutectic substrate
CN102842511A (en) * 2012-08-20 2012-12-26 上海凯虹科技电子有限公司 Chip packaging method and wafer manufactured through chip packaging method
CN104157775A (en) * 2014-06-17 2014-11-19 京东方光科技有限公司 LED lighting device and packaging method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107393840A (en) * 2017-06-15 2017-11-24 江苏长电科技股份有限公司 A kind of cutting method of ceramic substrate encapsulation
CN108767089A (en) * 2018-05-22 2018-11-06 江苏欧密格光电科技股份有限公司 A kind of LED chip adhesion technique
CN108767101A (en) * 2018-05-25 2018-11-06 苏州市汇涌进光电有限公司 A kind of LED die-bonding methods
CN109920752A (en) * 2019-02-28 2019-06-21 厦门信达光电物联科技研究院有限公司 A kind of cutting technique
WO2021185002A1 (en) * 2020-03-19 2021-09-23 深圳纽迪瑞科技开发有限公司 Preparation method for strain sensitive film, strain sensitive film, and pressure sensor
CN111524815A (en) * 2020-03-26 2020-08-11 江苏长电科技股份有限公司 Glue brushing process method for semiconductor wafer
CN111524815B (en) * 2020-03-26 2023-08-18 江苏长电科技股份有限公司 Glue brushing process method for semiconductor wafer
CN112018272A (en) * 2020-09-10 2020-12-01 紫旸升光电科技(苏州)有限公司 Wafer laminating and packaging method of silicon-based OLED
CN113035720A (en) * 2021-03-01 2021-06-25 紫光宏茂微电子(上海)有限公司 Chip mounting method

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