WO2014063281A1

WO2014063281A1 - Semiconductor device including stacked bumps for emi/rfi shielding

Info

Publication number: WO2014063281A1
Application number: PCT/CN2012/083297
Authority: WO
Inventors: Fuqiang Xiao; Zhong Lu; Peng FU; Enyong Tai; Chin Tien Chiu; Cheeman Yu
Original assignee: Sandisk Information Technology (Shanghai) Co., Ltd.
Priority date: 2012-10-22
Filing date: 2012-10-22
Publication date: 2014-05-01

Abstract

The present disclosure relates to a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device comprises: a substrate, a semiconductor die disposed above the substrate, and a bonding member. The substrate further comprises a bonding finger. The semiconductor die further comprises a first and an adjacent second bonding pads. The bonding member further comprises a single bonding wire having a ball disposed on a first end that electrically connects the first bonding pad and the second bonding pad and an opposite second end bonded directly on the bonding finger.

Description

SEMICONDUCTOR DEVICE INCLUDING

STACKED BUMPS FOR EMI/RFI SHIELDING

BACKGROUND

[0001] The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.

[0002] While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate in a stacked configuration. An edge view of a conventional semiconductor package 20 (without molding compound) is shown in prior art Figs. 1 and 2. Typical packages include a plurality of semiconductor die 22, 24 mounted to a substrate 26. Although not shown in Figs. 1 and 2, the semiconductor die are formed with die bond pads on an upper surface of the die. Substrate 26 may be formed of an electrically insulating core sandwiched between upper and lower conductive layers. The upper and/or lower conductive layers may be etched to form conductance patterns including electrical leads and contact pads. Wire bonds 30 are soldered between the die bond pads of the semiconductor die 22, 24 and the contact pads of the substrate 26 to electrically connect the semiconductor die to the substrate. The electrical leads on the substrate in turn provide an electrical path between the die and a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.

[0003] It is known to layer semiconductor die on top of each other either with an offset (prior art Fig. 1) or in a stacked configuration (prior art Fig. 2). In the offset configuration of Fig. 1, the die are stacked with an offset so that the bond pads of the next lower die are left exposed. In the stacked configuration of Fig. 2, two or more semiconductor die are stacked directly on top of each other, thereby taking up less footprint on the substrate as compared to an offset configuration. However, in a stacked configuration, space must be provided between adjacent semiconductor die for the bond wires 30. In addition to the height of the bond wires 30 themselves, additional space must be left above the bond wires, as contact of the bond wires 30 of one die with the next die above may result in an electrical short. As shown in Fig. 2, it is therefore known to provide a dielectric spacer layer 34 to provide enough room for the bond wires 30 to be bonded to the die bond pad on the lower die 24.

[0004] As electronic components get smaller and operate at higher frequencies, the noise and cross talk caused by electromagnetic interference (EMI) and radiofrequency interference (RFI) is becoming more of a concern. EMI is the induction of electromagnetic radiation, which is emitted by electrical circuits carrying rapidly changing signals, as a by-product of their normal operation, which causes unwanted signals (interference or noise). RFI is transmission of radiofrequency electromagnetic radiation from one circuit to another, also causing unwanted interference or noise.

[0005] Some semiconductor packages have attempted to shield the transmission and receipt of EMI and RFI radiation at the semiconductor package level. While preventing interference, these conventional solutions have other disadvantages which have made inclusion of such features at the package level undesirable. Thus, shielding is typically performed at the host device level in which a semiconductor package is used. Host device level solutions typically involve providing a metal shield around the space where a semiconductor package is received or mounted. Instead of shielding, it is also known to absorb EMI and RFI. However, conventional absorptive solutions have not satisfactorily addressed EMI and/or RFI in a semiconductor package..

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIGURES 1 and 2 are prior art edge views of two conventional semiconductor package designs with the molding compound omitted.

[0007] FIGURE 3 is a flowchart showing the assembly of a semiconductor device according to the present disclosure.

[0008] FIGURE 4 is a top view of a substrate according to an embodiment of the present disclosure.

[0009] FIGURE 5 is an edge view of a substrate including semiconductor die wire bonded to the substrate according to an embodiment of the present disclosure. [0010] FIGURE 6 is a top view of a substrate including semiconductor die wire bonded to the substrate according to an embodiment of the present disclosure.

[0011] FIGURE 7 is an enlarged, simplified perspective view of a substrate including semiconductor die wire bonded to the substrate according to an embodiment of the present disclosure.

[0012] FIGURE 8 is an enlarged, simplified perspective view as in Fig. 7 and further including bumps on a wire bond according to an embodiment of the present disclosure.

[0013] FIGURES 8A and 8B are enlarged, simplified perspective views of alternative embodiments to that shown in Fig. 8. [0014] FIGURE 9 is an edge view of a panel of semiconductor devices on an upper mold plate and a shielding material on a lower mold plate prior to encapsulating the memory devices.

[0015] FIGURE 10 is an edge view as in Fig. 9, further including molding compound in the lower mold plate.

[0016] FIGURE 11 illustrates the edge view of the mold plates and molding compound of Fig. 10, with the memory devices immersed in the molding compound.

[0017] FIGURE 12 is an edge view of the upper and lower mold plates and the memory devices in the molding compound after curing of the molding compound.

[0018] FIGURE 13 is a top view of an embodiment having a meshed shielding layer formed on the molding compound. [0019] FIGURE 14 is a finished memory device according to embodiments of the present disclosure.

[0020] FIGURE 15 illustrates an alternative embodiment where a shielding and/or absorption layer is formed on the molding compound after encapsulation.

DETAILED DESCRIPTION [0021] Embodiments will now be described with reference to Figs. 3 through 15, which relate to a semiconductor device including EMI shielding. While embodiments may be described with reference to EMI shielding, it is understood that embodiments may further protect the semiconductor device by providing EMI absorption, RFI shielding and/or RFI absorption. It is understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be clear to those of ordinary skill in the art that the present invention may be practiced without such specific details.

[0022] The terms "top" and "bottom," "upper" and "lower" and "vertical" and "horizontal" as may be used herein are for convenience and illustrative purposes only, and are not meant to limit the description of the invention inasmuch as the referenced item can be exchanged in position.

[0023] An embodiment of the present technology will now be explained with reference to the flowchart of Fig. 3, and the top, edge and perspective views of Figs. 4 through 15. Fig. 4 is a top view of a substrate panel 201 including a plurality of substrates 202. Panel 201 allows batch processing of substrates 202 into a number of semiconductor devices 200 at the same time to achieve economies of scale. The number of rows and columns of substrates 202 on the substrate panel 201 is shown by way of example only and the number of rows and/or columns of substrates 202 may vary in further embodiments.

[0024] The substrates 202 on panel 201 may be a variety of different chip carrier mediums, including a printed circuit board (PCB), a leadframe or a tape automated bonded (TAB) tape. Where substrate 202 is a PCB, the substrate may be formed of various conductive layers 204, each separated by a dielectric core 203, as shown in the edge view of Fig. 5. Fig. 5 shows a single core 203 surrounded by a pair of conductive layers 204 for simplicity, but the substrate 202 may include a number of conductive layers separated by a number of dielectric cores in further embodiments.

[0025] The core 203 may be formed of various dielectric materials such as for example, polyimide laminates, epoxy resins including FR4 and FR5, bismaleimide triazine (BT), and the like. Although not critical to the present invention, the core may have a thickness of between 40 microns (μιη) to 200 μπι, although the thickness of the core may vary outside of that range in alternative embodiments. The core may be ceramic or organic in alternative embodiments. As explained below, an EMI/RFI absorber may be added or otherwise included as part of core 203.

[0026] The conductive layers 204 surrounding the core 203 may be formed of copper or copper alloys, plated copper or plated copper alloys, copper plated steel, or other metals and materials known for use on substrate panels. The conductive layers may have a thickness of about 10 μπι to 25 μπι, although the thickness of the conductive layers may vary outside of that range in alternative embodiments.

[0027] In a step 100, the substrate 202 may be drilled to define through-hole vias 205 in the substrate 202. The vias 205 (some of which are numbered in the figures) are provided to communicate signals between different conductive layers of the substrate 202. The number and positions of vias 205 shown are by way of example, and the substrate may include many more vias 205 than are shown in the figures, and they may be in different locations than are shown in the figures.

[0028] Conductance patterns may next be formed in one or more of the conductive layers 204 provided on the core(s) 203 in step 104. The conductance pattern in the top and bottom conductive layers 204 may be formed by various methods including for example by silk screening and by photolithography. An example of a conductance pattern is partially shown in the top layer in Fig. 6.

[0029] The conductance pattern(s) in the layers 204 may include electrical traces 206and contact pads 208 (some of which are numbered in the figures). The electrical traces 206 and contact pads 208 visible in Fig. 6 are by way of example, and the substrate 202 may include more traces and/or contact pads than are shown in the figures, and they may be in different arrangements than are shown in the figures. Other structures may be provided in the conductance pattern such as for example test pins for testing the operation of the semiconductor device 200.

[0030] Referring again to Fig. 3, the substrate 202 may next be inspected in an automatic optical inspection (AOI) in step 108. Once inspected, a solder mask layer 210 may be applied to the upper and/or lower surfaces of the substrate 202 in step 112. The solder mask layer may serve multiple functions. In one example, the solder mask layer(s) are formed of a polymer that provides a protective coating for the copper traces of the conductance pattern and prevents solder from bleeding beyond the exposed contact pads and test pins during solder attachment of components, thereby preventing short circuits.

[0031] In further embodiments, the solder mask layer 210 may additionally be impregnated with an EMI/RFI absorber for absorbing EMI and RFI radiating within the semiconductor device 200 and radiating onto the semiconductor device 200 from external sources. Examples of such an EMI/RFI absorber in solder mask layer 210 are disclosed in PCT Application No. PCT/CN2012/074737, entitled, "Semiconductor Device Including Electromagnetic Absorption and Shielding," filed May 10, 2012, which application is incorporated herein by reference in its entirety.

[0032] After formation of the solder mask layer 210, the exposed portions of the conductance pattern (including for example contact pads 208) on the top layer and bottom layer may be plated with a Ni/Au layer or the like in step 114 in a known electrolytic plating, electro-less or thin film deposition process.

[0033] In step 116, the substrate 202 may be inspected and tested in an automated inspection process, and in step 120, the substrate may undergo a final visual inspection, to check electrical operation, and for contamination, scratches and discoloration.

[0034] Assuming the substrate 202 passes inspection, one or more semiconductor die 224, 225 may next be affixed to the top surface of the substrate 202 in a step 122 as shown in the edge and top views of Figs. 5 and 6. In the illustrated example, the semiconductor device 200 includes a pair of memory die 224 and a controller die 225. The memory die 224 may for example be flash memory chips (NOR/NAND), though other types of memory die are contemplated. It is understood that a single memory die 224 may be provided and that more than two memory die may be provided. The controller die 225 may for example be an ASIC.

[0035] The one or more semiconductor die 224, 225 may then be wire bonded to the substrate 202 in a step 124. The wire bonds 226may be connected between die bond pads 230 on the die 224, 225and the contact pads 208 on the substrate 202. Only some of the die bond pads 230 and wire bonds 226 are shown and labeled. While the die bond pads 230 are shown along a single side of the die 224, 225 in the figures, it is understood that the die bond pads 230 and wire bonds 226 may be off multiple sides of the die 224, 225 to contact pads 208 adjacent multiple edges of the substrate 202.

[0036] Referring to the enlarged perspective view of Fig. 7, in one embodiment, the wire bonds 226 may be formed in step 124 as reverse ball bonds. These may be fashioned by first depositing a ball bond 232 on die bond pads of a die, such as bottom die 224, using a wire bonding capillary of known construction (not shown). The ball bonds 232 (one of which is numbered in Fig. 7) may be formed by feeding a length of wire (typically gold or silver alloy) through a central cavity of the wire bonding capillary. The wire protrudes through a tip of the capillary, where a high-voltage electric charge is applied to the wire from a transducer associated with the capillary tip. The electric charge melts the wire at the tip and the wire forms into a ball 232 owing to the surface tension of the molten metal.

[0037] As the ball solidifies, the capillary is lowered to the surface of the die bond pad 230. The surface of die bond pad 230 may be heated to facilitate a better bond. The ball bond 232 is deposited on the die bond pad 230 under a load, while the transducer applies ultrasonic energy. The combined heat, pressure, and ultrasonic energy create a bond between the ball bond 232 and the die bond pad 230. The wire bonding capillary may then pay out a small length of wire, and the wire may be severed at the conductive ball to leave the ball bond 232 on the die bond pad 230. The small tail of wire hanging from the end of the capillary may then be used to form the ball bond 232 for the next subsequent die bond pad 230. Ball bonds 232 may be formed at the bond pads of semiconductor die 224, 225 by a variety of other methods including for example stud bumping or gold bumping at the wafer level, or by a variety of other methods.

[0038] Thereafter, another ball bond is formed on the next lower level (for example on substrate 202)as explained above. However, instead of severing the wire, the wire is paid out and brought into contact with a ball bond 232 on the next higher level (though one or more levels may be skipped in further embodiments). The wire is applied to the ball bond 232 under a load, while the transducer applies ultrasonic energy. The combined heat, pressure, and ultrasonic energy create a bond between the wire and ball bond 232. The wire bonding capillary may then pay out a small length of wire, and the wire may be severed to form the wire bond 226 between pads on different levels.

[0039] This process may be repeated, both horizontally across the pads on the die and substrate, and vertically between the pads on the die and substrate, until all wire bonds 226 have been formed. The order with which wire bonds 226 are formed (horizontally or vertically) may vary in different embodiments. It is understood that the substrate 202, die 224 and/or die 225 may include many more wire bonds 226 than are shown in Fig. 8. Moreover, while the wire bonds 226 are shown generally in a straight vertical column from one layer to the next in the vertical stack of die and substrate, one or more of the wire bonds may extend diagonally from one layer to the next. Further, it may be that a wire bond skips one or more layers in the vertical stack.

[0040] Referring now to Fig. 8, at least one die bond pad 230a on each die 224, 225 may be a ground pad for grounding the die 224, 225. Similarly, at least one contact pad 208a on substrate 202 may be a ground pad for grounding the die 224, 225 and substrate 202. In embodiments, one such die bond ground pad 230a and a contact ground pad 208a may be electrically connected to each other with a series of wire bonds 226 as shown in Fig. 8. In accordance with aspects of the present technology, one of the ground die bond pads 230a and a ground contact pad 208a from a group of electrically connected pads may include a column of bumps 234 applied in step 126.

[0041] The bumps 234 may be formed in a manner similar to forming a ball bond 232 as explained above. However, in order to form the column, successive bumps 234 are laid one atop another. Thus, a first bump 234 may be formed at the tip of the wire bonding capillary and applied atop a wire bond 226 at a pad 230a, 208a under a load, while the transducer applies ultrasonic energy. The combined heat, pressure, and ultrasonic energy create a bond between the bump and the wire bond on which it sits. The first bump in the stack, resting atop a wire bond 226 at a pad 230a, 208a, may be in contact with the wire and/or the ball bond which together form the wire bond 226 at a pad. The bumps 234 may be formed of the same material from which wire bonds 226 are formed. However, the bumps 234 may be formed of a different material than wire bonds 226 in further embodiments.

[0042] Successive bumps 234 in the stack may thereafter be formed in the column by applying a new bump 234 under a load atop an existing bump 234, while the transducer applies ultrasonic energy. The combined heat, pressure, and ultrasonic energy create a bond between adjoining bumps 234.

[0043] The number of bumps 234 in a column of bumps may vary in embodiments, but may be sufficient so that a surface of a top bump 234 in the column will be exposed in the surface of a molding compound to be applied to the semiconductor device 200 as explained below. In particular, the thickness of the molding compound above a given die (for example die 225) is known, and a column of bumps 234 may be formed on that given die to that thickness, or slightly greater. In one example, there may be five bumps in a column of bumps extending off of the top die (controller die 225 in this example), but there may be more or less than that in further embodiments. It is further contemplated that the desired height of the bump column may be achieved using a single bump 234 in embodiments. The bumps may be the same general size as a ball bond 232, though a bump 234 may be larger or smaller than a ball bond 232 in further embodiments.

[0044] In embodiments, the column of bumps 234 may be applied to the uppermost die in the stack, thus requiring the shortest number of bumps in the column that will still be exposed in the surface of the molding compound. As indicated above, the use of "uppermost" does not imply a direction, but rather implies the die that is spaced the farthest from the substrate. In embodiments, this may be the controller die 225. However, in further embodiments, the controller die 225 may not be the uppermost die in the stack of die, and the uppermost die may instead be a memory die 224.

[0045] In further embodiments, it is understood that the column of bumps may be applied on a die 224, 225 below the uppermost die in the die stack. Such an example is shown in Fig. 8A, where the column of bumps 234 is applied to an intermediate die in the stack. In this embodiment, the height of the column may be increased relative to the embodiment of Fig. 8, so that the column extends to a point where the uppermost bump is exposed in a surface of the molding compound. It is further conceivable that the column of bumps 234 extend from a ground contact pad 208a on the substrate 202. In such an embodiment, the ground die bond pads on the die 224, 225 may be connected to the ground contact pad 208a having the bump column either by wire bonds 226, or a combination of wire bonds 226 and traces 206 on the substrate.

[0046] In Fig. 8 for example, the column of bumps 234 are affixed to a pad 230a, 208a also having a wire bond. However, in a further embodiment shown in Fig. 8B, the column of bumps 234 may be affixed to a pad 236 having no wire bond affixed thereto. The column of bumps 234 may be affixed to the pad 236 as described above. The pad 236 having the column may be electrically coupled to a ground pad, for example 230a on die 225, by an electrical trace 238 formed on a surface of the die. The trace 238 may be formed on the die by forming a redistribution pattern on a surface of the die by known processes. While shown on the uppermost die in the example of Fig. 8B, the column of bumps 234 may be formed on a pad 236 on a die or substrate below the uppermost die.

[0047] Although not shown, one or more passive components may also be affixed and electrically coupled to the substrate 202. The one or more passive components may be mounted on the substrate 202 and electrically coupled to the conductance pattern as by a connection to contact pads in known surface mount and reflow processes. The passive components may include for example one or more capacitors, resistors and/or inductors, though other components are contemplated.

[0048] In step 128, the semiconductor device 200 may undergo a plasma clean process to remove particulate and to improve the wettability of the surface to allow better flow properties of a molding compound used to protect the semiconductor die and wire bonds.

[0049] After the die 224 have been mounted and wire bonded to the substrate, and the column of bumps 234 are affixed, the die 224, 225, wire bonds 226 and most of the column of bumps 234 may be encapsulated in a molding compound in step 130. In one example described now with reference to Figs. 9-12, the semiconductor device 200 may be encapsulated using a molding compound 260. The encapsulation process may be performed by FFT (Flow Free Thin) compression molding. Such an FFT compression molding process is known and described for example in a publication by Matsutani, H. of Towa Corporation, Kyoto, Japan, entitled "Compression Molding Solutions For Various High End Package And Cost Savings For Standard Package Applications," Microelectronics and Packaging Conference, 2009, which publication is incorporated by reference herein in its entirety.

[0050] In general, an FFT compression machine makes use of a technique where the panel of substrates including the die 224, 225 and bumps 234 is immersed in a mold containing molten molding compound. The molding compound fills all voids on the immersed portions of the panel, and encapsulates each semiconductor device together in the molding compound, without exerting pressure on the die, bond wires or column of bumps. In one example, FFT compression may be performed using a PMC 1040 molding system from Towa Corporation, Kyoto, Japan. Other types of FFT compression techniques may be used in further embodiments. Additionally, the molding compound may be applied by known transfer molding techniques in further embodiments, using an epoxy for example from Nitto Denko Corp. of Japan.

[0051] The encapsulation process may be performed using top and bottom mold plates 254 and 256 as shown in Figs. 9-12. The substrate panel 201 may be held on the top mold plate 254, which may for example include a vacuum chuck for holding the substrate panel. The bottom mold plate 256 may be lined with a metallic layer transfer assembly 270. The metallic layer transfer assembly 270 may be formed of a variety of layers including at least one metallic layer. As explained below, the metallic layer transfers onto the surface of the molding compound during the encapsulation process.

[0052] Examples of metallic layer transfer assembly 270 may include heat transfer foil, such as that from Shanghai HongNi Printing and Packing Material Co., Ltd., having a place of business in Shanghai, China, or IMR (in mold roller) foil, such as that from Nissha Printing Co., Ltd., having a place of business in Kyoto, Japan. Heat transfer foil and IMR foil may use a PET film as a backing film. The metallic layer transfer assembly 270 may include an ETFE (ethylene tetrafluoroethylene) backing film (combined with a metal layer), such as for example that marketed under the brand name Fluon® from Asahi Glass Co., Ltd., having a place of business in Tokyo, Japan. Other metallic layer transfer assemblies are contemplated.

[0053] The metallic layer transfer assembly 270 may be formed into a long roll, collected between a pair of reels, such as take-up and supply reels 252 shown in Fig. 9. Thus, a single roll of metallic layer transfer assembly 270 may provide shielding for several substrate panels 201. An example of such a roll is used in a Towa FFT-1030 molding machine from Towa Corporation of Kyoto, Japan. However, in further embodiments, the metallic layer transfer assembly 270 may be formed with a shorter length. In one such embodiment, the metallic layer transfer assembly 270 may have a length and width only slightly larger or matching the length and width of panel 201. An example of such a sheet of metallic layer transfer assembly 270 is used in a Towa PMC- 1040 molding machine, also from Towa Corporation of Kyoto, Japan.

[0054] Referring to Fig. 10, once metallic layer transfer assembly 270 is provided in the bottom mold plate 256, molding compound 260 may be added into the bottom mold plate, over the metallic layer transfer assembly 270. In embodiments, the molding compound may be applied as a powder or as granules at room temperature. It may be applied onto the metallic layer transfer assembly 270, and then the metallic layer transfer assembly 270 and molding compound may be moved onto the bottom mold plate 256. In a further example, the metallic layer transfer assembly 270 may be positioned on the bottom mold plate 256 first, and then the molding compound 260 applied. The molding compound 260 may be a commercially available resin, for example sold by Kyocera Chemical Corporation, having a place of business in Saitama, Japan, under model number KE-G1250AH-W3E.

[0055] The top and bottom mold plates 254, 256 may then slowly be brought together under vacuum or near vacuum conditions, as shown by the transition from Fig. 10 to Fig. 11. The molding compound 260 may be heated to approximately 175°C at the time the semiconductor devices 200 are dipped into the molding compound. At that temperature, the molding compound 260 may be in a liquid phase having a viscosity of approximately 16.2 Pa^»s. It is understood that both the temperature and viscosity may vary above and below these values in further embodiments.

[0056] The mold plates may compress the substrate panel 201 against the bottom mold plate 256 as shown in Fig. 11 at a temperature of 175°C for a period of about 10 to 90 seconds, though the time may be longer or shorter than that in further embodiments. This may accomplish two functions. First, the molding compound 260may be cured to a solid, protective layer around the electronic components of each semiconductor device 200 on panel 201.

[0057] Second, the heat and pressure may transfer a metallic layer 272 of the metallic layer transfer assembly 270 to the adjacent surface of the molding compound 260. In one example, the metallic layer 272 may be covered by an adhesive layer (conductive adhesive layer or patternized-adhesive layer to benefit bump contact to metal layer or keep a good conductivity and good binding force). The adhesive layer may cross-link with the molding compound 260 under the heat and pressure to bond the metallic layer 272 to the molding compound. Thus, when the mold plates 254, 256 are separated from each other as shown in Fig. 12, the metallic layer 272 of the metallic layer transfer assembly 270 remains in or on the surface of the molding compound 260.

[0058] Where a roll of metallic layer transfer assembly 270 is used, after the above-described steps are performed, the roll may be advanced to position a next length of metallic layer transfer assembly 270 inside the mold plates, and the process repeated with another panel 201. Where precut sections of metallic layer transfer assembly 270 are used, a handler may place a new section of pre-cut metallic layer transfer assembly 270 on the bottom mold plate 256.

[0059] The encapsulation process leaves the column of bumps 234 exposed through the surface of molding compound 260 and the metallic layer 272, or at least in contact with the metallic layer 272. In one example, the metallic layer 272 may be aluminum foil, with a layer of aluminum oxide formed between the aluminum foil and molding compound. The column of bumps 234 may have a height such that it is slightly compressed during the encapsulation process, to ensure its contact with the aluminum or other conductor of metallic layer 272. In further embodiments, a second encapsulation step may be performed to bury the metallic layer 272 and exposed column of bumps 234 in molding compound. This second encapsulation step may be omitted in further embodiments.

[0060] In embodiments, the metallic layer 272 may be a solid, continuous layer of metal, with a thickness of a few microns to several hundred microns on the molding compound, though the thickness may be greater or lesser than that in further embodiments. The metallic layer 272 may for example be formed of aluminum foil, gold foil, ferric/nickel foil, fluorine plastic and copper foil, or other materials in further embodiments. The metallic layer 272 may be effective at EMI/RFI shielding and/or absorption. However, in further embodiments, instead of metallic layer 272 being a single uniform layer, the metallic layer 272 may be two discrete layers applied contiguously to each other. In such an embodiment, one layer may be effective at EMI/RFI shielding, and the second layer may be effective at EMI/RFI absorption. Details relating to such an embodiment are disclosed in PCT Application No. PCT/CN2012/074737, previously incorporated herein by reference in its entirety.

[0061] Moreover, in further embodiments, the metallic layer 272 may be formed with openings or in a mesh pattern, one such pattern being shown in Fig. 13. Fig. 13 shows a metallic layer 272 including a plurality of rectangular shaped openings 274 generally defining a mesh pattern in the metallic layer 272. In one example, each opening 274 may be 0.8mm x 0.15mm, and may be spaced from each other 1mm along the length dimension and 0.4mm along the width dimension. The size and spacing of openings 274 may vary from these dimensions in further embodiments. Furthermore, the openings 274 need not be rectangular, but can be square, circular, oval, elliptical or other shapes in further embodiments. [0062] In embodiments, the semiconductor device 200 may be a ball grid array (BGA) package. Following encapsulation, solder balls 280 may be applied to contact fingers 282 on the bottom surface of the semiconductor device 200in step 140 as shown in the edge view of Fig. 14. The solder balls allow the device 200 to be surface mounted to a PCB (not shown) in a host device. The contact fingers 282may include one or more ground fingers282a, which may each receive a solder ball 280a.

[0063] After the solder balls are applied, the semiconductor devices 200 may be singulated from the panel 201 in step 144 to form the finished semiconductor device 200 as shown in Fig. 14. Each device 200 may be singulated by any of a variety of cutting methods including sawing, water jet cutting, laser cutting, water guided laser cutting, dry media cutting, and diamond coating wire cutting. While straight line cuts will define a generally rectangular or square shaped device 200, it is understood that device 200 may have shapes other than rectangular and square in further embodiments of the present invention.

[0064] Once cut into devices 200, the devices may be tested in a step 148 to determine whether the devices are functioning properly. As is known in the art, such testing may include electrical testing, burn in and other tests. The devices may optionally be encased within a lid in step 150.

[0065] As described above and shown in Fig. 14, the metallic layer 272 lies in contact with the column of bumps 234 in a finished semiconductor device 200. As also described, the bumps 234 are in turn electrically coupled to a ground contact pad 208a on the substrate via wire bonds 226. The ground contact pad 208a may be connected by a via 205 to a ground finger 282a on a bottom surface of the semiconductor device 200. The ground finger 282a (along with the other fingers 282) may be soldered to a PCB or other host device to provide a path to ground for the metallic layer 272 and semiconductor device 200. The grounded metallic layer 272 may thus effectively provide EMI and/or RFI shielding and/or absorption of electromagnetic interference.

[0066] Instead of a BGA package, the semiconductor device may be a land grid array (LGA) package. In such an embodiment, the solder balls 280 may be omitted, and the ground finger 282a mates with a ground pad in a host device (not shown) upon removable insertion of the semiconductor device 200 into the host device. In an LGA package, the grounded metallic layer 272 is similarly effective at providing EMI and/or RFI shielding and/or absorption of electromagnetic interference in the semiconductor device 200.

[0067] In the embodiments described above, the metallic layer 272, also referred to herein as a shielding layer, may be formed on one or more outer surfaces of the molding compound 260 during the encapsulation process. However, in further embodiments, an electrically conductive shielding layer 272 may be formed on one or more outer surfaces of the molding compound 260 after the encapsulation process is complete. For example, as shown in Fig. 15, one or more print heads 290 may be provided for printing an electrically conductive shielding layer 272 on one or more surfaces of molding compound 260. The layer 272 may for example be a resin including aluminum, gold or other electrical conductor. The layer 272 in Fig. 15 may be applied either before or after singulation of the memory devices 200 from panel 201.

[0068] The print head 290 may deposit layer 272 by a variety of technologies, including for example continuous and/or drop on demand (DOD) printing. A variety of other technologies may be used to deposit layer 272 by print head 290 or otherwise, including for example, plating, screen printing and thin film deposition. In such embodiments, the metallic layer 272 may be applied to a top surface of the semiconductor devices 200 prior to singulation from panel 201. In further embodiments, the metallic layer 272 may be applied to a top surface, and side surfaces extending down from the top surface, after singulation of respective semiconductor devices 200 from panel 201. In embodiments, the applied layer 272 may be a solid, continuous layer. In further embodiments, the layer 272 may be patterned, for example including a mesh pattern as shown in Fig. 13.

[0069] The shielding layer 272 of the above-described embodiments may be effective at protecting the semiconductor device 200 by shielding and/or absorbing electromagnetic and radio frequency radiation. The radiation may be prevented from leaving the memory device 200 and/or penetrating into the memory device 200. It is further contemplated that the layer 272 may additionally or alternatively act as a heat sink for dissipating thermal energy generated by memory devices 200.

[0070] In summary, the present technology relates to a semiconductor device, comprising: a substrate having a ground pad; one or more semiconductor die on the substrate; molding compound for encapsulating the one or more semiconductor die; an electrical conductor formed on a surface of the molding compound for reducing at least one of EMI and RFI; and a column of one or more electrically conductive bumps electrically coupling the electrical conductor formed on the surface of the molding compound with the ground pad on the substrate.

[0071] In a further example, the present technology relates to a semiconductor device, comprising: a substrate; one or more semiconductor die on the substrate, a semiconductor die of the one or more semiconductor die including a die bond pad; molding compound for encapsulating the one or more semiconductor die; an electrical conductor formed on a surface of the molding compound for reducing at least one of EMI and RFI; and a column of one or more electrically conductive bumps electrically coupling the electrical conductor formed on the surface of the molding compound with the die bond pad on the semiconductor die.

[0072] In another example, the present technology relates to a semiconductor device, comprising: a substrate having a substrate ground pad; one or more semiconductor die on the substrate, each of the one or more semiconductor die including a die bond ground pad; wire bonds electrically connecting the die bond ground pad on each of the one or more semiconductor die with each other and the ground pad on the substrate; molding compound for encapsulating the one or more semiconductor die; an electrical conductor formed on a surface of the molding compound for reducing at least one of EMI and RFI; and a column of one or more electrically conductive bumps electrically coupling the electrical conductor formed on the surface of the molding compound with the wire bonds electrically connecting the die bond ground pad on each of the one or more semiconductor die and the ground pad on the substrate.

[0073] In a further example, the present technology relates to a semiconductor device, comprising: a substrate; one or more semiconductor die on the substrate; molding compound for encapsulating the one or more semiconductor die; an electrical conductor formed on a surface of the molding compound for reducing at least one of EMI and RFI; and a column of electrically conductive bumps, a first bump in the column of electrically conductive bumps physically in contact with a surface of the one of the semiconductor die or substrate, and a second bump in the column of electrically conductive bumps physically in contact with the electrical conductor formed on the surface of the molding compound.

[0074] The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims

CLAIMS We claim:

1. A semiconductor device, comprising:

a substrate having a ground pad;

one or more semiconductor die on the substrate;

molding compound for encapsulating the one or more semiconductor die;

an electrical conductor formed on a surface of the molding compound for reducing at least one of EMI and RFI; and

a column of one or more electrically conductive bumps electrically coupling the electrical conductor formed on the surface of the molding compound with the ground pad on the substrate.

2. The semiconductor device of claim 1, wherein the column of one or more electrically conductive bumps have an electrically conductive bump mounted on a die bond pad of a semiconductor die of the one or more semiconductor die.

3. The semiconductor device of claim 1, wherein the column of one or more electrically conductive bumps have an electrically conductive bump mounted on a contact pad of the substrate.

4. The semiconductor device of claim 1, wherein the column of one or more electrically conductive bumps is mounted atop a wire bond on a pad formed on a semiconductor die or substrate.

5. The semiconductor device of claim 1, wherein the column of one or more electrically conductive bumps are mounted on a pad formed on a semiconductor die or substrate, the pad having no wire bond formed thereon.

6. The semiconductor device of claim 5, wherein the pad is a first pad and the first pad is electrically coupled to a second pad having a wire bond affixed thereto.

7. The semiconductor device of claim 1, wherein the one or more semiconductor die includes a memory die stack of at least one memory die, and a controller die atop the memory die stack.

8. The semiconductor device of claim 7, wherein the column of electrically conductive bumps is formed on a surface of the controller die.

9. The semiconductor device of claim 7, wherein the column of electrically conductive bumps is formed on a surface of a memory die in the memory die stack.

10. The semiconductor device of claim 7, wherein the column of electrically conductive bumps is formed on an uppermost memory die in the memory die stack.

11. The semiconductor device of claim 1, wherein an uppermost electrically conductive bump in the column of electrically conductive bumps lies in physical contact with the electrical conductor formed on a surface of the molding compound.

12. The semiconductor device of claim 1, wherein the electrical conductor formed on a surface of the molding compound is a planar layer affixed to a surface of the molding compound.

13. The semiconductor device of claim 1, wherein the electrical conductor formed on a surface of the molding compound is a planar layer covering an entire surface of the molding compound.

14. The semiconductor device of claim 1, wherein the electrical conductor formed on a surface of the molding compound shields the semiconductor device against at least one of EMI and RFI.

15. The semiconductor device of claim 1, wherein the electrical conductor formed on a surface of the molding compound absorbs at least one of EMI and RFI.

16. A semiconductor device, comprising:

a substrate;

one or more semiconductor die on the substrate, a semiconductor die of the one or more semiconductor die including a die bond pad;

molding compound for encapsulating the one or more semiconductor die; an electrical conductor formed on a surface of the molding compound for reducing at least one of EMI and RFI; and

a column of one or more electrically conductive bumps electrically coupling the electrical conductor formed on the surface of the molding compound with the die bond pad on the semiconductor die.

17. The semiconductor device of claim 16, wherein the column of one or more electrically conductive bumps lie in physical contact with the die bond pad on the semiconductor die and the electrical conductor formed on the surface of the molding compound.

18. The semiconductor device of claim 16, wherein the column of one or more electrically conductive bumps are mounted atop a wire bond on a pad formed on the die bond pad.

19. The semiconductor device of claim 16, wherein the column of one or more electrically conductive bumps are mounted on the die bond pad and the die bond pad has no wire bond formed thereon.

20. A semiconductor device, comprising:

a substrate having a substrate ground pad;

one or more semiconductor die on the substrate, each of the one or more semiconductor die including a die bond ground pad;

wire bonds electrically connecting the die bond ground pad on each of the one or more semiconductor die with each other and the ground pad on the substrate;

molding compound for encapsulating the one or more semiconductor die;

a column of one or more electrically conductive bumps electrically coupling the electrical conductor formed on the surface of the molding compound with the wire bonds electrically connecting the die bond ground pad on each of the one or more semiconductor die and the ground pad on the substrate.

21. The semiconductor device of claim 20, wherein the one or more semiconductor die includes at least two memory die, the wire bonds electrically couples die bond ground pads on the at least two memory die with the ground pad on the substrate.

22. The semiconductor device of claim 21, wherein in the column of electrically conductive bumps is physically affixed atop a surface of an uppermost memory die of the at least two memory die.

23. The semiconductor device of claim 20, wherein the one or more semiconductor die includes at least two memory die and a controller die, the wire bonds electrically coupling die bond ground pads on the at least two memory die and controller die with the ground pad on the substrate.

24. The semiconductor device of claim 23, wherein in the column of electrically conductive bumps is physically affixed atop a surface of an uppermost die of the at least two memory die and controller die.

25. A semiconductor device, comprising:

a substrate;

one or more semiconductor die on the substrate;

molding compound for encapsulating the one or more semiconductor die;

a column of electrically conductive bumps, a first bump in the column of electrically conductive bumps physically in contact with a surface of the one of the semiconductor die or substrate, and a second bump in the column of electrically conductive bumps physically in contact with the electrical conductor formed on the surface of the molding compound.

26. The semiconductor device of claim 25, wherein the first bump in the column of electrically conductive bumps is mounted on a die bond pad of a semiconductor die of the one or more semiconductor die.

27. The semiconductor device of claim 25, wherein the first bump in the column of electrically conductive bumps is mounted on a contact pad of the substrate.

28. The semiconductor device of claim 25, wherein the first bump in the column of electrically conductive bumps is mounted atop a wire bond on a pad formed on a semiconductor die or substrate.

29. The semiconductor device of claim 25, wherein the first bump in the column of electrically conductive bumps is mounted on a pad formed on a semiconductor die or substrate, the pad having no wire bond formed thereon.

30. The semiconductor device of claim 29, wherein the pad is a first pad and the first pad is electrically coupled to a second pad having a wire bond affixed thereto.

31. The semiconductor device of claim 25, wherein the one or more semiconductor die includes a memory die stack of at least one memory die, and a controller die atop the memory die stack.

32. The semiconductor device of claim 31, wherein the first bump of the column of electrically conductive bumps is mounted to a die bond pad of the controller die.

33. The semiconductor device of claim 31, wherein the first bump of the column of electrically conductive bumps is mounted to a die bond pad of a memory die.

34. The semiconductor device of claim 31, wherein the first bump of the column of electrically conductive bumps is mounted to a die bond pad of an uppermost semiconductor die of the one or more semiconductor die.