CN101339940A - Encapsulation construction and encapsulation method - Google Patents
Encapsulation construction and encapsulation method Download PDFInfo
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- CN101339940A CN101339940A CN 200810213614 CN200810213614A CN101339940A CN 101339940 A CN101339940 A CN 101339940A CN 200810213614 CN200810213614 CN 200810213614 CN 200810213614 A CN200810213614 A CN 200810213614A CN 101339940 A CN101339940 A CN 101339940A
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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Abstract
The present invention discloses an encapsulation structure, which comprises a substrate, a semiconductor component, an adhesive body, a conductive protrusion and a conductive film. The substrate has a first surface, a second surface, a first side surface and a grounding component, wherein the first side surface is connected to the first surface and the second surface. The semiconductor component is arranged on the first surface and electrically connected to the substrate. The adhesive body covers the semiconductor component, and the second side surface of the adhesive body is substantially aligned with the first side surface of the substrate. The conductive protrusion is electrically connected to the grounding component. The conductive film is directly formed on the outer surface of the adhesive body, the exposed surface of the conductive protrusion and the side surface of the substrate, and the conductive film is electrically connected to the conductive protrusion.
Description
[technical field]
The invention relates to a kind of encapsulating structure and method for packing thereof, and particularly relevant for a kind of anti-electromagnetic interference encapsulating structure and method for packing thereof.
[background technology]
In general, the semiconductor subassembly encapsulation is that circuit is arranged on the circuit substrate, for example on printed circuit board (PCB) or the ceramic substrate.The usefulness of its circuit may be adversely affected because of electromagnetic interference (EMI).Electromagnetic interference (EMI) is signal interference or the noise that produces owing to the energy of electromagnetic field radiation.Because the density that electronic building brick is put in the system is more and more higher, relevant frequency of operation also toward higher frequency range development, so unnecessary radiated noise is more obvious, and then causes more serious electromagnetic interference.Therefore, the multiple encapsulating structure that prevents electromagnetic interference that utilizes electric conducting material to form shielding construction is developed.
Existing a kind of anti-electromagnetic interference encapsulating structure is after assembly carries out the adhesive body processing procedure, forms conducting film again on adhesive body behind the cutting adhesive body.Then, again substrate cut is formed independently package assembling.Please refer to Figure 1A and Figure 1B, it illustrates first road cutting processing procedure of a kind of anti-electromagnetic interference encapsulating structure of tradition and the schematic diagram of second road cutting processing procedure respectively.Shown in Figure 1A, chip 12 electrically connects with gold thread 13 and substrate 17, and conductive projection 16 electrically connects with the grounding assembly 15 of substrate 17.In this step with cutter 10a with adhesive body 14 cutting and separating, but cutting substrate 17 not.Then, shown in Figure 1B, form conducting film 18.Conducting film 18 is coated on the adhesive body 14, and wherein conductive projection 16 couples with conducting film 18.In this step, with the cutter 10b cutting substrate 17 of thinner thickness, to form independently package assembling 10, shown in 1C figure.Owing to this kind encapsulating structure must be through cutting twice in encapsulation process, because of the cutting failure causes the qualification rate reduction, because twice cutting processing procedure can be wasted more baseplate material, so the utilance of substrate is also relatively low except easily.
The anti-electromagnetic interference encapsulating structure of existing another kind, be with conductive shell for example a crown cap be arranged on the assembly of finishing encapsulation with viscose.Shown in Fig. 1 D, it illustrates the schematic diagram of the another kind of anti-electromagnetic interference encapsulating structure of tradition.Package assembling 20 comprises substrate 21, chip 22, adhesive body 25, conductive shell 26, reaches a plurality of surperficial interconnection techniques (SMT) assembly 28.Chip 22 electrically connects substrate 21 with gold thread 23.Conductive shell 26 is arranged on the adhesive body 25 with viscose 27.Surface interconnection technique assembly 28 is disposed on the substrate 21.But this kind practice is with the fixing conductive shell of viscose, except the complexity that increases processing procedure and the time, and the problem that causes conductive shell to come off because temperature, humidity cause viscose character to change easily.In addition, conductive shell must cooperate with the size of packaging part, and the packaging part of different size must be made different housings, increases the degree of difficulty that conductive shell is made.
Therefore, how to overcome the shortcoming of conventional package structure, producing high qualification rate, the package assembling that has anti-electromagnetic interference cheaply is one of problem of endeavouring of industry.
[summary of the invention]
The present invention is relevant for a kind of encapsulating structure and method for packing thereof, directly forms conducting film in encapsulation process, can reach to simplify the encapsulation flow process, save the encapsulation time to reduce cost and to improve the advantage of processing procedure qualification rate.The present invention more applicable to the packaging part of various sizes, also can save baseplate material simultaneously, improves packaging part density to improve the substrate utilization rate.
According to the present invention, a kind of encapsulating structure is proposed, comprise a substrate, semiconductor assembly, an adhesive body, a conductive projection and a conducting film.Substrate has a first surface, a second surface, one first side and a grounding assembly, and first side connects first surface and second surface.Semiconductor subassembly is arranged on the first surface and with substrate and electrically connects.Adhesive body is covered on the semiconductor subassembly, and one second side of adhesive body and first side of substrate trim in fact.Conductive projection is arranged on the first surface and has a plane, and the plane of conductive projection is exposed in second side of adhesive body, and second side of plane and adhesive body trims in fact.Conductive projection and grounding assembly electrically connect.Conducting film directly is formed on the side of an outer surface of adhesive body, plane that conductive projection exposes and substrate.
According to the present invention, a kind of method for packing is proposed, comprise the following steps.At first, one substrate is provided, at least have one first adjacent base board unit and one second base board unit, one first semiconductor subassembly and one second semiconductor subassembly are disposed on first base board unit and second base board unit, substrate has a first surface, a second surface and a side, and the side connects first surface and second surface.First semiconductor subassembly and second semiconductor subassembly are arranged on the first surface and with substrate and electrically connect, and an adhesive tape is attached on the second surface.Then, a conductive projection is set on first surface, conductive projection is between first semiconductor subassembly and second semiconductor subassembly.Then, form an adhesive body, adhesive body covers the first surface of first semiconductor subassembly, second semiconductor subassembly and conductive projection and part.Then, form a cutting slit, the cutting slit is cut apart the adhesive tape of adhesive body, conductive projection, substrate and part, is attached at first semiconductor device of 1 on the adhesive tape and one second semiconductor device with formation.The cutting degree of depth of cutting slit in adhesive tape is less than the thickness of adhesive tape, and a plane of conductive projection exposes to adhesive body.Then, directly form a conducting film on adhesive body and cutting slit, so that conducting film covers the outer surface of the adhesive body of first semiconductor device and second semiconductor device, plane that conductive projection exposes and the side of substrate.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
[description of drawings]
Figure 1A illustrates the schematic diagram of first road cutting processing procedure of a kind of anti-electromagnetic interference encapsulating structure of tradition;
Figure 1B illustrates the schematic diagram of second road cutting processing procedure of a kind of anti-electromagnetic interference encapsulating structure of tradition;
Fig. 1 C illustrates the schematic diagram of the anti-electromagnetic interference encapsulating structure of resulting tradition behind the processing procedure that uses 1A and 1B figure;
Fig. 1 D illustrates the schematic diagram of the another kind of anti-electromagnetic interference encapsulating structure of tradition;
Fig. 2 illustrates the schematic diagram according to a kind of anti-electromagnetic interference encapsulating structure of a preferred embodiment of the present invention;
Fig. 3 A-3F illustrates the encapsulation flow chart according to a kind of anti-electromagnetic interference encapsulating structure of a preferred embodiment of the present invention;
Fig. 4 illustrates the schematic diagram according to a kind of anti-electromagnetic interference encapsulating structure of another preferred embodiment of the present invention;
Fig. 5 A illustrates the schematic diagram of array type substrate; And
Fig. 5 B illustrates the schematic diagram of long strip type substrate.
[embodiment]
The present invention proposes a kind of encapsulating structure, comprises a substrate, semiconductor assembly, an adhesive body, a conductive projection and a conducting film.Substrate has a first surface, a second surface, one first side and a grounding assembly, and first side connects first surface and second surface.Semiconductor subassembly is arranged on the first surface and with substrate and electrically connects.Adhesive body is covered on the semiconductor subassembly, and one second side of adhesive body and first side of substrate trim in fact.Conductive projection is arranged on the first surface and has a plane, and the plane of conductive projection is exposed in second side of adhesive body, and second side of plane and adhesive body trims in fact.Conductive projection and grounding assembly electrically connect.Conducting film directly is formed at an outer surface of adhesive body, plane that conductive projection exposes and the side of substrate.
Please refer to Fig. 2, it illustrates the schematic diagram according to a kind of anti-electromagnetic interference encapsulating structure of a preferred embodiment of the present invention.As shown in Figure 2, the encapsulating structure of semiconductor device 100c comprises substrate 110a, semiconductor subassembly 120a, adhesive body 140a, conductive projection 151a and 152a, and conducting film 160a.Substrate 110a has surface 112, surface 114, side 116 and 118 and grounding assembly 181 and 182, and side 116,118 connects surface 112 and surperficial 114 respectively. Grounding assembly 181 and 182 for example is the ground connection weld pad, or the ground connection cabling.In addition, grounding assembly 181 and 182 respectively and have a preset distance between side 116 and 118.The preset distance of grounding assembly 181 and 116 of sides can equate with preset distance between the side 118 with grounding assembly 182 or not wait.
The side 142 and 144 of adhesive body 140a is exposed planar S 1 and the S2 of conductive projection 151a and 152a respectively, and planar S 1 and S2 trim in fact with the side 142 and 144 of adhesive body 140a respectively. Conductive projection 151a and 152a electrically connect with grounding assembly 181 and 182 respectively.Preferably, the composition material of conductive projection 151a and 152a is by selecting in the group that tin cream and conducting resinl constituted.In addition, the height of conductive projection 151a and 152a is less than the thickness of adhesive body 140a.
Conducting film 160a directly is formed on the side 116 and 118 of planar S 1 that outer surface, conductive projection 151a and the 152a of adhesive body 140a expose and S2 and substrate 110a, and conducting film 160a and conductive projection 151a and 152a electrically connect.Preferably, the composition material of conducting film 160a is by selecting in the group that aluminium, copper, chromium, tin, gold, silver and nickel constituted.Therefore, by conductive projection 151a and 152a, grounding assembly 181 and 182 can not need be arranged at the edge of substrate 110a, can electrically connect with conducting film 160a.
As for the method for packing of encapsulating structure of the present invention, please refer to 3A-3F figure, it illustrates the encapsulation flow chart according to a kind of anti-electromagnetic interference encapsulating structure of a preferred embodiment of the present invention.
At first, as shown in Figure 3A, provide a substrate 110, substrate 110 has adjacent base board unit Sb1 and Sb2, disposes a plurality of semiconductor subassemblies on the substrate 110, for example is semiconductor subassembly 120a and 120b, is disposed at respectively on base board unit Sb1 and the Sb2.Substrate 110 has surface 112, surface 114 and side 111 and 113, and side 111 and 113 connects surface 112 and surface 114.Semiconductor subassembly 120a and semiconductor subassembly 120b are arranged on the surface 112 and with substrate 110 and electrically connect.Semiconductor subassembly 120a and semiconductor subassembly 120b for example electrically connect with gold thread 130 and substrate 110.Adhesive tape 101 is attached on the surface 114, is scattered after cutting to avoid substrate 110.
Then, shown in Fig. 3 B, at least one conductive projection being set on surface 112, for example is conductive projection 151,152 and 153 to be set on surface 112.Conductive projection 152 is between semiconductor subassembly 120a and semiconductor subassembly 120b.Preferably, substrate 110 has Cutting Road 110a, 110b and 110c, and conductive projection 151,152 and 153 is disposed at respectively on Cutting Road 110a, 110b and the 110c.Conductive projection 151,152 and 153 composition material are for example by selecting in the group that tin cream and conducting resinl constituted.Conductive projection 151,152 and 153 material also can be other and can cut and conductive material.
In addition, method for packing of the present invention more comprises and is respectively provided to a few grounding assembly on base board unit Sb1 and base board unit Sb2.It for example is the grounding assembly 181,182,183 and 184 of Fig. 3 A-Fig. 3 F.Conductive projection 152 is between grounding assembly 182 and 183, and while and grounding assembly 182 and 183 electric connections.Grounding assembly 181 and 184 electrically connect with conductive projection 151 and 153 respectively.
Then, shown in Fig. 3 C, form adhesive body 140.Adhesive body 140 covers semiconductor subassembly 120a, semiconductor subassembly 120b, conductive projection 151,153 and 153 and surperficial 112.Preferably, conductive projection 151,152 and 153 height are less than the thickness of adhesive body 140.
Then, shown in Fig. 3 D, all cut slit at least in formation, for example are cutting slits 141,143 and 145.Preferably, cutting slit 141,143 and 145 is formed at respectively on Cutting Road 110a, the 110b and 110c of Fig. 3 C.Cutting slit 141,143 and 145 is cut apart the adhesive tape 101 of adhesive body 140, conductive projection 151,152 and 153, substrate 110 and part, is attached at semiconductor device 100a and semiconductor device 100b on the adhesive tape 101 with formation.In forming after all cut slit at least, each conductive projection is cut into two conductive projections, for example conductive projection 152 is cut into conductive projection 152a and 152b, adhesive body 140 also is cut into a plurality of adhesive bodies, for example be adhesive body 140a and 140b, and substrate 110 also is divided into a plurality of substrates, for example is substrate 110a and 110b.Semiconductor device 100a comprises semiconductor subassembly 120a, substrate 110a, conductive projection 151a and 152a, and adhesive body 140a; Semiconductor device 100b comprises semiconductor subassembly 120b, substrate 110b, conductive projection 152b and 153b, and adhesive body 140b.The depth of cut D1 of cutting slit 141,143 and 145 in adhesive tape 101 is less than the thickness D2 of adhesive tape 101.In addition, grounding assembly 182 and the mode of cutting slit 143 with the preset distance of being separated by, grounding assembly 182 will be set be arranged on the base board unit Sb1,143 modes with another preset distance of being separated by of grounding assembly 183 and cutting slit are arranged at grounding assembly 183 on the base board unit Sb2.
In this step,, will make the conductive projection that originally is coated in the adhesive body 140 expose out in forming after all cut slit at least.For example, planar S 1 and the S2 of conductive projection 151a and 152a expose.In addition, by the formation of cutting slit, the side 116 of the surface 142 of adhesive body 140, the planar S 1 of conductive projection 151a and substrate 110a trims in fact; Same, the surface 118 of the surface 144 of adhesive body 140, the planar S 2 of conductive projection 152a and substrate 110a also trims in fact.
Then, shown in Fig. 3 E, directly form conducting film 160 on adhesive body 140a and 140b and cutting slit 141,143 and 145, to form semiconductor device 100c and semiconductor device 100d.Preferably, the generation type of conducting film 160 is for example by selecting in chemical vapour deposition (CVD), electroless-plating, metallide, spraying, printing and the group that sputter constituted, and the composition material of conducting film 160 is by selecting in the group that aluminium, copper, chromium, tin, gold, silver and nickel constituted.Conducting film 160 covers planar S 1 and the S2 of semiconductor device 100c and the outer surface of adhesive body 140a, the conductive projection 151a that exposes and 152a, and whole sides 116 and 118 of substrate 110a.Same, conducting film 160 also covers semiconductor device 100d in an identical manner.
Then, shown in Fig. 3 F, remove adhesive tape 101, so, can obtain the semiconductor device of structure shown in Figure 2 with separating semiconductor device 100c and semiconductor device 100d.
Please refer to Fig. 4, it illustrates the schematic diagram according to a kind of anti-electromagnetic interference encapsulating structure of another preferred embodiment of the present invention.The difference of the encapsulating structure of the semiconductor device 100c of the encapsulating structure of semiconductor device 200 and Fig. 2 is that semiconductor subassembly 220 is to cover crystal type and substrate 210 electric connections.Be connected to example with substrate and do explanation though semiconductor subassembly of the present invention connects with routing or covers crystal type, so the present invention is not limited to this, and other electric connection mode is also applicable to the present invention.
And substrate 110 of the present invention also can be an array type substrate or long strip type substrate, has a plurality of base board units of arranging with an array form or bar row form.Please refer to Fig. 5 A and Fig. 5 B, it illustrates the schematic diagram of array type substrate and long strip type substrate respectively.Shown in Fig. 5 A, array type substrate 2 has a plurality of base board unit 2a, and two adjacent base board unit 2a separate with Cutting Road 2b.Semiconductor subassembly 120a and semiconductor subassembly 120b can be arranged at respectively on two adjacent base board unit 2a and encapsulate.After the adhesive body processing procedure is finished, can after Cutting Road 2b cutting, form conducting film again.
Shown in Fig. 5 B, long strip type substrate 4 has a plurality of base board unit 4a, and each base board unit 4a separates with Cutting Road 4b.Same, semiconductor subassembly 120a and semiconductor subassembly 120b can be arranged at respectively on two adjacent base board unit 4a and encapsulate.After the adhesive body processing procedure is finished, can after Cutting Road 4b cutting, form conducting film again.
Disclosed encapsulating structure of the above embodiment of the present invention and method for packing thereof are attached to the substrate back with a plurality of semiconductor devices with adhesive tape, and conductive projection is arranged on the substrate.And after adhesive body is finished, aim at the position at conductive projection place and cut, directly form conducting film again on adhesive body, again each semiconductor device is separated at last.By using adhesive tape, a plurality of semiconductor devices after cutting can not be scattered, and all semiconductor devices after the cutting still are attached on the adhesive tape.So, can allow the conducting film of all semiconductor devices form simultaneously, to save the processing procedure time.And, do not need secondary cut, only needing once, cutting can separate adhesive body and substrate simultaneously.In addition,, more can reduce the probability of cutting failure, to improve product percent of pass owing to only need once cut.Also because of the cutting number of times reduces, can improve the configuration density of assembly on the substrate, and increase the utilance of substrate simultaneously.
In addition, the conducting film so that the mode that directly is formed on the adhesive body produces can adapt to various size of components, also can resist the variation of temperature, humidity simultaneously, the lifting subassembly reliability.In addition, because the setting of conductive projection, the grounding assembly on the substrate can be provided with the inboard on the substrate and needn't be arranged at substrate edges, makes the configuration bit of grounding assembly on substrate be equipped with bigger design flexibility.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (20)
1. encapsulating structure comprises:
One substrate has a first surface, a second surface, one first side and a grounding assembly, and this first side connects this first surface and this second surface;
The semiconductor assembly is arranged on this first surface and electrically connects with this substrate;
One adhesive body is covered on this semiconductor subassembly, and one second side of this adhesive body and this first side of this substrate trim in fact;
One conductive projection is arranged on this first surface and has a plane, and this plane of this conductive projection is exposed in this of this adhesive body second side, and this second side of this plane and this adhesive body trims in fact, and this conductive projection and this grounding assembly electrically connect; And
One conducting film directly is formed on this side of an outer surface of this adhesive body, this plane that this conductive projection exposes and this substrate.
2. encapsulating structure according to claim 1 is characterized in that, this semiconductor subassembly is connected with this substrate routing.
3. encapsulating structure according to claim 1 is characterized in that, this semiconductor subassembly electrically connects to cover crystal type and this substrate.
4. encapsulating structure according to claim 1 is characterized in that, this grounding assembly comprises a ground connection cabling or a ground connection weld pad.
5. encapsulating structure according to claim 4 is characterized in that, has a preset distance between this ground connection cabling or this ground connection weld pad and this first side.
6. encapsulating structure according to claim 1 is characterized in that the height of this conductive projection is less than the thickness of this adhesive body.
7. encapsulating structure according to claim 1 is characterized in that the composition material of this conducting film is by selecting in the group that aluminium, copper, chromium, tin, gold, silver and nickel constituted.
8. encapsulating structure according to claim 1 is characterized in that the composition material of this conductive projection is by selecting in the group that tin cream and conducting resinl constituted.
9. method for packing comprises:
(a) provide a substrate, at least have one first adjacent base board unit and one second base board unit, one first semiconductor subassembly and one second semiconductor subassembly are disposed on this first base board unit and this second base board unit, this substrate has a first surface, a second surface and a side, this side connects this first surface and this second surface, this first semiconductor subassembly and this second semiconductor subassembly are arranged on this first surface and with this substrate and electrically connect, and an adhesive tape is attached on this second surface;
(b) conductive projection is set on this first surface, this conductive projection is between this first semiconductor subassembly and this second semiconductor subassembly;
(c) form an adhesive body, this adhesive body covers this first semiconductor subassembly, this second semiconductor subassembly and this conductive projection and this first surface;
(d) form a cutting slit, this cutting slit is cut apart this adhesive tape of this adhesive body, this conductive projection, this substrate and part, be attached at one first semiconductor device and one second semiconductor device on this adhesive tape with formation, the cutting degree of depth of this cutting slit in this adhesive tape is less than the thickness of this adhesive tape, and a plane of this conductive projection exposes to this adhesive body; And
(e) directly form a conducting film on this adhesive body and this cutting slit, so that this conducting film covers an outer surface of this adhesive body of this first semiconductor device and this second semiconductor device, this plane that this conductive projection exposes and this side of this substrate.
10. method for packing according to claim 9 is characterized in that, more comprises:
Remove this adhesive tape is coated with this conducting film with separation this first semiconductor device and this second semiconductor device.
11. method for packing according to claim 9 is characterized in that, in this step (e), the generation type of this conducting film is by selecting in chemical vapour deposition (CVD), electroless-plating, metallide, spraying, printing and the group that sputter constituted.
12. method for packing according to claim 9 is characterized in that, this substrate is an array type substrate, and this array type substrate has a plurality of base board units of arranging with an array form.
13. method for packing according to claim 9 is characterized in that, this step (d) comprises this cutting slit of formation on a Cutting Road of this substrate, and this conductive projection is disposed on this Cutting Road.
14. method for packing according to claim 9 is characterized in that, the composition material of this conducting film is by selecting in the group that aluminium, copper, chromium, tin, gold, silver and nickel constituted.
15. method for packing according to claim 9 is characterized in that, the composition material of this conductive projection is by selecting in the group that tin cream and conducting resinl constituted.
16. method for packing according to claim 9 is characterized in that, more comprises:
(f) one first grounding assembly and one second grounding assembly are set respectively on this first base board unit and this second base board unit;
(g) electrically connect this conductive projection and this first grounding assembly; And
(h) electrically connect this conductive projection and this second grounding assembly.
17. method for packing according to claim 16, it is characterized in that, in this step (f), this first grounding assembly is set on this first base board unit in the be separated by mode of one first preset distance of this first grounding assembly and this cutting slit, and this second grounding assembly is set on this second base board unit in the be separated by mode of one second preset distance setting of this second grounding assembly and this cutting slit.
18. method for packing according to claim 9 is characterized in that the thickness of the height of this conductive projection less than this adhesive body.
19. method for packing according to claim 9 is characterized in that this first semiconductor subassembly and this second semiconductor subassembly electrically connect with routing ways of connecting and this substrate.
20. method for packing according to claim 9 is characterized in that, this first semiconductor subassembly and this second semiconductor subassembly electrically connect to cover crystal type and this substrate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US689308P | 2008-02-05 | 2008-02-05 | |
| US61/006,893 | 2008-02-05 |
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| CN101339940A true CN101339940A (en) | 2009-01-07 |
| CN101339940B CN101339940B (en) | 2011-02-23 |
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| CN 200810213614 Active CN101339940B (en) | 2008-02-05 | 2008-08-22 | Encapsulation construction and encapsulation method |
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| CN (1) | CN101339940B (en) |
| TW (1) | TWI358117B (en) |
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Also Published As
| Publication number | Publication date |
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| TW200935577A (en) | 2009-08-16 |
| TWI358117B (en) | 2012-02-11 |
| CN101339940B (en) | 2011-02-23 |
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