TW200935577A - Packaging structure and packaging method thereof - Google Patents

Packaging structure and packaging method thereof

Info

Publication number
TW200935577A
TW200935577A TW97115986A TW97115986A TW200935577A TW 200935577 A TW200935577 A TW 200935577A TW 97115986 A TW97115986 A TW 97115986A TW 97115986 A TW97115986 A TW 97115986A TW 200935577 A TW200935577 A TW 200935577A
Authority
TW
Taiwan
Prior art keywords
substrate
conductive
semiconductor component
conductive bump
disposed
Prior art date
Application number
TW97115986A
Other languages
Chinese (zh)
Other versions
TWI358117B (en
Inventor
Chi-Tsung Chiu
Chih-Pin Hung
Jui-Cheng Huang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to US12/336,407 priority Critical patent/US8022511B2/en
Publication of TW200935577A publication Critical patent/TW200935577A/en
Application granted granted Critical
Publication of TWI358117B publication Critical patent/TWI358117B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

A packaging structure includes a substrate, a semiconductor element, a compound, a conductive bump and a conductive film. The substrate has a first surface, a second surface, a first lateral surface and a ground element. The first lateral surface connects the first surface and the second surface. The semiconductor element is disposed on the first surface and is electrically connected with the substrate. The compound covers the semiconductor element. A second lateral surface of the compound is aligned with the first lateral surface of the substrate. The conductive bump is disposed on the first surface and has a flat surface. The flat surface is exposed out of and aligned the second lateral surface of the compound. The conductive bump is electrically connected to the ground element. The conductive film is directly formed on an outward surface of the compound, the exposed flat surface of the ground element, and the first lateral surface of the substrate. The conductive film is electrically connected to the conductive bump.

Description

200935577 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種封裝結構及其封裝方法，且特別 是有關於一種抗電磁干擾封裝結構及其封裝方法。 【先前技術】 一般來說，半導體元件封裝是將電路設置在電路基 板上，例如印刷電路板或陶瓷基板上。其電路的效能可能 ⑩ 會因電磁干擾（EMI)而受到不利的影響。電磁干擾（EMI) 是由於電磁場能量放射而產生之信號干擾或雜訊。由於系 統内電子元件擺放的密度越來越高，相關的操作頻率亦往 更高的頻段發展，於是不必要的輻射雜訊更趨明顯，進而 導致更嚴重的電磁干擾。因此，多種利用導電材料形成屏 蔽結構之防止電磁干擾的封裝結構已經被開發出來。 現有的一種抗電磁干擾封裝結構，是在元件進行封 膠體製程後，切割封膠體後再形成導電膜於封膠體上。然 φ 後，再將基板切割形成獨立之封裝元件。請參照第1A圖 及第1B圖，其分別繪示傳統一種抗電磁干擾封裝結構的 第一道切割製程及第二道切割製程之示意圖。如第1A圖 所示，晶片12係以金線13與基板17電性連接，導電凸 塊16與基板17之接地元件15電性連接。本步驟中係以 切割刀10a將封膠體14切割分離，但不切割基板17。然 後，如第1B圖所示，形成導電膜18。導電膜18係塗佈 於封膠體14上，其中導電凸塊16係與導電膜18耦接。 本步驟中，以厚度較薄之切割刀10b切割基板17，以形 6 200935577 成獨立之封裝元件10，如1C圖所示。由於此種封裝結構 在封裝過程中必須經過兩次切割，除了容易因切割失敗導 致良率降低外’由於兩道切割製程會浪費較多的基板材 料，因此基板的利用率也相對較低。 現有的另一種抗電磁干擾封裝結構，是將導電殼體 例如一金屬蓋以黏膠設置在完成封裝的元件上。如第1D 圖所示’其繪示傳統另一種抗電磁干擾封裝結構的示意 圖。封裝元件20包括基板21、晶片22、封膠體25、導 0 電殼體26、及多個表面連接技術（SMT)元件28。晶片22 係以金線23電性連接基板21。導電殼體26係以黏膠27 設置在封膠體25上。表面連接技術元件28係配置於基板 21上。但是此種作法係以黏膠固定導電殼體除了增加製 程的複雜度及時間外，容易因為溫度、濕度導致黏膠性質 改變而導致導電殼體脫落的問題。此外，導電殼體與封裝 件的尺寸必須配合，不同尺寸的封裝件必須製作不同的殼 體，增加導電殼體製造的困難度。 © 因此，如何克服傳統封裝結構的缺點，以產生高良 率，低成本之具有抗電磁干擾之封裝元件，乃業界所致力 的課題之一。 【發明内容】 ㈣關於—種封裝結構及料裝方法，在封裝 ，中直接形成導電膜，可以達到簡化封裝流程、節省封 低成本、並提高製程良率之優點:本發明更可 適用於各種尺寸之封裝件，同_可節省基板材料，提高 7 200935577 封裝件密度以提高基板使用率。 根據本發明，提出一種封裝結構，包括一基板、一半 導體元件、一封膠體、一導電凸塊以及一導電膜。基板具 有一第一表面、一第二表面、一第一側面及一接地元件， 第一側面連接第一表面及第二表面。半導體元件設置於第 一表面上並與基板電性連接。封膠體覆蓋於半導體元件 上，封膠體之一第二側面係與基板之第一侧面實質上切 齊。導電凸塊設置於第一表面上並具有一平面，封膠體之 ❹ 第二側面露出導電凸塊之平面，平面係與封膠體之第二側 面實質上切齊。導電凸塊係與接地元件電性連接。導電膜 直接形成於封膠體之一外表面、導電凸塊外露之平面及基 板之側面上。 根據本發明，提出一種封裝方法，包括下列步驟。首 先，提供一基板，至少具有相鄰之一第一基板單元及一第 二基板單元，一第一半導體元件及一第二半導體元件係配 置於第一基板單元及第二基板單元上，基板具有一第一表 ® 面、一第二表面及一側面，側面連接第一表面及第二表 面。第一半導體元件及第二半導體元件設置於第一表面上 並與基板電性連接，一膠帶係貼附於第二表面上。然後， 設置一導電凸塊於第一表面上，導電凸塊位於第一半導體 元件及第二半導體元件之間。接著，形成一封膠體，封膠 體覆蓋第一半導體元件、第二半導體元件及導電凸塊及部 分之第一表面。然後，形成一切割狹縫，切割狹縫分割封 膠體、導電凸塊、基板及部分之膠帶，以形成貼附於膠帶 8 200935577 二中：—：導體裝置及一第二半導體裝置。切割狹縫於 1帶中之—切贿度係小於膠帶之厚度，導電凸塊之一平 = 封膠體。接著’直接形成一導電膜於封膠體及 刀。m縫上’以使導電膜覆蓋第—半導體裝置及第 =置之封膠體之外表面、導電凸塊外露之平面及 „之上述内容能更明顯易懂，下文特舉較佳 實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 ^發明提出-種封裝結構，包括—基板、一半導體元 =-封膠體、—導電凸塊以及—導電膜。基板具有一第 面，二：第二表面、一第一側面及-接地元件，第-侧 表面及第二表面。半導體元件設置於第一表面 板電性連接。封賴覆^铸體元件上，封膠 ❹ 塊二==第:側面實質上切齊。導電凸 出導雷凸地夕正、八有平面，封膠體之第二侧面露 導電凸塊之平面，平面係與封膠體 齊。導電凸塊係與接地元件電性連接側面實質上切 tm16、導電㈣外露之平面及絲之侧面。 »月參…第2圖，其繪示依照本發 :抗電磁干擾封震結構之示意圖=實施=體 封膠體MOa、導電凸塊ma =:件： α 从及導電膜160a。 9 200935577 基板ii〇a具有表面U2、表面U4、侧面叫及丨以及接 地元件18!及182，侧面116、118分別連接表面112及表 面114。接地元件181及182例如為接地銲墊，或是接地 走線此外，接地元件181及182分別與側面及118 之間係具有-預定距離。接地元件181與側面ιΐ6間之預 定距離可與接地元件182與側面118之間之預定距離相等 或不等。 +導體元件120a設置於表面112上並與基板110af ❿性連接。較佳地，半導體元件120a係以至少一金線130 與基板110a打線連接。封膠體140a覆蓋於半導體元件 120a上’封膠體140a之侧面142及144係分別與基板 之側面116及118實質上切齊。導電凸塊151&及152a分 別設置於表面112上之相對兩側，並分別具有平面S1及 S2。 封膠體140a之侧面142及144分別露出導電凸塊 151&及152a之平面S1及S2，且平面S1及82係分別與 ® 封膠體140a之侧面142及144實質上切齊。導電凸塊151a 及152a係分別與接地元件181及182電性連接。較佳地， 導電凸塊151 a及152a的組成材料係由錫膏及導電勝所構 成的群組中選出。此外，導電凸塊151a及i52a之高度小 於封膠體140a之厚度。 導電膜160a直接形成於封膠體140a之外表面、導電 凸塊151a及152a外露之平面S1及S2及基板11〇a之侧 面116及118上’導電膜160a與導電凸塊i51a及152a 200935577 電性連接。較佳地，導電膜160a的組成材料係由鋁、銅、 鉻、錫、金、銀及鎳所構成的群組中選出。因此，藉由導 電凸塊151a及152a，接地元件181及182可以不需設置 於基板110a之邊緣，即可與導電臈160a電性連接。 至於本發明之封裝結構之封裝方法，請參照第3a_3f 圖，其繪示依照本發明一較佳實施例的一種抗電磁干擾封 裝結構之封裝流程圖。 首先，如第3A圖所示，提供一基板u〇，基板u〇 ® 具有相鄰之基板單元Sbl及Sb2，基板110上係配置有多 個半導體元件’例如是半導體元件120a及120b，分別配 置於基板單元Sbl及Sb2上。基板110具有表面112、表 面114及側面in及113，側面ill及113連接表面112 及表面114。半導體元件12〇a及半導體元件12〇b設置於 表面112上並與基板110電性連接。半導體元件12〇a及半 導體元件120b例如係以金線130與基板11〇電性連接。 膠帶101係貼附於表面114上’以避免基板110在切割後 散落。 然後’如第3B圖所示，設置至少一導電凸塊於表面 112上，例如是設置導電凸塊151、152及153於表面112 上。導電凸塊152位於半導體元件120a及半導體元件12〇b 之間。較佳地，基板110具有切割道ll〇a、ll〇b及li〇c， 導電凸塊151、152及153係分別配置於切割道ll〇a、ll〇b 及110c上。導電凸塊15丨、152及153的組成材料例如係 由錫膏及導電膠所構成的群組中選出。導電凸塊151、152 200935577 及153之材質亦可為其他可切割且可導電之材質。 此外，本發明之封裝方法更包括分別設置至少一接地 元件於基板單元Sbl與基板單元sb2上。例如是第3A圖-第3F圖之接地元件181、182、183及184。導電凸塊152 係位於接地元件182及183之間’並同時與接地元件182 及183電性連接。接地元件i8l及184則分別與導電凸塊 151及153電性連接。 接著’如第3C圖所示’形成封膠體丨4〇。封膠體140 β 覆蓋半導體元件120a、半導體元件12〇b、導電凸塊151、 153及153及表面112。較佳地，導電凸塊151、152及153 之高度小於封膠體140之厚度。 然後’如第3D圖所示，形成至少一切割狹縫，例如 是切割狹縫141、143及145。較佳地，切割狹縫141、143 及145係分別形成於第3C圖之切割道ii〇a、ii〇b及ll〇c 上。切割狹縫141、143及145分割封膠體140、導電凸塊 151、152及153、基板110及部分之膠帶1〇1，以形成貼 ❹ 附於膠帶101上之半導體裝置100a及半導體裝置100b。 於形成至少一切割狹縫之後，每個導電凸塊係被切割成兩 個導電凸塊，例如導電凸塊152係被切割成導電凸塊152a 及152b，封膠體140亦被切割成多個封膠體，例如是封膠 體140a及140b，而基板110亦被分割成多個基板，例如 是基板ll〇a及ll〇b。半導體裝置100a包括半導體元件 120a、基板110a、導電凸塊151a及152a，以及封膠體140a; 半導體裝置l〇〇b包括半導體元件120b、基板110b、導電 12 200935577 凸塊152b及153b，以及封膠體140b。切割狹縫141、143 及145於膠帶101中之切割深度D1係小於膠帶ι〇1之厚 度D2。此外，接地元件182與切割狹縫143以相隔一預 定距離的方式，將設置接地元件182設置於基板單元sbl 上’接地元件183與切割狹縫143則以相隔另一預定距離 的方式’將接地元件183設置於基板單元Sb2上。 於此步驟中，於形成至少一切割狹縫之後，將使原本 包覆於封膠體14〇中之導電凸塊外露出來。例如，導電凸 ❹ 塊151 a及152a之平面S1及S2係外露。此外，藉由切割 狹縫之形成，封膠體140之表面142、導電凸塊151a之平 面S1及基板110a之側面116係實質上切齊；同樣的，封 膠體140之表面144、導電凸塊152a之平面S2及基板110a 之表面118亦實質上切齊。 接著，如第3E圖所示’直接形成導電膜160於封膠 體140a及i4〇b及切割狹縫141、143及145上，以形成 半導體裝置100c及半導體裝置l〇〇d。較佳地，導電膜160 ® 的形成方式例如由化學氣相沈積、無電電鍍、電解電鍍、 喷塗、印刷及滅鍍所構成的群組中選出，而導電膜160的 組成材料係由|g、銅、鉻、錫、金、銀及鎳所構成的群組 中選出。導電膜160覆蓋半導體裝置100c及封膠體140a 之外表面、外露之導電凸塊151a及152 a之平面S1及S2 ’ 及基板110a之全部側面I16及U8。同樣的，導電膜I60 亦以相同之方式覆蓋半導體裝置1〇〇d° 然後，如第3F圖所示’除去膠帶ιοί以分離半導體 13 200935577 裝置100c及半導體裝置100d，如此，即可得到第2圖所 示之結構之半導體裝置。 請參照第4圖，其繪示依照本發明另一較佳實施例的 一種抗電磁干擾封裝結構之示意圖。半導體裝置200之封 裝結構與第2圖之半導體裝置100c之封裝結構的差別在 於，半導體元件220係以覆晶方式與基板210電性連接。 雖然本發明之半導體元件係以打線連接或覆晶方式與基 板連接為例做說明，然本發明並不限於此，其他的電性連 ® 接方式亦可適用於本發明。 而本發明之基板110，也可以是一陣列式基板或長條 式基板，具有以一陣列形式或條列形式排列之複數個基板 單元。請參照第5A及第5B圖，其分別繪示陣列式基板及 長條式基板之示意圖。如第5A圖所示，陣列式基板2具 有多個基板單元2a，相鄰之兩個基板單元2a係以切割道 2b隔開。半導體元件120a及半導體元件120b可以分別設 置於相鄰之兩個基板單元2a上進行封裝。當封膠體製程 ❿ 完成後，可以沿切割道2b切割後，再形成導電膜。 如第5B圖所示，長條式基板4具有多個基板單元 4a，每一基板單元4a係以切割道4b隔開。同樣的，半導 體元件120a及半導體元件120b可以分別設置於相鄰之兩 個基板單元4a上進行封裝。當封膠體製程完成後，可以 沿切割道4b切割後，再形成導電膜。 本發明上述實施例所揭露之封裝結構及其封裝方 法，係將膠帶貼在具有複數個半導體裝置之基板背面，並 200935577 將導電凸塊設置於基板上。並在封膠體完成後，對準導電 凸塊所在之位置進行切割，再直接形成導電膜於封膠體 上，最後再將各半導體裝置分離。藉由使用膠帶，進行切 割後的多個半導體裝置不會散落，切割後之所有的半導體 裝置係仍然黏著於膠帶上。如此，可以讓所有的半導體裝 置之導電膜可以同時形成，以節省製程時間。而且，不需 二次切割’只需一次切割即可同時分離封膠體及基板。此 外，由於僅需進行一次切割’更可以降低切割失敗的機 〇 率，以提高產品良率。同時也因切割次數減少，可以提高 基板上元件的配置密度，而增加基板的利用率。 另外，以直接形成於封膠體上之方式產生的導電膜， 可以適應各種元件尺寸，同時也可以抵抗溫、濕度的變 化，提升元件可靠度。此外，由於導電凸塊的設置，基板 上的接地元件可以設置基板上的内侧而不必設置於基板 邊緣，使得接地元件在基板上的配置位置有較大的設計彈 性。 β 綜上所述，雖然本發明已以較佳實施例揭露如上，然 其並非用以限定本發明。本發明所屬技術領域中具有通常 知識者，在不脫離本發明之精神和範圍内，當可作各種之 更動與潤飾。因此，本發明之保護範圍當視後附之申請專 利範圍所界定者為準。 15 200935577 【圖式簡單說明】 第1A圖繪示傳統一種抗電磁干擾封裝結構的第一道 切割製程之示意圖； 第1B圖繪示傳統一種抗電磁干擾封裝結構的第二道 切割製程之示意圖； 第1C圖繪示使用第1A及1B圖之製程後所得到之傳 統抗電磁干擾封裝結構的示意圖； 第1D圖繪示傳統另一種抗電磁干擾封裝結構的示意 圖； 第2圖繪示依照本發明一較佳實施例的一種抗電磁 干擾封裝結構之示意圖； 第3A-3F圖繪示依照本發明一較佳實施例的一種抗 電磁干擾封裝結構之封裝流程圖； 第4圖繪示依照本發明另一較佳實施例的一種抗電 磁干擾封裝結構之示意圖； 第5A圖繪示陣列式基板之示意圖；以及 ® 第5B圖繪示長條式基板之示意圖。 【主要元件符號說明】 2 :陣列式基板 2a、4a :基板單元 2b、4b、110a、110b、110c :切割道 4 :長條式基板 10、20 :封裝元件 16 200935577 10a、10b :切割刀 12、 22 :晶片 13、 23、130 :金線 14、 25、140、140a、140b :封膠體 15、 181、182、183、184 :接地元件 16、 151、151a、152、152a、152b、153、153b :導電 凸塊 17、 21、110、110a、110b、210 :基板 〇 18、160、160a、160b :導電膜 26 :導電殼體 27 :黏膠 100a、100b、100c、100d、200 :半導體裝置 101 :膠帶 112、114 :表面 111、113、116、118、142、144 :側面 120a、120b、220 :半導體元件 ❹ 141、143、145 :切割狹縫 SI、S2 :平面 Sbl、Sb2 :基板單元 17200935577 IX. Description of the Invention: [Technical Field] The present invention relates to a package structure and a package method thereof, and more particularly to an EMI-resistant package structure and a package method therefor. [Prior Art] In general, a semiconductor component package is provided with a circuit on a circuit board such as a printed circuit board or a ceramic substrate. The performance of its circuit may be adversely affected by electromagnetic interference (EMI). Electromagnetic interference (EMI) is signal interference or noise generated by the emission of electromagnetic fields. Due to the increasing density of electronic components placed in the system, the associated operating frequencies are also developed in higher frequency bands, so unnecessary radiated noise is more pronounced, leading to more severe electromagnetic interference. Therefore, a variety of package structures for preventing electromagnetic interference using a conductive material to form a shield structure have been developed. An existing anti-electromagnetic interference package structure is formed by cutting a sealant after the component is subjected to a sealing process to form a conductive film on the sealant. After φ, the substrate is then cut to form a separate package component. Please refer to FIG. 1A and FIG. 1B respectively, which respectively illustrate schematic diagrams of a first cutting process and a second cutting process of a conventional anti-electromagnetic interference package structure. As shown in Fig. 1A, the wafer 12 is electrically connected to the substrate 17 by a gold wire 13, and the conductive bump 16 is electrically connected to the grounding member 15 of the substrate 17. In this step, the sealant 14 is cut and separated by the cutter 10a, but the substrate 17 is not cut. Then, as shown in Fig. 1B, a conductive film 18 is formed. The conductive film 18 is coated on the encapsulant 14, wherein the conductive bumps 16 are coupled to the conductive film 18. In this step, the substrate 17 is cut by a thin cutting blade 10b to form a separate package component 10 in the form of 200935577, as shown in Fig. 1C. Since the package structure must be cut twice during the packaging process, in addition to the easy yield reduction due to the failure of the cutting process, the utilization rate of the substrate is relatively low because the two cutting processes waste a lot of base material. Another existing EMI-resistant package structure is to place a conductive housing such as a metal cover with an adhesive on the finished package. As shown in Fig. 1D, it shows a schematic view of another conventional EMI-resistant package structure. The package component 20 includes a substrate 21, a wafer 22, a sealant 25, a conductive housing 26, and a plurality of surface mount technology (SMT) components 28. The wafer 22 is electrically connected to the substrate 21 by a gold wire 23. The conductive housing 26 is disposed on the sealant 25 with an adhesive 27. The surface connection technology element 28 is disposed on the substrate 21. However, this method is to fix the conductive shell with adhesive, in addition to increasing the complexity and time of the process, it is easy to cause the peeling of the conductive shell due to the change of the adhesive properties caused by temperature and humidity. In addition, the size of the conductive housing and the package must be matched. Different sizes of packages must be made of different shells, which increases the difficulty in manufacturing the conductive housing. © Therefore, how to overcome the shortcomings of the traditional package structure to produce high-yield, low-cost package components with electromagnetic interference resistance is one of the topics of the industry. SUMMARY OF THE INVENTION (4) Regarding a package structure and a material loading method, directly forming a conductive film in a package can achieve the advantages of simplifying the packaging process, saving the cost of sealing, and improving the yield of the process: the present invention is more applicable to various Dimensions of the package, the same as _ can save substrate material, increase the density of 7 200935577 package to improve substrate utilization. According to the present invention, a package structure is provided comprising a substrate, a half conductor element, a gel, a conductive bump, and a conductive film. The substrate has a first surface, a second surface, a first side and a grounding member, the first side connecting the first surface and the second surface. The semiconductor component is disposed on the first surface and electrically connected to the substrate. The encapsulant is overlying the semiconductor component, and the second side of the encapsulant is substantially tangential to the first side of the substrate. The conductive bump is disposed on the first surface and has a flat surface, and the second side of the seal body exposes a plane of the conductive bump, and the plane is substantially aligned with the second side surface of the sealant. The conductive bump is electrically connected to the grounding element. The conductive film is formed directly on the outer surface of one of the sealing bodies, the exposed surface of the conductive bumps, and the side of the substrate. According to the present invention, a packaging method is proposed comprising the following steps. First, a substrate is provided, which has at least one adjacent first substrate unit and a second substrate unit. A first semiconductor component and a second semiconductor component are disposed on the first substrate unit and the second substrate unit, and the substrate has a first surface, a second surface and a side surface connected to the first surface and the second surface. The first semiconductor component and the second semiconductor component are disposed on the first surface and electrically connected to the substrate, and a tape is attached to the second surface. Then, a conductive bump is disposed on the first surface, and the conductive bump is located between the first semiconductor component and the second semiconductor component. Next, a gel is formed, the encapsulant covering the first surface of the first semiconductor element, the second semiconductor element, and the conductive bumps and portions. Then, a slit slit is formed, and the slit is divided into a sealing body, a conductive bump, a substrate and a part of the tape to form a tape attached to the tape 8 200935577: -: a conductor device and a second semiconductor device. The cutting slit is in the belt 1 - the bribe is less than the thickness of the tape, and one of the conductive bumps is flat = sealant. Then, a conductive film is directly formed on the sealant and the blade. m is sewed to make the conductive film cover the surface of the first semiconductor device and the outer surface of the sealing body, the exposed surface of the conductive bump, and the above contents can be more clearly understood, and the preferred embodiment is hereinafter, and With reference to the drawings, a detailed description is as follows: [Embodiment] The invention provides a package structure including a substrate, a semiconductor element, a sealing body, a conductive bump, and a conductive film. The substrate has a first surface. Two: a second surface, a first side surface and a grounding element, a first side surface and a second surface. The semiconductor component is electrically connected to the first surface plate, and the sealing element is sealed on the casting component. == No.: The side is substantially tangential. The conductive bulge is convex and convex, and the second side of the encapsulant is exposed to the plane of the conductive bump. The plane is flush with the sealant. The conductive bump is grounded. The electrical connection side of the component is substantially cut by tm16, the conductive (4) exposed plane and the side of the wire. » The monthly reference... Figure 2 shows the schematic diagram of the anti-electromagnetic interference sealing structure according to the present invention = implementation = body sealant MOa , conductive bump ma =: piece: α from The conductive film 160a. 9 200935577 The substrate ii〇a has a surface U2, a surface U4, a side surface and a grounding member 18! and 182, and the side surfaces 116, 118 are respectively connected to the surface 112 and the surface 114. The grounding members 181 and 182 are, for example, grounded welding. Pad, or ground trace In addition, ground elements 181 and 182 have a predetermined distance from side and 118. The predetermined distance between ground element 181 and side ΐ6 can be a predetermined distance from ground element 182 and side 118. The conductor element 120a is disposed on the surface 112 and is connected to the substrate 110af. Preferably, the semiconductor element 120a is connected to the substrate 110a by at least one gold wire 130. The sealing body 140a covers the semiconductor element 120a. The sides 142 and 144 of the upper encapsulant 140a are substantially aligned with the sides 116 and 118 of the substrate. The conductive bumps 151 & 152a are respectively disposed on opposite sides of the surface 112 and have planes S1 and S2, respectively. The sides 142 and 144 of the encapsulant 140a expose the planes S1 and S2 of the conductive bumps 151 & 152a, respectively, and the planes S1 and 82 are substantially aligned with the sides 142 and 144 of the ® encapsulant 140a, respectively. The conductive bumps 151a and 152a are electrically connected to the grounding members 181 and 182, respectively. Preferably, the constituent materials of the conductive bumps 151a and 152a are selected from the group consisting of solder paste and conductive material. The height of the bumps 151a and i52a is smaller than the thickness of the sealant 140a. The conductive film 160a is directly formed on the outer surface of the sealant 140a, the exposed surfaces S1 and S2 of the conductive bumps 151a and 152a, and the sides 116 and 118 of the substrate 11A. The conductive film 160a is electrically connected to the conductive bumps i51a and 152a 200935577. Preferably, the constituent material of the conductive film 160a is selected from the group consisting of aluminum, copper, chromium, tin, gold, silver, and nickel. Therefore, the grounding members 181 and 182 can be electrically connected to the conductive cymbal 160a without being disposed at the edge of the substrate 110a by the conductive bumps 151a and 152a. For the packaging method of the package structure of the present invention, please refer to FIG. 3a-3f, which illustrates a package flow chart of an anti-electromagnetic interference package structure according to a preferred embodiment of the present invention. First, as shown in FIG. 3A, a substrate u is provided, the substrate u〇® has adjacent substrate units Sb1 and Sb2, and a plurality of semiconductor elements 'for example, semiconductor elements 120a and 120b are disposed on the substrate 110, respectively. On the substrate units Sb1 and Sb2. The substrate 110 has a surface 112, a surface 114 and side surfaces in and 113, and side surfaces ill and 113 connect the surface 112 and the surface 114. The semiconductor element 12A and the semiconductor element 12A are disposed on the surface 112 and electrically connected to the substrate 110. The semiconductor element 12A and the semiconductor element 120b are electrically connected to the substrate 11 by, for example, a gold wire 130. The tape 101 is attached to the surface 114 to prevent the substrate 110 from scattering after cutting. Then, as shown in FIG. 3B, at least one conductive bump is disposed on the surface 112, for example, conductive bumps 151, 152, and 153 are disposed on the surface 112. The conductive bump 152 is located between the semiconductor element 120a and the semiconductor element 12〇b. Preferably, the substrate 110 has dicing streets 11a, 11b, and 153, and the conductive bumps 151, 152, and 153 are disposed on the dicing streets 11a, 11b, and 110c, respectively. The constituent materials of the conductive bumps 15A, 152, and 153 are selected, for example, from the group consisting of solder paste and conductive paste. The conductive bumps 151, 152 200935577 and 153 can also be made of other materials that can be cut and electrically conductive. In addition, the packaging method of the present invention further includes disposing at least one grounding element on the substrate unit Sb1 and the substrate unit sb2, respectively. For example, the grounding elements 181, 182, 183, and 184 of FIGS. 3A-3F. The conductive bumps 152 are located between the ground elements 182 and 183 and are electrically connected to the ground elements 182 and 183 at the same time. The grounding elements i8l and 184 are electrically connected to the conductive bumps 151 and 153, respectively. Next, the sealant 丨4〇 is formed as shown in Fig. 3C. The encapsulant 140 β covers the semiconductor element 120a, the semiconductor element 12〇b, the conductive bumps 151, 153 and 153, and the surface 112. Preferably, the height of the conductive bumps 151, 152 and 153 is smaller than the thickness of the sealant 140. Then, as shown in Fig. 3D, at least one slit is formed, for example, slits 141, 143, and 145. Preferably, the slits 141, 143 and 145 are formed on the dicing streets ii 〇 a, ii 〇 b and ll 〇 c of FIG. 3C, respectively. The slits 141, 143, and 145 divide the encapsulant 140, the conductive bumps 151, 152, and 153, the substrate 110, and a portion of the tape 1〇1 to form the semiconductor device 100a and the semiconductor device 100b attached to the tape 101. After forming at least one cutting slit, each of the conductive bumps is cut into two conductive bumps, for example, the conductive bumps 152 are cut into conductive bumps 152a and 152b, and the sealant 140 is also cut into a plurality of seals. The colloids are, for example, sealants 140a and 140b, and the substrate 110 is also divided into a plurality of substrates, for example, substrates 11a and 11b. The semiconductor device 100a includes a semiconductor element 120a, a substrate 110a, conductive bumps 151a and 152a, and a sealant 140a. The semiconductor device 100b includes a semiconductor device 120b, a substrate 110b, conductive electrodes 200935577 bumps 152b and 153b, and a sealant 140b. . The cutting depth D1 of the slits 141, 143 and 145 in the tape 101 is smaller than the thickness D2 of the tape ι. In addition, the grounding member 182 is disposed on the substrate unit sb1 with the cutting slit 143 spaced apart by a predetermined distance. The grounding member 183 and the cutting slit 143 are grounded at another predetermined distance. The element 183 is disposed on the substrate unit Sb2. In this step, after the at least one slit is formed, the conductive bumps originally wrapped in the sealant 14〇 are exposed. For example, the planes S1 and S2 of the conductive bump blocks 151a and 152a are exposed. In addition, by the formation of the slit, the surface 142 of the encapsulant 140, the plane S1 of the conductive bump 151a and the side 116 of the substrate 110a are substantially aligned; likewise, the surface 144 of the encapsulant 140, the conductive bump 152a The plane S2 and the surface 118 of the substrate 110a are also substantially aligned. Next, as shown in Fig. 3E, the conductive film 160 is directly formed on the sealants 140a and i4b and the slits 141, 143 and 145 to form the semiconductor device 100c and the semiconductor device 100d. Preferably, the formation of the conductive film 160 ® is selected, for example, from the group consisting of chemical vapor deposition, electroless plating, electrolytic plating, spray coating, printing, and deplating, and the constituent material of the conductive film 160 is |g Selected from the group consisting of copper, chromium, tin, gold, silver and nickel. The conductive film 160 covers the outer surfaces of the semiconductor device 100c and the encapsulant 140a, the planes S1 and S2' of the exposed conductive bumps 151a and 152a, and all the side surfaces I16 and U8 of the substrate 110a. Similarly, the conductive film I60 covers the semiconductor device 1〇〇d° in the same manner. Then, as shown in FIG. 3F, the tape is removed to separate the semiconductor 13 200935577 device 100c and the semiconductor device 100d. A semiconductor device of the structure shown in the drawing. Please refer to FIG. 4, which is a schematic diagram of an anti-electromagnetic interference package structure according to another preferred embodiment of the present invention. The difference between the package structure of the semiconductor device 200 and the package structure of the semiconductor device 100c of Fig. 2 is that the semiconductor device 220 is electrically connected to the substrate 210 by flip chip. Although the semiconductor device of the present invention is described by way of a wire bonding or flip chip connection to a substrate, the present invention is not limited thereto, and other electrical connection methods are also applicable to the present invention. The substrate 110 of the present invention may also be an array substrate or a long substrate having a plurality of substrate units arranged in an array or in a strip. Please refer to FIGS. 5A and 5B for a schematic view of the array substrate and the elongated substrate, respectively. As shown in Fig. 5A, the array substrate 2 has a plurality of substrate units 2a, and the adjacent two substrate units 2a are separated by a dicing street 2b. The semiconductor element 120a and the semiconductor element 120b may be respectively disposed on the adjacent two substrate units 2a for packaging. After the sealing process is completed, the conductive film can be formed after cutting along the cutting path 2b. As shown in Fig. 5B, the elongated substrate 4 has a plurality of substrate units 4a, each of which is separated by a dicing street 4b. Similarly, the semiconductor element 120a and the semiconductor element 120b may be respectively disposed on the adjacent two substrate units 4a for packaging. After the sealing process is completed, it can be cut along the cutting path 4b to form a conductive film. The package structure and the packaging method thereof disclosed in the above embodiments of the present invention are characterized in that a tape is attached to the back surface of a substrate having a plurality of semiconductor devices, and a conductive bump is disposed on the substrate in 200935577. After the sealing body is completed, the position of the conductive bump is aligned to cut, and then the conductive film is directly formed on the sealing body, and finally the semiconductor devices are separated. By using the tape, the plurality of semiconductor devices after the cutting are not scattered, and all the semiconductor devices after the cutting are still adhered to the tape. Thus, the conductive films of all the semiconductor devices can be simultaneously formed to save process time. Moreover, there is no need for secondary cutting. The encapsulant and substrate can be separated at the same time with one cut. In addition, since only one cut is required, the machine rate of cutting failure can be reduced to improve product yield. At the same time, as the number of times of cutting is reduced, the density of components on the substrate can be increased, and the utilization ratio of the substrate can be increased. In addition, the conductive film produced in a manner directly formed on the encapsulant can be adapted to various component sizes, and can also resist changes in temperature and humidity, thereby improving component reliability. In addition, due to the arrangement of the conductive bumps, the grounding member on the substrate can be disposed on the inner side of the substrate without being disposed on the edge of the substrate, so that the position of the grounding member on the substrate has a large design flexibility. In the above, the present invention has been disclosed in the preferred embodiments, and is not intended to limit the invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 15 200935577 [Simple description of the drawing] FIG. 1A is a schematic view showing a first cutting process of a conventional anti-electromagnetic interference package structure; FIG. 1B is a schematic view showing a second cutting process of a conventional anti-electromagnetic interference package structure; FIG. 1C is a schematic view showing a conventional anti-electromagnetic interference package structure obtained by using the processes of FIGS. 1A and 1B; FIG. 1D is a schematic view showing another conventional anti-electromagnetic interference package structure; FIG. 2 is a schematic view of the present invention. A schematic diagram of an anti-electromagnetic interference package structure according to a preferred embodiment; FIG. 3A-3F is a package flow chart of an anti-electromagnetic interference package structure according to a preferred embodiment of the present invention; FIG. 4 is a diagram showing a package according to the present invention. A schematic diagram of an anti-electromagnetic interference package structure according to another preferred embodiment; FIG. 5A is a schematic view showing an array substrate; and FIG. 5B is a schematic view showing a long strip substrate. [Main component symbol description] 2: Array substrate 2a, 4a: substrate unit 2b, 4b, 110a, 110b, 110c: dicing street 4: elongated substrate 10, 20: package component 16 200935577 10a, 10b: cutting blade 12 22, wafer 13, 23, 130: gold wire 14, 25, 140, 140a, 140b: sealant 15, 181, 182, 183, 184: grounding element 16, 151, 151a, 152, 152a, 152b, 153, 153b: conductive bumps 17, 21, 110, 110a, 110b, 210: substrate 〇 18, 160, 160a, 160b: conductive film 26: conductive case 27: adhesive 100a, 100b, 100c, 100d, 200: semiconductor device 101: Tapes 112, 114: Surfaces 111, 113, 116, 118, 142, 144: Side faces 120a, 120b, 220: Semiconductor element 141 141, 143, 145: Cutting slits SI, S2: Plane Sb1, Sb2: Substrate unit 17

Claims (1)

200935577 十、申請專利範圍： 1. 一種封裝結構，包括： 一基板，具有一第一表面、一第二表面、一第一側面 及一接地元件，該第一侧面連接該第一表面及該第二表 面； 一半導體元件，設置於該第一表面上並與該基板電性 連接； 一封膠體，覆蓋於該半導體元件上，該封膠體之一第 ⑩ 二侧面係與該基板之該第一側面實質上切齊； 一導電凸塊，設置於該第一表面上並具有一平面，該 封膠體之該第二侧面露出該導電凸塊之該平面，該平面係 與該封膠體之該第二側面實質上切齊，該導電凸塊係與該 接地元件電性連接；以及 一導電膜，直接形成於該封膠體之一外表面、該導電 凸塊外露之該平面及該基板之該側面上。 2. 如申請專利範圍第1項所述之封裝結構，其中該 ® 半導體元件係與該基板打線連接。 3. 如申請專利範圍第1項所述之封裝結構，其中該 半導體元件係以覆晶方式與該基板電性連接。 4. 如申請專利範圍第1項所述之封裝結構，其中該 接地元件包括係一接地走線或一接地銲墊。 5. 如申請專利範圍第4項所述之封裝結構，其中該 接地走線或該接地銲墊與該第一側面之間係具有一預定 距離。 18 200935577 6. 如申請專利範圍第1項所述之封裝結構，其中該 導電凸塊之高度小於該封膠體之厚度。 7. 如申請專利範圍第1項所述之封裝結構，其中該 導電膜的組成材料係由銘、銅、鉻、錫、金、銀及鎳所構 成的群組中選出。 8. 如申請專利範圍第1項所述之封裝結構，其中該 導電凸塊的組成材料係由錫膏及導電膠所構成的群組中 選出。 ❹ 9. 一種封裝方法，包括： (a)提供一基板，至少具有相鄰之一第一基板單元及一 第二基板單元，一第一半導體元件及一第二半導體元件係 配置於該第一基板單元及該第二基板單元上，該基板具有 一第一表面、一第二表面及一侧面，該側面連接該第一表 面及該第二表面，該第一半導體元件及該第二半導體元件 設置於該第一表面上並與該基板電性連接，一膠帶係貼附 於該第二表面上； ® (b)設置一導電凸塊於該第一表面上，該導電凸塊位 於該第一半導體元件及該第二半導體元件之間； (c) 形成一封膠體，該封膠體覆蓋該第一半導體元件、 該第二半導體元件及該導電凸塊及該第一表面； (d) 形成一切割狹縫，該切割狹縫分割該封膠體、該 導電凸塊、該基板及部分之該膠帶，以形成貼附於該膠帶 上之一第一半導體裝置及一第二半導體裝置，該切割狹縫 於該膠帶中之一切割深度係小於該膠帶之厚度，該導電凸 19 200935577 塊之一平面係外露於該封膠體；以及 (e)直接形成一導電膜於該封膠體及該切割狹縫上，以 使該導電膜覆蓋該第一半導體裝置及該第二半導體裝置 之該封膠體之一外表面、該導電凸塊外露之該平面及該基 板之該側面。 10.如申請專利範圍第9項所述之封裝方法，更包括： 除去該膠帶以分離覆蓋有該導電膜之該第一半導體 裝置及該第二半導體裝置。 ❹ 11.如申請專利範圍第9項所述之封裝方法，其中該 步驟(e)中，該導電膜的形成方式係由化學氣相沈積、無電 電鍍、電解電鍍、喷塗、印刷及濺鍍所構成的群組中選出。 12. 如申請專利範圍第9項所述之封裝方法，其中該 基板係為一陣列式基板，該陣列式基板具有以一陣列形式 排列之複數個基板單元。 13. 如申請專利範圍第9項所述之封裝方法，其中該 步驟(d)包括形成該切割狹縫於該基板之一切割道上，該導 ® 電凸塊係配置於該切割道上。 14. 如申請專利範圍第9項所述之封裝方法，其中該 導電膜的組成材料係由铭、銅、鉻、錫、金、銀及錄所構 成的群組中選出。 15. 如申請專利範圍第9項所述之封裝方法，其中， 該導電凸塊的組成材料係由錫骨及導電膠所構成的群組 中選出。 16. 如申請專利範圍第9項所述之封裝方法，更包括： 20 200935577 (f) 分別設置一第一接地元件及一第二接地元件於該 第一基板單元與該第二基板單元上； (g) 電性連接該導電凸塊與該第一接地元件；以及 (h) 電性連接該導電凸塊與該第二接地元件。 17. 如申請專利範圍第16項所述之封裝方法，其中， 於該步驟⑴中，係以該第一接地元件與該切割狹縫相隔一 第一預定距離的方式設置該第一接地元件於該第一基板 單元上，並以該第二接地元件與該切割狹縫相隔一第二預 ❹ 定距離設置的方式設置該第二接地元件於該第二基板單 元上。 18. 如申請專利範圍第9項所述之封裝方法，其中該 導電凸塊之高度小於該封膠體之厚度。 19. 如申請專利範圍第9項所述之封裝方法，其中該 第一半導體元件及該第二半導體元件係以打線連接的方 式與該基板電性連接。 20. 如申請專利範圍第9項所述之封裝方法，其中該 ⑩ 第一半導體元件及該第二半導體元件係以覆晶方式與該 基板電性連接。 21200935577 X. Patent application scope: 1. A package structure comprising: a substrate having a first surface, a second surface, a first side, and a grounding member, the first side connecting the first surface and the first a second surface; a semiconductor component disposed on the first surface and electrically connected to the substrate; a gel covering the semiconductor component, the first side of the encapsulant and the first of the substrate The side surface is substantially aligned; a conductive bump is disposed on the first surface and has a flat surface, the second side of the seal body exposing the plane of the conductive bump, the plane being the same as the sealant The two sides are substantially aligned, the conductive bumps are electrically connected to the grounding member, and a conductive film is directly formed on an outer surface of the sealant, the plane on which the conductive bump is exposed, and the side of the substrate on. 2. The package structure of claim 1, wherein the ® semiconductor component is wire bonded to the substrate. 3. The package structure of claim 1, wherein the semiconductor component is electrically connected to the substrate in a flip chip manner. 4. The package structure of claim 1, wherein the grounding element comprises a grounding trace or a grounding pad. 5. The package structure of claim 4, wherein the ground trace or the ground pad has a predetermined distance from the first side. The package structure of claim 1, wherein the height of the conductive bump is less than the thickness of the sealant. 7. The package structure of claim 1, wherein the constituent material of the conductive film is selected from the group consisting of: ingot, copper, chromium, tin, gold, silver, and nickel. 8. The package structure of claim 1, wherein the constituent material of the conductive bump is selected from the group consisting of solder paste and conductive paste. ❹ 9. A packaging method comprising: (a) providing a substrate having at least one adjacent first substrate unit and a second substrate unit, wherein a first semiconductor component and a second semiconductor component are disposed in the first On the substrate unit and the second substrate unit, the substrate has a first surface, a second surface and a side surface connecting the first surface and the second surface, the first semiconductor component and the second semiconductor component Provided on the first surface and electrically connected to the substrate, a tape attached to the second surface; (b) a conductive bump is disposed on the first surface, the conductive bump is located at the first surface Between a semiconductor component and the second semiconductor component; (c) forming a colloid covering the first semiconductor component, the second semiconductor component and the conductive bump and the first surface; (d) forming a cutting slit that divides the encapsulant, the conductive bump, the substrate and a portion of the tape to form a first semiconductor device and a second semiconductor device attached to the tape, the cutting The depth of the slit in the tape is less than the thickness of the tape, and one of the planes of the conductive protrusion 19 200935577 is exposed to the sealant; and (e) directly forming a conductive film on the sealant and the cutting slit Sewing the conductive film to cover an outer surface of the first semiconductor device and the second semiconductor device, an outer surface of the conductive bump, and the side surface of the substrate. 10. The packaging method of claim 9, further comprising: removing the tape to separate the first semiconductor device and the second semiconductor device covered with the conductive film.封装 11. The encapsulation method of claim 9, wherein in the step (e), the conductive film is formed by chemical vapor deposition, electroless plating, electrolytic plating, spraying, printing, and sputtering. Selected from the group formed. 12. The packaging method of claim 9, wherein the substrate is an array substrate having a plurality of substrate units arranged in an array. 13. The packaging method of claim 9, wherein the step (d) comprises forming the cutting slit on one of the dicing streets of the substrate, the conductive bump being disposed on the scribe line. 14. The encapsulation method of claim 9, wherein the constituent material of the electroconductive film is selected from the group consisting of: ingot, copper, chromium, tin, gold, silver, and recording. 15. The encapsulation method of claim 9, wherein the constituent material of the conductive bump is selected from the group consisting of tin and conductive paste. 16. The packaging method of claim 9, further comprising: 20 200935577 (f) respectively providing a first grounding component and a second grounding component on the first substrate unit and the second substrate unit; (g) electrically connecting the conductive bump to the first ground element; and (h) electrically connecting the conductive bump to the second ground element. 17. The packaging method of claim 16, wherein in the step (1), the first grounding element is disposed with the first grounding element at a first predetermined distance from the cutting slit. The second grounding element is disposed on the first substrate unit and the second grounding element is disposed on the second substrate unit in a manner that the second grounding element is disposed at a second predetermined distance from the cutting slit. 18. The method of packaging of claim 9, wherein the height of the conductive bump is less than the thickness of the sealant. 19. The packaging method of claim 9, wherein the first semiconductor component and the second semiconductor component are electrically connected to the substrate by wire bonding. 20. The packaging method of claim 9, wherein the 10 first semiconductor component and the second semiconductor component are electrically connected to the substrate in a flip chip manner. twenty one
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