CN101339939B - Encapsulation construction and encapsulation method - Google Patents
Encapsulation construction and encapsulation method Download PDFInfo
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- CN101339939B CN101339939B CN2008102136138A CN200810213613A CN101339939B CN 101339939 B CN101339939 B CN 101339939B CN 2008102136138 A CN2008102136138 A CN 2008102136138A CN 200810213613 A CN200810213613 A CN 200810213613A CN 101339939 B CN101339939 B CN 101339939B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
A package structure comprises a substrate, a semiconductor assembly, a sealing glue and a conductive film. The substrate possesses a first surface, a second surface, a first side surface and an earthing assembly. The first side surface connects first surface and second surface. The earthing assembly is disposed inside of substrate and exposed at the first side surface and possesses a plane. The semiconductor assembly is disposed at the first surface and electrically connected with substrate. The sealing glue is covered on semiconductor assembly; a second side surface of sealing glue is trimming with plane. The conductive film directly forms on one external surface of sealing glue, exposed plane of earthing assembly and the first side surface of substrate; the conductive film is electrically connected with earthing assembly.
Description
[technical field]
The invention relates to a kind of encapsulating structure and method for packing thereof, and particularly relevant for a kind of anti-electromagnetic interference encapsulating structure and method for packing thereof.
[background technology]
In general, the semiconductor subassembly encapsulation is that circuit is arranged on the circuit substrate, for example on printed circuit board (PCB) or the ceramic substrate.The usefulness of its circuit may be adversely affected because of electromagnetic interference (EMI).Electromagnetic interference (EMI) is signal interference or the noise that produces owing to the energy of electromagnetic field radiation.Because the density that electronic building brick is put in the system is more and more higher, relevant frequency of operation also toward higher frequency range development, so unnecessary radiated noise is more obvious, and then causes more serious electromagnetic interference.Therefore, the multiple encapsulating structure that prevents electromagnetic interference that utilizes electric conducting material to form shielding construction is developed.
Existing a kind of anti-electromagnetic interference encapsulating structure is after assembly carries out the adhesive body processing procedure, forms conducting film again on adhesive body behind the cutting adhesive body.Then, again substrate cut is formed independently package assembling.Please refer to Figure 1A and Figure 1B, it illustrates first road cutting processing procedure of a kind of anti-electromagnetic interference encapsulating structure of tradition and the schematic diagram of second road cutting processing procedure respectively.Shown in Figure 1A, chip 12 electrically connects with gold thread 13 and substrate 17, and conductive projection 16 electrically connects with the grounding assembly 15 of substrate 17.In this step with cutter 10a with adhesive body 14 cutting and separating, but cutting substrate 17 not.Then, shown in Figure 1B, form conducting film 18.Conducting film 18 is coated on the adhesive body 14, and wherein conductive projection 16 couples with conducting film 18.In this step, with the cutter 10b cutting substrate 17 of thinner thickness, to form independently package assembling 10, shown in 2 figure.Owing to this kind encapsulating structure must be through cutting twice in encapsulation process, because of the cutting failure causes the yield reduction, because twice cutting processing procedure can be wasted more baseplate material, so the utilance of substrate is also relatively low except easily.
The anti-electromagnetic interference encapsulating structure of existing another kind, be with conductive shell for example a crown cap be arranged on the assembly of finishing encapsulation with viscose.As shown in Figure 3, it illustrates the schematic diagram of the another kind of anti-electromagnetic interference encapsulating structure of tradition.Package assembling 20 comprises substrate 21, chip 22, adhesive body 25, conductive shell 26 and a plurality of surperficial interconnection technique (SMT) assembly 28.Chip 22 electrically connects substrate 21 with gold thread 23.Conductive shell 26 is arranged on the adhesive body 25 with viscose 27.Surface interconnection technique assembly 28 is disposed on the substrate 21.But this kind practice is with the fixing conductive shell of viscose, except the complexity that increases processing procedure and the time, and the problem that causes conductive shell to come off because temperature, humidity cause viscose character to change easily.In addition, conductive shell must cooperate with the size of packaging part, and the packaging part of different size must be made different housings, increases the degree of difficulty that conductive shell is made.
Therefore, how to overcome the shortcoming of conventional package structure, producing high yield, the package assembling that has anti-electromagnetic interference cheaply is one of problem of endeavouring of industry.
[summary of the invention]
The present invention is relevant for a kind of encapsulating structure and method for packing thereof, directly forms conducting film in encapsulation process, can reach to simplify the encapsulation flow process, save the encapsulation time to reduce cost and to improve the advantage of process rate.The present invention more applicable to the packaging part of various sizes, also can save baseplate material simultaneously, improves packaging part density to improve the substrate utilization rate.
According to the present invention, a kind of encapsulating structure is proposed, comprise a substrate, semiconductor assembly, an adhesive body and a conducting film.Substrate has a relative first surface and a second surface, one first side and a ground connection perforation (groundvia), and first side connects first surface and second surface.Semiconductor subassembly is arranged on the first surface and with substrate and electrically connects.The ground connection perforation is arranged at substrate inside and exposes to first side and be somebody's turn to do and be extended to this second surface and be had a plane by this first surface.Adhesive body is covered on the semiconductor subassembly, and one second side of adhesive body and the plane of grounding assembly trim in fact.Conducting film directly be formed in the outer surface, this ground connection perforation of adhesive body extend to this second surface by this first surface and expose to the plane of this first side and the side of substrate on, conducting film and grounding assembly electrically connect.
According to the present invention, a kind of method for packing is proposed, comprise the following steps.At first, one substrate is provided, at least have one first adjacent base board unit and one second base board unit, one first semiconductor subassembly and one second semiconductor subassembly are disposed on first base board unit and second base board unit, and substrate has a first surface, a second surface and a grounding assembly.First surface is relative with second surface, and grounding assembly is between first surface and second surface.First semiconductor subassembly and second semiconductor subassembly are arranged on the first surface and with substrate and electrically connect, and grounding assembly is between first semiconductor subassembly and second semiconductor subassembly.One adhesive tape is attached on the second surface.Then, form an adhesive body, adhesive body covers first semiconductor subassembly, second semiconductor subassembly and first surface.Then, form a cutting slit, the cutting slit is cut apart the adhesive tape of adhesive body, substrate, grounding assembly and part, is attached at first semiconductor device of 1 on the adhesive tape and one second semiconductor device with formation.The cutting degree of depth of cutting slit in adhesive tape is less than the thickness of adhesive tape, and a plane of grounding assembly exposes to adhesive body.Then, directly form a conducting film on adhesive body and cutting slit, so that conducting film covers the outer surface of the adhesive body of first semiconductor device and second semiconductor device, plane that grounding assembly exposes and the side of substrate.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
[description of drawings]
Figure 1A illustrates the schematic diagram of first road cutting processing procedure of a kind of anti-electromagnetic interference encapsulating structure of tradition;
Figure 1B illustrates the schematic diagram of second road cutting processing procedure of a kind of anti-electromagnetic interference encapsulating structure of tradition;
Fig. 2 illustrates the schematic diagram of the anti-electromagnetic interference encapsulating structure of resulting tradition behind the processing procedure that uses Figure 1A and 1B;
Fig. 3 illustrates the schematic diagram of the another kind of anti-electromagnetic interference encapsulating structure of tradition;
Fig. 4 illustrates the schematic diagram according to a kind of anti-electromagnetic interference encapsulating structure of a preferred embodiment of the present invention;
Fig. 5 A-5E illustrates the encapsulation flow chart according to a kind of anti-electromagnetic interference encapsulating structure of a preferred embodiment of the present invention;
Fig. 6 illustrates the schematic diagram according to a kind of anti-electromagnetic interference encapsulating structure of another preferred embodiment of the present invention;
Fig. 7 A illustrates the schematic diagram of array type substrate; And
Fig. 7 B illustrates the schematic diagram of long strip type substrate.
[embodiment]
The present invention proposes a kind of encapsulating structure, comprises a substrate, semiconductor assembly, an adhesive body and a conducting film.Substrate has a first surface, a second surface, one first side and a grounding assembly, and first side connects first surface and second surface.Semiconductor subassembly is arranged on the first surface and with substrate and electrically connects.Grounding assembly is arranged at substrate inside and exposes to first side, and has a plane.Adhesive body is covered on the semiconductor subassembly, and one second side of adhesive body and the plane of grounding assembly trim in fact.Conducting film directly is formed on the side of an outer surface of adhesive body, plane that grounding assembly exposes and substrate, and conducting film and grounding assembly electrically connect.Now be described as follows for embodiment.
Please refer to Fig. 4, it illustrates the schematic diagram according to a kind of anti-electromagnetic interference encapsulating structure of a preferred embodiment of the present invention.As shown in Figure 4, the encapsulating structure of semiconductor device 100c comprises substrate 110a, semiconductor subassembly 120a, adhesive body 140a, and conducting film 160a.Substrate 110a has surface 112, surface 114, side 116 and 118 and grounding assembly 151a and 152a, and side 116,118 connects surface 112 and surperficial 114 respectively. Grounding assembly 151a and 152a are arranged at substrate 110a inside and have a planar S 1, S2 respectively, and planar S 1, S2 also expose to side 116 and 118 respectively.Preferably, grounding assembly 151a, 152a are the ground connection perforation, and the height of grounding assembly 151a, 152a equals the thickness of substrate 110a in fact, and extend to surface 114 by surface 112.
Conducting film 160a directly is formed at flat that outer surface, grounding assembly 151a, the 152a of adhesive body 140a expose On the side 116 and 118 of face S1 and S2 and substrate 110a, conducting film 160a and grounding assembly 151a and 152a Electrically connect.Preferably, the composition material of conducting film 160a is by selecting in the group that aluminium, copper, chromium, tin, gold, silver and nickel constituted.Therefore, grounding assembly 151a and the 152a of the inner 110a of substrate contact with conducting film 160a, and semiconductor device 100c can finish ground connection.
Method for packing as for encapsulating structure of the present invention please refer to Fig. 5 A-5E, and it illustrates the encapsulation flow chart according to a kind of anti-electromagnetic interference encapsulating structure of a preferred embodiment of the present invention.
At first, shown in 5A figure, provide a substrate 110, substrate 110 has adjacent base board unit Sb1 and Sb2, disposes a plurality of semiconductor subassemblies on the substrate 110, for example is semiconductor subassembly 120a and 120b, is disposed at respectively on base board unit Sb1 and the Sb2.Substrate 110 has surface 112 and surface 114, and surface 112 is relative with surface 114.Comprise at least one grounding assembly between surface 112 and the surface 114, for example comprise grounding assembly 151,152 and 153.Wherein, grounding assembly 152 is between semiconductor subassembly 120a and 120b.In the present embodiment, grounding assembly 151,152 and 153 height equal the thickness of substrate 110a in fact.Preferably, grounding assembly 151,152 and 153 is the ground connection perforation, and extends to surface 114 by surface 112.
Then, shown in 5B figure, form adhesive body 140.Adhesive body 140 covers semiconductor subassembly 120a, semiconductor subassembly 120b and surface 112.
Then, shown in 5C figure, all cut slit at least in formation, for example are cutting slits 141,143 and 145.Cutting slit 141,143 and 145 is cut apart the adhesive tape 101 of adhesive body 140, grounding assembly 151,152 and 153, substrate 110 and part, is attached at semiconductor device 100a and semiconductor device 100b on the adhesive tape 101 with formation.In forming after all cut slit at least, each grounding assembly is cut into two grounding assemblies, and for example grounding assembly 152 is cut into grounding assembly 152a and 152b, and grounding assembly 151 and 153 also is cut and forms grounding assembly 151a and 153b.Adhesive body 140 also is cut into a plurality of adhesive bodies, for example be adhesive body 140a and 140b, and substrate 110 also is divided into a plurality of substrates, for example is substrate 110a and 110b.Semiconductor device 100a comprises semiconductor subassembly 120a, substrate 110a, grounding assembly 151a and 152a, and adhesive body 140a; Semiconductor device 100b comprises semiconductor subassembly 120b, substrate 110b, grounding assembly 152b and 153b, and adhesive body 140b.The depth of cut D1 of cutting slit 141,143 and 145 in adhesive tape 101 is less than the thickness D2 of adhesive tape 101.
In this step, in forming after all cut slit at least, the grounding assembly that is arranged in substrate will expose out.For example, planar S 1 and the S2 of grounding assembly 151a and 152a expose.In addition, by the formation of cutting slit, the side 116 of the surface 142 of adhesive body 140, the planar S 1 of grounding assembly 151a and substrate 110a trims in fact; Same, the surface 118 of the surface 144 of adhesive body 140, the planar S 2 of grounding assembly 152a and substrate 110a also trims in fact.
Then, shown in 5D figure, directly form conducting film 160 on adhesive body 140a and 140b and cutting slit 141,143 and 145, to form semiconductor device 100c and semiconductor device 100d.Preferably, the generation type of conducting film 160 is for example by selecting in chemical vapour deposition (CVD), electroless-plating, metallide, spraying, printing and the group that sputter constituted, and the composition material of conducting film 160 is by selecting in the group that aluminium, copper, chromium, tin, gold, silver and nickel constituted.Conducting film 160 covers planar S 1 and the S2 of semiconductor device 100c and the outer surface of adhesive body 140a, the grounding assembly 151a that exposes and 152a, and whole sides 116 and 118 of substrate 110a.Same, conducting film 160 also covers semiconductor device 100d in an identical manner.
Then, shown in 5E figure, remove adhesive tape 101, so, can obtain the semiconductor device of structure shown in Figure 4 with separating semiconductor device 100c and semiconductor device 100d.
Please refer to Fig. 6, it illustrates the schematic diagram according to a kind of anti-electromagnetic interference encapsulating structure of another preferred embodiment of the present invention.The difference of the encapsulating structure of the semiconductor device 100c of the encapsulating structure of semiconductor device 200 and Fig. 4 is that semiconductor subassembly 220 is to cover crystal type and substrate 210 electric connections.Be connected to example with substrate and do explanation though semiconductor subassembly of the present invention connects with routing or covers crystal type, so the present invention is not limited to this, and other electric connection mode is also applicable to the present invention.
And substrate 110 of the present invention also can be an array type substrate or long strip type substrate, has a plurality of base board units of arranging with an array form or bar row form.Please refer to 7A and Fig. 7 B, it illustrates the schematic diagram of array type substrate and long strip type substrate respectively.Shown in Fig. 7 A, array type substrate 2 has a plurality of base board unit 2a, and two adjacent base board unit 2a separate with Cutting Road 2b.Semiconductor subassembly 120a and semiconductor subassembly 120b can be arranged at respectively on two adjacent base board unit 2a and encapsulate, and the Cutting Road 2b of adjacent two base board unit 2a is then by the grounding assembly top, for example by grounding assembly 152 tops.After the adhesive body processing procedure is finished, can after Cutting Road 2b cutting, form conducting film again.
Shown in Fig. 7 B, long strip type substrate 4 has a plurality of base board unit 4a, and each base board unit 4a separates with Cutting Road 4b.Same, semiconductor subassembly 120a and semiconductor subassembly 120b can be arranged at respectively on two adjacent base board unit 4a and encapsulate, and the Cutting Road 4b of adjacent two base board unit 4a is then by the grounding assembly top, for example by grounding assembly 152 tops.After the adhesive body processing procedure is finished, can after Cutting Road 4b cutting, form conducting film again.
Disclosed encapsulating structure of the above embodiment of the present invention and method for packing thereof are that adhesive tape is attached to the substrate back with a plurality of semiconductor devices, and substrate inside has ground connection perforation or other grounding assembly.And after adhesive body is finished, aim at the position at ground connection perforation or other grounding assembly place and cut, directly form conducting film again on adhesive body, again each semiconductor device is separated at last.By using adhesive tape, a plurality of semiconductor devices after cutting can not be scattered, and all semiconductor devices after the cutting still are attached on the adhesive tape.So, can allow the conducting film of all semiconductor devices form simultaneously, to save the processing procedure time.And, do not need secondary cut, only needing once, cutting can separate adhesive body and substrate simultaneously.In addition,, more can reduce the probability of cutting failure, to improve the product yield owing to only need once cut.Also because of the cutting number of times reduces, can improve the configuration density of assembly on the substrate, and increase the utilance of substrate simultaneously.
In addition, the conducting film so that the mode that directly is formed on the adhesive body produces can adapt to various size of components, also can resist the variation of temperature, humidity simultaneously, the lifting subassembly reliability.In addition, utilize in the substrate original ground connection perforation can with conducting film ground connection, do not need to be provided with in addition grounding assembly, can save Material Cost and fabrication steps.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (16)
1. encapsulating structure comprises:
One substrate, have a relative first surface and a second surface, one first side and a ground connection perforation (ground via), this first side connects this first surface and this second surface, wherein this ground connection perforation is arranged at this substrate inside, and has a plane that is exposed to this first side by this first surface with extending to this second surface;
The semiconductor assembly is arranged on this first surface and electrically connects with this substrate;
One adhesive body is covered on this semiconductor subassembly, and one second side and this plane of this adhesive body trim; And
One conducting film directly is formed in the outer surface, this ground connection perforation of this adhesive body by this first surface and exposes on this side of the plane of this first side and substrate with extending to this second surface.
2. encapsulating structure according to claim 1 is characterized in that, this semiconductor subassembly is connected with this substrate routing.
3. encapsulating structure according to claim 1 is characterized in that, this semiconductor subassembly electrically connects to cover crystal type and this substrate.
4. encapsulating structure according to claim 1 is characterized in that, the height of this ground connection perforation equals the thickness of this substrate.
5. encapsulating structure according to claim 1 is characterized in that the composition material of this conducting film is by selecting in the group that aluminium, copper, chromium, tin, gold, silver and nickel constituted.
6. method for packing comprises:
(a) provide a substrate, at least have one first adjacent base board unit and one second base board unit, one first semiconductor subassembly and one second semiconductor subassembly are disposed on this first base board unit and this second base board unit, this substrate has a first surface, one second surface and a grounding assembly, this first surface is relative with this second surface, this grounding assembly is between this first surface and this second surface, this first semiconductor subassembly and this second semiconductor subassembly are arranged on this first surface and with this substrate and electrically connect, this grounding assembly is between this first semiconductor subassembly and this second semiconductor subassembly, and an adhesive tape is attached on this second surface;
(b) form an adhesive body, this adhesive body covers this first semiconductor subassembly, this second semiconductor subassembly and this first surface;
(c) form a cutting slit, this cutting slit is cut apart this adhesive tape of this adhesive body, this substrate, this grounding assembly and part, be attached at one first semiconductor device and one second semiconductor device on this adhesive tape with formation, the cutting degree of depth of this cutting slit in this adhesive tape is less than the thickness of this adhesive tape, and a plane of this grounding assembly exposes to this substrate; And
(d) directly form a conducting film on this adhesive body and this cutting slit, so that this conducting film covers the outer surface of this adhesive body of this first semiconductor device and this second semiconductor device, this plane that this grounding assembly exposes and this side of this substrate.
7. method for packing according to claim 6 is characterized in that, more comprises:
Remove this adhesive tape is coated with this conducting film with separation this first semiconductor device and this second semiconductor device.
8. method for packing according to claim 6 is characterized in that, in this step (d), the generation type of this conducting film is by selecting in chemical vapour deposition (CVD), electroless-plating, metallide, spraying, printing and the group that sputter constituted.
9. method for packing according to claim 6 is characterized in that, this substrate is an array type substrate, and this array type substrate has a plurality of base board units of arranging with an array form.
10. method for packing according to claim 6 is characterized in that, this step (c) comprises this cutting slit of formation on a Cutting Road of this substrate, and this Cutting Road is by this grounding assembly.
11. method for packing according to claim 6 is characterized in that, the composition material of this conducting film is by selecting in the group that aluminium, copper, chromium, tin, gold, silver and nickel constituted.
12. method for packing according to claim 6 is characterized in that, this grounding assembly is a ground connection perforation.
13. method for packing according to claim 12 is characterized in that, this ground connection perforation extends to this second surface by this first surface.
14. method for packing according to claim 6 is characterized in that, the height of this grounding assembly equals the thickness of this substrate.
15. method for packing according to claim 6 is characterized in that, this first semiconductor subassembly and this second semiconductor subassembly electrically connect with routing ways of connecting and this substrate.
16. method for packing according to claim 6 is characterized in that, this first semiconductor subassembly and this second semiconductor subassembly electrically connect to cover crystal type and this substrate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US689408P | 2008-02-05 | 2008-02-05 | |
| US61/006,894 | 2008-02-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101339939A CN101339939A (en) | 2009-01-07 |
| CN101339939B true CN101339939B (en) | 2011-08-24 |
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| CN2008102136138A Active CN101339939B (en) | 2008-02-05 | 2008-08-22 | Encapsulation construction and encapsulation method |
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| CN (1) | CN101339939B (en) |
| TW (1) | TWI358116B (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010219210A (en) * | 2009-03-16 | 2010-09-30 | Renesas Electronics Corp | Semiconductor device, and method of manufacturing the same |
| CN101930969B (en) * | 2009-06-22 | 2012-06-13 | 日月光半导体制造股份有限公司 | Semiconductor package with electromagnetic interference protection cover |
| US8575006B2 (en) | 2009-11-30 | 2013-11-05 | Alpha and Omega Semiconducotr Incorporated | Process to form semiconductor packages with external leads |
| TWI397139B (en) * | 2009-12-01 | 2013-05-21 | Alpha & Omega Semiconductor | Process for packaging semiconductor device with external leads |
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-
2008
- 2008-04-30 TW TW097115985A patent/TWI358116B/en active
- 2008-08-22 CN CN2008102136138A patent/CN101339939B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101339939A (en) | 2009-01-07 |
| TW200935576A (en) | 2009-08-16 |
| TWI358116B (en) | 2012-02-11 |
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