CN102593046B - 制造半导体器件封装件的方法 - Google Patents

制造半导体器件封装件的方法 Download PDF

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Publication number
CN102593046B
CN102593046B CN201110463335.3A CN201110463335A CN102593046B CN 102593046 B CN102593046 B CN 102593046B CN 201110463335 A CN201110463335 A CN 201110463335A CN 102593046 B CN102593046 B CN 102593046B
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hole
layer
patterning
semiconductor device
interconnection
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CN102593046A (zh
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P·A·麦康内李
A·V·高达
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General Electric Co
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General Electric Co
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Abstract

提供制造半导体器件封装件的方法。该方法包括：提供叠层，其包括设置在第一金属层上的介电膜，所述叠层具有介电膜外表面和第一金属层外表面；根据预定图案形成多个延伸通过该叠层的通孔；将一个或多个半导体器件附连到该介电膜外表面使得半导体器件在附连后接触一个或多个通孔；在该第一金属层外表面和多个通孔的内表面上设置导电层来形成互连层，其包括该第一金属层和所述导电层；以及根据预定电路配置图案化该互连层来形成图案化的互连层，其中该图案化的互连层的一部分延伸通过一个或多个通孔来形成与半导体器件的电接触。还提供半导体器件封装件。

Description

制造半导体器件封装件的方法
技术领域
本发明大体上涉及电子封装技术，并且更具体地涉及能适用于功率半导体器件的电子封装技术。
背景技术
例如集成门双极晶体管(IGBT)、金属氧化物半导体场效应晶体管(MOSFET)、MOS控制晶闸管(MCT)等先进的半导体器件技术为在广泛的功率水平中的大范围应用提供提高的热和电性能。然而，为了充分使用这样的器件的能力，需要提供改进的封装设计。
典型的半导体模块设计采用引线接合用于将半导体器件连接到电力总线和控制端子。这些半导体器件通常焊接到金属化的绝缘陶瓷衬底上并且随后接合到均热器(heat spreader)。典型地，注入模塑的聚合物壳覆盖模块，仅暴露输入/输出和控制端子以及均热器。均热器附连到散热器(heat sink)并且均热器与散热器之间的热接触通过热膏或导热聚合物实现。基于引线接合的半导体模块设计的劣势包括相对高的寄生阻抗、大的体积和重量、高的热阻和有限的可靠性(主要由于引线接合引起)。
电力覆盖(POL)技术消除使用引线接合并且提供优于基于引线接合的功率模块封装的明显的优势，例如，更高的封装密度、更低的封装寄生、提高的可靠性、更低的重量、更小的尺寸以及更高的效率。典型的电力覆盖制造工艺牵涉使用在框架上拉伸的介电膜。粘合层施加于该介电膜，在其上通过激光烧蚀形成通孔，接着将半导体器件附连到该介电膜。接着通过在该介电膜上电镀厚的铜层并且将厚的铜层电镀进入通孔而在膜上金属化电路并且形成电路。然后将所得的封装件附连到衬底。在一些实例中，用于电连接金属化层与衬底的“馈通”结构或“垫片(shim)”可分开地附连到介电膜。因此，在POL技术中，通过金属化的通孔实现到器件的电力和控制电路，从而排除对接合引线的需要。
然而，目前的POL制造工艺可因为步骤数和每个步骤牵涉的时间而仍提出经济和技术挑战。例如，金属化步骤典型地牵涉电镀几小时来实现期望的铜厚度用于当前处理，其明显地增加POL工艺的成本。此外，框架(frame)的使用降低用于封装的可用面积并且还增加加工步骤到POL制造工艺。分开的铜垫片的使用可进一步增加制造步骤的成本并且可提出技术挑战，例如，更低的粘合。
从而，需要简化POL制造工艺以便提供克服与当前POL工艺关联的一个或多个劣势的成本有效的半导体器件封装制造工艺。
发明内容
提供本发明的实施例以满足这些和其他需要。一个实施例是制造半导体器件封装件的方法。该方法包括：提供叠层，其包括设置在第一金属层上的介电膜，所述叠层具有介电膜外表面和第一金属层外表面；根据预定图案形成多个延伸通过该叠层的通孔；将一个或多个半导体器件附连到该介电膜外表面使得半导体器件在附连后接触一个或多个通孔；在该第一金属层外表面和多个通孔的内表面上设置导电层来形成互连层，其包括该第一金属层和该导电层；以及根据预定电路配置图案化该互连层来形成图案化的互连层，其中该图案化的互连层的一部分延伸通过一个或多个通孔来形成与半导体器件的电接触。
另一个实施例是制造半导体器件封装件的方法。该方法包括：提供叠层，其包括介于第一金属层和第二金属层之间的介电膜，所述叠层具有第一金属层外表面和第二金属层外表面；根据预定图案图案化该第二金属层来形成图案化的第二金属层；根据预定图案形成多个延伸通过该叠层的通孔；将一个或多个半导体器件附连到该图案化的第二金属层的一部分的第二金属层外表面；在该第一金属层外表面和一个或多个通孔的内表面上设置导电层来形成互连层，其包括该第一金属层和该导电层；以及根据预定电路配置图案化该互连层来形成图案化的互连层，其中该图案化的互连层的一部分延伸通过一个或多个通孔来形成与半导体器件的电接触。
再另一个实施例是半导体器件封装件。该半导体器件封装件包括：叠层，其包括设置在介电膜上的第一金属层；根据预定图案延伸通过该叠层的多个通孔；一个或多个半导体器件，其附连到该介电膜使得该半导体器件接触一个或多个通孔；设置在介电膜上的图案化的互连层，所述图案化的互连层包括第一金属层和导电层的一个或多个图案化区域，其中该图案化的互连层的一部分延伸通过一个或多个通孔来形成与该半导体器件的电接触。该图案化的互连层包括顶部互连区和通孔互连区，其中封装互连区具有大于该通孔互连区的厚度的厚度。
附图说明
当下列详细说明参照附图阅读时，本发明的这些和其他特征、方面和优势将变得更好理解，其中：
图1是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
图2是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
图3是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
图4是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
图5是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
图6是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
图7是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
图8是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
图9是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
图10是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
图11是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
图12是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
图13是根据本发明的一个实施例的制造工艺步骤的截面侧视图。
具体实施方式
如在下文详细论述的，本发明的实施例中的一些提供用于使用预金属化的介电膜制造半导体器件封装件的方法。
如在本文中在整个说明书和权利要求书中使用的近似语言可应用于修饰任何定量表示，其可以获准地改变而不引起与之有关的基本功能中的变化。因此，由例如“大约”等术语或多个术语修饰的值不限于规定的精确值。在一些实例中，该近似语言可对应于用于测量该值的仪器的精确度。
在下列说明书和权利要求书中，单数形式“一”和“该”包括复数个指代物，除非上下文清楚地另外指明。
如本文使用的，术语“可”和“可以是”指示：在一组情况内发生的可能性；具有规定的性质、特性或功能；和/或通过表达与修饰的动词关联的能力、性能或可能性中的一个或多个来修饰另一个动词。因此，“可”和“可以是”的使用指示所修饰的术语对于指示的能力、功能或使用是明显适当的、有能力的或合适的，但考虑在一些情况下该修饰的术语可能有时不是适当的、有能力的或合适的。例如，在一些情况下，可以预期事件或能力，而在其他情况下该事件或能力不能发生，该区别由术语“可”和“可以是”正确表达。
示范性半导体器件封装件根据下列工艺步骤参照附图描述。本文给出的任何尺寸和部件值是示范性的，仅用于说明用途，并且不意在限制本文描述的本发明的范围。图1-13是根据本发明的一些实施例的制造工艺的步骤的截面侧视图。如本文使用的，术语“设置在...上”或“附连到...”指互相直接接触地设置或附连或通过具有其之间的介入层而互相间接接触地设置或附连的层或器件。
如在图1中图示的，方法包括提供叠层100，其包括设置在第一金属层130上的介电膜120。如在图1中图示的，该叠层100进一步包括介电膜外表面122和第一金属层外表面132。该介电膜120进一步包括内表面121并且该第一金属层包括内表面131，使得该第一金属层内表面131设置成邻近该介电层内表面121。尽管叠层100图示为具有矩形形状，叠层100可具有适合用于形成本申请的结构的任何期望的形状或大小。
在一个实施例中，介电膜120包括选择成具有特定热、结构和电性质、适合用于在半导体封装结构中使用的有机介电材料。在一些实施例中，介电膜120具有低模量(高顺应性)、低的x、y和z轴热膨胀系数(CTE)和高的玻璃化转变温度(Tg)或熔化温度(Tm)，从而提高所得的半导体器件封装件的热和结构可靠性。在一个实施例中，介电膜120包括稳定用于在高于150℃温度连续使用的电绝缘聚合物。适合的材料的非限制性示例包括：聚酰亚胺，例如KAPTON(E.I.DuPont de Nemours and Co.的商标)；聚醚酰亚胺，例如ULTEM(General Electric Company的商标)；聚喹啉；聚喹喔啉；聚醚酮；和双马来酰亚胺-三嗪树脂。在一个特定实施例中，介电膜120包括聚酰亚胺，例如KAPTON。
在一个实施例中，第一金属层130包括铜并且通过在介电层120上设置第一金属层130提供叠层100。在一些实施例中，第一金属层130可直接附连到介电膜120，即，在介电膜120和第一金属层130之间可没有粘合层存在。在一些其他实施例中，粘合层(未示出)介于介电膜120和第一金属层130之间。在一些实施例中，第一金属层可使用滚涂(roll-on)制造法层叠在介电膜上。
在一个实施例中，介电膜120具有从大约1微米至大约1000微米范围中的厚度。在另一个实施例中，介电膜120具有从大约5微米至大约200微米范围中的厚度。在一个实施例中，第一金属层具有从大约10微米至大约200微米范围中的厚度。在另一个实施例中，第一金属层具有从大约25微米至大约150微米范围中的厚度。在特定实施例中，第一金属层具有从大约50微米至大约125微米范围中的厚度。如在下文详细描述的，通过提供包括第一金属层130(其具有期望的厚度)的叠层100，随后导电层沉积和通孔金属化所花的时间可因此减少。
如先前指出的，叠层100不包括框架并且因此方法不牵涉为介电膜120装框架的步骤。在一些实施例中，第一金属层130为介电膜120提供结构支撑并且对由此制造的半导体器件封装件提供尺寸稳定性。此外，第一金属层130可在缺乏典型地用于电力覆盖制造工艺的载体框架情况下提供便于拿捏和便于运输。无框架介电膜有利地提供增加的可用面积用于附连半导体器件，并且因此大量的半导体器件可使用本发明的方法附连。
如在图2中图示的，方法进一步包括根据预定图案形成多个延伸通过叠层100的通孔150。多个通孔(例如代表性通孔150)可通过例如标准机械冲压工艺、置于水中的冲压(water set punch)工艺、化学蚀刻工艺、等离子体蚀刻、反应离子蚀刻或激光加工而形成通过叠层100。在一个实施例中，通孔150通过激光烧蚀形成通过叠层。通孔图案由要附连的器件的数量、器件接触盘的数量、器件接触盘的大小和期望的电路配置中的一个或多个确定。如在图2中示出的，多个通孔150进一步包括通孔内表面152。
在一个实施例中，如在图2中图示的，通孔150具有带有垂直侧壁的圆形形状。然而，通孔150的形状没有限制并且通孔可包括任何适合的形状。例如，通孔150可具有带有圆角的椭圆形形状或方形形状，或另一个更复杂的形状。在另一个实施例中，通孔150具有锥形侧壁。通孔的大小和数量可部分取决于接触盘210和220的大小以及器件200的电流要求。例如，如在图4中图示的，在一个示范性实施例中，传导层180通过两个通孔来接触接触盘210以及通过一个通孔来接触接触盘220，以便满足器件200的期望的电流要求。在另一个实施例中，三个或以上的通孔150可接触接触盘210。在备选实施例中，可采用更少的具有更大开口的通孔来满足相同的期望的电流要求。例如，在图4的实施例中，单个大的通孔可以代替多个通孔与接触盘210接触。在一个实施例中，多个通孔150具有从大约25微米至大约10000微米范围中的直径。在另一个实施例中，多个通孔150具有大于大约10000微米的范围中的直径。在再另一个实施例中，多个通孔150具有从大约2000微米至大约40000微米范围中的直径。在一个实施例中，第一金属层130可提高叠层100的尺寸稳定性，从而实现对于通孔150更紧密的间隔。增加通孔150密度可有利地减少电阻损耗和电流拥挤。形成通过通孔到单个接触盘的多个连接提供电连接，其可优于单个引线接合。
方法进一步包括在介电层120和器件200之间插入粘合层160。在一个实施例中，如在图3中示出的，方法包括在介电外表面122上设置粘合层160。该粘合层160可在通孔形成之前或之后施加。在一些实施例中，保护脱模层(未示出)可施加在该粘合层160上以在通孔形成过程期间使该粘合层160保持干净。粘合层160可通过任何适合的方法施加于介电外表面122。例如，粘合层160可通过旋涂、弯月面涂覆、喷涂、真空沉积或叠层技术施加。在图3中图示的实施例中，粘合层160在通孔150形成之后施加于介电膜外表面122。在备选实施例中，粘合层160在通孔150形成之前施加于介电膜外表面122。通孔150然后使用例如上文提到的机械钻孔、激光处理、等离子体蚀刻、反应离子蚀刻或化学蚀刻技术等任何适合的技术形成通过介电膜120和粘合层160两者。
在另一个实施例中，方法包括在器件200的有效表面202上设置粘合层160。该粘合层160可在通孔形成之前或之后施加。在一些实施例中，保护脱模层(未示出)可施加在该粘合层160上以在通孔形成过程期间使该粘合层160保持干净。粘合层160可通过任何适合的方法施加于有效表面202。例如，粘合层160可通过旋涂、弯月面涂覆、喷涂、真空沉积或叠层技术施加。
粘合层160可包括热固性聚合物或热塑性聚合物中的一个或多个。对于粘合层160的适合的非限制性示例包括丙烯酸(acrylic)、环氧树脂和聚醚酰亚胺。在一个实施例中，低温固化热固性物质可用作粘合层以使高温加工减至最少。在一个实施例中，粘合层具有从大约1微米至大约100微米范围中的厚度。在一个实施例中，对于粘合层160适合的材料包括具有从大约10微米至大约25微米范围中的厚度的聚醚酰亚胺。
如在图3中示出的，方法进一步包括将一个或多个半导体器件200附连到介电膜外表面122，使得半导体器件在附连后接触一个或多个通孔150。在特定实施例中，半导体器件200代表功率器件。在一个实施例中，半导体器件200代表各种类型的功率半导体器件，例如但不限于在功率开关应用中采用的功率MOSFET(金属氧化物场效应晶体管)和IGBT(绝缘栅双极晶体管)。在另一个实施例中，半导体器件200是二极管。仅通过示例提供单个半导体器件200。然而，在实际电力覆盖制造工艺中，多个半导体器件可附连到介电膜外表面122。在示范性实施例中，在任何封装或互连之前，这些器件200一般采用具有有效表面202和相反表面204的半导体芯片的形式。有效表面202被图案化并且具有金属化的I/O(输入/输出)盘210和220，其在功率半导体器件220的情况下包括至少两个端子，即，例如由接触盘210代表的源极端子等器件主端子，和例如由接触盘220代表的栅极端子等控制端子。在一些实施例中，为了提供低阻抗连接，在有效表面202上存在大的主端子210，或存在全部并联的多个主端子210(未示出)，并且另外地存在同样并联的一个或多个控制端子220(未示出)。均匀的相反表面204包括另一个器件主端子230，例如漏极端子。
在一个实施例中，在介电膜外表面122或器件200的有效表面202上设置粘合层160之后，器件200的有效表面202接触到粘合层160使得通孔150与接触盘210和220对齐，如在图3中示出的。在一个示范性实施例中，器件200使用拾取和安置机器安置到粘合层160上。器件200然后接合到介电膜120。在一个实施例中，粘合层160是热塑性材料(thermoplastic)，并且通过提升温度直到在该热塑性材料中发生足够的流动以允许接合发生而完成接合。在另一个实施例中，粘合层160是热固性物质并且通过提升粘合层的温度直到发生交联而完成接合。在一个实施例中，器件200使用热固化循环和真空(如需要的话)接合到介电膜160以便于从粘合层160去除夹带空气并且放气。备选的固化选择包括例如微波固化和紫外光固化。
在一个实施例中，如在图4中示出的，方法进一步包括在第一金属层外表面132上设置导电层180。方法进一步包括在多个通孔150的内表面152上设置导电层180。如在图4中图示的，导电层180和第一金属层130在介电膜外表面122上形成互连层190。如在图4中示出的，互连层190进一步延伸通过通孔并且包括通孔150中的导电层180。
导电层180可包括适合于在半导体器件互连中使用的任何传导材料。在一个实施例中，导电层180包括难熔金属、贵金属或其的组合。适合的金属和金属合金的非限制性示例包括钨、钼、钛/钨、金、铂、钯、金/铟和金/锗。在另一个实施例中，可采用铜、铝或铜或铝的合金作为导电层180。用于导电层180的材料可选择成耐受住预期半导体器件180操作的温度。在一个实施例中，导电层180包括与第一金属层130相同的材料。在特定实施例中，导电层180包括铜。
在一个实施例中，导电层180可通过溅射、化学气相沉积、电镀、无电镀(electroless plating)或任何其他适合的方法设置在第一金属层外表面132和通孔的内表面152上。在特定实施例中，导电层180通过电镀设置。在一些实施例中，方法可进一步包括在设置导电层之前设置一个或多个附加层，例如，种子层(未示出)。在一个实施例中，该种子层包括例如Ti、Cr或Ni等阻挡金属，或在备选实施例中，该种子层包括例如Cu等非阻挡金属。典型地，种子层是可取的以在导电层180和介电膜120之间获得良好的粘合性。在一些实施例中，本发明的方法排除沉积分开的种子层的需要，因为第一金属层130提供用于沉积导电层180所需要的表面特性并且还在导电层180和介电膜120之间提供提高的粘合性。
导电层180的厚度可部分取决于将通过互连层的电流量、图案化的互连层192中的图案化区域的宽度以及已经在介电膜上存在的第一金属层130的厚度。在一个实施例中，导电层180具有从大约10微米至大约100微米范围中的厚度。在特定实施例中，导电层具有从大约25微米至大约50微米范围中的厚度。如先前指出的，导电层180的更低的厚度表示沉积导电层180(例如，使导电层180镀层)所需要的时间更少，并且从而降低成本。在一个实施例中，导电层180沉积到一定厚度，使得所得的互连层190的厚度能够承载典型的用于半导体器件相对低电阻损耗地操作的相对高的电流。如先前指出的，本发明的方法有利地允许在介电膜上形成厚的互连层并且同时减少制造的时间和关联的成本。例如，用于沉积125微米厚的互连层的典型的电镀工艺可需要5-6小时的电镀时间。在本发明的示范性实施例中，25微米厚的导电层可沉积在具有100微米厚的第一金属层上，其可有利地使制造时间降低五分之一。
方法进一步包括根据预定电路配置图案化互连层190以形成图案化的互连层192，其中图案化的互连层192的一部分延伸通过一个或多个通孔150来形成与半导体器件200的电接触，如在图5中图示的。图5图示在图案化互连层192之后附连到介电膜120的器件200的横截面视图。通过选择性地去除互连层190的部分来图案化互连层192以形成图案化的互连层192，其包括封装结构互连。如在图5中示出的，图案化的互连层192包括顶部互连区194和通孔互连区196。该顶部互连区194包括第一导电层180和第一金属层130的图案化部分，并且邻近介电膜外表面122形成。图案化的互连层192进一步包括在多个通孔150中形成的通孔互连区196。该通孔互连区196的第一部分设置成邻近通孔150的侧壁并且第二部分设置成邻近半导体器件200的一个或多个接触盘210/220。该通孔互连区196包括导电层180。
如在图5中图示的，顶部互连区194具有大于通孔互连区196的厚度的厚度。在一个实施例中，通孔互连区196具有从大约10微米至大约75微米范围中的厚度。在一个实施例中，通孔互连区196具有从大约25微米至大约50微米范围中的厚度。在一个实施例中，顶部互连区194具有从大约50微米至大约200微米范围中的厚度。在另一个实施例中，顶部互连区194具有从大约75微米至大约150微米范围中的厚度。
顶部互连区194和通孔互连区196可提供低电阻和低阻抗互连。在一个实施例中，包括顶部互连区194和通孔互连区196、与接触盘210电接触的互连区可起封装主端子接触的作用，并且可具有对于器件200足够的电流承载能力。相似地，包括顶部互连区194和通孔互连区196、与接触盘220电接触的互连区可起封装栅极端子接触的作用。
在一个实施例中，互连层190通过消减蚀刻法、半添加加工技术或例如自适应光刻等光刻而图案化。例如，在一个实施例中，光掩模材料可施加在互连层190的表面上，接着将该光掩模材料光显影为期望的互连图案，并且然后使用标准湿蚀刻浴来蚀刻互连层190的暴露部分。在备选实施例中，薄金属种子层可在金属层130上形成。光掩模材料施加在该薄金属种子层的表面上，接着光显影该光掩模材料使得该薄金属种子层在要形成期望的互连图案的地方暴露。然后采用电镀工艺以在暴露的种子层上选择性地沉积另外的金属来形成更厚的层，接着去除剩余的光掩模材料并且蚀刻暴露的薄金属种子层。
在一个实施例中，如在图5中示出的，提供半导体器件封装件300。该半导体器件封装件300包括叠层100，其包括设置在介电膜120上的第一金属层130。该半导体器件封装件300包括根据预定图案延伸通过叠层100的多个通孔150。一个或多个半导体器件200附连到介电膜120使得半导体器件200接触一个或多个通孔150。图案化的互连层192设置在介电膜120上，所述图案化的互连层192包括第一金属层130和导电层1 80的一个或多个图案化区域，其中图案化的互连层192的一部分延伸通过一个或多个通孔150来形成与半导体器件200的电接触。图案化的互连层192进一步包括顶部互连区194和通孔互连区196，其中封装互连区194具有大于通孔互连区196的厚度的厚度。
在本文上文中描述的实施例中，叠层包括只设置在介电膜的一侧上的金属层。在另一个实施例中，如在图6中示出的，方法包括提供叠层100，其包括介于第一金属层130和第二金属层140之间的介电膜120。该叠层100进一步包括第一金属层外表面132和第二金属层外表面142。该第一金属层进一步包括邻近介电膜内表面121设置的第一金属层内表面131。该第二金属层140进一步包括邻近介电膜外表面122设置的第二金属层内表面111。在一个实施例中，该第二金属层140包括铜。
如先前指出的，叠层不包括框架并且因此方法不牵涉为介电膜装框架的步骤。在一些实施例中，第一金属层130和第二金属层140共同为介电膜120提供结构支撑并且对由此制造的半导体器件封装件提供尺寸稳定性。此外，第一金属层130和第二金属层140可在缺乏典型地用于电力覆盖制造工艺的载体框架情况下提供便于拿捏和便于运输。
在一个实施例中，如在图7中示出的，方法进一步包括根据预定图案图案化第二金属层140以形成图案化的第二金属层140。在一些实施例中，第二金属层140通过消减蚀刻法或例如自适应光刻而图案化。在一个实施例中，第二金属层140被图案化以在介电膜120上形成多个图案化的第二金属层区域，例如图案化的第二金属层区域141、143和145。在一个实施例中，第二金属层140被图案化以形成一个或多个馈通结构145。在一些实施例中，该一个或多个馈通结构145可允许与设置在器件200的相反表面204上的漏极端子接触230的电接触，从而将所有电连接带到半导体器件封装件的顶部。在典型的电力覆盖制造工艺中，馈通结构分开制造并且随后附连到介电膜120，其可增加制造步骤的数量并且还增加关联的成本。此外，分开附连的馈通结构可具有较低的粘合性以及在馈通结构和介电膜之间的界面处具有缺陷增加的可能性。在一些实施例中，本发明的方法有利地提供用于使用第二金属层140制造馈通结构的集成工艺，其可导致制造步骤的数量降低并且在经济上可以是有利的。
图案化区域141、143和145的大小和厚度可部分取决于器件厚度、期望的馈通结构的厚度和通孔图案。在一个实施例中，第二金属层140被进一步图案化以形成一个或多个图案化区域141和143，其具有由要附连到介电膜120的器件的厚度所确定的厚度。在这样的实例中，例如图案化的第二金属层区域141和143的厚度可选择性地调整使得附连的器件200与馈通结构145大致上成平面，这可便于随后平坦的衬底的附连。
方法进一步包括根据预定图案形成多个延伸通过叠层的通孔150。如在图8中示出的，这样形成的这些多个通孔150延伸通过第一金属层130、介电膜120和图案化的第二金属层140的一部分。如在图8中图示的，这些多个通孔151、153和155延伸通过第一金属层图案化区域141和143，并且不通过馈通结构145。这些多个通孔150可通过如先前描述的任何适合的方法形成。在一些实施例中，这些多个通孔可选择性地形成通过叠层，使得仅去除图案化的第二金属层140的一部分来形成通孔。例如，如在图8中示出的，图示的通孔155形成通过叠层100使得通孔155与一个或多个馈通结构145对齐并且不延伸通过馈通结构145。在一些实施例中，在第二金属层140图案化之后形成多个通孔。在备选实施例中，在第二金属层140图案化之前形成多个通孔。
在一些其他实施例中，第二金属层140在形成通孔150之前被选择性地图案化以基于例如通孔151和153的预定图案选择性地去除图案化的第二金属层区域(例如图案化区域141和143)的部分。如在图9中图示的，第二金属层140被图案化以形成图案化的第二金属层140，其中图案化的金属层140进一步包括图案化区域141和143，使得图案化区域的一部分基于通孔图案而去除。在一些实施例中，如在图9中示出的，第一金属层130进一步在通孔150形成之前被选择性地图案化以基于例如通孔151和153的预定图案选择性地去除第一金属层130的部分。在这样的实施例中，如在图8中示出的，通孔150的形成只包括去除介电膜120的选择的部分以形成延伸通过叠层的通孔150。
在一个实施例中，第二金属层图案化区域145中的一个或多个不与通孔150和互连层192接触。在这样的实施例中，在通孔形成期间，通孔155例如可不存在并且第二金属层图案化区域145可提供对介电膜的机械支撑并且在缺乏载体框架的情况下可起到框架的作用。
方法进一步包括将一个或多个半导体器件200附连到图案化的第二金属层140的一部分的第二金属层外表面142。如在图10中图示的，器件200附连到图案化的第二金属层区域141和143的第二金属层外表面142。在一些实施例中，方法可进一步包括在附连器件之前在器件200和第二金属层外表面142之间插入粘合层160。该粘合层160可通过如先前描述的方法设置。在一个实施例中，如在图10中示出的，在设置粘合层160之后，器件200的有效的主要表面202接触到粘合层160使得通孔151和153与接触盘210和220对齐。如上文指出的，图案化的第二金属层区域141和143允许器件对齐使得器件200的相反表面204与馈通结构145的外表面对齐以形成大致上平坦的表面。
在一个实施例中，如在图11中示出的，方法进一步包括在第一金属层外表面132上设置导电层180。方法进一步包括在多个通孔150的内表面152上设置导电层180。如在图11中图示的，导电层180和第一金属层130在介电膜120上形成互连层190。如在图11中示出的，互连层190进一步延伸通过通孔，其中互连层190包括通孔150中的导电层180。
如在图12中图示的，方法进一步包括根据预定电路配置图案化互连层190来形成图案化的互连层192，其中该图案化的互连层192的一部分延伸通过一个或多个通孔150来形成与半导体器件200的电接触。图12图示在互连层190被图案化之后附连到介电膜120的器件200的横截面视图。通过选择性地去除互连层190的部分而图案化互连层190来形成图案化的互连层192，其包括封装结构互连。如在图12中示出的，图案化的互连层192包括顶部互连区194和通孔互连区196。该顶部互连区194包括第一导电层180和第一金属层130的图案化部分，并且邻近介电膜形成。图案化的互连层192进一步包括在多个通孔150中形成的通孔互连区196。该通孔互连区196的第一部分设置成邻近通孔150的侧壁并且第二部分设置成邻近半导体器件200的一个或多个接触盘210/220。该通孔互连区196包括导电层180。此外，在一个实施例中，如在图12中图示的，图案化的互连层192的一部分延伸通过一个或多个通孔150来形成与一个或多个馈通结构145的电接触。
在一个实施例中，方法进一步包括在附连一个或多个器件之前图案化第二金属层140来形成多个图案化区域，其中至少两个图案化区域具有互不相同的厚度。在这样的实施例中，不同的厚度的图案化区域可有利地容纳具有不同厚度的半导体器件，使得这些半导体器件的相反表面全部对齐并且提供用于衬底附连的大致上平坦的表面。在一个实施例中，方法进一步包括将多个半导体器件附连到图案化的第二金属层，其中至少两个半导体器件具有互不相同的厚度。如在图13中图示的，具有不同厚度的半导体器件200和400有利地附连到介电膜使得半导体器件的相反表面互相对齐并且与馈通结构的外表面对齐。在图1 3中，仅示出一个接触盘与通孔150对齐，然而，半导体器件200和400可包括多个与通孔150对齐的接触盘，如在上文描述的。
在一个实施例中，如在图12中图示的，提供半导体器件封装件300。该半导体器件封装件300包括叠层100，其包括设置在介电膜120上的第一金属层130。该半导体器件封装件300进一步包括设置在与第一金属层130相反的侧上的介电膜120上的图案化的第二金属层140。该图案化的第二金属层140包括图案化的第二金属层区域(例如141和143)，和一个或多个馈通结构145。该半导体器件封装件300包括根据预定图案延伸通过叠层100的多个通孔150。一个或多个半导体器件200附连到图案化的第二金属层140的一部分的第二金属层外表面142，使得半导体器件200接触一个或多个通孔150。图案化的互连层192设置在介电膜120上，所述图案化的互连层192包括第一金属层130和导电层180，其中图案化的互连层192的一部分延伸通过一个或多个通孔150来形成与半导体器件200的电接触。图案化的互连层192包括顶部互连区194和通孔互连区196，其中封装互连区194具有大于通孔互连区196的厚度的厚度。此外，图案化的互连层192的一部分延伸通过一个或多个通孔150来形成与一个或多个馈通结构145的电接触。
在一个实施例中，半导体器件封装件300可进一步附连到半导体器件衬底(未示出)。半导体器件衬底可包括绝缘衬底，其具有半导体器件200可与之电耦合的一个或多个导电衬底接触。例如，半导体器件200可焊接到衬底接触。半导体器件衬底还可包括背面传导层，其可便于半导体器件200附连到例如散热器。
在一些实施例中，得到的半导体器件封装件300提供高电流承载能力，以及提供用于将热传导远离半导体器件的有效表面202的低阻抗热通路。在一些实施例中，散热器结构、电互连结构或这两者可安装到封装件顶部、底部或顶部及底部二者。
附上的权利要求意在如它已经设想的那样宽泛地要求本发明的权利并且本文提供的示例说明从所有可能实施例的集合中选择的实施例。因此，申请者的意图是附上的权利要求不受到用于说明本发明的特征的示例选择的限制。如在权利要求书中使用的，词“包括”和它在逻辑上的语法变化形式还对应并且包括变化和不同程度的短语，例如但不限于“基本上包括”和“由...组成”。在必要的地方，已经提供范围；那些范围包括其间的所有子范围。期望这些范围中变化形式将为本领域内技术人员和还未致力于公众的地方的从业者想起，如可能，那些变化形式应该解释为由附上的权利要求涵盖。还预期科学和技术的进步将使由于语言的不精确而现在未预想的等同物和替代成为可能，并且如可能，这些变化形式还应该解释为由附上的权利要求涵盖。
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Claims (11)

1.一种制造半导体器件封装件的方法，其包括：
提供叠层，其包括设置在第一金属层上的介电膜，所述叠层具有介电膜外表面和第一金属层外表面；
根据预定图案形成多个延伸通过所述叠层的通孔；
将一个或多个半导体器件附连到所述介电膜外表面使得所述半导体器件在附连后接触一个或多个通孔；
在所述第一金属层外表面和所述多个通孔的内表面上设置导电层来形成互连层，其包括所述第一金属层和所述导电层；以及
根据预定电路配置图案化所述互连层来形成图案化的互连层，其中所述图案化的互连层的一部分延伸通过一个或多个通孔来形成与所述半导体器件的电接触。
2.如权利要求1所述的方法，其中所述图案化的互连层包括顶部互连区和通孔互连区，并且其中所述顶部互连区具有大于所述通孔互连区的厚度的厚度。
3.如权利要求2所述的方法，其中所述通孔互连区具有从5微米至125微米范围中的厚度。
4.如权利要求2所述的方法，其中所述顶部互连区具有从25微米至200微米范围中的厚度。
5.如权利要求1所述的方法，其中所述叠层是无框架的。
6.一种制造半导体器件封装件的方法，其包括：
提供叠层，其包括介于第一金属层和第二金属层之间的介电膜，所述叠层具有第一金属层外表面和第二金属层外表面；
根据预定图案图案化所述第二金属层来形成图案化的第二金属层；
根据预定图案形成多个延伸通过所述叠层的通孔；
将一个或多个半导体器件附连到所述图案化的第二金属层的一部分的所述第二金属层外表面；
在所述第一金属层外表面和一个或多个通孔的内表面上设置导电层来形成互连层，其包括所述第一金属层和所述导电层；以及
根据预定电路配置图案化所述互连层来形成图案化的互连层，其中所述图案化的互连层的一部分延伸通过一个或多个通孔来形成与所述半导体器件的电接触。
7.如权利要求6所述的方法，其中所述图案化的第二金属层进一步包括与一个或多个通孔对齐的一个或多个馈通结构，并且所述图案化的互连层的一部分延伸通过所述一个或多个通孔来形成与所述一个或多个馈通结构的电接触。
8.如权利要求6所述的方法，其进一步包括在形成所述多个通孔之前根据通孔预定图案图案化所述第一金属层。
9.如权利要求6所述的方法，其中所述图案化的第二金属层进一步包括多个图案化区域，其中至少两个图案化区域具有互不相同的厚度。
10.如权利要求6所述的方法，其进一步包括将多个半导体器件附连到所述图案化的第二金属层，其中至少两个半导体器件具有互不相同的厚度。
11.一种半导体器件封装件，其包括：
叠层，其包括设置在介电膜上的第一金属层；
根据预定图案延伸通过所述叠层的多个通孔；
一个或多个半导体器件，其附连到所述介电膜使得所述半导体器件接触一个或多个通孔；以及
设置在所述介电膜上的图案化的互连层，所述图案化的互连层包括导电层和所述第一金属层的一个或多个图案化区域，其中所述图案化的互连层的一部分延伸通过一个或多个通孔来形成与所述半导体器件的电接触，并且
所述图案化的互连层包括顶部互连区和通孔互连区，其中所述顶部互连区具有大于所述通孔互连区的厚度的厚度。
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