JP6862087B2 - 配線基板、配線基板を有する半導体パッケージ、およびその製造方法 - Google Patents
配線基板、配線基板を有する半導体パッケージ、およびその製造方法 Download PDFInfo
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- JP6862087B2 JP6862087B2 JP2015241907A JP2015241907A JP6862087B2 JP 6862087 B2 JP6862087 B2 JP 6862087B2 JP 2015241907 A JP2015241907 A JP 2015241907A JP 2015241907 A JP2015241907 A JP 2015241907A JP 6862087 B2 JP6862087 B2 JP 6862087B2
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- Ceramic Engineering (AREA)
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- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
本実施形態では、本発明の一実施形態の配線基板で用いる配線構造、ならびにその作製方法を図1を参照して説明する。この配線構造は図1(E)に示すように、大きな電流を流すことができる大きな膜厚を有する層(第1の層125)と、微細加工が可能な小さな膜厚を有する層(第2の層130)が積層され、互いに電気的に接続された配線(第2の配線140)を有している。また、膜厚の小さい第2の層130はビアの中にも形成されている。このような配線構造は、積層された複数の配線層や配線基板を電気的に接続するために利用することができる。
本実施形態では、第1実施形態と異なる配線基板の配線構造を図2を用いて記述する。なお、第1実施形態と同じ構成に関しては記述を省略することがある。
本実施形態では、第1、第2実施形態と異なる配線基板の配線構造を図3、4を用いて記述する。なお、第1、第2実施形態と同じ構成に関しては記述を省略することがある。
本実施形態では、第1実施形態で述べた配線構造を有する配線基板が半導体パッケージに適用された一例を図5乃至7を用いて記述する。なお、第1実施形態と同じ構成に関しては記述を省略することがある。
本実施形態では、第1、第2実施形態で述べた配線構造を有する配線基板が半導体パッケージに適用された一例を図8乃至10を用いて記述する。なお、第1、第2実施形態と同じ構成に関しては記述を省略することがある。
本実施形態では、大電流用の配線と小電流用の配線が同一層に共存し、かつ、小電力で駆動される半導体デバイスと大電流が印加されるパワーデバイスが同一層に共存した半導体パッケージに関し、図11、12を用いて述べる。
本実施形態では、大電流用の配線と小電流用の配線が同一層に共存し、かつ、小電力で駆動される半導体デバイスと大電流が印加されるパワーデバイスが同一層に共存した半導体パッケージに関し、図11、13を用いて述べる。なお、本実施形態は、第2の配線構造が第6実施形態と異なる。第6実施形態と異なる構成を主に説明し、同様の構成の説明は省略することがある。
Claims (35)
- 第1の端子と第2の端子と、
前記第1の端子と前記第2の端子を覆う絶縁膜と、
前記絶縁膜と前記第2の端子の上に位置し、前記第1の端子上に位置しない第1の層と、
前記第1の層に形成され、前記第2の端子と重なる開口部と、
前記絶縁膜を貫通し、前記第1の端子の少なくとも一部を露出する第1のビアと、
前記開口部から前記絶縁膜を貫通して延伸し、前記第2の端子の少なくとも一部を露出する第2のビアと、
前記第1のビア内に位置する第1の部分、および前記第1の層上に位置し前記開口部と前記第2のビア内に位置する第2の部分を有する第2の層を備え、
前記第2の層の前記第1の部分は第1の導電経路を形成し、
前記第2の層の前記第2の部分と前記第1の層は第2の導電経路を形成し、
前記第1の導電経路は前記第1の層を含まない、配線基板。 - 前記第2の層の前記第2の部分は、前記第1の層の上面と重なり、
前記第2の層の前記第2の部分は、前記第1の層の前記上面上における第1の厚さ、および前記第2のビア内における第2の厚さを有し、
前記第1の厚さは前記第2の厚さよりも小さい、請求項1に記載の配線基板。 - 前記第1の層は第3の厚さを有し、
前記第1の厚さは前記第3の厚さよりも小さい、請求項2に記載の配線基板。 - 前記第1の層は、パターニングされた金属板を有する、請求項1に記載の配線基板。
- 前記絶縁膜の上面は、前記第2のビアと前記第1の層の間に凹部を有する、請求項1に記載の配線基板。
- 前記開口部は第1の深さを有し、
前記第2のビアは、前記第1の深さと異なる第2の深さを有する、請求項1に記載の配線基板。 - 前記第1の層は、前記開口部を定義する側面を有し、
前記側面は、第1の傾斜を有する第1部分を有し、
前記側面は、前記第1部分と接続され、第2の傾斜を有する第2部分を有する、請求項1に記載の配線基板。 - 前記第1の層と前記第2の層は、互いに導電率が異なる、請求項1に記載の配線基板。
- 前記第1の層と前記第2の層が銅を含む、請求項1に記載の配線基板。
- 第1の端子と第2の端子を有する半導体デバイスと、
前記第1の端子と前記第2の端子を覆う絶縁膜と、
前記絶縁膜と前記第2の端子の上に位置し、前記第1の端子上に位置せず、前記第2の端子と重なる複数の開口部を有する第1の層と、
前記絶縁膜を貫通し、前記第1の端子を露出する第1のビアと、
前記複数の開口部から前記絶縁膜を貫通して延伸し、前記第2の端子を露出する複数の第2のビアと、
前記第1のビア内に位置する第1の部分、および前記第1の層上に位置し前記複数の開口部と前記複数の第2のビア内に位置する第2の部分を有する第2の層を備え、
前記第2の層の前記第1の部分は、前記半導体デバイスに対して小電流導電経路を形成し、
前記第2の層の前記第2の部分と前記第1の層は、前記半導体デバイスに対して大電流導電経路を形成する、半導体パッケージ。 - 前記第2の層の前記第2の部分は、前記第1の層の上面と重なり、
前記第2の層の前記第2の部分は、前記第1の層の前記上面上における第1の厚さ、および前記第2のビア内における第2の厚さを有し、
前記第1の厚さは前記第2の厚さよりも小さい、請求項10に記載の半導体パッケージ。 - 前記第1のビアは、横方向において、前記第1の層の最近接端から離隔する、請求項10に記載の半導体パッケージ。
- 前記第1の層は、前記絶縁膜に固定された金属板を含む、請求項10に記載の半導体パッケージ。
- 前記絶縁膜の上面は、前記複数の第2のビアの各々と対応する前記開口部との間に凹部を有する、請求項10に記載の半導体パッケージ。
- 前記複数の開口部はそれぞれ第1の幅を有し、
前記複数の第2のビアはそれぞれ、前記第1の幅よりも小さい第2の幅を有する、請求項10に記載の半導体パッケージ。 - 前記第2の層の前記第2の部分は、前記第1の層の側面と重なる、請求項10に記載の半導体パッケージ。
- 前記第1の層と前記第2の層が銅を含む、請求項10に記載の半導体パッケージ。
- 前記第1の層と前記第2の層は、互いに導電率が異なる、請求項10に記載の半導体パッケージ。
- 第1の端子と第2の端子を準備し、
前記第1の端子と前記第2の端子を覆うように絶縁膜を形成し、
前記第2の端子上に位置し、前記第1の端子上に位置せず、前記第2の端子上において前記絶縁膜を露出する開口部を有する第1の層を形成し、
前記絶縁膜を貫通し、前記第1の端子の少なくとも一部を露出する第1のビアを形成し、
前記開口部から延伸し、前記絶縁膜を貫通し、前記第2の端子の少なくとも一部を露出する第2のビアを形成し、
前記第1のビア内に位置する第1の部分、および前記第1の層上に位置し前記開口部と前記第2のビア内に位置する第2の部分を有する第2の層を形成することを含み、
前記第2の層の前記第1の部分は第1の導電経路を形成し、
前記第2の層の前記第2の部分と前記第1の層は第2の導電経路を形成し、
前記第1の導電経路は前記第1の層を含まない、配線基板の製造方法。 - 第1の端子と第2の端子を準備し、
前記第1の端子と前記第2の端子を覆うように絶縁膜を形成し、
前記絶縁膜を形成した後に、第1の層と第2の層を備える配線を前記絶縁膜の上に形成することを含み、
前記配線の前記形成は、
前記絶縁膜に金属板を接合することで前記第1の層を形成し、
前記絶縁膜を露出する開口部を前記金属板に形成し、
前記金属板の前記開口部を介して前記第1の端子と第2の端子を露出するビアを前記絶縁膜に形成し、
前記第1の端子、第2の端子、および前記第1の層の上に、前記第1の端子、第2の端子、および前記第1の層と接する前記第2の層を電解めっき法によって形成することを含む、配線基板の製造方法。 - 前記第2のビア内における前記第2の層の前記第2の部分の膜厚は、前記第1の層と重なる領域における前記第2の層の前記第2の部分の膜厚よりも大きい、請求項19に記載の配線基板の製造方法。
- 前記第1の層の膜厚は、前記第1の層と重なる領域における前記第2の層の前記第2の部分の膜厚よりも大きい、請求項19に記載の配線基板の製造方法。
- 前記第1の層の前記形成は、
前記絶縁膜に金属板を接合し、
前記金属板が前記第2の端子と重なり、前記第1の端子と重ならず、前記開口部を与えるように、前記金属板を部分的に除去することを含む、請求項19に記載の配線基板の製造方法。 - 前記金属板は凹部を有し、
前記ビアは前記凹部上に位置する、請求項20に記載の配線基板の製造方法。 - 前記第1の層と前記第2の層が銅を含む、請求項19または20に記載の配線基板の製造方法。
- 前記第1の層と前記第2の層は、互いに導電率が異なる、請求項19または20に記載の配線基板の製造方法。
- 第1の端子と第2の端子を有する半導体デバイスを第1の配線上に設置し、
前記第1の配線、前記半導体デバイス、および前記第2の端子上に絶縁膜を形成し、
前記絶縁膜上に、第1の層と第2の層を有する第2の配線を形成することを含み、
前記第2の配線の形成は、
前記絶縁膜を形成した後、前記絶縁膜に金属板を接合させ、
前記金属板の第1の部分が前記第1の配線の上に位置し、前記金属板の第2の部分が前記第2の端子の上に位置するように、かつ、前記金属板の前記第1の部分に前記第1の配線上に位置する第1の開口部を与え、前記金属板の前記第2の部分に前記第2の端子上に位置する第2の開口部を与えるように前記金属板の一部を除去することで前記第1の層を形成し、
前記第1の開口部を介し、前記第1の配線を露出する第1のビアを前記絶縁膜に形成し、
前記第2の開口部を介し、前記第2の端子を露出する第2のビアを前記絶縁膜に形成し、
前記第2の層の第1の部分が前記第1のビアを介して前記第1の配線と接続され、前記第2の層の第2の部分が前記第2のビアを介して前記第2の端子と接続されるように、前記第2の層を電解めっき法で形成することを含み、
前記第2の層の前記第1の部分は、前記第1の配線を介して前記第1の端子に電気的に接続される、半導体パッケージの製造方法。 - 前記半導体デバイスは第3の端子を有し、
前記絶縁膜は、前記第3の端子の上に形成され、
前記金属板の前記一部の除去は、前記金属板が前記第3の端子と重ならないように行われ、
前記製造方法はさらに、前記第3の端子を露出するように前記絶縁膜を貫通する第3のビアを形成することを含み、
前記第2の層の形成は、前記第3のビアを介して前記第3の端子と接続される第3の部分を前記第2の層に形成することを含み、
前記第2の層の前記第2の部分と前記金属板の前記第2の部分は第1の導電経路として構成され、
前記第2の層の前記第3の部分は、第2の導電経路として構成され、
前記第2の導電経路は、前記金属板を含まない、請求項27に記載の半導体パッケージの製造方法。 - 前記第2のビア内における前記第2の層の前記第2の部分の膜厚は、前記金属板の前記第2の部分と重なる領域における前記第2の層の前記第2の部分の膜厚よりも大きい、請求項27に記載の半導体パッケージの製造方法。
- 前記第1の層の膜厚は、前記第1の層と重なる領域における前記第2の層の膜厚よりも大きい、請求項27に記載の半導体パッケージの製造方法。
- 前記絶縁膜の上面が、前記第2のビアと前記第1の層の間に凹部を有する、請求項27に記載の半導体パッケージの製造方法。
- 前記第1のビア内の前記第2の層の膜厚は、前記絶縁膜と重なる領域における前記第2の層の膜厚よりも大きい、請求項27に記載の半導体パッケージの製造方法。
- 前記第2の層の前記第1の部分は、前記第1のビアを充填し、前記第1のビアにおいて前記絶縁膜と直接接する、請求項27に記載の半導体パッケージの製造方法。
- 前記第1の層と前記第2の層が銅を含む、請求項27に記載の半導体パッケージの製造方法。
- 前記第1の層と前記第2の層は、互いに導電率が異なる、請求項27に記載の半導体パッケージの製造方法。
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US20200066623A1 (en) | 2020-02-27 |
KR102584116B1 (ko) | 2023-10-04 |
US11189553B2 (en) | 2021-11-30 |
TW202127612A (zh) | 2021-07-16 |
TWI718217B (zh) | 2021-02-11 |
KR20170069925A (ko) | 2017-06-21 |
US11908783B2 (en) | 2024-02-20 |
CN107039391A (zh) | 2017-08-11 |
KR20230142406A (ko) | 2023-10-11 |
JP2017108039A (ja) | 2017-06-15 |
TWI801795B (zh) | 2023-05-11 |
TW201721821A (zh) | 2017-06-16 |
US20220044991A1 (en) | 2022-02-10 |
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