CN106024755B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN106024755B
CN106024755B CN201610011726.4A CN201610011726A CN106024755B CN 106024755 B CN106024755 B CN 106024755B CN 201610011726 A CN201610011726 A CN 201610011726A CN 106024755 B CN106024755 B CN 106024755B
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face
electrode
conductive layer
semiconductor chip
semiconductor device
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CN106024755A (zh
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鹭谷纯
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

半导体装置具有：第一半导体芯片，具有第一面、与第一面为相反侧的第二面、设置在第一面的第一电极、设置在第二面的第二电极、及将第一电极与第二电极电连接的第一接点；第二半导体芯片，具有与第一面对向配置的第三面、作为第三面的相反侧的面的第四面及设置在第四面的第三电极；金属导线，将第三电极与第一电极电连接；第一绝缘层，配置在第一半导体芯片的第二面，且具有第一开口部；第一导电层，配置在第一开口部及第一绝缘层上的一部分，且在第一开口部与第二电极电连接；及第一外部端子，电连接于第一导电层。

Description

半导体装置
[相关申请案]
本申请案享有以日本专利申请案2015-70401号(申请日：2015年3月30日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置。
背景技术
近年来，众所周知的是在一个半导体装置包含有多个半导体芯片。
发明内容
本发明的实施方式减少半导体装置的面积。
实施方式的半导体装置具有：第一半导体芯片，具有第一面、与所述第一面为相反侧的第二面、设置在所述第一面的第一电极、设置在所述第二面的第二电极、以及将所述第一电极与所述第二电极电连接的第一接点；第二半导体芯片，具有与所述第一面对向配置的第三面、作为所述第三面的相反侧的面的第四面、以及设置在所述第四面的第三电极；金属导线，将所述第三电极与所述第一电极电连接；第一绝缘层，配置在所述第一半导体芯片的所述第二面且具有第一开口部；第一导电层，配置在所述第一开口部及所述第一绝缘层上的一部分，且在所述第一开口部与所述第二电极电连接；以及第一外部端子，电连接于所述第一导电层。
附图说明
图1是说明第一实施方式的半导体装置的示意性剖视图。
图2是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图3是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图4是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图5是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图6是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图7是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图8是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图9是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图10是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图11是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图12是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图13是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图14是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图15是说明第一实施方式的半导体装置的制造方法的示意性剖视图。
图16是说明第一实施方式的半导体装置的第三变形例的示意性剖视图。
图17是说明第一实施方式的半导体装置的第六变形例的示意性剖视图。
具体实施方式
以下，一面参照附图一面对实施方式进行说明。在以下的说明中，对于大致相同的功能及构成要素标注相同的符号。
(第1实施方式)
使用图1对第一实施方式的半导体装置5进行说明。
图1是示意性地表示切割后的晶片的剖视图。此处，示出2个单片化的第一半导体芯片20。此外，为了便于观看，存在仅对2个第一半导体芯片20中的一者标注符号的情况。
半导体装置5包含第一半导体芯片20、第二半导体芯片70、以及第三半导体芯片100。第一半导体芯片20、第二半导体芯片70、第三半导体芯片100以阶梯状配置。在第一半导体芯片20、第二半导体芯片70、第三半导体芯片100的周围配置着树脂层140。第一半导体芯片20、第二半导体芯片70、第三半导体芯片100例如为半导体存储装置，具体而言为NAND(Not And，与非)存储器。或者，第一半导体芯片20、第二半导体芯片70、第三半导体芯片100中的一个半导体芯片为半导体存储装置的控制器。
在第一半导体芯片20与第二半导体芯片70之间设置着第二粘接材层80。在第二半导体芯片70与第三半导体芯片100之间设置着第三粘接材层110。第二粘接材层80及第三粘接材层110粘接上下的半导体芯片。
第一半导体芯片20、第二半导体芯片70、第三半导体芯片100分别具有第一电极垫60、第二电极垫90、第三电极垫120。以下，在无须区分第一半导体芯片20、第二半导体芯片70、第三半导体芯片100的情况下简单地称为半导体芯片。另外，在无须区分第一电极垫60、第二电极垫90、第三电极垫120的情况下简单地称为电极垫。
金属导线130将第一电极垫60、第二电极垫90、第三电极垫120电连接。金属导线130例如为Au导线或Cu导线等金属导线。此外，金属导线130可将任意半导体芯片的电极垫间电连接。例如，金属导线130可将第一电极垫60与第二电极垫90、或第一电极垫60与第三电极垫120连接。另外，在半导体芯片具有多个电极垫与多个金属导线130的情况下，各个金属导线130可将任意的半导体芯片间电连接。
第一半导体芯片20具有第一面20a与第二面20b。另外，第一半导体芯片20具有第一导电接点50b、50c。
第一面20a具有第一电极垫60。第一面20a在其附近具有晶体管等电路元件、配线、接点或电极。第二面20b是第一半导体芯片20的与第一面20a为相反侧的面，且具有第一电极40a、40b、40c。
第一电极垫60与金属导线130及第一导电接点50c电连接。此外，第一电极垫60也可与配置在第一面20a附近的晶体管等电路元件、配线、接点或电极连接。
第一电极40a、40b、40c是设置在第二面20b的电极。第一电极40a、40b、40c包含导电层，且是使用例如激光加工与溅镀而形成。此外，在无须特意区分的情况下，第一电极40a、40b、40c称为第一电极40。
第一电极40a与第一导电层160a电连接。
第一电极40b与第一导电接点50b及第一导电层160b电连接。也就是说，第一电极40b是经由第一导电接点50b而将配置在第一面20a附近的晶体管等电路元件、配线、接点或电极与第一电极40b电连接。
第一电极40c与第一导电接点50c及第一导电层160电连接。也就是说，第一电极40c是经由第一导电接点50c及金属导线130而与第二半导体芯片70及第三半导体芯片100连接。
第一导电接点50b、50c是包含导电层的接点。第一导电接点50是包含例如铜或镍的接点。第一导电接点50b将配置在第一面20a附近的晶体管等电路元件、配线、接点或电极与第一电极40b电连接。第一导电接点50c将第一电极垫60与第一电极40c电连接。此外，在无须特意区分的情况下，第一导电接点50b、50c称为第一导电接点50。
第一导电接点50贯通第一半导体芯片20而配置。或者，第一导电接点50也可不贯通第一半导体芯片20的一部分即可连接于配置在第一面20a或第二面20b附近的电极(包含第一电极40、第一电极垫60，也可为其他电极)。
第二半导体芯片70、第三半导体芯片100也可为任意的半导体芯片且是与第一半导体芯片20相同构造的半导体芯片。第二半导体芯片70与第三半导体芯片100分别具有第三面70a与第四面70b、第五面100a与第六面100b。第三面70a与第五面100a是在其附近配置着晶体管等电路元件、配线或接点等的面。第三面70a及第五面100a配置在图1的下方侧。第三面70a与第五面100a分别具有第二电极垫90、第三电极垫120。
第一绝缘层150配置在第一半导体芯片20的第二面20b及树脂层140上。第一绝缘层150例如为聚酰亚胺。树脂层140存在与第一绝缘层150的下表面及侧面接触的情况。从上方观察存在如下情况，即第一绝缘层150在与第一半导体芯片20重叠的区域配置得较该区域的周围更低。因此，与第一半导体芯片20重叠的区域的第一绝缘层150在其侧面与树脂层140接触。通过第一绝缘层150在其侧面与树脂层140接触而提高第一绝缘层150与树脂层140的密接性。
第一绝缘层150具有第一开口部155a、155b、155c。第一开口部155a、155b、155c分别配置在与第一电极40a、40b、40c对应的区域。此外，在无须特意区分的情况下，第一开口部155a、155b、155c称为第一开口部155。
第一开口部155a、155b、155c分别于其内侧具有第一导电层160a、160b、160c及第二导电层180a、180b、180c。
第一导电层160a、160b、160c分别与第一电极40a、40b、40c电连接。第二导电层180a、180b、180c分别与第一导电层160a、160b、160c的正上方接触而配置。第一导电层160a、160b、160c例如为钛、铜、镍、或其等的积层层。第二导电层180a、180b、180c例如为铜、镍。此外，在无须特意区分的情况下，第一导电层160a、160b、160c称为第一导电层160。第二导电层180a、180b、180c称为第二导电层180。
另外，第一导电层160及第二导电层180以特定长度在第一绝缘层150上的一部分配置成任意图案。通过使第一导电层160及第二导电层180以特定长度配置成任意图案，而下述的焊料凸块200能够配置在与半导体装置5对应的树脂层140上的任意位置。
另外，换句话说，第一导电层160具有：第一部分S1，沿与第二面20b交叉的第一方向延伸，且与所述第一电极40连接；以及第二部分S2，沿与所述第一方向交叉的第二方向延伸而配置。
第二绝缘层175配置在第一绝缘层150及第二导电层180上。第二绝缘层175例如为聚酰亚胺。第二绝缘层175具有多个第二开口部177a、177b、177c。第二开口部177a、177b、177c分别配置在与第二导电层180a、180b、180c对应的区域。此外，在无须特意区分的情况下，第二开口部177a、177b、177c称为第二开口部177。第二导电层180a、180b、180c称为第二导电层180。
第二开口部177a、177b、177c分别在其内侧具有第三导电层190a、190b、190c。
第三导电层190a、190b、190c分别与第二导电层180a、180b、180c电连接。第三导电层190a、190b、190c例如为钛。此外，在无须特意区分的情况下，第三导电层190a、190b、190c称为第三导电层190。
另外，换句话说，第三导电层190配置在第二导电层180的至少一部分区域的正上方。
焊料凸块(外部端子)200a、200b、200c分别配置在第三导电层190a、190b、190c上。如上所述，以任意图案配置第一导电层160及第二导电层180，由此焊料凸块200能够配置在特定位置。具体而言，例如相邻的焊料凸块200的中心的第二间隔W2宽于该焊料凸块200所连接的第一电极40的第一间隔W1，从而能够配置焊料凸块200。也就是说，能够获得足够配置焊料凸块200的空间。另外，例如可根据安装半导体装置5的外部基板来配置焊料凸块200。此外，在无须特意区分的情况下，焊料凸块200a、200b、200c称为焊料凸块200。
另外，焊料凸块200b是经由第一电极40b连接于第一半导体芯片20。焊料凸块200c是经由第一电极40c连接于第二半导体芯片70及第三半导体芯片100。
(第一实施方式的制造方法)
使用图2～图15对第一实施方式的半导体装置5的制造方法进行说明。此外，图2～图4是与图1翻转而图示。
如图2所示，第一半导体芯片20设置在支撑基板10。首先，第一粘接材层30设置在第二面20b。而且，通过使第一粘接材层30粘接在支撑基板10而将第一半导体芯片20固定在支撑基板10。
支撑基板10例如为硅，但只要其后能够剥离，则可为任意材料。
第一粘接材层30例如为DAF(Die Attach Film，芯片粘接膜)。
如上所述，第一半导体芯片20具有第一电极40、第一导电接点50、以及第一电极垫60。
如图3所示，第二半导体芯片70、第三半导体芯片100设置在第一半导体芯片20上。第二粘接材层80设置在第二半导体芯片70的下表面。通过第二粘接材层80而将第二半导体芯片70固定在第一半导体芯片20。
同样，第三粘接材层110设置在第三半导体芯片100的下表面。通过第三粘接材层110而将第三半导体芯片100固定在第二半导体芯片70。
第二半导体芯片70具有第二电极垫90，第三半导体芯片100具有第三电极垫120。
如图4所示，金属导线130是将第一电极垫60、第二电极垫90、第三电极垫120连接而设置。
如图4所示般形成有树脂层140。所述树脂层140例如是通过在将半导体装置5装入模具后使树脂流入模具中，其后使所述树脂硬化而形成。此外，树脂层140也可通过将支撑基板10导入至预先装入有树脂的模具中并使树脂硬化而形成。也就是说，树脂层140能够以各种成形法形成。
如图5所示，半导体装置5被上下翻转，且支撑基板10及第一粘接材层30被剥离。支撑基板10例如是利用干式蚀刻或使用有化学液的蚀刻而被去除。另外，第一粘接材层30同样也利用干式蚀刻或使用有化学液的蚀刻而被去除。此外，如图5所示，在树脂层140的上表面与第二面20b之间产生有阶差。通过该阶差而与后述的第一绝缘层150的膜的密接性提高，从而变得不易剥离。
如图6所示般形成有第一绝缘层150。第一绝缘层150例如为聚酰亚胺，且是使用涂布及热处理而形成。第一绝缘层150可为硅氧化层或硅氮化层，也可使用CVD(ChemicalVapor Deposition，化学气相沉积)法而形成。
如图6所示，第一绝缘层150形成在整个表面。也就是说，从上方观察，第一绝缘层150是与树脂层140重叠而设置。
如图7所示，第一电极40的正上方的第一绝缘层150是其一部分被选择性地去除而形成有第一开口部155。
例如通过光刻法在第一绝缘层150上形成掩模图案。基于该掩模图案，通过蚀刻而将第一绝缘层150选择性地去除。此处，被选择去除的区域是分别与第一半导体芯片的多个第一电极40对应的区域。
如图8所示，第一导电层160形成在第一绝缘层150上，及隔着第一开口部155形成在第一电极40的正上方的一部分。第一导电层160例如为钛、铜、镍、或其等的积层层。典型而言，第一导电层160为导电材料，例如为钛与铜的积层、或钛与镍的积层，且是利用溅镀法或CVD法而形成。
进而，如图8所示，第一掩模图案170形成在第一导电层160上。第一掩模图案170例如为抗蚀剂。第一掩模图案170例如是使用光刻法而形成。
如图9所示，第二导电层180设置在未设置第一掩模图案170的第一导电层160上。第二导电层180例如是将第一掩模图案170作为掩模，且将第一导电层160作为籽晶层并通过金属镀敷法而形成。第二导电层180为导电材料，例如使用铜或镍。或者，第二导电层180也可在利用溅镀或CVD法将导电材料成层之后，通过利用光刻法的图案化与蚀刻去除而形成。
如图10所示，去除第一掩模图案170。去除是使用例如灰化法。
如图11所示，局部去除第一导电层160。通过将第二导电层180作为掩模进行蚀刻而将第一导电层160局部性地去除。另外，通过该蚀刻而将第二导电层180的表面的一部分去除而成为第二导电层180'。
如图12所示，第二绝缘层175形成在第一绝缘层150及第二导电层180'上。第二绝缘层175例如为聚酰亚胺，且是使用涂布及热处理而形成。第二绝缘层175可为硅氧化层或硅氮化层，也可通过CVD(Chemical Vapor Deposition)法而成层。
如图13所示，选择性地去除第二导电层180'正上方的第二绝缘层175。
例如通过光刻法而在第二绝缘层175上形成掩模图案。基于该掩模图案，通过蚀刻而将第二绝缘层175选择性地去除而形成第二开口部177。
如图14所示，第三导电层190形成在第二开口部177内。换句话说，第三导电层190形成在图13中被去除的区域的第二导电层180'上。第三导电层190为导电材料，例如为钛。所述第三导电层190是将第二导电层180'作为籽晶层并通过金属镀敷法而形成。另外，第三导电层190也可在利用溅镀或CVD法在第二绝缘层175及第二导电层180'上将导电材料成层之后，通过利用光刻法的图案化与蚀刻去除而形成。
如图15所示，在第三导电层190上形成有焊料凸块200。焊料凸块200例如是在涂布焊料膏之后通过回流焊而形成。焊料膏例如可包含锡与银，也可包含锡与铜。
如图1所示，通过切割而将半导体装置5单片化，由此形成有半导体装置5。如图1所示，第一绝缘层150及第二绝缘层175从上方观察与树脂层140重叠而设置，另外，于通过切割而被切断的剖面露出有树脂层140、第一绝缘层150、第二绝缘层175。
(第一实施方式的效果)
根据本实施方式，第二半导体芯片70、第三半导体芯片100是经由设置在第一半导体芯片20的第一导电接点50及第一电极40而电连接于焊料凸块200。也就是说，根据本实施方式，第二半导体芯片70及第三半导体芯片100与第一导电接点50电连接，并经由第一导电接点50而与焊料凸块200电连接。具体而言，如图1所示，第二半导体芯片70、第三半导体芯片100与焊料凸块200c电连接。此外，该第一导电接点50也可与第一半导体芯片20电连接，第二半导体芯片70及第三半导体芯片100也可与第一半导体芯片20电连接。
另外，配置在第一半导体芯片20的第一面20a附近的晶体管等电路元件、配线、接点或电极也经由第一导电接点50及第一电极40而电连接于焊料凸块200。具体而言，如图1所示，配置在第一半导体芯片20的第一面20a附近的晶体管等电路元件、配线、接点或电极是经由第一导电接点50b而与焊料凸块200b电连接。
也就是说，根据本实施方式，无与半导体芯片不同的另行具备电极垫的配线基板或连接于该配线基板的金属导线即能够将第一半导体芯片20、第二半导体芯片70、及第三半导体芯片100电连接于焊料凸块200。更具体而言，向焊料凸块200的电连接例如能够在无绝缘树脂配线基板、陶瓷配线基板、使用有玻璃环氧树脂的印刷配线板等硅中介板、引线架等的情况下进行。
另外，金属导线130也为只要将半导体芯片间电连接即可，从而能够减少金属导线130的使用量。
也就是说，根据本实施方式，可减少配置电极垫的面积，从而可使半导体装置5小型化。而且，通过减少配线基板或金属导线130的使用量而可节约材料，从而可获得低价且对环境无害的半导体装置5。
根据本实施方式，在第一半导体芯片20上设置着具备与第一电极40对应的第一开口部155的第一绝缘层150。而且，第一导电层160、第二导电层180是以特定长度在第一开口部155及第一绝缘层150上配置成任意图案。而且，通过将第一导电层160、第二导电层180以特定长度配置成任意图案，而能够将焊料凸块200配置在任意位置。例如，能够将相邻的焊料凸块200的中心的第二间隔W2以宽于该焊料凸块200所连接的第一电极40的第一间隔W1且能够与外部端子连接的距离设置。或者，例如能够根据安装半导体装置5的外部基板而配置焊料凸块200。
根据本实施方式，在第一半导体芯片20与焊料凸块200之间具备第一绝缘层150、第二绝缘层175、第一导电层160、第二导电层180、以及第三导电层190。也就是说，由于未设置上述般的配线基板，故而能够使第一半导体芯片20与焊料凸块200之间变薄，从而能够实现半导体装置5的更小型化。
根据本实施方式，树脂层140、第一绝缘层150及第二绝缘层175从上方观察重叠而设置。另外，在通过切割而被切断的剖面露出有树脂层140、第一绝缘层150、第二绝缘层175。也就是说，能够以并非密封配线基板等而是能够密封半导体芯片的树脂层的大小形成半导体装置5。
(第一实施方式的第一变形例)
如图5所示的支撑基板10的剥离能够以如下方式进行。
第一粘接材层30使用热塑树脂。其次，进行使第一粘接材层30塑化的热处理来代替图5中所说明的蚀刻。使第一粘接材层30塑化而能够将支撑基板10剥离。
或者，在支撑基板10的表面形成UV(ultraviolet，紫外线)硬化树脂。其次，从支撑基板10侧照射UV来代替图5中所说明的蚀刻。由此，使UV硬化树脂硬化而降低支撑基板10与第一粘接材层30的粘接性，从而能够将支撑基板10剥离。
(第一实施方式的第二变形例)
在图1中，对存在第一半导体芯片20、第二半导体芯片70、第三半导体芯片100的情况进行了说明，但半导体芯片的片数并不限定于3片，可为任意片数。
(第一实施方式的第三变形例)
如图16所示，第一半导体芯片20也可不包含第一电极40及第一电极垫60。在此情况下，第一导电接点50在第一面20a及第二面20b成为电极，并与金属导线130及第一导电层160电连接。
(第一实施方式的第四变形例)
在图1中，表示第一半导体芯片20经由第一导电层160、第二导电层180、第三导电层190连接于焊料凸块200的例，但并不限定于此。例如，半导体装置5也可不具备第三导电层190而是在第二导电层180上具备焊料凸块200。另外，半导体装置5也可不具备第二导电层180、第三导电层190而是在第一导电层160上具备焊料凸块200。另外，反之，半导体装置5也可在第三导电层190上具备新的导电层，并在该新的导电层上具备焊料凸块200。
(第一实施方式的第五变形例)
在图1中，表示第一半导体芯片20包含第一电极40a、40b、40c、第一导电接点50b、50c的情况，但并不限定于此。第一半导体芯片20可仅包含其中一部分，也可包含更多的第一电极40、第一导电接点50。
另外，第一电极40c与第二半导体芯片70及第三半导体芯片100电连接，但也可仅与其中之一芯片电连接。
(第一实施方式的第六变形例)
如图17所示，第二半导体芯片70、第三半导体芯片100也可不包含第二电极垫90、第三电极垫120。在此情况下，第二半导体芯片70、第三半导体芯片100与第一半导体芯片20同样地包含第二导电接点52、第三导电接点54。而且，第二半导体芯片70、第三半导体芯片100经由第二导电接点52、第三导电接点54连接于第一半导体芯片20。由于无须将第一半导体芯片20、第二半导体芯片70、第三半导体芯片100以阶梯状错开而积层，故而可实现半导体装置5的更小型化。
此外，第二导电接点52、第三导电接点54的构造为与第一导电接点50相同的构造即可。也就是说，第二半导体芯片70、第三半导体芯片100在第四面70b与第六面100b具有第二电极与第三电极。而且，第二导电接点与形成在第三面70a的电路元件及第二电极电连接，第三导电接点与形成在第五面100a的电路元件及第三电极电连接。
此外，至于本变形例的各半导体芯片的动作方法，例如记载于题为“半导体装置”的在2013年3月15日申请的美国专利申请案13/843165号。这些专利申请案的全部内容通过参照而援用在本说明书中。
已对本发明的实施方式进行了说明，但本实施方式是作为例而提出者，并非意图限定发明的范围。该新颖的实施方式能够以其他各种方式实施，且能够在不脱离发明主旨的范围内进行各种省略、替换、变更。本实施方式或其变形包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
5 半导体装置
10 支撑基板
20 第一半导体芯片
20 第一粘接材层
30 第一电极
50 第一导电接点
42 第二导电接点
54 第三导电接点
60 第一电极垫
70 第二半导体芯片
80 第二粘接材层
90 第二电极垫
100 第三半导体芯片
110 第三粘接材层
120 第三电极垫
130 金属导线
140 树脂层
150 第一绝缘层
155 第一开口部
160 第一导电层
170 第一掩模图案
175 第二绝缘层
177 第二开口部
180 第二导电层
190 第三导电层
200 焊料凸块

Claims (15)

1.一种半导体装置，其特征在于具有：
第一半导体芯片，具有第一面、与所述第一面为相反侧的第二面、设置在所述第一面的第一电极、设置在所述第二面的第二电极、以及将所述第一电极与所述第二电极电连接的第一接点；
第二半导体芯片，具有与所述第一面对向配置的第三面、作为所述第三面的相反侧的面的第四面、以及设置在所述第四面的第三电极；
金属导线，将所述第三电极与所述第一电极电连接；
第一绝缘层，配置在所述第一半导体芯片的所述第二面，且具有第一开口部；
第一导电层，配置在所述第一开口部及所述第一绝缘层上的一部分，且在所述第一开口部与所述第二电极电连接；
第二导电层，配置在所述第一导电层的正上方；
第二绝缘层，配置在所述第一绝缘层与所述第二导电层上，且具有第二开口部；
第三导电层，配置在所述第二开口部内，且在所述第二开口部与所述第二导电层电连接；以及
第一外部端子，不经由配线基板而设置，电连接于所述第一导电层，且配置在所述第三导电层的正上方。
2.根据权利要求1所述的半导体装置，其特征在于：所述第一面具备第一电路元件，
所述第四面具备第二电路元件，
所述第二电路元件与所述第三电极电连接。
3.根据权利要求2所述的半导体装置，其特征在于：所述第二面具备第四电极，
所述第一半导体芯片具备将所述第一电路元件与所述第四电极电连接的第二接点，
所述第一绝缘层具备第三开口部，且所述半导体装置还具备：
第四导电层，配置在所述第三开口部及所述第四电极上的一部分，且在所述第三开口部与所述第四电极电连接；以及
第二外部端子，电连接于所述第四导电层。
4.根据权利要求3所述的半导体装置，其特征在于还具备：
第五导电层，配置在所述第四导电层的正上方；
第二绝缘层，配置在所述第五导电层上，且具有第四开口部；
以及第六导电层，配置在所述第四开口部内，且在所述第四开口部与所述第五导电层电连接；
所述第二外部端子配置在所述第六导电层的正上方。
5.根据权利要求1至4中任一项所述的半导体装置，其特征在于：所述第一半导体芯片与所述第二半导体芯片具有实质上相同的构造。
6.根据权利要求1所述的半导体装置，其特征在于：所述第一外部端子为焊料凸块。
7.根据权利要求3所述的半导体装置，其特征在于：所述第一外部端子与所述第二外部端子的距离长于所述第二电极与所述第四电极的距离。
8.根据权利要求1至4中任一项所述的半导体装置，其特征在于还具备覆盖所述第一半导体芯片及所述第二半导体芯片的树脂层，且
所述树脂层与所述第一绝缘层的下表面及侧面接触。
9.一种半导体装置，其特征在于具有：
第一半导体芯片，具有第一面、与所述第一面为相反侧的第二面、设置在所述第一面的第一电极、设置在所述第二面的第二电极、以及将所述第一电极与所述第二电极电连接的第一接点；
第二半导体芯片，具有与所述第一面对向配置的第三面、作为所述第三面的相反侧的面的第四面、以及设置在所述第四面的第三电极；
金属导线，将所述第三电极与所述第一电极电连接；
第一导电层，具有沿与所述第二面交叉的第一方向延伸且与所述第二电极连接的第一部分、以及沿与所述第一方向交叉的第二方向延伸而配置的第二部分；
第二导电层，配置在所述第一导电层的正上方；
第三导电层，配置在所述第二导电层的至少一部分区域的正上方；以及
第一外部端子，不经由配线基板而设置，电连接于所述第一导电层，且配置在所述第三导电层的正上方。
10.根据权利要求9所述的半导体装置，其特征在于：所述第一面具备第一电路元件，
所述第四面具备第二电路元件，
所述第二电路元件与所述第三电极电连接。
11.根据权利要求10所述的半导体装置，其特征在于：所述第二面具备第四电极，
所述第一半导体芯片具备将所述第一电路元件与所述第四电极电连接的第二接点，且所述半导体装置还具备：
第四导电层，具有沿所述第一方向延伸且与所述第四电极连接的第三部分、以及沿与所述第一方向交叉的第三方向延伸而设置的第四部分；以及
第二外部端子，电连接于所述第四导电层。
12.根据权利要求11所述的半导体装置，其特征在于还具有：
第五导电层，配置在所述第四导电层的正上方；
以及第六导电层，配置在所述第五导电层的至少一部分区域的正上方；
所述第二外部端子配置在所述第六导电层的正上方。
13.根据权利要求9至12中任一项所述的半导体装置，其特征在于：所述第一半导体芯片与所述第二半导体芯片具有实质上相同的构造。
14.根据权利要求9所述的半导体装置，其特征在于：所述第一外部端子为焊料凸块。
15.根据权利要求11所述的半导体装置，其特征在于：所述第一外部端子与所述第二外部端子的距离长于所述第二电极与所述第四电极的距离。
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