CN102270619A - 用于电子封装组件的焊盘配置 - Google Patents
用于电子封装组件的焊盘配置 Download PDFInfo
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- CN102270619A CN102270619A CN2011101534568A CN201110153456A CN102270619A CN 102270619 A CN102270619 A CN 102270619A CN 2011101534568 A CN2011101534568 A CN 2011101534568A CN 201110153456 A CN201110153456 A CN 201110153456A CN 102270619 A CN102270619 A CN 102270619A
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85447—Copper (Cu) as principal constituent
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01005—Boron [B]
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- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US35147110P | 2010-06-04 | 2010-06-04 | |
US61/351,471 | 2010-06-04 |
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CN102270619A true CN102270619A (zh) | 2011-12-07 |
CN102270619B CN102270619B (zh) | 2014-03-19 |
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CN201110153456.8A Expired - Fee Related CN102270619B (zh) | 2010-06-04 | 2011-06-03 | 用于电子封装组件的焊盘配置 |
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US (3) | US8860193B2 (zh) |
CN (1) | CN102270619B (zh) |
TW (1) | TWI458062B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106104792A (zh) * | 2014-03-24 | 2016-11-09 | 技术研究组合光电子融合基盘技术研究所 | 用于将ic芯片搭载在基板上的基板上的焊盘阵列结构、以及具有该焊盘阵列结构的光模块 |
US10833590B2 (en) | 2012-11-14 | 2020-11-10 | Power Integrations, Inc. | Magnetically coupled galvanically isolated communication using lead frame |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8860193B2 (en) * | 2010-06-04 | 2014-10-14 | Marvell World Trade Ltd. | Pad configurations for an electronic package assembly |
US20150206829A1 (en) * | 2014-01-17 | 2015-07-23 | Yin Kheng Au | Semiconductor package with interior leads |
CN105826285B (zh) * | 2015-01-04 | 2018-07-03 | 华为技术有限公司 | 芯片及电子设备 |
US9653419B2 (en) | 2015-04-08 | 2017-05-16 | Intel Corporation | Microelectronic substrate having embedded trace layers with integral attachment structures |
Citations (2)
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US20070077414A1 (en) * | 2005-10-05 | 2007-04-05 | Claus Rudiger | Light-scattering plastics composition having high brightness and use thereof in flat screens |
CN101587868A (zh) * | 2008-05-19 | 2009-11-25 | 联发科技股份有限公司 | 方形扁平无引线半导体封装及其制作方法 |
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US5148265A (en) * | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
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US5659952A (en) * | 1994-09-20 | 1997-08-26 | Tessera, Inc. | Method of fabricating compliant interface for semiconductor chip |
JPH09232465A (ja) * | 1996-02-27 | 1997-09-05 | Fuji Kiko Denshi Kk | 半導体実装用プリント配線板 |
TW351008B (en) * | 1996-12-24 | 1999-01-21 | Matsushita Electronics Corp | Lead holder, manufacturing method of lead holder, semiconductor and manufacturing method of semiconductor |
US5889324A (en) * | 1998-03-30 | 1999-03-30 | Nec Corporation | Package for a semiconductor device |
JP3506211B2 (ja) * | 1998-05-28 | 2004-03-15 | シャープ株式会社 | 絶縁性配線基板及び樹脂封止型半導体装置 |
US6906414B2 (en) * | 2000-12-22 | 2005-06-14 | Broadcom Corporation | Ball grid array package with patterned stiffener layer |
US7132744B2 (en) * | 2000-12-22 | 2006-11-07 | Broadcom Corporation | Enhanced die-up ball grid array packages and method for making the same |
JP3895570B2 (ja) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
US6720207B2 (en) * | 2001-02-14 | 2004-04-13 | Matsushita Electric Industrial Co., Ltd. | Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device |
US6608375B2 (en) * | 2001-04-06 | 2003-08-19 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus with decoupling capacitor |
JP4173346B2 (ja) * | 2001-12-14 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置 |
US6879039B2 (en) * | 2001-12-18 | 2005-04-12 | Broadcom Corporation | Ball grid array package substrates and method of making the same |
US7323767B2 (en) * | 2002-04-25 | 2008-01-29 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US6800930B2 (en) * | 2002-07-31 | 2004-10-05 | Micron Technology, Inc. | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies |
JP2004349316A (ja) * | 2003-05-20 | 2004-12-09 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US7060535B1 (en) * | 2003-10-29 | 2006-06-13 | Ns Electronics Bangkok (1993) Ltd. | Flat no-lead semiconductor die package including stud terminals |
TWI245350B (en) * | 2004-03-25 | 2005-12-11 | Siliconware Precision Industries Co Ltd | Wafer level semiconductor package with build-up layer |
US7250684B2 (en) * | 2004-06-30 | 2007-07-31 | Intel Corporation | Circular wire-bond pad, package made therewith, and method of assembling same |
JP2007103423A (ja) * | 2005-09-30 | 2007-04-19 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US7675157B2 (en) | 2006-01-30 | 2010-03-09 | Marvell World Trade Ltd. | Thermal enhanced package |
TWI357647B (en) * | 2007-02-01 | 2012-02-01 | Siliconware Precision Industries Co Ltd | Semiconductor substrate structure |
US20110042794A1 (en) * | 2008-05-19 | 2011-02-24 | Tung-Hsien Hsieh | Qfn semiconductor package and circuit board structure adapted for the same |
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US8860193B2 (en) * | 2010-06-04 | 2014-10-14 | Marvell World Trade Ltd. | Pad configurations for an electronic package assembly |
JP5467959B2 (ja) * | 2010-07-21 | 2014-04-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9263374B2 (en) * | 2010-09-28 | 2016-02-16 | Dai Nippon Printing Co., Ltd. | Semiconductor device and manufacturing method therefor |
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2011
- 2011-06-03 US US13/153,181 patent/US8860193B2/en not_active Expired - Fee Related
- 2011-06-03 CN CN201110153456.8A patent/CN102270619B/zh not_active Expired - Fee Related
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2016
- 2016-04-25 US US15/137,776 patent/US9543236B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20070077414A1 (en) * | 2005-10-05 | 2007-04-05 | Claus Rudiger | Light-scattering plastics composition having high brightness and use thereof in flat screens |
CN101587868A (zh) * | 2008-05-19 | 2009-11-25 | 联发科技股份有限公司 | 方形扁平无引线半导体封装及其制作方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10833590B2 (en) | 2012-11-14 | 2020-11-10 | Power Integrations, Inc. | Magnetically coupled galvanically isolated communication using lead frame |
CN106104792A (zh) * | 2014-03-24 | 2016-11-09 | 技术研究组合光电子融合基盘技术研究所 | 用于将ic芯片搭载在基板上的基板上的焊盘阵列结构、以及具有该焊盘阵列结构的光模块 |
CN106104792B (zh) * | 2014-03-24 | 2018-09-18 | 技术研究组合光电子融合基盘技术研究所 | 用于将ic芯片搭载在基板上的基板上的焊盘阵列结构、以及具有该焊盘阵列结构的光模块 |
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US20110298117A1 (en) | 2011-12-08 |
TW201216430A (en) | 2012-04-16 |
CN102270619B (zh) | 2014-03-19 |
US20160240459A1 (en) | 2016-08-18 |
US9543236B2 (en) | 2017-01-10 |
US9331052B2 (en) | 2016-05-03 |
US8860193B2 (en) | 2014-10-14 |
US20150035160A1 (en) | 2015-02-05 |
TWI458062B (zh) | 2014-10-21 |
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