201110299 六、發明說明： 【發明所屬之技術領域】 本發明關於欲將具備貫穿Si基板之貫穿電極（TSV : Thfough Silicon Vias)的半導體晶圓或半導體晶片彼此予 以積層而獲得高性能、低消費電力之積層半導體裝置，除 電性導通用之貫穿電極以外，將形成有電性不導通之電極 的半導體裝置彼此予以積層而獲得之積層半導體裝置及積 層半導體裝置之製造方法。 【先前技術】 近年來，電子機器之小型、輕量化、高性能化、低消 費電力化之要求日益增加。爲滿足該要求需要將半導體裝 置之形狀構成更小、更薄，但是形狀之更小、更薄已漸漸 接近物理上之限制。 另外，隨著半導體製程之微細化接近其限制，微細化 速度有鈍化之同時，最先端製品之製造成本亦大爲增加。 因此，不容易獲得更高性能化、低消費電力化之半導體裝 置。 另外，不依賴半導體製程之微細化’而作爲能實現半 導體裝置之小型、輕量化、高性能化、低消費電力化的方 法，有對半導體裝置形成貫穿電極，將半導體裝置彼此施 予三維方式積層的三維積層技術之硏究、開發正被進行。 和習知二維方式之安裝技術’或藉由導線接合之半導體裝 置之多段積層技術比較’將形成有貫穿電極之半導體裝置 -5- 201110299 彼此施予三維方式積層的技術，可以極端縮短配線長度之 同時，可達成理想之配線配置，因此，不僅能大幅減低配 線電阻或配線容量，亦使習知技術上無法實現之新的電路 技術之開發成爲可能。 通常，欲使用貫穿電極對半導體裝置施予三維方式積 層時，以高信賴性將貫穿電極彼此予以連接之技術乃重要 者，另外，隨積層數之增加，發熱量亦增加，熱傳導率之 提升亦成爲重要之關鍵。 爲解決此一問題，專利文獻1揭示在未形成貫穿電極 的區域，形成金屬焊墊或金屬凸塊的半導體裝置之連接方 法。但是，在有貫穿電極的區域和無貫穿電極的區域之間 存在材料之差異，因而在無貫穿電極的區域大多存在金屬 焊墊或金屬凸塊之接著性變弱，容易剝離。另外，貫穿電 極端上之金屬焊墊或金屬凸塊之高度，和無貫穿電極區域 之金屬焊墊或金屬凸塊之高度亦大多存在差異，導致半導 體裝置面內容易被施加不均勻之應力》 另外，專利文獻2揭示在多層基板（印刷配線板）上 介由凸塊連接第1半導體晶片（裝置），第1半導體晶片介 由中介層（interposer )連接於積層半導體裝置之例。 即使在無貫穿電極的區域形成金屬焊墊或金屬凸塊， 據此來減低全體高度之不均勻之情況下，在有貫穿電極的 區域和無貫穿電極的區域之間亦存在著熱傳導率大幅差異 之問題。有貫穿電極區域因爲貫穿電極存在於Si基板內之 故，半導體裝置之表面側與背面側之熱傳導率較高。另外 (S) -6- 201110299 ，在無貫穿電極的區域，不僅電極未直接接觸si基板’貫 穿電極不存在於Si基板內，熱傳導率明顯變低。此舉不僅 降低積層半導體裝置產生之熱之散熱（冷卻）效果’於半 導體裝置面內亦因爲位置不同而產生溫度差，各區域之溫 度差將成爲引起半導體裝置之特性變動的原因。 專利文獻1 :特開2003- 1 335 1 9號公報 專利文獻2 :特開2008-263 005號公報 【發明內容】 (發明所欲解決之課題） 通常，於半導體裝置配置貫穿電極時雖亦受到目的或 設計內容之影響，但大多情況下無法將貫穿電極均等配置 於半導體裝置內。另外，無貫穿電極區域係以和貫穿電極 不同之材料構成，因而無助於半導體裝置之直接連接》 特別是在連接信賴性提升等之目的下，於貫穿電極端 形成金屬焊墊或金屬凸塊時，不僅金屬焊墊或金屬凸塊之 高度部分，就連有貫穿電極區域和無貫穿電極區域間之高 度誤差亦會產生。因此，無貫穿電極區域基於完全未接觸 ，因而無助於半導體裝置之連接。另外，通常在積層半導 體裝置時壓力會被施加於積層方向，在有貫穿電極區域和 無貫穿電極區域，於半導體裝置面內會被施加不均勻之應 力，如此則將導致半導體裝置之破損，或者引起元件特性 之不良之可能性變高。 本發明目的在於提供即使在半導體裝置內之任意位置 201110299 不均勻配置電性導通之貫穿電極時，亦可以實現高信賴性 之半導體裝置之連接，以及高熱傳導率的積層半導體裝置 及積層半導體裝置之製造方法。 (用以解決課題的手段） 本案申請人爲解決上述問題，經由深刻檢討結果發現 ，藉使用和電性導通之貫穿電極不同的電性不導通之電極 、亦即所謂虛擬之電極，將彼等電極均等配置於半導體裝 置面內，則於半導體裝置面內不會被施加不均勻之應力， 可以獲得高信賴性之半導體裝置之連接，可獲得具有高熱 傳導率之積層半導體裝置，而完成本發明。 第1發明之特徵爲’ （1)積層半導體裝置，係將具備 電性導通之貫穿電極與電性不導通之電極的半導體裝置複 數個予以積層而成。 於（1) ’ （2)可於上述兩電極之電極端形成金屬焊 墊或金屬凸塊。金屬焊墊或金屬凸塊，係由元件面側使取 出電極與電性導通之貫穿電極之間介由配線層實施電性導 通。電性導通之貫穿電極係介由配線層對元件區域之電路 動作帶來影響。相對於此，電性不導通之電極，基於未到 達配線層’因而對元件之電路動作不會造成影響。 於（2) ’ （3)可考慮將上述金屬焊墊或金屬凸塊， 形成於元件面側或半導體裝置背面側之其中一方，或（4 )將上述金屬焊墊或金屬凸塊，形成於元件面側及半導體 裝置背面側之兩方。 ⑧ -8 - 201110299 於（1) ， （5)較好是將上述電性導通之貫穿電極與 上述電性不導通之電極，均勻配置於上述半導體裝置內。 於（5) ’ （6)較好是將上述電性導通之貫穿電極與上述 電性不導通之電極’於上述半導體裝置內之至少元件區域 以格子狀均勻配置。 於（2) ’ （7)較好是將上述電性導通之貫穿電極與 上述電性不導通之電極，均勻配置於上述半導體裝置內。 於（7) ，（8)較好是將上述電性導通之貫穿電極與上述 電性不導通之電極’於上述半導體裝置內之至少元件區域 以格子狀均勻配置。 於（3) ’ （9)較好是將上述電性導通之貫穿電極與 上述電性不導通之電極，均勻配置於上述半導體裝置內。 於（9 )’（ 1 〇 )較好是將上述電性導通之貫穿電極與上 述電性不導通之電極，於上述半導體裝置內之至少元件區 域以格子狀均勻配置。 於（4) ’ （11)較好是將上述電性導通之貫穿電極 與上述電性不導通之電極，均勻配置於上述半導體裝置內 。於（11) ，（12)較好是將上述電性導通之貫穿電極與 上述電性不導通之電極，於上述半導體裝置內之至少元件 區域以格子狀均勻配置。 第2發明之特徵爲，（13)積層半導體裝置之製造方 法，係具有： (a )對半導體基板之元件面側之相反側的基板背面 進行硏磨的工程； -9 - 201110299 (b)由上述基板背面對電性不導通之電極孔進行加 工的工程； (C )由上述基板背面對電性導通之貫穿電極孔進行 加工的工程： (d)於上述兩電極孔中沈積側壁絕緣膜、進行加工 ，進而埋設電極材而形成電極的工程； (e )進行上述兩電極端之平坦化而形成半導體裝置 的工程：及 (f) 將藉由上述（a)〜（e)之工程而獲得之半導 體裝置複數個予以積層的工程。 於（13) ，（14)可以另外具有由 (g) 於上述半導體基板上之元件面側形成金屬焊墊 或金屬凸塊的工程；及 (h )於上述半導體基板上之上述貫穿電極側形成金 屬焊墊或金屬凸塊的工程，之中選擇之至少之一工程。 於（1 3 )，（ 1 5 )較好是，上述側壁絕緣膜之加工， 係除去沈積於電極內之絕緣膜之孔底絕緣膜之同時，加工 直至元件面側之電極面爲止。 第3發明之特徵爲，（16)積層半導體裝置之製造方 法，係具有： (a )對半導體基板之元件面側之相反側的基板背面 進行硏磨的工程； (i)於上述基板背面沈積遮罩材的工程； (j )作成用於加工電性不導通之電極孔的遮罩，而 ⑧ -10 - 201110299 進行加工的工程； (k) 作成用於加工電性導通之貫穿電極孔的遮罩， 而進行加工的工程； (d.)於上述兩電極孔中沈積側壁絕緣膜、進行加工 ，進而埋設電極材而形成電極的工程； (e) 進行上述兩電極端之平坦化而形成半導體裝置 的工程；及 (f) 將藉由上述（a )〜（e )之工程而獲得之半導 體裝置複數個予以積層的工程。 於（16)，（丨7)較好是另具有由 (g) 於上述半導體基板上之元件面側形成金屬焊墊 或金屬凸塊的工程；及 (h) 於上述半導體基板上之上述貫穿電極側形成金 屬焊墊或金屬凸塊的工程，之中選擇之至少之一工程。 於（1 6 )，（ 1 8 )較好爲上述側壁絕緣膜之加工，係 除去沈積於電極內之絕緣膜之孔底絕緣膜之同時，加工直 至元件面側之電極面爲止。 第4發明之特徵爲，（19)積層半導體裝置之製造方 法，係具有： (l) 於半導體基板之一面埋設電極材而形成電性導 通之貫穿電極的工程； (m) 硏磨半導體基板之另一面，使電性導通之貫穿 電極露出的工程； (b’）保護上述露出面之同時，由和上述露出面呈同 -11 - 201110299 一方向之面對電性不導通之電極孔進行加工的工程； (d’）於上述電性不導通之電極孔中埋設電極材而形 成電極的工程； (e)進行上述兩電極端之平坦化而形成半導體裝置 的工程；及 (Γ)將藉由上述（1)〜（e)之工程而獲得之半導 體裝置複數個予以積層的工程。 於（1 9 ) ， （ 2 0 )較好是另具有由 (g) 於上述半導體基板上之元件面側形成金屬焊墊 或金屬凸塊的工程；及 (h) 於上述半導體基板上之上述貫穿電極側形成金 屬焊墊或金屬凸塊的工程，之中選擇之至少之一工程。 通常，將形成有貫穿電極之半導體裝置予以積層時所 使用的半導體裝置可以大類區分爲，如圖1所示，在元件 面側與半導體裝置背面側未形成有凸形之金屬焊墊或金屬 凸塊8或9者；如圖2所示，在元件面側或半導體裝置背面 側之其中一方形成有金屬焊墊或金屬凸塊8或9之凸形之電 極者；以及如圖3所示，在元件面側或半導體裝置背面側 之雙方形成有凸形之金屬焊墊或金屬凸塊8或9之者。於圖 1 ’基板1通常爲Si基板，在其表面側被製作之元件區域2 ，係被形成CMOS電路或記憶體元件等，於彼等上部被形 成保護膜3及取出電極4，此乃大多情況者。 將圖1之半導體裝置之元件面側與半導體裝置背面側 接合而積層複數個半導體裝置時，不會發生金屬焊墊或金 -12- ⑧ 201110299 屬凸塊引起之高度不均勻。將該半導體裝置之取出電極4 與電性導通之貫穿電極5予以連接時，通常大多情況下， 無貫穿電極的區域7之接觸面係不供作連接之用，因此無 法藉由無貫穿電極的區域7來強化接合力量。另外，基於 無凹凸、平坦性高，因此元件面側之取出電極4與貫穿電 極5之高度精確度不佳時，Si基板厚度之面內分布變爲不 均勻惡化而導致Si基板之彎曲時，半導體裝置面內將被施 加不均勻之應力，容易導致連接不良。在被連接之電極面 積變爲越小，數目變爲越多時該問題成爲越顯著。 將圖2之半導體裝置之元件面側與半導體裝置背面側 接合而積層複數個半導體裝置時，其中一方側之金屬焊墊 或金屬凸塊8或9之高度部分，將導致有貫穿電極之區域6 與無之區域7間之高度不均勻，雖然元件側之取出電極4與 貫穿電極5之高度精確度多少會惡化，但是乃難以引起連 接不良，此爲其優點。但是，未形成有貫穿電極的區域7 ，基於其中一方側之金屬焊墊或金屬凸塊8或9之高度不均 勻，積層時之壓力容易引起Si基板之彎曲或應力集中等， 引起Si基板之破損或元件特性變動等亦變高。 將圖3之半導體裝置之元件面側與半導體裝置背面側 接合而積層複數個半導體裝置時，基於兩側之金屬焊墊或 金屬凸塊8或9，和圖2比較，即使元件側之取出電極4之高 度與貫穿電極側之電性導通之貫穿電極5之高度精確度呈 現惡化，進而使Si基板厚度之面內分布不均勻而惡化情況 下，亦可以抑制連接不良。但是，積層時係由元件面側與 -13- 201110299 半導體裝置背面側之兩面承受壓力之影響，因此半導體裝 置面內之應力不均勻之發生無法被抑制。 如上述說明，積層半導體裝置時，電極之連接不良、 各電極之高度差異、以及Si基板之平坦性之間存在著密不 可分之關係。 如圖4所示，可以考慮在無貫穿電極的區域7形成金屬 焊墊或金屬凸塊1 〇等，據以減少電極彼此之連接不良之同 時，提升Si基板之平坦性。但是，此一方法中，在電性導 通之貫穿電極5之材料與無貫穿電極的區域7之接觸面基於 材料差異，將導致和無貫穿電極的區域7上被形成之金屬 焊墊或金屬凸塊10之間的密接性惡化，或者在取出電極4 之端或電性導通之貫穿電極5之端所形成之金屬焊墊或金 屬凸塊8、9之高度差異等問題。另外，由圖亦可知，在無 貫穿電極的區域7被作成之金屬焊墊或金屬凸塊1〇，基於 未直接接觸Si基板1，因此和有貫穿電極之區域6比較，熱 傳導率會惡化。 本發明有鑑於上述問題，目的在於提供如圖5之半導 體裝置面內之電極之均勻配置圖所示，除了電性導通之貫 穿電極1 1以外亦將電性不導通之電極1 2，均勻地（例如格 子狀）配置於半導體裝置1 3，如此則可以抑制金屬焊墊或 金屬凸塊引起之高度不均勻之同時，可以提高熱傳導率之 方法。 【實施方式】 ⑧ -14- 201110299 首先，說明電極之形狀。 本發明使用之電性導通之貫穿電極之直徑或形狀、其 間隔並未特別限定，電極爲圓柱時其直徑（或長度）爲 0.3〜200μηι範圍，間隔爲電極直徑之5倍〜1/5程度爲較 好（例如電極直徑爲1 Ομιη時間隔爲50μιη〜2μιη之範圍） 〇 電極之直徑小於0·3μπι時，電極之靜電容量變大之同 時，電阻本身亦增加，虛擬之電極之利用優點變少。反之 ，電極之直徑大於200μιη時，半導體裝置內之電極之面積 佔比變大，能配置半導體元件之面積變小，虛擬之電極之 利用優點變少。 電極間隔大於直徑之5倍時，無電極區域增加太多， 對該區域進行積層加壓時之應力容易集中。另外，電極間 隔小於直徑之5時，相鄰電極間連接之可能性變高。 另外，電性不導通之電極之直徑或其間隔亦無特別限 制，可以和電性導通之貫穿電極同樣考量。但是，於電極 端形成金屬凸塊等時，較好是電性導通之貫穿電極與電性 不導通之電極成爲同一形狀。此乃因爲形成金屬凸塊等時 ，凸塊形狀不同時，凸塊高度會變化，因此藉由其他方法 再度調整凸塊高度時不限定於此。 以下說明電極之深度（長度）。 通常、電極之深度非以形狀爲優先被決定者，就電路 設計之觀點而言，係由最終之積層數及其厚度之限制値， 製程上之技術限制等來決定。電極之深度越淺，亦即晶圓 -15- 201110299 厚度或晶片厚度越薄時，不僅薄厚度之晶圓厚度或晶片厚 度之控制變難’晶圓或晶片之處理以及作業亦變難，晶圓 或晶片容易破損。 反之’電極之深度越深，亦即晶圓厚度或晶片厚度變 爲越厚時’小徑（高深寬比）孔之形成變爲困難。當然， 電極之深度越深，電阻値亦增加，靜電容量亦增加，不利 於虛擬之電極之使用。通常，作爲信號線使用之電極之深 度較好是1〇〇μηι以下，較理想爲5〜50μηι之範圍。 另外’電性導通之貫穿電極係貫穿基板而需要和元件 面側之內部電極（或元件區域最上部之取出電極）接觸， 但是電性不導通之電極不貫穿基板而停止於基板這邊乃重 要者。電性不導通之電極太早停止於元件區域這邊時，基 於基板內不存在電極之部分之影響，就熱傳導率觀點而言 爲不利。反之，貫穿時，會對元件面側之電路帶來不良影 響。因此，較好是電性不導通之電極之深度（長度）僅較 電性導通之貫穿電極之深度（長度）稍微淺。理想上，較 好是由元件區域分離1 μ m以上。 同樣地，貫穿基板的電性導通之貫穿電極，其和元件 區域間之距離太近時對電路特性會有不良影響，因此，電 性導通之貫穿電極較好是配置於由元件區域起分離數μιη ，理想爲1 μ m以上之位置。 以下說明電極之形成方法。通常，電極之形成方法可 以大分爲前鑕孔（via-First)與後鑽孔（via-Last)。 如圖6所示，前鑽孔，係在半導體裝置完成前，於此 ⑧ -16- 201110299 爲元件區域2之製作前欲形成電性導通之貫穿電極孔15 ’ 定位精確度高 '適合於微細電極之形成。於貫穿電極I5之 中，沈積貫穿電極內之側壁絕緣膜1 6，之後形成塡埋電極 1 7，最後使塡埋電極1 7之端平坦化，而形成個別電性獨立 之電性導通之貫穿電極5。此情況下，之後接續之製程熱 處理溫度大多較高，因此，作爲貫穿電極材料大多使用多 晶矽（Poly-Si )或鎢（W)等。另外，亦有在元件區域2 製作之後形成貫穿電極孔1 5，但此情況下，之後接續之製 程熱處理溫度可以抑制爲較低，因此大多使用Cu (銅）等 之金屬。 電性導通之貫穿電極5之形成後，形成元件區域2、配 線層14、取出電極4，完成半導體裝置。之後，於取出電 極4上形成元件面側之金屬焊墊或金屬凸塊8之後，藉由基 板硏磨使基板薄化，露出貫穿電極端而獲得貫穿電極露出 面18。以不堵塞貫穿電極露出面18的方式藉由保護膜3保 護半導體裝置背面側，最後，形成半導體裝置背面側之金 屬焊墊或金屬凸塊9。 如上述說明，前鑽孔時，欲形成電性不導通之電極時 ，於該區域無法配置電路，因而無法使用之浪費之區域增 加。因此，前鑽孔時，同時作成電性導通之貫穿電極與電 性不導通之電極乃極爲困難者。 於前鑽孔欲形成電性不導通之電極時，須於半導體裝 置之完成後，如圖7 ( 1 )所示，薄化基板使電性導通之貫 穿電極5由基板背面露出之後，形成（貫穿電極露出面18 -17- 201110299 )、電性不導通之電極19。 首先，藉由某一方法將電性導通之貫穿電極露出面18 覆蓋之同時，進行電性不導通之電極孔1 9之加工，對電極 孔1 9內部1之側壁絕緣膜1 6之沈積與塡埋電極1 7之形成， 之後進行1 7端之平坦化，而形成電性不導通之電極2〇。之 後，藉由微影成像技術與乾蝕刻工程，進行電性導通之貫 穿電極5之端之開口，於兩電極5與20之端形成電極之後， 進行平坦化處理來調整電性導通之貫穿電極5與電性不導 通之電極20之端之高度。最後，欲於兩電極端形成金屬焊 墊或金屬凸塊9，不僅製程時間變長，製程成本亦變高等 諸多問題存在。 如上述說明，欲調整電極之高度時’可於電極形成後 削薄兩電極端而調整高度之方法，另外’薄化基板時’在 電性導通之貫穿電極露出基板表面之稍前停止薄化’於此 狀態下形成電性不導通之電極’之後’依據各S丨基板進行 電極之加工而調整兩電極之高度之法法亦可。 另外，如圖8所示，後鑽孔’係在半導體裝置完成後 薄化基板之後，由元件面側之相反側之基板背面形成貫穿 電極。基於薄的基板之處理方法之問題’或熱處理溫度之 限制（通常於強固之支撐基板等藉由樹脂或接著劑等任一 方法予以貼合）等，而容易受到製程之限制。但是’容易 大略同時作成電性導通之貫穿電極5與電性不導通之電極 20 〇 圖8表示大略同時作成電性導通之貫穿電極5與電性不 ⑧ -18- 201110299 導通之電極20之方法。首先，於完成之半導體裝置之元件 面側形成金屬焊墊或金屬凸塊8，之後，硏磨基板使薄化 。之後，進行電性不導通之電極用的微影成像技術工程與 電極孔19之加工（不貫穿基板），之後，進行電性導通之 貫穿電極用的微影成像技術工程與其之貫穿電極孔1 5之加 工（使貫穿基板直至元件側爲止）。 阻劑除去之後，於電性導通之貫穿電極孔15與電性不 導通之電極孔1 9之兩電極孔同時沈積側壁絕緣膜1 6之後， 除去電性導通之貫穿電極孔15之孔底絕緣膜之全部。此時 ，於電性導通之貫穿電極孔1 5之孔底存在元件分離絕緣膜 或層間絕緣膜等時，彼等亦同時被除去。除去孔底絕緣膜 之全部之後，形成塡埋電極17，最後進行電極端之平坦化 〇 如此則，可以同時作成電性導通之貫穿電極5與電性 不導通之電極20。此情況下，電性導通之貫穿電極5之端 之高度與電性不導通之電極20之端之高度成爲相同。最後 ，於兩電極端形成金屬焊墊或金屬凸塊9，而獲得積層半 導體裝置。 另外，如圖9所不’對電極加工用遮罩採取對策，可 以更簡單作成電性導通之貫穿電極5與電性不導通之電極 20 〇 如圖9(1)所示，薄化完成之半導體裝置之後，沈積 作爲硬質遮罩之CVD氧化膜21。首先，於CVD氧化膜21之 表面，進行電性不導通之電極用的微影成像技術工程與該 -19 - 201110299 電極用之硬質遮罩之加工。此時，CVD氧化膜並未全部被 加工而殘留適當之厚度，決不使露出Si表面。接著，對該 CVD氧化膜2 1進行電性導通之貫穿電極用的微影成像技術 工程，進行該貫穿電極用之硬質遮罩之加工。此時，此時 ，CVD氧化膜21全部被除去而使Si表面露出。於此狀態下 ，進行電性導通之貫穿電極孔1 5之加工時，C VD氧化膜2 1 之薄的區域較快被蝕刻而被除去，S i呈露出而作爲電性不 導通之電極用之孔，時電性不導通之電極孔19被形成，因 此可以同時形成電性導通之貫穿電極孔15與電性不導通之 電極孔1 9。之後，經由圖8 ( 5 )〜（7 )之工程，獲得和 圖8同樣之積層半導體裝置。 以下參照圖1 〇之流程圖，以圖8爲例說明半導體裝置 之積層方法及積層半導體裝置之一實施形態，係以後鑽孔 爲例加以說明。 首先，於完成之半導體裝置之元件側形成金屬焊墊或 金屬凸塊8。該金屬凸塊8之佈局，係和該元件面側之相反 側之半導體裝置背面側成爲同一佈局，因此積層時，係於 同一位置呈重疊的方式進行佈局。在藉由捲帶等對形成有 該金屬凸塊8的元件面施予保護之狀態下，使基板薄化。 之後’於薄化之基板之背面，進行電性不導通之電極 20用的微影成像技術工程與其之電極孔19之加工（不貫穿 基板），之後’進行電性導通之貫穿電極5用的微影成像 技術工程與其之貫穿電極孔1 5之加工（使貫穿基板直至元 件側爲止）。於電性導通之貫穿電極孔1 5與電性不導通之 ⑧ -20- 201110299 電極孔1 9，藉由CVD氧化膜來沈積側壁絕緣膜1 6，藉由乾 蝕刻完全除去孔底之CVD氧化膜、元件分離絕緣膜、層間 絕緣膜等，使元件側內部之電極露出。之後，於兩電極之 內壁藉由濺鍍裝置沈積種層（Ta/ Cu )之後，藉由銅（ Cu)鍍層完全塡埋電極內而形成塡埋電極17，最後藉由 CMP使兩電極端平坦化。 接著，於兩電極端進行金屬凸塊9之形成用的微影成 像技術工程，藉由濺鍍裝置沈積種金屬之後，進行金屬凸 塊9用之金屬鍍層。藉由CMP平坦化鍍層後之金屬凸塊之 後，除去阻劑而於半導體裝置背面側形成金屬凸塊9。如 此則，獲得積層半導體裝置。 將此狀態之積層半導體裝置之元件側與另一積層半導 體裝置之半導體裝置背面側進行定位，施加適當之加熱與 壓力予以積層。此時，凸塊彼此之連接係以暫固定之程度 實施連接。進行目的之積層數之積層後，作爲實質連接而 藉由較暫時連接更強之壓力時施加壓而將積層半導體彼此 予以連接。藉由切片工程將獲得之積層半導體裝置切斷， 獲得積層半導體晶片。由該積層半導體晶片側面塡充塡料 (under-fill )劑，最後加熱硬化塡料劑而完成積層半導 體裝置。 以下更詳細說明本發明之實施形態，但本發明不限定 於以下實施形態之內容。 (第1實施形態） -21 - 201110299 於此’說明以後鑽孔方式形成有貫穿電極之積層半導 體裝置之實施形態。首先，說明於完成之半導體裝置之元 件側形成金屬凸塊之方法。於側壁絕緣膜之最上部，於面 內均勻配置以A1形成之取出用之A1電極，彼等之高度均爲 同一。介由電路設計事先形成和內部電路之間成爲電性導 通之A1電極與電性不導通之A1電極之雙方。 藉由濺鍍裝置沈積成爲種之金屬，阻劑塗布之後，藉 由微影成像技術僅於A丨電極區域實施開口，之後，藉由鍍 層於開口部成長金屬。作爲金屬材料通常較好是使用Au 、Cu、Ni等，但亦有使用焊接材料之Sn (錫）。另外， 金屬鍍層材料並非一種，而可爲複數種。之後，爲整合金 屬凸塊高度，而使金屬凸塊上端平坦化。平坦化之後，除 去阻劑，藉由溼蝕刻除去種金屬，僅於A1金屬上形成金屬 凸塊。 於元件側被形成有凸塊，因此，以保護帶保護凸塊面 之狀態下將晶圓薄化至30μηι。晶圓之薄化可使用通常之 背面硏磨裝置進行，硏磨面被施予應力消除處理。 以下說明由上述半導體裝置之背面形成電極之方法。 薄化之半導體裝置，基於無法依自重來保持而被貼合於支 撐基板。首先，爲於基板背面形成電性不導通之電極用之 孔，而使用氧化膜作爲硬質遮罩。該硬質遮罩，不僅爲防 止電極與Si基板，以及電極間之導通，亦作爲背面之保護 膜機能。使用200°C以下之低溫可以成膜的CVD氧化膜。 硬質遮罩用之微影成像技術工程之後，藉由乾蝕刻進BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer or a semiconductor wafer having a through-substrate (TSV: Thfough Silicon Vias) through a Si substrate, which is laminated to obtain high-performance, low-consumption power. The multilayer semiconductor device is a method of manufacturing a multilayer semiconductor device and a multilayer semiconductor device obtained by laminating semiconductor devices in which electrical non-conducting electrodes are formed, in addition to a through-electrode. [Prior Art] In recent years, there has been an increasing demand for small size, light weight, high performance, and low power consumption of electronic equipment. To meet this requirement, the shape of the semiconductor device needs to be smaller and thinner, but the smaller and thinner shape has gradually approached the physical limit. In addition, as the miniaturization of the semiconductor process approaches its limitation, the miniaturization speed is passivated, and the manufacturing cost of the most advanced products is greatly increased. Therefore, it is not easy to obtain a semiconductor device with higher performance and lower power consumption. Further, as a method for realizing reduction in size, weight, performance, and power consumption of a semiconductor device without depending on the miniaturization of the semiconductor process, a through electrode is formed on the semiconductor device, and the semiconductor device is laminated in a three-dimensional manner. Research and development of three-dimensional layering technology are being carried out. Compared with a conventional two-dimensional mounting technique or a multi-layer lamination technique of a semiconductor device by wire bonding, a technique in which a semiconductor device having a through-electrode is formed in a three-dimensional manner can be extremely shortened. At the same time, an ideal wiring arrangement can be achieved, so that not only the wiring resistance or the wiring capacity can be greatly reduced, but also the development of new circuit technologies that cannot be realized by conventional techniques becomes possible. In general, when a three-dimensional layer is applied to a semiconductor device using a through electrode, a technique of connecting the through electrodes with high reliability is important, and as the number of layers increases, the amount of heat generation increases, and the heat conductivity increases. Be the key to success. In order to solve this problem, Patent Document 1 discloses a method of connecting semiconductor devices in which metal pads or metal bumps are formed in a region where a through electrode is not formed. However, there is a difference in material between the region having the through electrode and the region having no through electrode. Therefore, in the region without the through electrode, the adhesion of the metal pad or the metal bump is often weakened, and the peeling is easy. In addition, the height of the metal pad or the metal bump on the electrode end and the height of the metal pad or the metal bump without the through electrode region are mostly different, which causes the unevenness of the semiconductor device to be unevenly applied. Further, Patent Document 2 discloses an example in which a first semiconductor wafer (device) is connected to a multilayer substrate (printed wiring board) via a bump, and the first semiconductor wafer is connected to the laminated semiconductor device via an interposer. Even if a metal pad or a metal bump is formed in a region without a through electrode, and thus the unevenness of the entire height is reduced, there is a large difference in thermal conductivity between the region having the through electrode and the region having no through electrode. The problem. In the through electrode region, since the through electrode exists in the Si substrate, the thermal conductivity of the surface side and the back side of the semiconductor device is high. In addition, (S) -6- 201110299, in the region without the through electrode, not only the electrode does not directly contact the si substrate, but the through electrode does not exist in the Si substrate, and the thermal conductivity is remarkably low. This not only reduces the heat dissipation (cooling) effect of the heat generated by the laminated semiconductor device, but also causes a temperature difference in the surface of the semiconductor device due to the difference in position, and the temperature difference between the regions causes a variation in the characteristics of the semiconductor device. [Patent Document 1] Japanese Laid-Open Patent Publication No. JP-A No. 2008-263 005. SUMMARY OF THE INVENTION (Problems to be Solved by the Invention) Generally, when a through electrode is disposed in a semiconductor device, it is also subjected to The purpose or the influence of the design content, but in many cases, the through electrodes cannot be equally disposed in the semiconductor device. In addition, the non-through electrode region is made of a material different from the through electrode, and thus does not contribute to the direct connection of the semiconductor device. In particular, in the purpose of improving the connection reliability, a metal pad or a metal bump is formed at the through electrode end. In addition, not only the height portion of the metal pad or the metal bump, but also the height error between the through electrode region and the non-through electrode region may occur. Therefore, the non-through electrode region is based on being completely untouched, and thus does not contribute to the connection of the semiconductor device. In addition, generally, when a semiconductor device is laminated, pressure is applied to the lamination direction, and in the through-electrode region and the non-penetrating electrode region, uneven stress is applied to the surface of the semiconductor device, which may cause damage of the semiconductor device, or The possibility of causing a defect in the characteristics of the element becomes high. An object of the present invention is to provide a highly reliable semiconductor device connection and a high thermal conductivity laminated semiconductor device and a multilayer semiconductor device, even when an electrically conductive through electrode is unevenly disposed at any position in the semiconductor device 201110299. Production method. (Means for Solving the Problem) In order to solve the above problems, the applicant of the case found through the deep review that the electrodes that are electrically non-conducting, that is, the so-called virtual electrodes, which are different from the through electrodes of the electrical conduction, are When the electrodes are uniformly disposed in the surface of the semiconductor device, uneven stress is not applied to the surface of the semiconductor device, and connection of a highly reliable semiconductor device can be obtained, and a laminated semiconductor device having high thermal conductivity can be obtained, and the present invention can be completed. . According to a first aspect of the invention, the (1) laminated semiconductor device is obtained by laminating a plurality of semiconductor devices including an electrically conductive through electrode and an electrically non-conductive electrode. A metal pad or a metal bump may be formed on the electrode ends of the above two electrodes at (1)' (2). The metal pad or the metal bump is electrically connected to the through electrode of the electrode and the conductive electrode through the wiring layer from the element surface side. The electrically conductive through-electrode affects the circuit operation of the component region via the wiring layer. On the other hand, the electrode that is electrically non-conductive does not affect the circuit operation of the element based on the failure of the wiring layer. (2) ' (3) It is conceivable that the metal pad or the metal bump is formed on one of the element surface side or the back side of the semiconductor device, or (4) the metal pad or the metal bump is formed on the metal pad or the metal bump. Both the element side and the back side of the semiconductor device. In the above (1), (5), it is preferable that the above-mentioned electrically conductive through electrode and the electrically non-conductive electrode are uniformly disposed in the semiconductor device. In (5)' (6), it is preferable that at least the element region of the above-mentioned semiconductor device in which the above-mentioned electrically conductive through electrode and the electrically non-conductive electrode are disposed in a lattice shape are uniformly arranged. Preferably, in (2)' (7), the electrically conductive through electrode and the electrically non-conductive electrode are uniformly disposed in the semiconductor device. Preferably, in (7) and (8), at least the element regions of the electrically conductive through electrode and the electrically non-conductive electrode are disposed in a lattice shape in a uniform manner in the semiconductor device. Preferably, in (3)' (9), the electrically conductive through electrode and the electrically non-conductive electrode are uniformly disposed in the semiconductor device. Preferably, the (9)' (1 〇 ) electrode is electrically conductively connected to the penetrating electrode and the electrically non-conductive electrode, and at least the element region of the semiconductor device is uniformly arranged in a lattice shape. Preferably, in (4)' (11), the electrically conductive through electrode and the electrically non-conductive electrode are uniformly disposed in the semiconductor device. Preferably, in (11) and (12), the electrically conductive through electrode and the electrically non-conductive electrode are uniformly arranged in a lattice shape in at least an element region of the semiconductor device. According to a second aspect of the invention, in the method of manufacturing the laminated semiconductor device, the method of manufacturing the laminated semiconductor device includes: (a) honing the back surface of the substrate opposite to the element surface side of the semiconductor substrate; -9 - 201110299 (b) (C) a process of processing the electrically conductive through-electrode hole from the back surface of the substrate: (d) depositing a sidewall insulating film in the two electrode holes, a process of forming an electrode by embedding an electrode material; (e) performing a planarization of the two electrode ends to form a semiconductor device: and (f) obtaining the process by the above (a) to (e) The semiconductor device has a plurality of layers to be stacked. (13), (14) may additionally have a process of forming a metal pad or a metal bump on the element surface side of the semiconductor substrate; and (h) forming the through electrode side on the semiconductor substrate At least one of the selection of metal pads or metal bumps works. In the above (1 3), (15), it is preferable that the processing of the side wall insulating film is performed until the hole bottom insulating film of the insulating film deposited in the electrode is removed, and the electrode surface is processed up to the element surface side. According to a third aspect of the invention, the method for manufacturing a multilayer semiconductor device includes: (a) honing a back surface of the substrate opposite to the element surface side of the semiconductor substrate; (i) depositing the back surface of the substrate (a) a mask for processing electrical non-conducting electrode holes, and a process for processing 8-10 - 201110299; (k) forming a through-electrode hole for processing electrical conduction a process of processing the mask; (d.) a process of depositing a sidewall insulating film in the two electrode holes, processing, and embedding the electrode material to form an electrode; (e) forming the planarization of the two electrode ends Engineering of a semiconductor device; and (f) a plurality of semiconductor devices obtained by the processes of the above (a) to (e) are stacked. (16), (丨7) preferably further comprising: (g) forming a metal pad or a metal bump on the surface side of the element on the semiconductor substrate; and (h) performing the above-described through-through on the semiconductor substrate At least one of the selections of the metal side forming the metal pad or the metal bump is performed. In the above (1 6 ), (18), it is preferable that the above-mentioned sidewall insulating film is processed until the hole bottom insulating film deposited on the electrode is removed, and the electrode surface is processed up to the element surface side. According to a fourth aspect of the invention, a method of manufacturing a multilayer semiconductor device includes: (1) a step of embedding an electrode material on one surface of a semiconductor substrate to form an electrically conductive through electrode; (m) honing the semiconductor substrate On the other hand, the through-electrode is electrically exposed; (b') protecting the exposed surface, and processing the electrode hole facing the electrically non-conducting direction in the same direction as the above-mentioned exposed surface -11 - 201110299 (d') a process of forming an electrode by embedding an electrode material in the electrode hole of the electrically non-conducting electrode; (e) performing a planarization of the two electrode ends to form a semiconductor device; and (Γ) A plurality of semiconductor devices obtained by the above-described processes (1) to (e) are stacked. Preferably, the (1 9 ) (20) project has a step of forming a metal pad or a metal bump on the surface side of the device on the semiconductor substrate; and (h) the above-mentioned semiconductor substrate At least one of the works selected to form a metal pad or a metal bump through the electrode side. In general, a semiconductor device used for laminating a semiconductor device having a through electrode can be classified into a large type, as shown in FIG. 1, a metal pad or a metal bump is not formed on the element side and the back side of the semiconductor device. Block 8 or 9; as shown in FIG. 2, a metal pad or a convex electrode of the metal bump 8 or 9 is formed on one of the element side or the back side of the semiconductor device; and as shown in FIG. A convex metal pad or metal bump 8 or 9 is formed on both the element surface side and the back surface side of the semiconductor device. In Fig. 1, the substrate 1 is usually a Si substrate, and the element region 2 formed on the surface side thereof is formed into a CMOS circuit or a memory device, and the protective film 3 and the extraction electrode 4 are formed on the upper portion thereof. Situation. When a plurality of semiconductor devices are laminated by bonding the element surface side of the semiconductor device of Fig. 1 to the back surface side of the semiconductor device, the height unevenness caused by the metal pad or the bumps of the metal -12-8 201110299 does not occur. When the extraction electrode 4 of the semiconductor device is connected to the electrically conductive through electrode 5, in many cases, the contact surface of the region 7 having no through electrode is often not used for connection, and therefore cannot be used without a through electrode. Zone 7 to strengthen the joint strength. In addition, since there is no unevenness and high flatness, when the height accuracy of the extraction electrode 4 and the penetrating electrode 5 on the element surface side is not good, when the in-plane distribution of the thickness of the Si substrate becomes uneven and the Si substrate is bent, Uneven stress is applied to the surface of the semiconductor device, which tends to cause poor connection. The smaller the number of electrodes to be connected becomes, the more significant the number becomes. When a plurality of semiconductor devices are laminated by bonding the element surface side of the semiconductor device of FIG. 2 to the back surface side of the semiconductor device, the metal pad or the height portion of the metal bump 8 or 9 on one of the sides will cause the region 6 through the electrode. The height unevenness between the area 7 and the area No. 7 is somewhat deteriorated, although the height accuracy of the extraction electrode 4 and the through electrode 5 on the element side is somewhat deteriorated, but it is difficult to cause connection failure, which is an advantage. However, the region 7 of the through electrode is not formed, and the height of the metal pad or the metal bump 8 or 9 on one side is not uniform, and the pressure at the time of lamination tends to cause bending or stress concentration of the Si substrate, etc., causing the Si substrate. Damage or variations in component characteristics also become high. When a plurality of semiconductor devices are laminated by bonding the element surface side of the semiconductor device of FIG. 3 to the back surface side of the semiconductor device, the metal pads or metal bumps 8 or 9 on both sides are compared with FIG. The height accuracy of the through electrode 5 which is electrically connected to the through electrode side is deteriorated, and the uneven distribution in the thickness of the Si substrate is deteriorated, and the connection failure can be suppressed. However, in the case of laminating, the influence of the stress on the surface side of the element side and the back side of the semiconductor device is not affected, so that the occurrence of stress unevenness in the surface of the semiconductor device cannot be suppressed. As described above, when the semiconductor device is laminated, there is a close relationship between the poor connection of the electrodes, the difference in height between the electrodes, and the flatness of the Si substrate. As shown in Fig. 4, it is conceivable to form a metal pad or a metal bump 1 in the region 7 having no through electrode, thereby reducing the flatness of the Si substrate while reducing the connection failure between the electrodes. However, in this method, the contact surface between the material of the electrically conductive through electrode 5 and the region 7 without the through electrode is based on the material difference, and the metal pad or metal bump formed on the region 7 with and without the through electrode will be formed. The adhesion between the blocks 10 is deteriorated, or the height difference of the metal pads or the metal bumps 8, 9 formed at the end of the electrode 4 or the end of the through electrode 5 which is electrically conducted. Further, as is apparent from the figure, the metal pad or the metal bump 1 which is formed in the region 7 without the through electrode is not directly in contact with the Si substrate 1, and therefore the thermal conductivity is deteriorated as compared with the region 6 through which the electrode is penetrating. The present invention has been made in view of the above problems, and it is an object of the present invention to provide an electrode 12 in an electrically non-conducting manner, in addition to the electrically conductive through electrode 1 1 , as shown in the uniform arrangement of the electrodes in the surface of the semiconductor device of FIG. 5 . The semiconductor device 13 is disposed (for example, in a lattice shape), and thus the method of improving the thermal conductivity while suppressing the height unevenness caused by the metal pad or the metal bump can be suppressed. [Embodiment] 8 -14- 201110299 First, the shape of the electrode will be described. The diameter or shape of the through-electrode of the electrically conductive electrode used in the present invention is not particularly limited. The diameter (or length) of the electrode when the electrode is a cylinder is in the range of 0.3 to 200 μm, and the interval is 5 times to 1/5 of the electrode diameter. It is preferable (for example, when the electrode diameter is 1 Ομηη, the interval is 50 μm 〜2 μιη). When the diameter of the 〇 electrode is less than 0·3 μπι, the electrostatic capacity of the electrode becomes larger, and the resistance itself increases, and the advantage of the virtual electrode is changed. less. On the other hand, when the diameter of the electrode is larger than 200 μm, the area ratio of the electrode in the semiconductor device becomes large, and the area where the semiconductor element can be arranged becomes small, and the advantage of use of the dummy electrode is small. When the electrode spacing is greater than 5 times the diameter, the electrodeless region is increased too much, and the stress is easily concentrated when the region is laminated and pressurized. Further, when the electrode spacing is less than 5 of the diameter, the possibility of connection between adjacent electrodes becomes high. Further, the diameter of the electrode which is electrically non-conductive or the interval thereof is not particularly limited, and may be considered in the same manner as the through-electrode which is electrically conductive. However, when a metal bump or the like is formed on the electrode end, it is preferable that the through-electrode that is electrically conductive has the same shape as the electrode that is electrically non-conductive. This is because when a metal bump or the like is formed, the height of the bump changes when the shape of the bump is different. Therefore, the height of the bump is not limited to this by other methods. The depth (length) of the electrode will be described below. Generally, the depth of the electrode is not determined by the shape priority, and from the viewpoint of circuit design, it is determined by the number of layers and the thickness of the final layer, the technical limitations of the process, and the like. The shallower the depth of the electrode, that is, the thinner the thickness of the wafer or the thickness of the wafer, the thinner the thickness of the wafer or the thickness of the wafer, the more difficult it is to control the wafer thickness or wafer thickness. The circle or wafer is easily broken. On the other hand, the deeper the depth of the electrode, that is, the thicker the wafer thickness or the thickness of the wafer, the more difficult it is to form the small diameter (high aspect ratio) hole. Of course, the deeper the electrode is, the higher the resistance 値 and the higher the electrostatic capacity, which is disadvantageous for the use of the dummy electrode. In general, the depth of the electrode used as the signal line is preferably 1 〇〇 μηι or less, more preferably 5 to 50 μηι. In addition, the 'electrical conduction through-electrode penetrates the substrate and needs to be in contact with the internal electrode on the element surface side (or the upper extraction electrode of the element region). However, it is important that the electrically non-conductive electrode does not penetrate the substrate and stops on the substrate. By. When the electrode which is electrically non-conductive is stopped too early on the element region, it is disadvantageous from the viewpoint of thermal conductivity based on the influence of the portion where the electrode is not present in the substrate. Conversely, when it is penetrated, it will adversely affect the circuit on the component side. Therefore, it is preferred that the depth (length) of the electrode which is electrically non-conductive is only slightly shallower than the depth (length) of the through electrode which is electrically conducted. Ideally, it is preferable to separate 1 μ m or more from the element region. Similarly, the through-electrode that is electrically conducted through the substrate has a bad influence on the circuit characteristics when the distance between the component and the device region is too close. Therefore, the electrically conductive through-electrode is preferably disposed in the component region. Μιη , ideally above 1 μ m. The method of forming the electrode will be described below. Generally, the electrode formation method can be broadly divided into a via-first and a via-Last. As shown in FIG. 6, the front hole is formed before the completion of the semiconductor device, and the through-electrode hole 15' is formed to be electrically conductive before the fabrication of the element region 2 from 8 to 16 to 201110299. The formation of electrodes. In the through electrode I5, the sidewall insulating film 16 is deposited in the electrode, and then the buried electrode 17 is formed, and finally the end of the buried electrode 17 is planarized to form an electrical independent electrical conduction. Electrode 5. In this case, since the subsequent process heat treatment temperature is often high, polycrystalline silicon (Poly-Si) or tungsten (W) is often used as the through electrode material. Further, although the through electrode hole 15 is formed after the element region 2 is formed, in this case, the subsequent heat treatment temperature of the process can be suppressed to be low, and therefore a metal such as Cu (copper) is often used. After the formation of the electrically conductive through electrode 5, the element region 2, the wiring layer 14, and the extraction electrode 4 are formed to complete the semiconductor device. Thereafter, after the metal pad or the metal bump 8 on the element surface side is formed on the take-out electrode 4, the substrate is thinned by the substrate honing, and the through electrode end is exposed to obtain the through electrode exposed surface 18. The back surface side of the semiconductor device is protected by the protective film 3 so as not to block the through electrode exposed surface 18, and finally, the metal pad or metal bump 9 on the back side of the semiconductor device is formed. As described above, when an electrode that is electrically non-conductive is formed in the front drilling, the circuit cannot be disposed in this area, and the wasteful area that cannot be used is increased. Therefore, it is extremely difficult to make the through-electrode and the electrically non-conducting electrode which are electrically conductive at the same time in the front drilling. When the electrode is to be drilled to form an electrically non-conducting electrode, after the completion of the semiconductor device, as shown in FIG. 7 (1), the thinned substrate is formed by exposing the electrically conductive through electrode 5 to the back surface of the substrate. Through the electrode exposed surface 18 -17- 201110299 ), the electrode 19 is electrically non-conductive. First, the electrically conductive non-conducting electrode hole 19 is processed while the electrically conductive through-electrode exposed surface 18 is covered by a method, and the sidewall insulating film 16 is deposited on the inner side of the electrode hole 19. The formation of the buried electrode 17 is followed by planarization of the 17 terminals to form an electrode 2 that is electrically non-conducting. Thereafter, by means of a lithography imaging technique and a dry etching process, an opening of the through-electrode 5 at the end of the electrical conduction is performed, and after forming electrodes at the ends of the two electrodes 5 and 20, a planarization process is performed to adjust the through-electrode of the electrical conduction. 5 is the height of the end of the electrode 20 that is electrically non-conducting. Finally, in order to form metal pads or metal bumps 9 at the two electrode ends, not only the process time becomes long, but also the process cost becomes high. As described above, when the height of the electrode is to be adjusted, the method of adjusting the height by thinning the two electrode ends after the electrode is formed, and the case of "thinning the substrate" is stopped before the electrically conductive through electrode exposes the surface of the substrate. It is also possible to adjust the height of the two electrodes by performing electrode processing on each of the S? substrates after forming an electrode that is electrically non-conductive in this state. Further, as shown in Fig. 8, the post-drilled hole is formed by forming a through electrode on the back surface of the substrate on the opposite side of the element surface side after the semiconductor device is thinned. The problem of the processing method based on a thin substrate or the limitation of the heat treatment temperature (usually, the bonding of a strong supporting substrate or the like by a resin or an adhesive) is liable to be limited by the process. However, it is easy to make the conductive electrode 5 and the electrically non-conducting electrode 20 at the same time. FIG. 8 shows a method in which the through electrode 5 and the electrode 20 which are electrically connected to each other are electrically connected. . First, a metal pad or metal bump 8 is formed on the surface side of the completed semiconductor device, and then the substrate is thinned. Thereafter, the lithography imaging technique for the electrode that is electrically non-conductive is performed, and the electrode hole 19 is processed (not through the substrate), and then the lithography imaging technology for the through-electrode that is electrically conductive is passed through the electrode hole 1 Processing of 5 (make the substrate through to the component side). After the resist is removed, after the sidewall insulating film 16 is simultaneously deposited between the electrically conductive through electrode hole 15 and the electrically non-conductive electrode hole 19, the hole bottom insulation of the electrically conductive through electrode hole 15 is removed. All of the film. At this time, when an element isolation insulating film or an interlayer insulating film or the like is present at the bottom of the through-electrode hole 15 which is electrically conducted, they are also removed at the same time. After removing all of the hole bottom insulating film, the buried electrode 17 is formed, and finally the electrode end is flattened. Thus, the conductive electrode 5 and the electrically non-conductive electrode 20 can be simultaneously formed. In this case, the height of the end of the through-electrode 5 electrically conductive is the same as the height of the end of the electrode 20 which is electrically non-conductive. Finally, a metal pad or metal bump 9 is formed on both electrode ends to obtain a laminated semiconductor device. Further, as shown in Fig. 9, the countermeasure for the electrode processing mask can be made to make the electrode 5 and the electrically non-conductive electrode 20 which are electrically conductive, as shown in Fig. 9 (1), and the thinning is completed. After the semiconductor device, a CVD oxide film 21 as a hard mask is deposited. First, on the surface of the CVD oxide film 21, a lithographic imaging technique for an electrode that is electrically non-conducting is performed, and a hard mask for the electrode of the -19 - 201110299 is processed. At this time, not all of the CVD oxide film was processed to have a proper thickness, and the Si surface was never exposed. Next, a lithographic imaging technique for a through electrode for electrically conducting the CVD oxide film 21 is performed, and the hard mask for the through electrode is processed. At this time, at this time, all of the CVD oxide film 21 is removed to expose the Si surface. In this state, when the through-electrode hole 15 is electrically conductive, the thin region of the C VD oxide film 2 1 is quickly removed by etching, and the S i is exposed to be used as an electrode for electrical non-conduction. The hole and the electrode hole 19 which is electrically non-conductive are formed, so that the electrically conductive through electrode hole 15 and the electrically non-conductive electrode hole 19 can be simultaneously formed. Thereafter, a multilayer semiconductor device similar to that of Fig. 8 is obtained through the processes of Figs. 8 (5) to (7). Hereinafter, an embodiment of a method of laminating a semiconductor device and an embodiment of a stacked semiconductor device will be described with reference to FIG. First, a metal pad or metal bump 8 is formed on the component side of the completed semiconductor device. The metal bumps 8 are arranged in the same layout on the back side of the semiconductor device on the opposite side of the element surface side. Therefore, when the layers are stacked, they are laid out at the same position. The substrate is thinned by the tape or the like to protect the surface of the element on which the metal bump 8 is formed. Then, on the back surface of the thinned substrate, the lithography imaging technique for the electrode 20 for electrical non-conduction is processed with the electrode hole 19 (not through the substrate), and then the through electrode 5 for electrically conducting is used. The lithography imaging process is followed by the processing of the through electrode holes 15 (so that the substrate is passed up to the component side). Through the electrode hole 15 and the electrically non-conducting 8 -20- 201110299 electrode hole 19 , the sidewall insulating film is deposited by a CVD oxide film, and the CVD oxidation of the hole bottom is completely removed by dry etching. The film, the element isolation insulating film, the interlayer insulating film, and the like expose the electrode inside the element side. Thereafter, after the seed layer (Ta/Cu) is deposited on the inner wall of the two electrodes by a sputtering apparatus, the buried electrode 17 is formed by completely burying the electrode in the copper (Cu) plating layer, and finally the two electrode ends are formed by CMP. flattened. Next, a lithography technique for forming a metal bump 9 is performed on both electrode ends, and after depositing a seed metal by a sputtering apparatus, a metal plating layer for the metal bump 9 is performed. After the plated metal bumps are planarized by CMP, the resist is removed to form metal bumps 9 on the back side of the semiconductor device. Thus, a laminated semiconductor device is obtained. The element side of the multilayer semiconductor device in this state is positioned on the back side of the semiconductor device of the other laminated semiconductor device, and appropriate heating and pressure are applied to laminate. At this time, the connection of the bumps to each other is performed to the extent that it is temporarily fixed. After the lamination of the number of layers of the purpose is performed, the laminated semiconductors are connected to each other by applying a pressure when the pressure is stronger than the temporary connection as a substantial connection. The obtained multilayer semiconductor device was cut by a slicing process to obtain a laminated semiconductor wafer. The laminated semiconductor device is filled with an under-filling agent from the side of the laminated semiconductor wafer, and finally the hardening agent is heated and cured to complete the laminated semiconductor device. Hereinafter, embodiments of the present invention will be described in more detail, but the present invention is not limited to the following embodiments. (First Embodiment) - 21 - 201110299 Here, an embodiment in which a laminated semiconductor device having a through electrode is formed by a drilling method will be described. First, a method of forming metal bumps on the element side of the completed semiconductor device will be described. On the uppermost portion of the side wall insulating film, the A1 electrodes for taking out formed by A1 are uniformly disposed in the plane, and the heights thereof are all the same. Both the A1 electrode electrically connected to the internal circuit and the A1 electrode electrically non-conducting are formed in advance by the circuit design. The metal is deposited as a seed by a sputtering apparatus. After the resist is applied, the opening is performed only in the A-electrode region by the lithography technique, and then the metal is grown in the opening by the plating. As the metal material, Au, Cu, Ni, or the like is usually used, but Sn (tin) using a solder material is also used. Further, the metal plating material is not one, but may be plural. Thereafter, the upper end of the metal bump is flattened to integrate the height of the metal bump. After planarization, in addition to the resist, the seed metal is removed by wet etching to form metal bumps only on the A1 metal. A bump is formed on the element side, and therefore, the wafer is thinned to 30 μm with the protective tape protecting the bump surface. The thinning of the wafer can be performed using a conventional back honing device, and the honing surface is subjected to stress relief processing. A method of forming an electrode from the back surface of the above semiconductor device will be described below. The thinned semiconductor device is bonded to the supporting substrate because it cannot be held by its own weight. First, an oxide film is used as a hard mask to form a hole for an electrode that is electrically non-conductive on the back surface of the substrate. The hard mask not only serves to prevent conduction between the electrode and the Si substrate but also between the electrodes, and also serves as a protective film function for the back surface. A CVD oxide film which can be formed by using a low temperature of 200 ° C or lower. After the hard mask is used for lithography imaging technology, it is dried by dry etching.
-22- (E 201110299 行電性不導通之電極孔用之硬質遮罩加工。此時’並非完 全除去硬質遮罩，而是於途中停止加工。不加工而殘餘之 氧化膜之膜厚’係由si與氧化膜之選擇比來決定°此情況 下，電性不導通之電極孔之深度最終被調整爲27〜29μιη 〇 電性不導通之電極孔用之硬質遮罩加工後’再度藉由 微影成像技術工程進行電性導通之貫穿電極用之硬質遮罩 加工。此情況下，電性導通之貫穿電極區域之硬質遮罩完 全被除去，直至Si基板爲止被露出。如此則，電性導通之 貫穿電極用之硬質遮罩圖案與電性不導通之硬質遮罩圖案 之2種類可於同一面上。 使用該硬質遮罩，藉由乾蝕刻加工電性導通之貫穿電 極孔。此時，雖完全貫穿Si基板，但硬質遮罩用之氧化膜 係設爲殘留之膜厚。此時，電性不導通之電極，係在硬質 遮罩未完全加工之殘留之氧化膜厚度分之範圍內，使電極 孔之深度被實施淺加工。 接著，爲於電極內之側面形成絕緣膜，而沈積低溫成 膜CVD氧化膜。電極內之孔底絕緣膜藉由乾蝕刻予以除去 ，孔底之元件區域之元件分離絕緣膜與電極之連接用的金 屬配線爲止之層間絕緣膜亦需要同時除去。最終係將孔底 之絕緣膜予以除去，直至到達元件側所形成之承受側之金 屬電極（配下層）爲止。該承受側之金屬電極係和電路呈 現電性連接。 以適當之洗淨液洗淨電極內之後，藉由濺鍍裝置形成 -23- 201110299 阻障膜與種層之Cu。之後，藉由鍍層法於電極內塡充Cu ，藉由CMP除去多餘之Cu，同時形成電性導通之貫穿電極 及電性不導通之電極。 以下說明在背面電極端形成金屬凸塊之方法。藉由和 在元件側形成之方法同一之方法予以作成。藉由濺鍍裝置 形成成爲種之金屬，阻劑塗布之後，藉由微影成像技術僅 於電極區域實施開口，之後，藉由鍍層於開口部成長金屬 。除去阻劑之後，藉由溼蝕刻除去種金屬，僅於電極端形 成金屬凸塊。 將在元件面側與半導體裝置背面側之雙方形成有凸塊 的積層半導體裝置，由支撐基板取下，藉由切片器分離爲 晶片，獲得兩面附加有凸塊的電極晶片22。 以下說明被分離爲各晶片之兩面附加有凸塊的電極晶 片22之積層方法。如圖11之積層半導體裝置之實施形態所 示，於積層之最下方之晶片，係和上述說明之半導體裝置 不同，爲以介面專用方式被製作之介面晶片23。該介面晶 片23，主要目的爲使被積層之兩面附加有凸塊的電極晶片 22與安裝基板25再度實施配線。 又，該介面晶片23之厚度爲200μιυ之厚度。此乃因爲 兩面附加有凸塊的電極晶片22爲極薄之30μπι，若僅積層 該薄之晶片時，晶片積層時產生晶片彎曲、破損之可能性 變高，無法進行高信賴性之積層。爲防止此一不良情況， 僅最下方之介面晶片23設爲晶片不會產生彎曲之厚度。 進行介面晶片23與兩面附加有凸塊的電極晶片22之定 201110299 位，使用接合裝置進行每一晶片之逐次積層。每一晶片之 逐次積層，剛開始並非實質連接’而是進行連接力較弱之 暫時連接。在目的之積層數爲止暫時連接之後’最後進行 實質連接而由晶片之上至下爲止全體施予強之壓力及熱實 施連接。將如此獲得之積層半導體裝置24介由焊接凸塊27 連接於安裝基板2 5。 針對將實質連接完成後之積層半導體裝置24連接於安 裝基板25之後，於兩面附加有凸塊的電極晶片22彼此之間 、兩面附加有凸塊的電極晶片22與介面晶片23之間、介面 晶片23與安裝基板25之間，塡充塡料劑26之方法予以說明 。由積層半導體裝置24之周邊注入塡料劑26。此時’故意 不提供壓力或流速，藉由毛細管現象使塡料劑26滲入各間 隙。在塡料劑26完全埋入各間隙之後，藉由熱處理使塡料 劑26固化，而獲得連接信賴性高的積層半導體裝置24。 如此獲得之積層半導體裝置以A表現。 使用一定數目之所獲得之積層半導體裝置A ’溫度循 環於-25 t〜125°C之間變化，重複元件動作，實施該溫度 循環時之凸塊連接信賴性試驗。該凸塊連接信賴性試驗之 結果設爲1 00%時，將對於以下比較例1、2、3之相對結果 表示於表1。 (比較例1 ) 於第1實施形態之中，除未形成電性不導通之電極以 外，均進行同樣之操作而獲得積層半導體裝置。如此獲得 -25- 201110299 之積層半導體裝置以B表現。 (比較例2 ) 於第1實施形態之中，除未形成電性不導通之電極， 另外在電性導通之貫穿電極以外之區域未形成金屬凸塊以 外，均進行同樣之操作而獲得積層半導體裝置。如此獲得 之積層半導體裝置以C表現。 (比較例3 ) 於第1實施形態之中，除在元件面側未形成金屬凸塊 ，另外在半導體裝置背面側未形成金屬凸塊以外，均進行 同樣之操作而獲得積層半導體裝置。如此獲得之積層半導 體裝置以D表現。 (表1 ) 表1 相對良品率（％ ) 半導體裝置A 100 半導體裝置B 85 半導體裝置c 10 半導體裝置D 72 (第2實施形態） 接著，說明以前鑽孔方式形成有貫穿電極之積層半導 體裝置之實施形態。於形成元件區域與最初之金屬配線（ Μ 1 )製作半導體裝置之後，由層間膜上形成電性導通之 貫穿電極用孔之開口，於該貫穿電極孔內壁以CVD氧化膜 ⑧ -26- 201110299 沈積側壁絕緣膜。此時之貫穿電極深度爲3 1 μπι。藉由濺 鍍裝置形成種層（Ta/ Cu )，藉由Cu鍍層於貫穿電極孔 內塡埋Cu之後，藉由CMP除去多餘之Cu並使平坦化，使 貫穿電極彼此呈電性獨立。之後，形成金屬配線層。此時 ，該貫穿電極與配線層係電連接，因此該貫穿電極成爲電 性導通之貫穿電極。 配線層之形成後，於元件側最上部形成作爲取出電極 之A1電極。該A1電極被均勻配置於半導體裝置面內，彼等 之高度均爲同一。藉由電路設計事先形成和內部電路間呈 現電性導通之A1電極與電性不導通之A1電極。 以下說明在A1電極上形成金屬凸塊之方法。藉由濺鍍 裝置沈積成爲種之金屬，阻劑塗布之後，藉由微影成像技 術僅於A1電極區域形成開口，之後，藉由鍍層於開口部成 長金屬。之後，爲整合金屬凸塊高度，而使金屬凸塊上端 平坦化。平坦化之後除去阻劑，藉由溼蝕刻除去種金屬， 僅於A1金屬上形成金屬凸塊。 於元件側被形成有凸塊，因此，以保護帶保護凸塊面 之狀態下將半導體裝置薄化至平均厚度成爲32 μηι。半導 體裝置之薄化可使用通常之背面硏磨裝置進行，硏磨面被 施予應力消除處理。於此階段，貫穿電極端係未露出（圖 7 ( 1 )之 18 )。 以下說明由上述半導體裝置之背面形成電性不導通之 電極之方法。薄化之半導體裝置，基於無法依自重來保持 而被貼合於支撐基板。首先，爲於半導體裝置背面形成電 -27- 201110299 性不導通之電極用之孔，而使用氧化膜作爲硬質遮罩 用200°C以下之低溫可以成膜的CVD氧化膜。 硬質遮罩用之微影成像技術工程之後，藉由乾蝕 行電性不導通之電極孔用之硬質遮罩加工。於電性不 之電極孔內部沈積側壁絕緣膜之後，藉由濺鍍裝置形 層（Ta/ Cu )。之後，藉由Cu鍍層塡埋電性不導通 極孔，藉由CMP除去多餘之Cu使平坦化。 爲使電性導通之貫穿電極端露出，依據已露出之 不導通之電極之每一個使半導體裝置背面薄化。藉由 化使基板之平均厚度成爲30μίΏ。 之後，半導體裝置背面形成作爲保護膜之CVD氧 ，進行微影成像技術工程及乾蝕刻針對電性導通之貫 極端與電性不導通之電極端之兩方形成開口。使兩電 露出之後，藉由濺鍍裝置形成種層（Ta/ Cu )，藉 鍍層於兩電極端成長Cu之後，藉由CMP除去多餘之 平坦化。 以下說明在背面電極端形成金屬凸塊之方法。藉 在元件側形成之方法同一之方法予以作成。藉由濺鍍 形成成爲種之金屬，阻劑塗布之後，藉由微影成像技 於貫穿電極之區域實施開口，之後，藉由鍍層於開口 長金屬。除去阻劑之後，藉由溼蝕刻除去種金屬，僅 穿電極端形成金屬凸塊，獲得在元件面側與半導體裝 面側之雙方形成有凸塊的積層半導體裝置。 將在元件面側與半導體裝置背面側之雙方形成有 。使 刻進 導通 成種 之電 電性 該薄 化膜 穿電 極端 由Cu Cu使 由和 裝置 術僅 部成 於貫 置背 凸塊 -28- ⑧ 201110299 的積層半導體裝置22，由支撐基板取下，藉由切片器分離 爲晶片，獲得兩面附加有凸塊的電極晶片22 (圖1 1 )。 被分離爲晶片之兩面附加有凸塊的電極晶片22之積層 方法係如上述。 如此獲得之積層半導體裝置以E表現。 使用一定數目之所獲得之積層半導體裝置E，溫度循 環於-2 5 °C〜125 °C之間變化，重複元件動作，實施該溫度 循環時之凸塊連接信賴性試驗。該凸塊連接信賴性試驗之 結果設爲100%時，將對於以下比較例4、5 ' 6之相對結果 表示於表2。 (比較例4 ) 於第2實施形態之中，除未形成電性不導通之電極以 外，均進行同樣之操作而獲得積層半導體裝置。如此獲得 之積層半導體裝置以F表現。 (比較例5 ) 於第2實施形態之中，除未形成電性不導通之電極， 另外在電性導通之貫穿電極以外之區域未形成金屬凸塊以 外’均進行同樣之操作而獲得積層半導體裝置。如此獲得 之積層半導體裝置以G表現。 (比較例6 ) 於第2實施形態之中，除在元件面側未形成金屬凸塊 -29- 201110299 ，另外在半導體裝置背面側未形成金屬凸塊以外’均進行 同樣之操作而獲得積層半導體裝置。如此獲得之積層半導 體裝置以Η表現。 (表2 ) 表2 相對良品率（％ ) 半導體裝置Ε 100 半導體裝置F 92 半導體裝置G 36 半導體裝置Η 84 (產業上可利用性） 藉由形成和電性導通之貫穿電極不同的電性不導通之 電極，可以兼顧良好控制性、高信賴性之連接技術與熱傳 導率之提升。 依據形成有該電極之半導體裝置彼此積層而成之積層 半導體裝置之製造條件，被形成於電極端之金屬焊墊或金 屬凸塊之高度成爲同一，而且均勻存在於面內，因此連接 時施加之壓力引起之不均勻之應力變爲不容易發生，可以 減低連接不良。另外，電極呈現均勻分布，基板之熱傳導 率變高’積層半導體裝置產生之熱可以有效散出（冷卻） 〇 由此’使用上述半導體裝置之積層半導體裝置可以顯 現良好信賴性》 (發明效果） -30- ⑧ 201110299 依據本發明提供之積層半導體裝置及積層半導體裝置 之製造方法，即使在半導體裝置內之任意位置不均勻地配 置電性導通之貫穿電極時，亦可實現高信賴性之半導體裝 置之連接，以及高熱傳導率。 【圖式簡單說明】 圖1表示在元件面側與半導體裝置背面側不存在金屬 焊墊或金屬凸塊之半導體裝置之積層圖。 圖2表示在元件面側與半導體裝置背面側之其中一方 存在金屬焊墊或金屬凸塊之半導體裝置之積層圖。 圖3表示表示在元件面側與半導體裝置背面側之兩方 存在金屬焊墊或金屬凸塊之半導體裝置之積層圖。 圖4表示在無貫穿電極區域形成有金屬焊墊或金屬凸 塊之半導體裝置之積層圖。 圖5表示半導體裝置面內之電極之均勻配置圖。 圖6表示藉由via First之電極之形成例。 圖7表示藉由via First之電性不導通之電極之形成例 〇 圖8表示藉由via Last之電性導通之貫穿電極與電性不 導通之電極之形成例。 圖9表示藉由對硬質遮罩採取對策，而一次形成vi a Last之電性導通之貫穿電極與電性不導通之電極之例。 圖10表示使用本發明之電極製作方法製作之積層半導 體晶片之製造方法之流程圖。 -31 - 201110299 圖1 1表示積層半導體裝置之實施形態。 【主要元件符號說明】 1 :基板 2 :元件區域 3 :保護膜 4 :取出電極（元件側） 5 :電性導通之貫穿電極（斷面） 6:有貫穿電極之區域 7:無貫穿電極之區域 8 :元件側之金屬焊墊或金屬凸塊 9:半導體裝置背面側之金屬焊墊或金屬凸塊 1 〇 :被形成於貫穿電極區域之金屬焊墊或金屬凸塊 1 1 :電性導通之貫穿電極端（平面） 1 2 :電性不導通之電極端（平面） 13 :半導體裝置 1 4 :配線層 1 5 :電性導通之貫穿電極孔 1 6 :電極內之側壁絕緣膜 17:電極內之塡埋電極 1 8 :貫穿電極露出面 1 9 :電性不導通之電極孔 20 :電性不導通之電極（斷面） 21 : CVD氧化膜 201110299 2 2 :兩面附加有凸塊的電極晶片 2 3 :介面晶片 24 ·’積層半導體裝置 25 :安裝基板 2 6 :塡料劑 2 7 :焊接凸塊 -33--22- (E 201110299 Electrode hole for electric conduction non-conducting is processed by hard mask. At this time, 'the hard mask is not completely removed, but the processing is stopped on the way. The film thickness of the residual oxide film is not processed. It is determined by the selection ratio of si and the oxide film. In this case, the depth of the electrode hole which is electrically non-conductive is finally adjusted to 27~29μηη, and the hard hole of the electrode hole for electrical non-conduction is processed again. The lithography imaging technique performs a hard mask process for electrically conducting the through electrodes. In this case, the hard mask of the electrically conductive through-electrode region is completely removed until the Si substrate is exposed. Thus, electrical properties The two types of hard mask patterns for the through electrodes for conduction and the hard mask patterns for electrical non-conduction can be on the same surface. Using the hard mask, the through-electrode holes that are electrically conductive are processed by dry etching. Although the Si substrate is completely penetrated, the oxide film for the hard mask is a residual film thickness. At this time, the electrode that is electrically non-conductive is the thickness of the remaining oxide film that is not completely processed by the hard mask. In the range, the depth of the electrode hole is subjected to shallow processing. Next, an insulating film is formed on the side surface of the electrode to deposit a low-temperature film-forming CVD oxide film. The hole bottom insulating film in the electrode is removed by dry etching, and the bottom of the hole is removed. In the element region, the interlayer insulating film from which the metal wiring for connecting the insulating film and the electrode is separated needs to be simultaneously removed. Finally, the insulating film at the bottom of the hole is removed until reaching the metal electrode on the receiving side formed on the element side ( The metal electrode system and the circuit on the receiving side are electrically connected. After the electrode is cleaned with a suitable cleaning solution, the barrier film and the seed layer Cu are formed by a sputtering apparatus. Thereafter, Cu is filled in the electrode by a plating method, and excess Cu is removed by CMP, and an electrically conductive through electrode and an electrically non-conductive electrode are formed. A method of forming a metal bump on the back electrode end will be described below. It is formed by the same method as the method of forming on the element side. The metal is formed into a seed by a sputtering device, and after the resist is coated, by lithography The opening is formed only in the electrode region, and then the metal is grown in the opening portion by plating. After the resist is removed, the seed metal is removed by wet etching, and only metal bumps are formed on the electrode end. A laminated semiconductor device having bumps formed thereon is removed from the support substrate, and is separated into wafers by a slicer to obtain electrode wafers 22 to which bumps are attached on both sides. The following description is separated into two sides of each wafer with bumps attached thereto. The method of laminating the electrode wafer 22 is as shown in the embodiment of the multilayer semiconductor device of Fig. 11, and the wafer at the bottom of the laminate is an interface wafer 23 which is formed by an interface-specific method, unlike the semiconductor device described above. The main purpose of the interface wafer 23 is to re-wire the electrode wafer 22 to which the bumps are attached on both sides of the laminate and the mounting substrate 25. Further, the thickness of the interface wafer 23 is 200 μm. This is because the electrode wafer 22 to which the bumps are attached on both sides is extremely thin 30 μm. When only the thin wafer is laminated, there is a high possibility that the wafer is bent and damaged during lamination, and a highly reliable laminate cannot be obtained. In order to prevent this problem, only the lowermost interface wafer 23 is set such that the wafer does not have a curved thickness. The interface wafer 23 and the electrode wafer 22 to which the bumps are attached on both sides are set to 201110299, and the bonding device is used to sequentially laminate each wafer. The successive lamination of each wafer is not a substantial connection at the beginning, but a temporary connection with a weak connection force. After the temporary connection is made for the number of layers of the purpose, the final connection is made substantially, and a strong pressure and heat are applied from the top to the bottom of the wafer. The multilayer semiconductor device 24 thus obtained is connected to the mounting substrate 25 via solder bumps 27. After the laminated semiconductor device 24 after the substantial connection is completed is connected to the mounting substrate 25, between the electrode wafers 22 to which the bumps are added on both surfaces, between the electrode wafer 22 and the interface wafer 23 to which the bumps are added on both surfaces, and the interface wafer The method of filling the sputum agent 26 between the 23 and the mounting substrate 25 will be described. The smear 26 is injected from the periphery of the laminated semiconductor device 24. At this time, the pressure or the flow rate is intentionally not supplied, and the wetting agent 26 is infiltrated into the respective spaces by capillary action. After the skimmer 26 is completely buried in each gap, the crucible 26 is cured by heat treatment to obtain a laminated semiconductor device 24 having high connection reliability. The multilayer semiconductor device thus obtained is represented by A. Using a certain number of obtained multilayer semiconductor devices A' temperature cycle to vary between -25 t and 125 ° C, the component operation was repeated, and the bump connection reliability test at the time of the temperature cycle was carried out. When the result of the bump connection reliability test was 100%, the relative results of the following Comparative Examples 1, 2, and 3 are shown in Table 1. (Comparative Example 1) In the first embodiment, a multilayer semiconductor device was obtained by performing the same operation except that the electrode which is not electrically non-conductive was formed. The multilayer semiconductor device thus obtained from -25 to 201110299 is represented by B. (Comparative Example 2) In the first embodiment, the same operation was performed to obtain a laminated semiconductor, except that the electrode which is not electrically conductive was not formed, and the metal bump was not formed in a region other than the electrically conductive through electrode. Device. The multilayer semiconductor device thus obtained is represented by C. (Comparative Example 3) In the first embodiment, a laminated semiconductor device was obtained by performing the same operation except that metal bumps were not formed on the element surface side and metal bumps were not formed on the back surface side of the semiconductor device. The laminated semiconductor device thus obtained is represented by D. (Table 1) Table 1 Relative yield (%) Semiconductor device A 100 Semiconductor device B 85 Semiconductor device c 10 Semiconductor device D 72 (Second embodiment) Next, a multilayer semiconductor device in which a through electrode is formed by a conventional drilling method will be described. Implementation form. After the semiconductor device is formed in the element region and the first metal wiring ( Μ 1 ), an opening of the through-electrode hole for electrically conducting is formed on the interlayer film, and a CVD oxide film is formed on the inner wall of the through electrode hole 8 -26- 201110299 A sidewall insulating film is deposited. The penetration electrode depth at this time was 3 1 μπι. A seed layer (Ta/Cu) is formed by a sputtering apparatus, and after Cu is buried in the through electrode hole by Cu plating, excess Cu is removed by CMP and planarized, so that the through electrodes are electrically independent from each other. Thereafter, a metal wiring layer is formed. At this time, since the through electrode and the wiring layer are electrically connected, the through electrode is a through electrode that is electrically conducted. After the formation of the wiring layer, an A1 electrode as a take-out electrode is formed on the uppermost portion of the element side. The A1 electrodes are uniformly disposed in the plane of the semiconductor device, and their heights are all the same. The A1 electrode and the electrically non-conducting A1 electrode which are electrically connected between the internal circuit and the internal circuit are formed in advance by the circuit design. A method of forming a metal bump on the A1 electrode will be described below. A metal is deposited by a sputtering apparatus. After the resist is applied, an opening is formed only in the A1 electrode region by lithography, and then a metal is grown in the opening portion by plating. Thereafter, the upper end of the metal bump is flattened to integrate the height of the metal bump. After the planarization, the resist is removed, and the seed metal is removed by wet etching to form metal bumps only on the A1 metal. A bump is formed on the element side, and therefore, the semiconductor device is thinned to an average thickness of 32 μm with the protective tape protecting the bump surface. The thinning of the semiconductor device can be carried out using a conventional back honing device, and the honing surface is subjected to stress relief treatment. At this stage, the through-electrode end is not exposed (Fig. 7 (1) 18). A method of forming an electrically non-conducting electrode from the back surface of the above semiconductor device will be described below. The thinned semiconductor device is bonded to the support substrate based on its inability to be held by its own weight. First, in order to form a hole for an electrode which is not electrically conductive on the back surface of a semiconductor device, an oxide film is used as a hard mask. A CVD oxide film which can be formed at a low temperature of 200 ° C or lower is used. After the lithography imaging technique for hard masking, it is processed by a hard mask for dry etching the electrode holes that are not electrically conductive. After depositing the sidewall insulating film inside the electrode holes of the electrical non-electrode, a layer (Ta/Cu) is formed by a sputtering device. Thereafter, the Cu plating layer is buried with an electrically non-conductive hole, and the excess Cu is removed by CMP to planarize it. In order to expose the through-electrode end of the electrical conduction, the back surface of the semiconductor device is thinned in accordance with each of the exposed non-conductive electrodes. The average thickness of the substrate was made 30 μί by crystallization. Thereafter, CVD oxygen as a protective film is formed on the back surface of the semiconductor device, and lithography imaging technology and dry etching are performed to form openings for both the electrode terminal of the electrical conduction and the electrode terminal of the electrical non-conduction. After the two electrodes are exposed, a seed layer (Ta/Cu) is formed by a sputtering apparatus, and after the Cu is grown at the both electrode ends by the plating layer, the excess planarization is removed by CMP. A method of forming a metal bump on the back electrode end will be described below. It is produced by the same method as the method of forming the element side. The metal is formed by sputtering, and after the resist is applied, the opening is performed by the lithography technique in the region penetrating the electrode, and then the metal is plated in the opening. After the resist is removed, the seed metal is removed by wet etching, and metal bumps are formed only through the electrode ends, thereby obtaining a laminated semiconductor device in which bumps are formed on both the element surface side and the semiconductor package side. Both the element surface side and the semiconductor device back side are formed. Electrolyticity of the thinned film is made by the Cu Cu and the device is formed only by the laminated semiconductor device 22 of the through bump -28-8 201110299, and is removed by the supporting substrate. The wafer is separated into wafers by a slicer to obtain electrode wafers 22 with bumps on both sides (Fig. 11). The method of laminating the electrode wafer 22 to which the bumps are separated on both sides of the wafer is as described above. The multilayer semiconductor device thus obtained is represented by E. Using a certain number of obtained multilayer semiconductor devices E, the temperature cycle is varied between -25 ° C and 125 ° C, the component operation is repeated, and the bump connection reliability test at the time of the temperature cycle is performed. When the result of the bump connection reliability test was 100%, the relative results for the following Comparative Examples 4 and 5' 6 are shown in Table 2. (Comparative Example 4) In the second embodiment, a laminated semiconductor device was obtained by performing the same operation except that the electrode which is not electrically non-conductive was formed. The multilayer semiconductor device thus obtained is represented by F. (Comparative Example 5) In the second embodiment, the same operation was performed to obtain a laminated semiconductor, except that the electrode which is not electrically conductive was not formed, and the metal bump was not formed in the region other than the electrically conductive through electrode. Device. The multilayer semiconductor device thus obtained is represented by G. (Comparative Example 6) In the second embodiment, the metal bumps -29 to 201110299 were not formed on the element surface side, and the metal bumps were not formed on the back side of the semiconductor device. Device. The laminated semiconductor device thus obtained is expressed in terms of ruthenium. (Table 2) Table 2 Relative yield (%) Semiconductor device Ε 100 Semiconductor device F 92 Semiconductor device G 36 Semiconductor device Η 84 (Industrial availability) Different electrical properties are formed by forming a through-electrode that is electrically conductive The conductive electrode can achieve both good controllability, high reliability connection technology and thermal conductivity. According to the manufacturing conditions of the laminated semiconductor device in which the semiconductor devices in which the electrodes are formed are laminated, the heights of the metal pads or the metal bumps formed at the electrode ends are the same, and are uniformly present in the plane, so that they are applied at the time of connection. The stress caused by the unevenness of the pressure becomes less likely to occur, and the connection failure can be reduced. Further, the electrodes are uniformly distributed, and the thermal conductivity of the substrate becomes high. The heat generated by the laminated semiconductor device can be efficiently dissipated (cooled). Thus, the 'semiconductor device using the above semiconductor device can exhibit good reliability. (Effect of the invention) - 30- 8 201110299 According to the method for manufacturing a multilayer semiconductor device and a laminated semiconductor device according to the present invention, even when an electrically conductive through electrode is unevenly arranged at any position in the semiconductor device, a highly reliable semiconductor device can be realized. Connection, as well as high thermal conductivity. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a laminated view of a semiconductor device in which a metal pad or a metal bump is not present on the element surface side and the back side of the semiconductor device. Fig. 2 is a laminated view showing a semiconductor device in which a metal pad or a metal bump is present on one of the element surface side and the back surface side of the semiconductor device. Fig. 3 is a laminated view showing a semiconductor device in which metal pads or metal bumps are present on both the element surface side and the back surface side of the semiconductor device. Fig. 4 is a laminated view showing a semiconductor device in which a metal pad or a metal bump is formed without a through electrode region. Fig. 5 is a view showing a uniform arrangement of electrodes in the plane of the semiconductor device. Fig. 6 shows an example of formation of an electrode by via First. Fig. 7 shows an example of formation of an electrode which is electrically non-conductive by via First. Fig. 8 shows an example of formation of an electrode which is electrically conductive by via Last and an electrode which is electrically non-conductive. Fig. 9 shows an example in which a through-electrode that electrically conducts vi a Last and an electrode that is electrically non-conducting are formed by taking countermeasures against a hard mask. Fig. 10 is a flow chart showing a method of manufacturing a laminated semiconductor wafer produced by the electrode manufacturing method of the present invention. -31 - 201110299 Fig. 11 shows an embodiment of a multilayer semiconductor device. [Description of main component symbols] 1 : Substrate 2 : Component region 3 : Protective film 4 : Takeout electrode (component side) 5 : Electrically conductive through electrode (section) 6 : Region with through electrode 7 : No through electrode Area 8: Metal pad or metal bump 9 on the element side: Metal pad or metal bump on the back side of the semiconductor device 1 : Metal pad or metal bump formed in the through electrode region 1 1 : Electrical conduction Through-electrode end (planar) 1 2 : Electrode non-conducting electrode end (planar) 13 : Semiconductor device 1 4 : Wiring layer 1 5 : Electrically conductive through-electrode hole 1 6 : Side wall insulating film 17 in electrode: Electrode buried electrode in the electrode 18: through electrode exposure surface 19: Electrode non-conducting electrode hole 20: Electrode non-conducting electrode (section) 21 : CVD oxide film 201110299 2 2 : Both sides are provided with bumps Electrode wafer 2 3 : interface wafer 24 · 'layered semiconductor device 25 : mounting substrate 2 6 : enamel 2 7 : solder bump -33-