WO2010119570A1 - Multilayer semiconductor device and method for manufacturing multilayer semiconductor device - Google Patents

Multilayer semiconductor device and method for manufacturing multilayer semiconductor device Download PDF

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Publication number
WO2010119570A1
WO2010119570A1 PCT/JP2009/057767 JP2009057767W WO2010119570A1 WO 2010119570 A1 WO2010119570 A1 WO 2010119570A1 JP 2009057767 W JP2009057767 W JP 2009057767W WO 2010119570 A1 WO2010119570 A1 WO 2010119570A1
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Prior art keywords
electrode
semiconductor device
electrical continuity
metal
electrodes
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PCT/JP2009/057767
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French (fr)
Japanese (ja)
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一幸 朴澤
武田　健一
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株式会社日立製作所
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Priority to PCT/JP2009/057767 priority Critical patent/WO2010119570A1/en
Priority to JP2011509163A priority patent/JP5559773B2/en
Priority to TW099111268A priority patent/TWI416689B/en
Publication of WO2010119570A1 publication Critical patent/WO2010119570A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Definitions

  • the present invention relates to a laminated semiconductor device obtained by laminating semiconductor devices each having an electrode having no electrical continuity in addition to a through electrode having a gap, and a method for manufacturing the laminated semiconductor device.
  • a first semiconductor chip (device) is connected to a multilayer substrate (printed wiring board) via bumps, and the first semiconductor chip is stacked via an interposer. There is also an example of connecting with.
  • the problem is that the thermal conductivity differs greatly between areas with and without through-electrodes. It becomes. Since the through electrode exists in the Si substrate in the region where the through electrode is present, the thermal conductivity on the front side and the back side of the semiconductor device is high. On the other hand, not only the electrode is not in direct contact with the Si substrate, but also the region without the through electrode has a clearly reduced thermal conductivity because the through electrode is not present in the Si substrate. This not only reduces the heat dissipation (cooling) effect of the heat generated from the stacked semiconductor device, but also causes a temperature difference depending on the location within the semiconductor device surface. It is also the cause that causes.
  • the penetrating electrodes are often not evenly arranged in the semiconductor device, although depending on the purpose and design contents.
  • the region without the through electrode is made of a material different from that of the through electrode, it hardly contributes to the connection of the semiconductor device.
  • An object of the present invention is to provide a highly reliable connection of a semiconductor device and a stacked semiconductor device that provides a high thermal conductivity even when through electrodes having electrical continuity are unevenly arranged at arbitrary positions in the semiconductor device, and
  • An object of the present invention is to provide a method for manufacturing a laminated semiconductor device.
  • the applicant of the present application uses, as a so-called dummy electrode, an electrode having no electrical continuity in addition to a through electrode having electrical continuity, and these electrodes are evenly arranged in the semiconductor device plane. If it is arranged in the semiconductor device, it is found that non-uniform stress is not applied in the surface of the semiconductor device, a highly reliable connection of the semiconductor device is obtained, and a laminated semiconductor device having high thermal conductivity is obtained, and the present invention is completed. It came to do.
  • the feature of the first invention resides in (1) a stacked semiconductor device in which a plurality of semiconductor devices each including a through electrode having electrical continuity and an electrode having no electrical continuity are stacked.
  • a metal pad or a metal bump may be formed on the electrode ends of both electrodes. From the device surface side, the metal pad or the metal bump is electrically connected to the through electrode having electrical conductivity through the extraction electrode and the wiring layer.
  • the through electrode having electrical continuity affects the circuit operation of the device region through the wiring layer. On the other hand, since the electrode without electrical continuity does not reach the wiring layer, it does not affect the circuit operation of the device.
  • the metal pad or metal bump is formed on either the device surface side or the semiconductor device back surface side, or (4) the metal pad or metal bump is formed on the device surface side or the semiconductor device back surface side. The case where it forms in both is considered.
  • the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in the semiconductor device.
  • the electrically conductive through electrode and the electrically nonconductive electrode are uniformly arranged in a lattice pattern at least in a device region in the semiconductor device.
  • the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in the semiconductor device.
  • the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device.
  • the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in the semiconductor device.
  • the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device.
  • the through electrode having electrical conduction and the electrode having no electrical conduction are arranged uniformly in the semiconductor device.
  • the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device.
  • the feature of the second invention is (13) (a) polishing the back surface of the substrate opposite to the device surface side of the semiconductor substrate; (b) a step of machining an electrode hole without electrical conduction from the back surface of the substrate; (c) a step of processing a through-electrode hole having electrical continuity from the back surface of the substrate (d) a step of depositing and processing a sidewall insulating film in both the electrode holes, and further embedding an electrode material to form an electrode; (e) a step of flattening both electrode ends to form a semiconductor device; (f) A method of manufacturing a laminated semiconductor device, including a step of laminating a plurality of semiconductor devices obtained in the steps (a) to (e).
  • the side wall insulating film is preferably processed to the electrode surface on the device side simultaneously with removal of the hole bottom insulating film of the insulating film deposited in the electrode.
  • a feature of the third invention is (16) (a) polishing the back surface of the substrate opposite to the device surface side of the semiconductor substrate; (i) a step of depositing a mask material on the back surface of the substrate; (j) creating and processing a mask for processing an electrode hole without electrical conduction; (k) creating and processing a mask for processing a through-electrode hole with electrical continuity; (d) depositing and processing a sidewall insulating film in both the electrode holes, further embedding an electrode material to form an electrode, (e) a step of flattening both electrode ends to form a semiconductor device; (f) A method of manufacturing a laminated semiconductor device, including a step of laminating a plurality of semiconductor devices obtained in the steps (a) to (e).
  • the method further includes at least one step selected from a step of forming a metal pad or a metal bump on the through electrode side on the semiconductor substrate.
  • the side wall insulating film is preferably processed to the electrode surface on the device side simultaneously with removal of the hole bottom insulating film of the insulating film deposited in the electrode.
  • the feature of the fourth invention is (19) (l) a step of forming an electrically conductive through electrode by embedding an electrode material on one surface of a semiconductor substrate; (m) a step of polishing the other surface of the semiconductor substrate to expose a conductive through electrode, (b ′) a step of machining an electrode hole without electrical conduction from a surface in the same direction as the exposed surface while protecting the exposed surface; (d ′) a step of forming an electrode by embedding an electrode material in the electrode hole without electrical conduction; (e) a step of flattening both electrode ends to form a semiconductor device; (f ′) A method of manufacturing a laminated semiconductor device, including a step of laminating a plurality of semiconductor devices obtained in the steps (l) to (e).
  • the method further includes at least one step selected from a step of forming a metal pad or a metal bump on the through electrode side on the semiconductor substrate.
  • a semiconductor device used when stacking semiconductor devices on which through electrodes are formed has a metal pad or metal bumps 8 and 9 that are convex on the device surface side and the back surface side of the semiconductor device. 2, those in which convex electrodes such as metal pads and metal bumps 8 and 9 are formed on either the device surface side or the semiconductor device rear surface side as shown in FIG. 2, as shown in FIG. In other words, it can be divided into those in which both convex metal pads and metal bumps 8 and 9 are formed on the device surface side and the semiconductor device back surface side.
  • a substrate 1 is usually a Si substrate, and a CMOS circuit, a memory element, etc. are formed in a device region 2 formed on the surface side, and a protective film 3 and a take-out electrode 4 are formed thereon. Is often formed.
  • a method of improving the flatness of the Si substrate while reducing the connection failure between the electrodes by forming a metal pad, a metal bump 10 or the like in the region 7 having no through electrode can be considered.
  • the metal pad or the metal bump 10 formed in the region 7 having no through electrode is in close contact.
  • problems such as poor performance, and the height of the metal pads and metal bumps 8 and 9 formed at the end of the extraction electrode 4 and the end of the through electrode 5 having electrical continuity.
  • the metal pads and metal bumps 10 formed in the region 7 without the through electrode are not in direct contact with the Si substrate 1, so that the thermal conductivity is higher than that of the region 6 with the through electrode. I know it ’s bad.
  • the present invention has been made in view of such problems, and as shown in the uniform arrangement diagram of the electrodes in the surface of the semiconductor device in FIG. It is an object of the present invention to provide a method of increasing the thermal conductivity while suppressing the height deviation due to the metal pads and the metal bumps by arranging 12 uniformly on the semiconductor device 13 (for example, in a lattice shape).
  • a highly reliable semiconductor device connection and a laminated semiconductor device that provides high thermal conductivity even when through electrodes having electrical continuity are unevenly arranged at arbitrary positions in the semiconductor device, and A method for manufacturing a stacked semiconductor device can be provided.
  • FIG. 6 is a stacked view of a semiconductor device having no metal pads or metal bumps on the device surface side and the semiconductor device back surface side.
  • FIG. 6 is a stacked view of a semiconductor device having metal pads or metal bumps on either the device surface side or the semiconductor device back surface side.
  • FIG. 6 is a stacked view of a semiconductor device having metal pads or metal bumps on both the device side and the back side of the semiconductor device.
  • FIG. 6 is a stacked view of a semiconductor device in which metal pads or metal bumps are formed in a region without through electrodes. The uniform arrangement figure of the electrode in a semiconductor device surface.
  • Example of electrode formation by via First Example of electrode formation without electrical continuity by via ⁇ ⁇ ⁇ First.
  • the diameter and shape of the through-electrodes used in the present invention there are no particular restrictions on the diameter and shape of the through-electrodes used in the present invention, but when the electrodes are cylindrical, the diameter (or length) is in the range of 0.3 to 200 ⁇ m, and the distance is the electrode diameter. Is preferably about 5 to 1/5 (for example, if the electrode diameter is 10 ⁇ m, the interval is in the range of 50 ⁇ m to 2 ⁇ m).
  • the electrode diameter is smaller than 0.3 ⁇ m, the electrostatic capacity of the electrode increases and the resistance increases at the same time, so the advantage of using a dummy electrode is reduced.
  • the electrode diameter is larger than 200 ⁇ m, the ratio of the electrode area in the semiconductor device becomes too large, and the area where the semiconductor element can be arranged decreases, so the merit of using the dummy electrode is reduced. End up.
  • the diameter of the electrode without electrical continuity or the distance between the electrodes is not particularly limited, but may be considered to be the same as that of the through electrode with electrical continuity.
  • a metal bump or the like is formed at the electrode end, it is desirable that the through electrode having electrical continuity and the electrode having no electrical continuity have the same shape. This is because the bump height changes when the bump shape is different when forming a metal bump or the like, and this is not the case when the bump height is readjusted by another method.
  • the depth of the electrode is not determined with priority on the shape, but is determined from the viewpoint of circuit design, the final number of stacked layers and the limit value of the thickness thereof, the technical limit on the process, and the like.
  • the electrode depth increases, that is, as the wafer thickness or chip thickness increases, it becomes more difficult to form a hole with a small diameter (high aspect ratio).
  • the resistance value increases and the capacitance also increases, so the advantage of using a dummy electrode tends to decrease.
  • the depth of an electrode used as a signal line is desirably 100 ⁇ m or less, and ideally a range of 5 to 50 ⁇ m is desirable.
  • the through electrode with electrical continuity needs to penetrate the substrate and contact the internal electrode on the device surface side (or the extraction electrode at the top of the device region), but the electrode without electrical continuity does not penetrate the substrate. It is important to stop before that. If an electrode without electrical conduction is stopped too far in front of the device region, there is a disadvantage in terms of thermal conductivity because the electrode is not present in the substrate. On the contrary, if it is penetrated, the circuit on the device surface side is adversely affected. For this reason, it is desirable that the depth (length) of the electrode without electrical conduction be slightly shallower (or shorter) than the depth (length) of the through electrode with electrical conduction. Ideally, it should be at least 1 ⁇ m away from the device area.
  • the through electrode with electrical continuity is several ⁇ m from the device region, Ideally, it should be placed in a place separated by 1 ⁇ m or more.
  • an electrode forming method will be described.
  • the method of forming an electrode is roughly classified into via-First and via-Last.
  • via-First forms a through-electrode hole 15 having electrical continuity before a semiconductor device is completed, here, before the device region 2 is manufactured. Suitable for forming.
  • a sidewall insulating film 16 in the through electrode is deposited in the through electrode hole 15, and then a buried electrode 17 is formed. Finally, the end of the buried electrode 17 is flattened, so that each of the electrically independent electrodes A conductive through electrode 5 is formed.
  • the through electrode hole 15 is formed after the device region 2 is manufactured. In this case, since the subsequent process heat treatment temperature can be kept low, a metal such as Cu is often used.
  • the device region 2, the wiring layer 14, and the extraction electrode 4 are formed to complete the semiconductor device. Then, after forming the device surface side metal pad or metal bump 8 on the extraction electrode 4, the substrate is thinned by substrate polishing to expose the end of the through electrode to obtain the through electrode exposed surface 18. The back surface side of the semiconductor device is protected by the protection film 3 so as not to block the exposed surface 18 of the through electrode, and finally metal pads or metal bumps 9 on the back surface side of the semiconductor device are formed.
  • the substrate is thinned and the through electrode 5 having electrical conduction is exposed from the back surface of the substrate as shown in FIG. It is necessary to form (penetrating electrode exposed surface 18) and electrode 19 having no electrical continuity.
  • the processing of the electrode hole 19 without electrical conduction, the deposition of the sidewall insulating film 16 in the electrode hole 19 and the formation of the embedded electrode 17, and 17 ends are flattened to form an electrode 20 having no electrical continuity.
  • the end of the electrically conductive through electrode 5 is opened by the photolithography process and the dry etching process, and the electrodes are formed at the ends of the electrodes 5 and 20, and then the electrically conductive through electrode 5 is not electrically connected.
  • a planarization process for adjusting the height of the end of the electrode 20 is performed.
  • metal pads or metal bumps 9 are formed on both electrode ends, there are many problems such as not only a long process time but also a high process cost.
  • via-Last forms a through electrode from the back surface of the substrate opposite to the device surface side after the substrate is thinned after completion of the semiconductor device.
  • the heat treatment temperature generally because it is affixed to a hard support substrate or the like by some method such as resin or adhesive.
  • FIG. 8 shows a method of forming the through electrode 5 having electrical conduction and the electrode 20 having no electrical conduction almost simultaneously.
  • metal pads or metal bumps 8 are formed on the device surface side of the completed semiconductor device, and then the substrate is thinned by polishing.
  • the photolithographic process for the electrode without electrical conduction and the processing of the electrode hole 19 are performed, and then the photolithographic process for the through electrode with electrical conduction and the processing of the through electrode hole 15 are performed. Perform (through the substrate to the device side).
  • the sidewall insulating film 16 is simultaneously deposited in both electrode holes of the electrically conductive through electrode hole 15 and the electrically nonconductive electrode hole 19, and then the hole bottom insulating film of the electrically conductive through electrode hole 15 is formed. Remove all. At this time, if there is an element isolation insulating film or an interlayer insulating film at the bottom of the through-electrode hole 15 having electrical conduction, these are also removed together. After all the hole bottom insulating film is removed, the buried electrode 17 is formed and finally the electrode end is flattened.
  • the through electrode 5 having electrical continuity is the same as the height of the end of the electrode 20 having no electrical continuity.
  • a CVD oxide film 21 is deposited as a hard mask.
  • lithography for electrodes having no electrical continuity on the surface of the CVD oxide film 21 and hard mask processing for the electrodes are performed. At this time, the CVD oxide film is not processed, leaving an appropriate thickness and never exposing the Si surface.
  • lithography for through electrodes having electrical continuity is performed on the CVD oxide film 21, and hard mask processing for the through electrodes is performed. At this time, the CVD oxide film 21 is completely removed to expose the Si surface.
  • metal bumps 8 are formed on the device side of the completed semiconductor device.
  • the layout of the metal bumps 8 is the same layout as the back side of the semiconductor device opposite to the device side, and is laid out so as to overlap at the same position when stacked.
  • the substrate is thinned while the device surface on which the metal bumps 8 are formed is protected with a tape or the like.
  • lithography for the electrode 20 having no electrical continuity and processing of the electrode hole 19 are performed on the back surface of the thinned substrate, followed by lithography for the through electrode 5 having electrical continuity and its
  • the through electrode hole 15 is processed (through the substrate to the device side).
  • a sidewall insulating film 16 is deposited with a CVD oxide film in the through-hole 15 having electrical continuity and the electrode hole 19 having no electrical continuity, and the CVD oxide film, element isolation insulating film, interlayer insulating film, etc. existing at the bottom of the hole are dry-etched. To remove all the electrodes and expose the electrodes inside the device.
  • a seed layer (Ta / Cu) was deposited on the inner walls of both electrodes by a sputtering apparatus, and then the entire electrode was embedded by Cu plating as the embedded electrode 17, and finally the ends of both electrodes were flattened by CMP. .
  • a lithography process for forming metal bumps 9 at the ends of both electrodes is performed, and after seed metal is deposited by sputtering, metal plating for the metal bumps 9 is performed. After the metal bumps after plating were planarized by CMP, the resist was removed to form metal bumps 9 on the back side of the semiconductor device. Thereby, a laminated semiconductor device was obtained.
  • the bumps are connected to the extent of temporary fixing.
  • the stacked semiconductors are connected to each other by pressing with a pressure stronger than the temporary connection as the main connection.
  • the obtained laminated semiconductor device was cut by a dicing process to obtain a laminated semiconductor chip.
  • An underfill agent was filled from the side surface of the laminated semiconductor chip, and finally the underfill agent was cured by heat to complete a laminated semiconductor device.
  • the seed metal is deposited by sputtering, and after applying the resist, only the Al electrode region is opened by a photolithography process, and then the metal is grown in the opening by plating.
  • the metal plating material Au, Cu, Ni or the like is generally preferable, but solder material Sn may be used. Further, the metal plating material is not one kind, and a plurality of metal plating materials may be stacked. Thereafter, in order to align the metal bump height, the upper end of the metal bump is flattened. After planarization, the resist was removed, and the seed metal was removed by wet etching to form metal bumps only on the Al metal.
  • the wafer thickness is reduced to 30 ⁇ m with the bump surface protected with a protective tape.
  • the wafer is thinned using a general back grinding apparatus, and the polished surface is subjected to stress relief processing.
  • a method for forming electrodes from the back surface of the semiconductor device Since the thinned semiconductor device cannot hold its own weight, it is attached to the support substrate.
  • a hard mask is formed using an oxide film in order to form a hole for an electrode without electrical conduction on the back surface of the substrate. This hard mask not only prevents conduction between the electrode and the Si substrate and the electrodes, but also serves as a protective film on the back surface.
  • hard mask processing for electrode holes without electrical conduction is performed by dry etching. At this time, the hard mask is not completely removed, but the processing is stopped halfway.
  • the film thickness of the oxide film that remains without being processed is determined by the selection ratio between Si and the oxide film. In this case, the depth of the electrode hole without electrical continuity is adjusted so that it finally becomes 27 to 29 ⁇ m.
  • the hard mask for through electrodes with electrical continuity is processed again in the photolithography process. In this case, all the hard masks in the through electrode regions having electrical continuity are removed and exposed to the Si substrate. Up to this point, two types of hard mask patterns for through electrodes having electrical conduction and hard mask patterns having no electrical conduction can be formed on the same surface.
  • a through electrode hole with electrical continuity is processed by dry etching. At this time, the Si substrate is completely penetrated, but the thickness is set such that the oxide film for the hard mask remains. At this time, the electrode without electrical continuity is processed so that the depth of the electrode hole is shallow by the remaining oxide film thickness that has not been completely processed by the hard mask.
  • a low-temperature CVD oxide film is deposited to form an insulating film on the side surface in the electrode.
  • the insulating film at the bottom of the hole in the electrode is removed by dry etching, the element isolation insulating film in the device region at the bottom of the hole and the interlayer insulating film up to the metal wiring connected to the electrode must be removed together.
  • the insulating film at the bottom of the hole is removed until the metal electrode (wiring layer) on the receiving side formed on the device side is reached. The receiving metal electrode is electrically connected to the circuit.
  • a barrier film and seed Cu are formed by sputtering. After that, if the electrode is filled with Cu by plating and excess Cu is removed by CMP, a through electrode having electrical continuity and an electrode having no electrical continuity are formed simultaneously.
  • a method for forming metal bumps on the electrode ends on the back surface will be described. It is created by the same method as that formed on the device side.
  • a metal to be a seed is formed by sputtering, and after applying a resist, only the electrode region is opened by a photolithography process, and then the metal is grown in the opening by plating. After removing the resist, the seed metal was removed by wet etching, and metal bumps were formed only at the electrode ends.
  • the electrode chip 22 with double-sided bumps was obtained by removing the laminated semiconductor device having bumps formed on both the device surface side and the back side of the semiconductor device from the support substrate and separating each chip by dicing.
  • the chip at the bottom of the stacked layer is an interface chip 23 manufactured exclusively for the interface, unlike the semiconductor device described above.
  • the purpose of the interface chip 23 is to electrically connect or rewiring the stacked double-sided bumped electrode chip 22 and the mounting substrate 25.
  • the thickness of the interface chip 23 is as thick as 200 ⁇ m. This is because the electrode chip 22 with the double-sided bumps is very thin as 30 ⁇ m, and if only the thin chip is stacked, the possibility of the chip being bent or damaged at the time of stacking the chips increases, so that the reliability is high. Lamination is not possible. In order to prevent such a problem, only the bottom interface chip 23 is thickened so that the chip does not warp.
  • the stacked semiconductor device obtained from this is expressed as A.
  • the device operation was repeated by using a certain number of the obtained stacked semiconductor devices A and changing the temperature cycle from -25 ° C. to 125 ° C., and a bump connection reliability test at this temperature cycle was performed.
  • Table 1 shows the relative results with respect to Comparative Examples 1 and 2 and 3 below when the result of the bump connection reliability test is 100%.
  • FIG. 2 An example of a laminated semiconductor device in which through electrodes are formed in via-first will be described.
  • a hole for the through electrode having electrical continuity is opened from above the interlayer film, and a CVD oxide film is formed on the inner wall of the through electrode hole.
  • a sidewall insulating film is deposited.
  • the penetration electrode depth at this time is 31 ⁇ m.
  • a seed layer (Ta / Cu) is formed by sputtering, Cu is embedded in the through-electrode hole by Cu plating, and then excess Cu is removed and planarized by CMP to electrically isolate the through-electrodes. I let you. Thereafter, a metal wiring layer is formed. At this time, since the through electrode and the wiring layer are electrically connected, the through electrode becomes a through electrode having electrical conduction.
  • an Al electrode was formed as an extraction electrode on the uppermost part on the device side.
  • the Al electrodes are uniformly arranged in the semiconductor device surface, and their heights are all the same. According to the circuit design, both an Al electrode having electrical continuity with the internal circuit and an Al electrode having no electrical continuity are formed in advance.
  • a metal to be a seed is deposited by sputtering, and after applying a resist, only the Al electrode region is opened by a photolithography process, and then metal is grown in the opening by plating. Thereafter, in order to align the metal bump height, the upper end of the metal bump is flattened. After planarization, the resist was removed, and the seed metal was removed by wet etching to form metal bumps only on the Al metal.
  • the semiconductor device Since bumps are formed on the device surface side, the semiconductor device is thinned to an average thickness of 32 ⁇ m with the bump surface protected by a protective tape.
  • the semiconductor device is thinned by using a general back grinding apparatus, and the polished surface is subjected to stress relief processing. At this stage, the end of the through electrode is not exposed (18 in FIG. 7 (1)).
  • a method for forming an electrode without electrical conduction from the back surface of the semiconductor device will be described. Since the thinned semiconductor device cannot hold its own weight, it is attached to the support substrate.
  • a hard mask is formed using an oxide film in order to form a hole for an electrode having no electrical continuity on the back surface of the semiconductor device.
  • a CVD oxide film that can be formed at a low temperature of 200 ° C. or lower was used.
  • hard mask processing for electrode holes without electrical conduction is performed by dry etching. After depositing a sidewall insulating film inside the electrode hole without electrical conduction, a seed layer (Ta / Cu) was formed by sputtering. After that, electrode holes without electrical continuity were filled with Cu plating, and excess Cu was removed by CMP to flatten it.
  • the back surface of the semiconductor device was thinned together with the exposed electrode without electrical continuity. With this thinning, the average thickness of the substrate became 30 ⁇ m.
  • a CVD oxide film was formed as a protective film on the back surface of the semiconductor device, and a photolithography process and dry etching were performed to open both the through-electrode end having electrical continuity and the electrode end having no electrical continuity.
  • a seed layer (Ta / Cu) was formed by sputtering, and Cu was grown on both electrode ends by Cu plating. Then, excess Cu was removed by CMP and planarized.
  • a method for forming metal bumps on the electrode ends on the back surface will be described. It is created by the same method as that formed on the device side.
  • a metal to be a seed is formed by sputtering, and after applying a resist, only the region of the through electrode is opened by a photolithography process, and then the metal is grown in the opening by plating. After removing the resist, the seed metal was removed by wet etching, metal bumps were formed only at the end of the through electrode, and a laminated semiconductor device having bumps formed on both the device surface side and the semiconductor device back surface side was obtained.
  • the laminated semiconductor device 22 having bumps formed on both the device surface side and the back surface side of the semiconductor device was removed from the support substrate and separated into each chip by dicing to obtain an electrode chip 22 with double-sided bumps (FIG. 11). ).
  • the method of laminating the electrode chip 22 with double-sided bumps separated into chips is as described above.
  • the multilayer semiconductor device obtained from this is expressed as E.
  • the temperature cycle was changed from -25 ° C. to 125 ° C. and the device operation was repeated, and a bump connection reliability test at this temperature cycle was performed.
  • Table 2 shows the relative results for the following Comparative Examples 4, 5 and 6 when the result of the bump connection reliability test is 100%.
  • the metal pads and metal bumps formed at the electrode ends have the same height and are in-plane. Since it exists uniformly, non-uniform stress is unlikely to occur due to the pressure applied at the time of connection, and connection failure can be reduced. Further, since the electrodes are uniformly distributed, the thermal conductivity of the substrate is high, and the heat generated from the laminated semiconductor device can be efficiently dissipated (cooled).
  • the stacked semiconductor device obtained using the semiconductor device exhibits high reliability.

Abstract

By laminating a plurality of semiconductor devices each comprising a conductive through electrode and a non-conductive electrode, highly reliable connection of semiconductor devices can be obtained even when conductive through electrodes are non-uniformly arranged in arbitrary positions of the semiconductor devices. A multilayer semiconductor device having high thermal conductivity and a method for manufacturing a multilayer semiconductor device are also disclosed.

Description

積層半導体装置及び積層半導体装置の製造方法Multilayer semiconductor device and method for manufacturing multilayer semiconductor device
　本発明は、Si基板を貫通する貫通電極（Through Silicon Vias：TSV）を備えた半導体ウェーハまたは半導体チップ同士を積層することで得られる高性能で低消費電力な積層半導体装置を得るため、電気導通のある貫通電極の他に電気導通のない電極を形成した半導体装置同士を積層して得られる積層半導体装置及び積層半導体装置の製造方法に関する。 In order to obtain a high performance and low power consumption stacked semiconductor device obtained by stacking semiconductor wafers or semiconductor chips each having a through silicon via (TSV) penetrating the Si substrate, The present invention relates to a laminated semiconductor device obtained by laminating semiconductor devices each having an electrode having no electrical continuity in addition to a through electrode having a gap, and a method for manufacturing the laminated semiconductor device.
　近年、電子機器の小型・軽量化、高性能化、低消費電力化の要求は増加の一途を辿っている。この要求を満たすためには、半導体装置の形状をより小さく薄いものにする必要があるが、形状を小さく薄くするにも物理的な限界が近づいている。 In recent years, demands for smaller, lighter, higher performance, and lower power consumption of electronic devices have been increasing. In order to satisfy this requirement, it is necessary to make the shape of the semiconductor device smaller and thinner, but the physical limit is approaching to make the shape smaller and thinner.
　また、半導体プロセスの微細化限界が近づくにつれて微細化速度が鈍化すると共に、最先端製品の製造コストが大きく増加してきている。このため、より高性能で低消費電力な半導体装置を得ることが容易ではなくなりつつある。 Also, as the miniaturization limit of the semiconductor process approaches, the speed of miniaturization slows down, and the manufacturing cost of cutting-edge products has greatly increased. For this reason, it is becoming difficult to obtain a semiconductor device with higher performance and lower power consumption.
　そこで、半導体プロセスの微細化に頼らずに、半導体装置の小型・軽量化、高性能化、低消費電力化を全て実現する方法として、半導体装置に貫通電極を形成し、半導体装置同士を三次元的に積層する三次元積層技術の研究・開発が行なわれている。従来の二次元的な実装技術や、ワイア・ボンディングによる半導体装置の多段積層技術と比較して、貫通電極が形成された半導体装置同士を三次元的に積層する技術は、配線長を極端に短縮可能であると共に理想的な配線配置等が可能であることから、配線抵抗や配線容量を飛躍的に低減できるだけでなく、従来技術では実現不可能であった新しい回路技術の開発も可能になる。 Therefore, as a method for realizing miniaturization, weight reduction, high performance, and low power consumption of semiconductor devices without relying on miniaturization of semiconductor processes, through electrodes are formed in the semiconductor devices, and the semiconductor devices are three-dimensionally connected. Research and development of three-dimensional stacking technology is being conducted. Compared with conventional two-dimensional mounting technology and multi-layered technology for semiconductor devices using wire bonding, the technology for three-dimensionally stacking semiconductor devices with through electrodes is extremely shortened. Since it is possible and ideal wiring arrangement is possible, not only can the wiring resistance and the wiring capacity be dramatically reduced, but also the development of a new circuit technology that could not be realized by the conventional technology becomes possible.
　一般的に、貫通電極を用いて三次元的に半導体装置を積層するには、貫通電極同士を信頼性高く接続する技術が重要であり、さらに積層数が増えると発熱量が増加するので、熱伝導率の向上も重要な鍵を握る。 In general, in order to stack semiconductor devices three-dimensionally using through electrodes, a technique for connecting through electrodes with high reliability is important, and as the number of stacked layers increases, the amount of heat generation increases. Improving conductivity is also an important key.
　このような課題を実現するために、特許文献１に記載があるように、貫通電極が形成されていない領域に金属パッドや金属バンプを形成する半導体装置の接続方法がある。しかし、貫通電極のある領域と貫通電極の無い領域とでは材料が異なるので、貫通電極の無い領域では金属パッドや金属バンプの接着性が弱まることが多く剥がれ易くなる。また、貫通電極端上の金属パッドや金属バンプの高さと、貫通電極がない領域の金属パッドや金属バンプの高さが異なることが多く、半導体装置面内に不均一な応力がかかり易くなる。 In order to realize such a problem, there is a connection method of a semiconductor device in which a metal pad or a metal bump is formed in a region where a through electrode is not formed, as described in Patent Document 1. However, since the material is different between the region having the through electrode and the region having no through electrode, the adhesion of the metal pad or the metal bump is often weakened and easily peeled off in the region without the through electrode. In addition, the height of the metal pad or metal bump on the end of the through electrode is often different from the height of the metal pad or metal bump in the region where there is no through electrode, and uneven stress is easily applied to the surface of the semiconductor device.
　また、特許文献２に記載があるように、多層基板（プリント配線版）上にバンプを介して第１の半導体チップ（装置）が接続され、第１の半導体チップがインターポーザを介して積層半導体装置と接続した例もある。 Further, as described in Patent Document 2, a first semiconductor chip (device) is connected to a multilayer substrate (printed wiring board) via bumps, and the first semiconductor chip is stacked via an interposer. There is also an example of connecting with.
　たとえ貫通電極のない領域に金属パッドや金属バンプを形成することで、全体的な高さ不均一を低減できたとしても、貫通電極がある領域とない領域では熱伝導率が大きく異なることが問題となる。貫通電極がある領域は、貫通電極がSi基板内に存在しているので、半導体装置の表面側と裏面側における熱伝導率が高い。一方、貫通電極がない領域は、電極がSi基板と直接接触していないだけでなく、貫通電極がSi基板内に存在しないので熱伝導率が明らかに低くなる。これは、積層半導体装置から発生する熱の放熱（冷却）効果を低下させるだけでなく、半導体装置面内でも場所によって温度差が生じることになるので、各領域の温度差による半導体装置の特性変動を引き起す原因にもなっている。 Even if the overall height non-uniformity can be reduced by forming metal pads and metal bumps in areas without through-electrodes, the problem is that the thermal conductivity differs greatly between areas with and without through-electrodes. It becomes. Since the through electrode exists in the Si substrate in the region where the through electrode is present, the thermal conductivity on the front side and the back side of the semiconductor device is high. On the other hand, not only the electrode is not in direct contact with the Si substrate, but also the region without the through electrode has a clearly reduced thermal conductivity because the through electrode is not present in the Si substrate. This not only reduces the heat dissipation (cooling) effect of the heat generated from the stacked semiconductor device, but also causes a temperature difference depending on the location within the semiconductor device surface. It is also the cause that causes.
特開2003-133519号公報JP 2003-133519 JP 特開2008-263005号公報JP 2008-263005 A
　一般的に半導体装置に貫通電極を配置する場合、目的や設計内容にも依存するが　貫通電極を半導体装置内に均等に配置できない場合が多い。また、貫通電極のない領域は貫通電極とは違う材料で構成されているので、半導体装置の接続に直接的に寄与することは少ない。 Generally, when penetrating electrodes are arranged in a semiconductor device, the penetrating electrodes are often not evenly arranged in the semiconductor device, although depending on the purpose and design contents. In addition, since the region without the through electrode is made of a material different from that of the through electrode, it hardly contributes to the connection of the semiconductor device.
　特に、接続信頼性向上等の目的で貫通電極端に金属パッドまたは金属バンプが形成されている場合は、金属パッドまたは金属バンプの高さ分だけ、貫通電極が形成された領域とされていない領域とで高さのずれが生ずる。このため、貫通電極が無い領域はまったく接触しないので半導体装置の接続に寄与しないことになる。さらに、一般的に半導体装置を積層する際は積層方向に圧力をかけるので、貫通電極が形成された領域と形成されていない領域とで半導体装置面内に不均一な応力が加わると、半導体装置の破損、または、デバイス特性不良を引き起こしてしまう可能性が高くなる。 In particular, when a metal pad or metal bump is formed at the end of the through electrode for the purpose of improving connection reliability, an area where the through electrode is not formed by the height of the metal pad or metal bump. And a height shift occurs. For this reason, since the area | region which does not have a penetration electrode does not contact at all, it does not contribute to the connection of a semiconductor device. Furthermore, since pressure is generally applied in the stacking direction when stacking semiconductor devices, if non-uniform stress is applied in the surface of the semiconductor device between the region where the through electrode is formed and the region where the through electrode is not formed, the semiconductor device There is a high possibility that the device will be damaged or the device characteristics may be deteriorated.
　本発明の目的は、半導体装置内の任意の位置に電気導通のある貫通電極を不均一に配置した場合でも、信頼性の高い半導体装置の接続、および、高い熱伝導率を与える積層半導体装置及び積層半導体装置の製造方法を提供することにある。 An object of the present invention is to provide a highly reliable connection of a semiconductor device and a stacked semiconductor device that provides a high thermal conductivity even when through electrodes having electrical continuity are unevenly arranged at arbitrary positions in the semiconductor device, and An object of the present invention is to provide a method for manufacturing a laminated semiconductor device.
　本願出願人は、上記課題を解決するために鋭意検討した結果、電気導通のある貫通電極とは別に電気導通のない電極をいわゆるダミーの電極として用いて、これらの電極を半導体装置面内に均等に配置すれば、半導体装置面内に不均一な応力がかからず信頼性の高い半導体装置の接続が得られ、高い熱伝導率を有する積層半導体装置が得られることを見出し、本発明を完成するに至った。 As a result of diligent study to solve the above problems, the applicant of the present application uses, as a so-called dummy electrode, an electrode having no electrical continuity in addition to a through electrode having electrical continuity, and these electrodes are evenly arranged in the semiconductor device plane. If it is arranged in the semiconductor device, it is found that non-uniform stress is not applied in the surface of the semiconductor device, a highly reliable connection of the semiconductor device is obtained, and a laminated semiconductor device having high thermal conductivity is obtained, and the present invention is completed. It came to do.
　第１の発明の特徴は、（１）電気導通のある貫通電極と電気導通のない電極を備えた半導体装置を複数積層した積層半導体装置にある。 The feature of the first invention resides in (1) a stacked semiconductor device in which a plurality of semiconductor devices each including a through electrode having electrical continuity and an electrode having no electrical continuity are stacked.
　（１）において、（２）前記両電極の電極端に金属パッドまたは金属バンプを形成しても良い。金属パッドまたは金属バンプはデバイス面側からは取り出し電極と配線層を介して電気導通のある貫通電極と電気的に導通される。電気導通のある貫通電極は配線層を介してデバイス領域の回路動作に影響を及ぼす。これに対し、電気導通のない電極は、配線層まで達していないので、デバイスの回路動作に影響を及ぼすことはない。 (1) In (2), a metal pad or a metal bump may be formed on the electrode ends of both electrodes. From the device surface side, the metal pad or the metal bump is electrically connected to the through electrode having electrical conductivity through the extraction electrode and the wiring layer. The through electrode having electrical continuity affects the circuit operation of the device region through the wiring layer. On the other hand, since the electrode without electrical continuity does not reach the wiring layer, it does not affect the circuit operation of the device.
　（２）において、（３）前記金属パッドまたは金属バンプをデバイス面側か半導体装置裏面側のいずれか一方に形成する場合や（４）前記金属パッドまたは金属バンプをデバイス面側と半導体装置裏面側の両方に形成する場合が考えられる。 In (2), (3) the metal pad or metal bump is formed on either the device surface side or the semiconductor device back surface side, or (4) the metal pad or metal bump is formed on the device surface side or the semiconductor device back surface side. The case where it forms in both is considered.
　（１）において、（５）前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内に均一に配置することが好ましい。（５）において、（６）前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内の少なくともデバイス領域に格子状に均一に配置することが好ましい。 (1) In (1), it is preferable that (5) the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in the semiconductor device. In (5), it is preferable that (6) the electrically conductive through electrode and the electrically nonconductive electrode are uniformly arranged in a lattice pattern at least in a device region in the semiconductor device.
　（２）において、（７）前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内に均一に配置することが好ましい。（７）において、（８）前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内の少なくともデバイス領域に格子状に均一に配置することが好ましい。 (2) In (7), it is preferable that (7) the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in the semiconductor device. In (7), it is preferable that (8) the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device.
　（３）において、（９）前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内に均一に配置することが好ましい。（９）において、（１０）前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内の少なくともデバイス領域に格子状に均一に配置することが好ましい。 (3) In (3), it is preferable that (9) the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in the semiconductor device. In (9), it is preferable that (10) the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device.
　（４）において、（１１）前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内に均一に配置することが好ましい。（１１）において、（１２）前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内の少なくともデバイス領域に格子状に均一に配置することが好ましい。 (4) In (4), it is preferable that (11) the through electrode having electrical conduction and the electrode having no electrical conduction are arranged uniformly in the semiconductor device. (11) In (11), it is preferable that (12) the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device.
　第２の発明の特徴は、（１３）
　(a)半導体基板のデバイス面側とは反対側の基板裏面を研磨する工程、
　(b)前記基板裏面から電気導通のない電極穴を加工する工程、
　(c)前記基板裏面から電気導通のある貫通電極穴を加工する工程
　(d)前記両電極穴中に側壁絶縁膜を堆積、加工し、さらに電極材を埋め込んで電極を形成する工程、
　(e)前記両電極端の平坦化を行い半導体装置を形成する工程、
　(f)前記(a)～(e)の工程で得られた半導体装置を複数積層する工程を有する積層半導体装置の製造方法にある。 The feature of the second invention is (13)
(a) polishing the back surface of the substrate opposite to the device surface side of the semiconductor substrate;
(b) a step of machining an electrode hole without electrical conduction from the back surface of the substrate;
(c) a step of processing a through-electrode hole having electrical continuity from the back surface of the substrate (d) a step of depositing and processing a sidewall insulating film in both the electrode holes, and further embedding an electrode material to form an electrode;
(e) a step of flattening both electrode ends to form a semiconductor device;
(f) A method of manufacturing a laminated semiconductor device, including a step of laminating a plurality of semiconductor devices obtained in the steps (a) to (e).
　（１３）において、（１４）
　(g)前記半導体基板上のデバイス面側に金属パッドまたは金属バンプを形成する工程と、
　(h)前記半導体基板上の前記貫通電極側に金属パッドまたは金属バンプを形成する工程から選ばれる少なくとも一つの工程をさらに有しても良い。 In (13), (14)
(g) forming a metal pad or metal bump on the device surface side of the semiconductor substrate;
(h) It may further include at least one step selected from a step of forming a metal pad or a metal bump on the through electrode side on the semiconductor substrate.
　（１３）において、（１５）
　前記側壁絶縁膜の加工は、電極内に堆積させた絶縁膜の穴底絶縁膜を除去すると同時にデバイス側の電極面まで加工することが好ましい。 In (13), (15)
The side wall insulating film is preferably processed to the electrode surface on the device side simultaneously with removal of the hole bottom insulating film of the insulating film deposited in the electrode.
　第３の発明の特徴は、（１６）
　(a)半導体基板のデバイス面側とは反対側の基板裏面を研磨する工程、
　(i)前記基板裏面にマスク材を堆積させる工程、
　(j)電気導通のない電極穴を加工するためのマスクを作成し、加工する工程、
　(k)電気導通のある貫通電極穴を加工するためのマスクを作成し、加工する工程、
　(d)前記両電極穴中に側壁絶縁膜を堆積、加工し、さらに電極材を埋め込んで電極を形成する工程、
　(e)前記両電極端の平坦化を行い半導体装置を形成する工程、
　(f)前記(a)～(e)の工程で得られた半導体装置を複数積層する工程を有する積層半導体装置の製造方法にある。 A feature of the third invention is (16)
(a) polishing the back surface of the substrate opposite to the device surface side of the semiconductor substrate;
(i) a step of depositing a mask material on the back surface of the substrate;
(j) creating and processing a mask for processing an electrode hole without electrical conduction;
(k) creating and processing a mask for processing a through-electrode hole with electrical continuity;
(d) depositing and processing a sidewall insulating film in both the electrode holes, further embedding an electrode material to form an electrode,
(e) a step of flattening both electrode ends to form a semiconductor device;
(f) A method of manufacturing a laminated semiconductor device, including a step of laminating a plurality of semiconductor devices obtained in the steps (a) to (e).
　（１６）において、（１７）
　(g)前記半導体基板上のデバイス面側に金属パッドまたは金属バンプを形成する工程と、
　(h)前記半導体基板上の前記貫通電極側に金属パッドまたは金属バンプを形成する工程から選ばれる少なくとも一つの工程をさらに有することが好ましい。 In (16), (17)
(g) forming a metal pad or metal bump on the device surface side of the semiconductor substrate;
(h) It is preferable that the method further includes at least one step selected from a step of forming a metal pad or a metal bump on the through electrode side on the semiconductor substrate.
　（１６）において、（１８）
　前記側壁絶縁膜の加工は、電極内に堆積させた絶縁膜の穴底絶縁膜を除去すると同時にデバイス側の電極面まで加工することが好ましい。 In (16), (18)
The side wall insulating film is preferably processed to the electrode surface on the device side simultaneously with removal of the hole bottom insulating film of the insulating film deposited in the electrode.
　第４の発明の特徴は、（１９）
　(l)半導体基板の一方の面に電極材を埋め込んで電気導通のある貫通電極を形成する工程、
　(m)半導体基板のもう一方の面を研磨して電気導通のある貫通電極を露出する工程、
　(b’)前記露出面を保護しながら前記露出面と同じ方向の面から電気導通のない電極穴を加工する工程、
　(d’)前記電気導通のない電極穴中に電極材を埋め込んで電極を形成する工程、
　(e)前記両電極端の平坦化を行い半導体装置を形成する工程、
　(f’)前記(l)～(e)の工程で得られた半導体装置を複数積層する工程を有する積層半導体装置の製造方法にある。 The feature of the fourth invention is (19)
(l) a step of forming an electrically conductive through electrode by embedding an electrode material on one surface of a semiconductor substrate;
(m) a step of polishing the other surface of the semiconductor substrate to expose a conductive through electrode,
(b ′) a step of machining an electrode hole without electrical conduction from a surface in the same direction as the exposed surface while protecting the exposed surface;
(d ′) a step of forming an electrode by embedding an electrode material in the electrode hole without electrical conduction;
(e) a step of flattening both electrode ends to form a semiconductor device;
(f ′) A method of manufacturing a laminated semiconductor device, including a step of laminating a plurality of semiconductor devices obtained in the steps (l) to (e).
　（１９）において、（２０）
　(g)前記半導体基板上のデバイス面側に金属パッドまたは金属バンプを形成する工程と、
　(h)前記半導体基板上の前記貫通電極側に金属パッドまたは金属バンプを形成する工程から選ばれる少なくとも一つの工程をさらに有することが好ましい。 In (19), (20)
(g) forming a metal pad or metal bump on the device surface side of the semiconductor substrate;
(h) It is preferable that the method further includes at least one step selected from a step of forming a metal pad or a metal bump on the through electrode side on the semiconductor substrate.
　一般的に、貫通電極が形成されている半導体装置を積層する際に用いる半導体装置は、図１に示すように、デバイス面側と半導体装置裏面側に凸形の金属パッドや金属バンプ８や９を形成しないもの、図２に示すように、デバイス面側または半導体装置裏面側のどちらかに金属パッドや金属バンプ８や９のような凸形の電極を形成するもの、図３に示すように、デバイス面側と半導体装置裏面側に凸形の金属パッドや金属バンプ８と９を両方形成するものに分けられる。図１の中で、基板１は通常Si基板、その表面側に作製されているデバイス領域２には、CMOS回路やメモリ素子等が形成されており、それら上部にはプロテクト膜３と取り出し電極４が形成されていることが多い。 In general, as shown in FIG. 1, a semiconductor device used when stacking semiconductor devices on which through electrodes are formed has a metal pad or metal bumps 8 and 9 that are convex on the device surface side and the back surface side of the semiconductor device. 2, those in which convex electrodes such as metal pads and metal bumps 8 and 9 are formed on either the device surface side or the semiconductor device rear surface side as shown in FIG. 2, as shown in FIG. In other words, it can be divided into those in which both convex metal pads and metal bumps 8 and 9 are formed on the device surface side and the semiconductor device back surface side. In FIG. 1, a substrate 1 is usually a Si substrate, and a CMOS circuit, a memory element, etc. are formed in a device region 2 formed on the surface side, and a protective film 3 and a take-out electrode 4 are formed thereon. Is often formed.
　図１の半導体装置のデバイス面側と半導体装置裏面側を接合することで複数の半導体装置を積層する場合、金属パッドや金属バンプによる高さのずれは生じない。この半導体装置の取り出し電極４と電気導通のある貫通電極５を接続する場合、一般的に貫通電極がない領域７の接触面は接続に寄与しない場合が多いので、貫通電極がない領域７によって接合力が強まることはない。また、凹凸が無く平坦性が高いために、デバイス面側の取り出し電極４と貫通電極５の高さ精度が悪い場合、Si基板厚さの面内分布が不均一で悪くSi基板が反っている場合は、半導体装置面内に不均一な応力がかかるため、接続不良を容易に引き起すことになる。これは接続される電極面積が小さく、その本数が多くなるほど顕著な問題となる。 1 When a plurality of semiconductor devices are stacked by bonding the device surface side and the semiconductor device back surface side of the semiconductor device of FIG. 1, there is no height shift due to metal pads or metal bumps. When the lead electrode 4 of this semiconductor device and the through electrode 5 having electrical continuity are connected, the contact surface of the region 7 where there is no through electrode generally does not contribute to the connection. Power does not increase. In addition, since there is no unevenness and the flatness is high, when the height accuracy of the extraction electrode 4 and the through electrode 5 on the device surface side is poor, the in-plane distribution of the Si substrate thickness is uneven and the Si substrate is warped. In this case, non-uniform stress is applied to the surface of the semiconductor device, so that poor connection is easily caused. This becomes a more significant problem as the area of electrodes to be connected is small and the number of electrodes is increased.
　図２の半導体装置のデバイス面側と半導体装置裏面側を接合することで複数の半導体装置を積層する場合、どちらか片方側の金属パッドや金属バンプ８や９の高さ分、貫通電極がある領域６と無い領域７で高さのずれが生じるが、デバイス側の取り出し電極４と貫通電極５の高さ精度が多少悪くても接続不良が起こり難いという利点がある。しかし、貫通電極が形成されていない領域７は、どちらか片方側の金属パッドや金属バンプ８や９の高さ分ずれが生じるので、積層時の圧力でSi基板が曲がったり応力集中などを起こしやすくなり、Si基板の破損、または、デバイス特性変動等を引き起こす可能性が高くなる。 When a plurality of semiconductor devices are stacked by bonding the device surface side and the semiconductor device back surface side of the semiconductor device of FIG. 2, there are through electrodes corresponding to the height of the metal pads or metal bumps 8 and 9 on either side. Although there is a difference in height between the region 6 and the non-region 7, there is an advantage that poor connection hardly occurs even if the height accuracy of the extraction electrode 4 and the through electrode 5 on the device side is somewhat poor. However, since the region 7 where the through electrode is not formed is displaced by the height of either one of the metal pads or the metal bumps 8 and 9, the Si substrate is bent or stress concentration is caused by the pressure during lamination. This is likely to cause damage to the Si substrate or fluctuations in device characteristics.
　図３の半導体装置のデバイス面側と半導体装置裏面側を接合することで複数の半導体装置を積層する場合、両側に金属パッドや金属バンプ８と９があるので、図２と比較してデバイス側の取り出し電極４の高さと貫通電極側の電気導通のある貫通電極５の高さ精度が悪かったり、さらに、Si基板厚の面内分布が不均一で悪い場合でも接続不良を抑制可能である。しかし、積層する時は、デバイス側と半導体装置裏面側の両面から圧力の影響を受けるので、半導体装置面内における応力不均一の発生は押さえられない。 When a plurality of semiconductor devices are stacked by bonding the device surface side and the semiconductor device back side of the semiconductor device of FIG. 3, since there are metal pads and metal bumps 8 and 9 on both sides, the device side compared to FIG. The connection failure can be suppressed even when the height of the extraction electrode 4 and the height accuracy of the through electrode 5 having electrical conduction on the side of the through electrode are poor or the in-plane distribution of the Si substrate thickness is uneven and bad. However, when laminating, since it is affected by pressure from both the device side and the back side of the semiconductor device, the occurrence of stress non-uniformity within the surface of the semiconductor device cannot be suppressed.
　以上のように、半導体装置を積層する場合は、電極の接続不良と各電極の高さの違いおよびSi基板の平坦性との間には密接な関係があることが判る。 As described above, when stacking semiconductor devices, it can be seen that there is a close relationship between poor connection of electrodes, the difference in height of each electrode, and the flatness of the Si substrate.
　そこで、図４のように、貫通電極の無い領域７に金属パッドや金属バンプ１０などを形成することで、電極同士の接続不良を低減しつつSi基板の平坦性を向上させる方法が考えられる。しかし、この方法でも、電気導通のある貫通電極５の材料と貫通電極の無い領域７の接触面とでは材料が異なるので、貫通電極の無い領域７に形成した金属パッドや金属バンプ１０との密着性が悪かったり、取り出し電極４の端や電気導通のある貫通電極５の端に形成された金属パッドや金属バンプ８と９の高さと異なるなどの問題が生じていた。また、図から明らかなように、貫通電極が無い領域７に作成した金属パッドや金属バンプ１０はSi基板１と直接接触していないので、貫通電極が有る領域６と比較して熱伝導率が悪いことが判る。 Therefore, as shown in FIG. 4, a method of improving the flatness of the Si substrate while reducing the connection failure between the electrodes by forming a metal pad, a metal bump 10 or the like in the region 7 having no through electrode can be considered. However, even in this method, since the material is different between the material of the through electrode 5 having electrical continuity and the contact surface of the region 7 having no through electrode, the metal pad or the metal bump 10 formed in the region 7 having no through electrode is in close contact. There are problems such as poor performance, and the height of the metal pads and metal bumps 8 and 9 formed at the end of the extraction electrode 4 and the end of the through electrode 5 having electrical continuity. Further, as is clear from the figure, the metal pads and metal bumps 10 formed in the region 7 without the through electrode are not in direct contact with the Si substrate 1, so that the thermal conductivity is higher than that of the region 6 with the through electrode. I know it ’s bad.
　本発明はこのような問題点を鑑みてなされたもので、図５の半導体装置面内における電極の均一配置図に示したように、電気導通のある貫通電極１１の他に電気導通のない電極１２を半導体装置１３に均一に（例えば、格子状に）配置することで、金属パッドや金属バンプによる高さずれを抑制しつつ熱伝導率を高められる方法を提供することを目的とする。 The present invention has been made in view of such problems, and as shown in the uniform arrangement diagram of the electrodes in the surface of the semiconductor device in FIG. It is an object of the present invention to provide a method of increasing the thermal conductivity while suppressing the height deviation due to the metal pads and the metal bumps by arranging 12 uniformly on the semiconductor device 13 (for example, in a lattice shape).
　本発明によれば、半導体装置内の任意の位置に電気導通のある貫通電極を不均一に配置した場合でも、信頼性の高い半導体装置の接続、および、高い熱伝導率を与える積層半導体装置及び積層半導体装置の製造方法を提供することができる。 According to the present invention, a highly reliable semiconductor device connection and a laminated semiconductor device that provides high thermal conductivity even when through electrodes having electrical continuity are unevenly arranged at arbitrary positions in the semiconductor device, and A method for manufacturing a stacked semiconductor device can be provided.
デバイス面側と半導体装置裏面側に金属パッドまたは金属バンプのない半導体装置の積層図。FIG. 6 is a stacked view of a semiconductor device having no metal pads or metal bumps on the device surface side and the semiconductor device back surface side. デバイス面側か半導体装置裏面側のどちらかに金属パッドまたは金属バンプのある半導体装置の積層図。FIG. 6 is a stacked view of a semiconductor device having metal pads or metal bumps on either the device surface side or the semiconductor device back surface side. デバイス側と半導体装置裏面側の両方に金属パッドまたは金属バンプのある半導体装置の積層図。FIG. 6 is a stacked view of a semiconductor device having metal pads or metal bumps on both the device side and the back side of the semiconductor device. 貫通電極のない領域に金属パッドまたは金属バンプを形成した半導体装置の積層図。FIG. 6 is a stacked view of a semiconductor device in which metal pads or metal bumps are formed in a region without through electrodes. 半導体装置面内における電極の均一配置図。The uniform arrangement figure of the electrode in a semiconductor device surface. via Firstによる電極の形成例。Example of electrode formation by via First. via Firstによる電気導通のない電極の形成例。Example of electrode formation without electrical continuity by via に よ る First. via Lastによる電気導通のある貫通電極と電気導通のない電極の形成例。Example of forming a through electrode with electrical conduction and an electrode without electrical conduction by via に よ る Last. ハードマスクを工夫することでvia Lastによる電気導通のある貫通電極と電気導通のない電極を一度に形成する例。An example of forming a through electrode with electrical conduction and an electrode without electrical conduction at once by devising a hard mask. 本発明の電極作製方法を用いて作製した積層半導体チップの製造方法に関するフローチャートThe flowchart regarding the manufacturing method of the laminated semiconductor chip manufactured using the electrode manufacturing method of this invention. 積層半導体装置の実施例Example of stacked semiconductor device
　初めに電極の形状に関して説明する。 First, the electrode shape will be described.
　本発明に使用する電気導通のある貫通電極の直径や形状その間隔に特に制限はないが、電極が円柱の場合、その直径（または長さ）は0.3～200μmの範囲で、間隔は電極の直径の5倍～1/5程度が望ましい（例えば電極の直径が10μmであれば、間隔は50μm～2μmの範囲）。 There are no particular restrictions on the diameter and shape of the through-electrodes used in the present invention, but when the electrodes are cylindrical, the diameter (or length) is in the range of 0.3 to 200 μm, and the distance is the electrode diameter. Is preferably about 5 to 1/5 (for example, if the electrode diameter is 10 μm, the interval is in the range of 50 μm to 2 μm).
　電極の直径が0.3μmよりも小さい場合は電極の静電容量が大きくなると同時に抵抗自体も増加するのでダミーの電極を利用する利点が減ってしまう。逆に、電極の直径が200μmよりも大きい場合は、半導体装置内に占める電極面積の割合が大きくなりすぎて半導体素子を配置できる面積が減少するので、ダミーの電極を利用するメリットが減少してしまう。 When the electrode diameter is smaller than 0.3 μm, the electrostatic capacity of the electrode increases and the resistance increases at the same time, so the advantage of using a dummy electrode is reduced. On the contrary, when the electrode diameter is larger than 200 μm, the ratio of the electrode area in the semiconductor device becomes too large, and the area where the semiconductor element can be arranged decreases, so the merit of using the dummy electrode is reduced. End up.
　電極の間隔が直径の5倍よりも大きい場合は、電極の無い領域が増えすぎてしまい、その領域に積層加圧時の応力が集中しやすくなる。また、電極の間隔が直径の1/5よりも狭い場合は、となり合う電極間で接続する恐れが高まる。 When the distance between the electrodes is larger than 5 times the diameter, the area without the electrodes increases too much, and stress at the time of stacking pressurization tends to concentrate on the area. In addition, when the distance between the electrodes is narrower than 1/5 of the diameter, the risk of connection between adjacent electrodes increases.
　一方、電気導通の無い電極の直径またはその間隔も特に制限はないが、電気導通のある貫通電極の場合と同じと考えて良い。しかし、電極端に金属バンプ等を形成する場合は、電気導通のある貫通電極と電気導通の無い電極は同じ形状であることが望ましい。これは、金属バンプ等を形成する際、バンプ形状が異なるとバンプ高さが変化してしまうためで、別の方法でバンプ高さを再調整する場合にはこの限りではない。 On the other hand, the diameter of the electrode without electrical continuity or the distance between the electrodes is not particularly limited, but may be considered to be the same as that of the through electrode with electrical continuity. However, when a metal bump or the like is formed at the electrode end, it is desirable that the through electrode having electrical continuity and the electrode having no electrical continuity have the same shape. This is because the bump height changes when the bump shape is different when forming a metal bump or the like, and this is not the case when the bump height is readjusted by another method.
　次に、電極の深さ（長さ）に関して説明する。 Next, the depth (length) of the electrode will be described.
　一般的に電極の深さは、形状を優先して決められるものではなく、回路設計の観点、最終的な積層数とその厚さの制限値、プロセス上の技術的限界等から決定される。電極の深さが浅くなるほど、つまりウェーハ厚やチップ厚が薄いほど、薄厚時のウェーハ厚やチップ厚の制御が難しくなるだけでなく、ウェーハやチップの取扱い、および，ハンドリングが困難になるのでウェーハやチップが破損しやすくなる。 In general, the depth of the electrode is not determined with priority on the shape, but is determined from the viewpoint of circuit design, the final number of stacked layers and the limit value of the thickness thereof, the technical limit on the process, and the like. The shallower the electrode depth, that is, the thinner the wafer thickness and chip thickness, the more difficult the wafer thickness and chip thickness control becomes, and the more difficult the wafer and chip handling and handling become. And the chip is easily damaged.
　逆に、電極の深さが深くなるほど、つまりウェーハ厚やチップ厚が厚くなるほど、径の小さい（高アスペクト比）穴を形成するのが難しくなる。当然であるが、電極の深さが深くなるほど抵抗値が増加し静電容量も増えるのでダミーの電極を使用する利点が減る方向である。通常、信号線として使用する電極の深さは100μm以下が望ましく、理想的には5～50μmの範囲が望ましい。 Conversely, as the electrode depth increases, that is, as the wafer thickness or chip thickness increases, it becomes more difficult to form a hole with a small diameter (high aspect ratio). As a matter of course, as the depth of the electrode increases, the resistance value increases and the capacitance also increases, so the advantage of using a dummy electrode tends to decrease. Usually, the depth of an electrode used as a signal line is desirably 100 μm or less, and ideally a range of 5 to 50 μm is desirable.
　また、電気導通のある貫通電極は基板を貫通させてデバイス面側の内部電極（またはデバイス領域最上部の取り出し電極）と接触させる必要があるが、電気導通のない電極は基板を貫通させずにその手前で止めることが重要である。電気導通のない電極を、デバイス領域の手前で止めすぎた場合は電極が基板内に存在しない分、熱伝導率の点で不利になる。逆に、貫通させてしまった場合は、デイバス面側の回路に悪影響を与えてしまう。このため、電気導通のない電極の深さ（長さ）は、電気導通のある貫通電極の深さ（長さ）よりも僅かに浅く（または短く）するのか望ましい。理想的には、デバイス領域よりも1μm以上離すのが望ましい。 In addition, the through electrode with electrical continuity needs to penetrate the substrate and contact the internal electrode on the device surface side (or the extraction electrode at the top of the device region), but the electrode without electrical continuity does not penetrate the substrate. It is important to stop before that. If an electrode without electrical conduction is stopped too far in front of the device region, there is a disadvantage in terms of thermal conductivity because the electrode is not present in the substrate. On the contrary, if it is penetrated, the circuit on the device surface side is adversely affected. For this reason, it is desirable that the depth (length) of the electrode without electrical conduction be slightly shallower (or shorter) than the depth (length) of the through electrode with electrical conduction. Ideally, it should be at least 1 μm away from the device area.
　同様に、基板を貫通させた電気導通のある貫通電極であっても、デバイス領域との距離が近すぎる場合は回路特性に悪影響を及ぼすため、電気導通のある貫通電極はデバイス領域から数μm、理想的には1μm以上離した場所に配置するのが望ましい。 Similarly, even through electrodes with electrical continuity that penetrate the substrate, if the distance to the device region is too close, circuit characteristics will be adversely affected, so the through electrode with electrical continuity is several μm from the device region, Ideally, it should be placed in a place separated by 1 μm or more.
　続いて、電極の形成方法に関して説明する。一般的に、電極を形成する方法は、おおまかにvia-Firstとvia-Lastに分類される。 Subsequently, an electrode forming method will be described. In general, the method of forming an electrode is roughly classified into via-First and via-Last.
　図６に示すように、via-Firstは半導体装置が完成する前、ここではデバイス領域２の作製前に電気導通のある貫通電極穴１５を形成するため、位置合わせ精度が高く、微細な電極を形成するのに適している。貫通電極穴１５の中に、貫通電極内の側壁絶縁膜１６を堆積させ、その後埋め込み電極１７を形成し、最後に埋め込み電極１７の端を平坦化することで、それぞれが電気的に独立した電気導通のある貫通電極5を形成している。この場合、この後に続くプロセス熱処理温度が高い場合が多いので、貫通電極材料としてPoly-SiやW等が使われる場合が多い。また、デバイス領域２作製後に貫通電極穴１５を形成する場合もあるが、この場合はあとに続くプロセス熱処理温度を低く抑えられるので、Cu等の金属が使用される場合が多い。 As shown in FIG. 6, via-First forms a through-electrode hole 15 having electrical continuity before a semiconductor device is completed, here, before the device region 2 is manufactured. Suitable for forming. A sidewall insulating film 16 in the through electrode is deposited in the through electrode hole 15, and then a buried electrode 17 is formed. Finally, the end of the buried electrode 17 is flattened, so that each of the electrically independent electrodes A conductive through electrode 5 is formed. In this case, since the subsequent process heat treatment temperature is often high, Poly-Si, W, or the like is often used as the through electrode material. In some cases, the through electrode hole 15 is formed after the device region 2 is manufactured. In this case, since the subsequent process heat treatment temperature can be kept low, a metal such as Cu is often used.
　電気導通のある貫通電極5の形成後、デバイス領域２、配線層１４、取り出し電極４を形成して、半導体装置を完成させる。その後、取り出し電極４上に、デバイス面側の金属パッドまたは金属バンプ８を形成した後で、基板研磨で基板を薄厚化して貫通電極端を露出させて貫通電極露出面１８を得る。貫通電極露出面１８を塞がないようにプロテクト膜３で半導体装置裏面側を保護し、最後に半導体装置裏面側の金属パッドまたは金属バンプ９を形成する。 After the formation of the electrically conductive through electrode 5, the device region 2, the wiring layer 14, and the extraction electrode 4 are formed to complete the semiconductor device. Then, after forming the device surface side metal pad or metal bump 8 on the extraction electrode 4, the substrate is thinned by substrate polishing to expose the end of the through electrode to obtain the through electrode exposed surface 18. The back surface side of the semiconductor device is protected by the protection film 3 so as not to block the exposed surface 18 of the through electrode, and finally metal pads or metal bumps 9 on the back surface side of the semiconductor device are formed.
　このようにvia-Firstの場合は、電気導通のない電極を形成しようとすると、その領域には回路を配置することができないので、使用できない無駄な領域ばかり増えてしまう。このため、via-Firstの場合は、電気導通のある貫通電極と電気導通のない電極とを同時に作成することは極めて困難である。 In this way, in the case of via-first, when an electrode without electrical continuity is formed, a circuit cannot be arranged in that region, so that only a useless region that cannot be used increases. For this reason, in the case of via-first, it is extremely difficult to simultaneously create a through electrode having electrical continuity and an electrode having no electrical continuity.
　via-Firstで電気導通のない電極を形成するには、半導体装置の完成後、図７（１）のように、基板を薄厚化して電気導通のある貫通電極５を基板裏面から露出させた後に（貫通電極露出面１８）、電気導通のない電極１９を形成する必要がある。 In order to form an electrode without electrical conduction by via-first, after the semiconductor device is completed, the substrate is thinned and the through electrode 5 having electrical conduction is exposed from the back surface of the substrate as shown in FIG. It is necessary to form (penetrating electrode exposed surface 18) and electrode 19 having no electrical continuity.
　初めに、電気導通のある貫通電極露出面１８を何らかの方法でカバーしつつ、電気導通のない電極穴１９の加工、電極穴１９内部への側壁絶縁膜１６の堆積と埋め込み電極１７の形成、そして１７端の平坦化を行い、電気導通のない電極２０を形成する。その後、フォトリソ工程とドライエッチング工程により、電気導通のある貫通電極５の端の開口を行い、両電極５と２０の端に電極を形成した後に、電気導通のある貫通電極５と電気導通のない電極２０の端の高さを合わせるための平坦化処理を行う。最後に、両電極端に金属パッドまたは金属バンプ９を形成するので、プロセス時間が長くかかるだけでなく、プロセスコストも高くなるなどの問題が多い。 First, while the through electrode exposed surface 18 having electrical conduction is covered by some method, the processing of the electrode hole 19 without electrical conduction, the deposition of the sidewall insulating film 16 in the electrode hole 19 and the formation of the embedded electrode 17, and 17 ends are flattened to form an electrode 20 having no electrical continuity. Thereafter, the end of the electrically conductive through electrode 5 is opened by the photolithography process and the dry etching process, and the electrodes are formed at the ends of the electrodes 5 and 20, and then the electrically conductive through electrode 5 is not electrically connected. A planarization process for adjusting the height of the end of the electrode 20 is performed. Finally, since metal pads or metal bumps 9 are formed on both electrode ends, there are many problems such as not only a long process time but also a high process cost.
　上記のように、電極の高さを合わせるために、電極形成後に両電極端を削ることで高さ調整する方法も一つだが、基板を薄厚化する際、電気導通のある貫通電極が基板表面に露出する少し前で薄厚化を止めて、この状態で電気導通のない電極を形成し、その後にSi基板ごと電極を加工して両電極の高さを合わせる方法もある。 As described above, in order to adjust the height of the electrode, there is one method of adjusting the height by scraping the ends of both electrodes after forming the electrode. There is also a method in which the thinning is stopped just before exposure to, and an electrode having no electrical continuity is formed in this state, and then the electrodes are processed together with the Si substrate to adjust the heights of both electrodes.
　一方、図８に示すように、via-Lastは、半導体装置の完成後に基板を薄厚化した後、デバイス面側とは反対側の基板裏面から貫通電極を形成する。薄い基板のハンドリング方法の問題や、熱処理温度に制限（一般的に固い支持基板等に樹脂や接着剤等の何らかの方法で貼り付けるため）があるなど、プロセス的な制限を受けやすい。しかし、電気導通のある貫通電極５と電気導通のない電極２０をほぼ同時に作成することが容易である。 On the other hand, as shown in FIG. 8, via-Last forms a through electrode from the back surface of the substrate opposite to the device surface side after the substrate is thinned after completion of the semiconductor device. There is a problem with thin substrate handling methods, and there are limitations on the heat treatment temperature (generally because it is affixed to a hard support substrate or the like by some method such as resin or adhesive). However, it is easy to produce the through electrode 5 having electrical continuity and the electrode 20 having no electrical continuity almost simultaneously.
　図８は、電気導通のある貫通電極５と電気導通のない電極２０をほぼ同時に作成する方法を示している。初めに、完成した半導体装置のデバイス面側に金属パッドまたは金属バンプ８を形成し、その後、基板を研磨により薄厚化する。次に、電気導通のない電極用のフォトリソ工程とその電極穴１９の加工（基板は貫通させない）を行ない、次に、電気導通のある貫通電極用のフォトリソ工程とその貫通電極穴１５の加工を行う（基板を貫通させデバイス側まで）。 FIG. 8 shows a method of forming the through electrode 5 having electrical conduction and the electrode 20 having no electrical conduction almost simultaneously. First, metal pads or metal bumps 8 are formed on the device surface side of the completed semiconductor device, and then the substrate is thinned by polishing. Next, the photolithographic process for the electrode without electrical conduction and the processing of the electrode hole 19 (the substrate is not penetrated) are performed, and then the photolithographic process for the through electrode with electrical conduction and the processing of the through electrode hole 15 are performed. Perform (through the substrate to the device side).
　レジスト除去後、電気導通のある貫通電極穴１５と電気導通のない電極穴１９の両電極穴に同時に側壁絶縁膜１６を堆積させた後に、電気導通のある貫通電極穴１５の穴底絶縁膜を全て除去する。この際、電気導通のある貫通電極穴１５の穴底には素子分離絶縁膜や層間絶縁膜などがある場合は、それらも一緒に除去する。穴底絶縁膜を全て除去した後に、埋め込み電極１７を形成して最後に電極端の平坦化を行なう。 After the resist is removed, the sidewall insulating film 16 is simultaneously deposited in both electrode holes of the electrically conductive through electrode hole 15 and the electrically nonconductive electrode hole 19, and then the hole bottom insulating film of the electrically conductive through electrode hole 15 is formed. Remove all. At this time, if there is an element isolation insulating film or an interlayer insulating film at the bottom of the through-electrode hole 15 having electrical conduction, these are also removed together. After all the hole bottom insulating film is removed, the buried electrode 17 is formed and finally the electrode end is flattened.
　こうすることで、電気導通のある貫通電極５と電気導通のない電極２０を同時に作成可能である。この場合、電気導通のある貫通電極５の端の高さと、電気導通のない電極２０の端の高さは同じになる。最後に、両電極端に金属パッドまたは金属バンプ９を形成することで、積層用半導体装置が得られる。 By doing so, it is possible to simultaneously create the through electrode 5 having electrical continuity and the electrode 20 having no electrical continuity. In this case, the height of the end of the through electrode 5 having electrical continuity is the same as the height of the end of the electrode 20 having no electrical continuity. Finally, by forming metal pads or metal bumps 9 on both electrode ends, a stacked semiconductor device can be obtained.
　また、図９に示すように、電極加工用のマスクを工夫することで、電気導通のある貫通電極５と電気導通のない電極２０をより簡便に作成することも可能である。 Further, as shown in FIG. 9, by devising a mask for electrode processing, it is possible to more easily create the through electrode 5 having electrical continuity and the electrode 20 having no electrical continuity.
　図９（１）のように、完成した半導体装置を薄厚化した後、ハードマスクとしてCVD酸化膜２１を堆積させる。初めに、CVD酸化膜２１表面に電気導通のない電極用のリソグラフィとその電極用のハードマスク加工を行なう。この際、CVD酸化膜は全て加工せずに適当な厚さを残し、Si表面まで決して露出させない。続いて、電気導通のある貫通電極用のリソグラフィをこのCVD酸化膜２１に行い、その貫通電極用のハードマスク加工を行なう。この際、CVD酸化膜２１は全て除去しSi表面を露出させる。この状態で、電気導通のある貫通電極穴１５を加工すると、CVD酸化膜２１の薄い領域が早めにエッチングされて無くなり、電気導通のない電極用の穴としてSiが露出して、電気導通のない電極穴１９が形成されることになるので、電気導通のある貫通電極穴１５と電気導通のない電極穴１９を同時に形成することができる。この後、図８（５）～（７）の工程を経ることで、図８と同様な積層用半導体装置が得られる。 As shown in FIG. 9A, after the completed semiconductor device is thinned, a CVD oxide film 21 is deposited as a hard mask. First, lithography for electrodes having no electrical continuity on the surface of the CVD oxide film 21 and hard mask processing for the electrodes are performed. At this time, the CVD oxide film is not processed, leaving an appropriate thickness and never exposing the Si surface. Subsequently, lithography for through electrodes having electrical continuity is performed on the CVD oxide film 21, and hard mask processing for the through electrodes is performed. At this time, the CVD oxide film 21 is completely removed to expose the Si surface. In this state, when the through-electrode hole 15 having electrical continuity is processed, the thin region of the CVD oxide film 21 is etched away early, and Si is exposed as a hole for an electrode without electrical continuity, and there is no electrical continuity. Since the electrode hole 19 is formed, the through-electrode hole 15 having electrical continuity and the electrode hole 19 having no electrical continuity can be formed simultaneously. Thereafter, through the steps of FIGS. 8 (5) to (7), a semiconductor device for stacking similar to that of FIG. 8 is obtained.
　次に半導体装置の積層方法、および、積層半導体装置について、一つの実施例としてvia-Lastの場合を例にとり、図１０に例示したフローチャートに従って、図８を例に説明する。 Next, a semiconductor device stacking method and a stacked semiconductor device will be described with reference to FIG. 8 according to the flowchart illustrated in FIG. 10, taking the case of via-Last as an example as an example.
　まず完成した半導体装置のデバイス側に金属バンプ８を形成する。この金属バンプ８のレイアウトは、デバイス面側とは反対の半導体装置裏面側と同じレイアウトになっており、積層する際、同じ位置で重なるようにレイアウトしている。この金属バンプ８が形成されたデバイス面をテープ等で保護した状態で、基板を薄厚化する。 First, metal bumps 8 are formed on the device side of the completed semiconductor device. The layout of the metal bumps 8 is the same layout as the back side of the semiconductor device opposite to the device side, and is laid out so as to overlap at the same position when stacked. The substrate is thinned while the device surface on which the metal bumps 8 are formed is protected with a tape or the like.
　次に、薄厚化した基板の裏面に、電気導通のない電極２０用のリソグラフィとその電極穴１９の加工（基板は貫通させない）を行い、続いて電気導通のある貫通電極５用のリソグラフィとその貫通電極穴１５の加工を行う（基板を貫通させデバイス側まで）。電気導通のある貫通電極穴１５と電気導通のない電極穴１９にCVD酸化膜で側壁絶縁膜１６を堆積させ、穴底に存在するCVD酸化膜、素子分離絶縁膜、層間絶縁膜等をドライエッチングにて全て除去してデバイス側内部の電極を露出させる。その後、両電極の内壁にスパッタ装置にてシード層（Ta/Cu）を堆積させてから、埋め込み電極１７としてCuメッキにて電極内を全て埋め込み、最後にCMPにて両電極端を平坦化した。 Next, lithography for the electrode 20 having no electrical continuity and processing of the electrode hole 19 (the substrate is not allowed to penetrate) are performed on the back surface of the thinned substrate, followed by lithography for the through electrode 5 having electrical continuity and its The through electrode hole 15 is processed (through the substrate to the device side). A sidewall insulating film 16 is deposited with a CVD oxide film in the through-hole 15 having electrical continuity and the electrode hole 19 having no electrical continuity, and the CVD oxide film, element isolation insulating film, interlayer insulating film, etc. existing at the bottom of the hole are dry-etched. To remove all the electrodes and expose the electrodes inside the device. After that, a seed layer (Ta / Cu) was deposited on the inner walls of both electrodes by a sputtering apparatus, and then the entire electrode was embedded by Cu plating as the embedded electrode 17, and finally the ends of both electrodes were flattened by CMP. .
　続いて、両電極の端に金属バンプ９を形成するためのリソグラフィ工程を行い、シード金属をスパッタで堆積させた後、金属バンプ９用の金属メッキを行なう。メッキ後の金属バンプをCMPにて平坦化した後に、レジストを除去することで半導体装置裏面側に金属バンプ９を形成した。これにより、積層半導体装置を得た。 Subsequently, a lithography process for forming metal bumps 9 at the ends of both electrodes is performed, and after seed metal is deposited by sputtering, metal plating for the metal bumps 9 is performed. After the metal bumps after plating were planarized by CMP, the resist was removed to form metal bumps 9 on the back side of the semiconductor device. Thereby, a laminated semiconductor device was obtained.
　この状態の積層半導体装置のデバイス側と、別の積層半導体装置の半導体装置裏面側を位置合わせして、適当な加熱と圧力をかけて積層していく。この際、バンプ同士の接続は仮止め程度に接続しておく。目的の積層数を積層後、本接続として仮接続よりも強い圧力で加圧して積層半導体同士を接続する。得られた積層半導体装置をダイシング工程により切断し、積層半導体チップを得た。この積層半導体チップの側面からアンダーフィル剤を充填させ、最後にアンダーフィル剤を熱により硬化させて積層半導体装置を完成させた。 Align the device side of the stacked semiconductor device in this state and the back side of the semiconductor device of another stacked semiconductor device, and stack them by applying appropriate heating and pressure. At this time, the bumps are connected to the extent of temporary fixing. After stacking the desired number of stacked layers, the stacked semiconductors are connected to each other by pressing with a pressure stronger than the temporary connection as the main connection. The obtained laminated semiconductor device was cut by a dicing process to obtain a laminated semiconductor chip. An underfill agent was filled from the side surface of the laminated semiconductor chip, and finally the underfill agent was cured by heat to complete a laminated semiconductor device.
　以下に本発明の実施の形態をさらに詳細に説明するが、本発明は以下の実施の形態の内容に限定されるものではない。 Hereinafter, although embodiments of the present invention will be described in more detail, the present invention is not limited to the contents of the following embodiments.
（実施の形態１）
　ここでは、via-Lastにおいて貫通電極を形成した積層半導体装置の実施例に関して説明する。はじめに、完成した半導体装置のデバイス側に金属バンプを形成する方法を説明する。デバイス側の最上部には、Alで形成された取り出し用のAl電極が面内に均一配置されており、それらの高さは皆同じである。回路設計により、予め内部回路との電気導通があるAl電極と電気導通がないAl電極の両方が形成されている。  (Embodiment 1)
Here, an example of a stacked semiconductor device in which a through electrode is formed in via-Last will be described. First, a method for forming metal bumps on the device side of a completed semiconductor device will be described. At the top of the device side, Al electrodes for extraction made of Al are uniformly arranged in the plane, and their heights are all the same. According to the circuit design, both an Al electrode having electrical continuity with the internal circuit and an Al electrode having no electrical continuity are formed in advance.
　シードとなる金属をスパッタで堆積させ、レジスト塗布後、Al電極領域のみフォトリソ工程で開口し、その後メッキにより開口部に金属を成長させる。金属メッキ材料としては、一般的にAu、Cu、Niなどが好ましいが、ハンダ系材料のSnが使われる場合もある。また、金属メッキ材料は一種ではなく、複数重ねても良い。この後、金属バンプ高さを揃えるために、金属バンプ上端を平坦化している。平坦化後、レジストを除去し、ウェットエッチングにてシード金属を取り除くことで、Al金属上にのみ金属バンプを形成した。 The seed metal is deposited by sputtering, and after applying the resist, only the Al electrode region is opened by a photolithography process, and then the metal is grown in the opening by plating. As the metal plating material, Au, Cu, Ni or the like is generally preferable, but solder material Sn may be used. Further, the metal plating material is not one kind, and a plurality of metal plating materials may be stacked. Thereafter, in order to align the metal bump height, the upper end of the metal bump is flattened. After planarization, the resist was removed, and the seed metal was removed by wet etching to form metal bumps only on the Al metal.
　デバイス側にバンプが形成されているので、バンプ面を保護テープで保護した状態でウェーハを30μmまで薄厚化する。ウェーハの薄厚化は、一般的なバックグラインディング装置を用いて行ない、研磨面はストレスリリーフ処理を行っている。 Since bumps are formed on the device side, the wafer thickness is reduced to 30μm with the bump surface protected with a protective tape. The wafer is thinned using a general back grinding apparatus, and the polished surface is subjected to stress relief processing.
　次に、上記半導体装置の裏面から電極を形成する方法を説明する。薄厚化した半導体装置は、自重保持できないのでサポート基板に貼付けてある。はじめに、基板裏面に電気導通のない電極用の穴を形成するため、酸化膜を用いてハードマスクを形成する。このハードマスクは、電極とSi基板、および、電極間の導通を防ぐだけでなく、裏面の保護膜としての役割も担っている。200℃以下の低温で成膜可能なCVD酸化膜を用いた。 Next, a method for forming electrodes from the back surface of the semiconductor device will be described. Since the thinned semiconductor device cannot hold its own weight, it is attached to the support substrate. First, a hard mask is formed using an oxide film in order to form a hole for an electrode without electrical conduction on the back surface of the substrate. This hard mask not only prevents conduction between the electrode and the Si substrate and the electrodes, but also serves as a protective film on the back surface. A CVD oxide film that can be formed at a low temperature of 200 ° C. or lower was used.
　ハードマスク用のフォトリソ工程後、ドライエッチングにて電気導通のない電極穴用のハードマスク加工を行う。この際、ハードマスクを完全に除去するのではなく、途中で加工を止める。加工せずに残す酸化膜の膜厚は、Siと酸化膜との選択比により決定される。この場合、電気導通のない電極穴の深さが最終的に27～29μmになるように調整している。 After the photolithography process for hard mask, hard mask processing for electrode holes without electrical conduction is performed by dry etching. At this time, the hard mask is not completely removed, but the processing is stopped halfway. The film thickness of the oxide film that remains without being processed is determined by the selection ratio between Si and the oxide film. In this case, the depth of the electrode hole without electrical continuity is adjusted so that it finally becomes 27 to 29 μm.
　電気導通のない電極穴用のハードマスク加工後、再びフォトリソ工程にて電気導通のある貫通電極用のハードマスクを加工する。この場合、電気導通のある貫通電極領域のハードマスクは全て除去し、Si基板まで露出させる。ここまでで、電気導通のある貫通電極用のハードマスクパターンと電気導通のないハードマスクパターンの２種類が同一面上にできる。 After processing the hard mask for electrode holes without electrical continuity, the hard mask for through electrodes with electrical continuity is processed again in the photolithography process. In this case, all the hard masks in the through electrode regions having electrical continuity are removed and exposed to the Si substrate. Up to this point, two types of hard mask patterns for through electrodes having electrical conduction and hard mask patterns having no electrical conduction can be formed on the same surface.
　このハードマスクを用いて、電気導通のある貫通電極穴をドライエッチングにて加工する。この際、Si基板を完全に貫通させるが、ハードマスク用の酸化膜は残るような膜厚に設定している。この時、電気導通のない電極は、ハードマスクを完全に加工しなかった残りの酸化膜厚分、電極穴の深さが浅く加工される。 Using this hard mask, a through electrode hole with electrical continuity is processed by dry etching. At this time, the Si substrate is completely penetrated, but the thickness is set such that the oxide film for the hard mask remains. At this time, the electrode without electrical continuity is processed so that the depth of the electrode hole is shallow by the remaining oxide film thickness that has not been completely processed by the hard mask.
　続いて、電極内の側面に絶縁膜を形成するため、低温成膜CVD酸化膜を堆積させる。電極内の穴底の絶縁膜をドライエッチングにて除去するが、穴底にあるデバイス領域の素子分離絶縁膜と電極と接続するメタル配線までの層間絶縁膜も一緒に除去する必要がある。最終的にはデバイス側に形成された受け側の金属電極（配線層）に到達するまで穴底の絶縁膜を除去する。この受け側の金属電極は、回路と電気的に繋がっている。 Subsequently, a low-temperature CVD oxide film is deposited to form an insulating film on the side surface in the electrode. Although the insulating film at the bottom of the hole in the electrode is removed by dry etching, the element isolation insulating film in the device region at the bottom of the hole and the interlayer insulating film up to the metal wiring connected to the electrode must be removed together. Finally, the insulating film at the bottom of the hole is removed until the metal electrode (wiring layer) on the receiving side formed on the device side is reached. The receiving metal electrode is electrically connected to the circuit.
　電極内を適当な洗浄液で洗浄した後、スパッタによりバリア膜とシードCuを形成する。その後、メッキ法にて電極内にCuを充填し、余分なCuをCMPにて除去すれば電気導通のある貫通電極と、電気導通のない電極が同時に形成される。 After cleaning the inside of the electrode with an appropriate cleaning solution, a barrier film and seed Cu are formed by sputtering. After that, if the electrode is filled with Cu by plating and excess Cu is removed by CMP, a through electrode having electrical continuity and an electrode having no electrical continuity are formed simultaneously.
　次に、裏面の電極端に金属バンプを形成する方法を説明する。デバイス側に形成した方法と同じ方法で作成する。シードとなる金属をスパッタで形成し、レジスト塗布後、電極の領域のみフォトリソ工程で開口し、その後メッキにより開口部に金属を成長させる。レジストを除去した後、ウェットエッチングにてシード金属を除去し、電極端にのみ金属バンプを形成した。 Next, a method for forming metal bumps on the electrode ends on the back surface will be described. It is created by the same method as that formed on the device side. A metal to be a seed is formed by sputtering, and after applying a resist, only the electrode region is opened by a photolithography process, and then the metal is grown in the opening by plating. After removing the resist, the seed metal was removed by wet etching, and metal bumps were formed only at the electrode ends.
　デバイス面側と半導体装置裏面側の両方にバンプが形成された積層半導体装置を、サポート基板から取り外し、ダイシングにて各チップに分離することで、両面バンプ付き電極チップ２２を得た。 The electrode chip 22 with double-sided bumps was obtained by removing the laminated semiconductor device having bumps formed on both the device surface side and the back side of the semiconductor device from the support substrate and separating each chip by dicing.
　各チップに分離した両面バンプ付き電極チップ２２を積層する方法を説明する。図１１の積層半導体装置の実施例に示すように、積層の一番下のチップは、前記記載の半導体装置とは異なり、インターフェース専用に作製されたインターフェースチップ２３である。このインターフェースチップ２３は、主に積層された両面バンプ付き電極チップ２２と実装基板２５とを電気的に導通または再配線させるのが目的である。 A method for laminating the electrode chip 22 with the double-sided bumps separated into each chip will be described. As shown in the example of the stacked semiconductor device in FIG. 11, the chip at the bottom of the stacked layer is an interface chip 23 manufactured exclusively for the interface, unlike the semiconductor device described above. The purpose of the interface chip 23 is to electrically connect or rewiring the stacked double-sided bumped electrode chip 22 and the mounting substrate 25.
　また、このインターフェースチップ２３の厚さは200μｍと厚い。これは、両面バンプ付き電極チップ２２が30μmと非常に薄いため、その薄いチップだけを積層しようとすると、チップ積層時にチップが曲がったり、破損したりする可能性が高くなるので、信頼性の高い積層が行なえない。このような不具合を防ぐために、一番下のインターフェースチップ２３だけはチップが反らないように厚くしている。 The thickness of the interface chip 23 is as thick as 200 μm. This is because the electrode chip 22 with the double-sided bumps is very thin as 30 μm, and if only the thin chip is stacked, the possibility of the chip being bent or damaged at the time of stacking the chips increases, so that the reliability is high. Lamination is not possible. In order to prevent such a problem, only the bottom interface chip 23 is thickened so that the chip does not warp.
　インターフェースチップ２３と両面バンプ付き電極チップ２２の位置を合わせて、ボンディング装置を使って１チップずつ積層していく。１チップずつの積層は、はじめに本接続ではなく、接続力の弱い仮接続で行なう。目的の積層数まで仮積層したら、最後に本接続としてチップの上から下まで全体に強い圧力と熱をかけて接続する。これより得られた積層半導体装置２４を、ハンダバンプ２７を介して実装基板２５と接続する。 Align the position of the interface chip 23 and the electrode chip 22 with double-sided bumps, and use a bonding device to stack one chip at a time. Stacking one chip at a time is not first performed by main connection but by temporary connection with weak connection force. After provisional lamination up to the desired number of laminations, the final connection is made by applying strong pressure and heat from the top to the bottom of the chip. The laminated semiconductor device 24 obtained from this is connected to the mounting substrate 25 via the solder bumps 27.
　本接続まで終了した積層半導体装置２４を実装基板２５に接続した後、両面バンプ付き電極チップ２２同士の間、両面バンプ付き電極チップ２２とインターフェースチップ２３の間、インターフェースチップ２３と実装基板２５の間に、アンダーフィル剤２６を充填する方法を説明する。積層半導体装置２４の周辺からアンダーフィル剤２６を注入する。この際、故意に圧力や流速を与えることはなく、毛細管現象でアンダーフィル剤２６は各隙間に浸入していく。アンダーフィル剤２６が各隙間に全て埋まった後、アンダーフィル剤２６を熱処理により固化させることで、接続信頼性の高い積層半導体装置２４が得られた。 After connecting the laminated semiconductor device 24 that has been completely connected to the mounting substrate 25, between the electrode chips 22 with double-sided bumps, between the electrode chip 22 with double-sided bumps and the interface chip 23, and between the interface chip 23 and the mounting substrate 25. Next, a method of filling the underfill agent 26 will be described. An underfill agent 26 is injected from the periphery of the laminated semiconductor device 24. At this time, no pressure or flow velocity is intentionally applied, and the underfill agent 26 enters the gaps by capillary action. After the underfill agent 26 was completely filled in the gaps, the underfill agent 26 was solidified by heat treatment, whereby the stacked semiconductor device 24 with high connection reliability was obtained.
　これより得られた積層半導体装置をＡと表現する。 The stacked semiconductor device obtained from this is expressed as A.
　得られた前記積層半導体装置Ａを一定数使用して、温度サイクルを-25℃～125℃まで変えてデバイス動作を繰り返し、この温度サイクル時のバンプ接続信頼性試験を実施した。このバンプ接続信頼性試験の結果を100%とした場合の、下記比較例１および２および３に対する相対結果を表１に示す。 The device operation was repeated by using a certain number of the obtained stacked semiconductor devices A and changing the temperature cycle from -25 ° C. to 125 ° C., and a bump connection reliability test at this temperature cycle was performed. Table 1 shows the relative results with respect to Comparative Examples 1 and 2 and 3 below when the result of the bump connection reliability test is 100%.
（比較例１）
　実施の形態１において、電気導通のない電極を形成しない以外は、全て同様の操作を行って積層半導体装置を得た。これにより得られた半導体装置を半導体装置Ｂと表現する。 (Comparative Example 1)
In the first embodiment, the same operation was performed except that an electrode without electrical continuity was formed to obtain a laminated semiconductor device. The semiconductor device thus obtained is expressed as a semiconductor device B.
（比較例２）
　実施の形態１において電気導通のない電極を形成せず、さらに電気導通のある貫通電極以外の領域に金属バンプを形成しない以外は、全て同様の操作を行って半導体装置を得た。これにより得られた半導体装置を半導体装置Ｃと表現する。 (Comparative Example 2)
A semiconductor device was obtained in the same manner as in Embodiment 1 except that no electrode without electrical conduction was formed and metal bumps were not formed in regions other than through electrodes with electrical conduction. The semiconductor device thus obtained is expressed as a semiconductor device C.
（比較例３）
　実施の形態１において、デバイス面側に金属バンプを形成せず、さらに、半導体装置裏面側に金属バンプを形成しない以外は、全て同様の操作を行って半導体装置を得た。これにより得られた半導体装置を半導体装置Ｄと表現する。 (Comparative Example 3)
In the first embodiment, the same operation was performed except that the metal bumps were not formed on the device surface side and the metal bumps were not formed on the back surface side of the semiconductor device, thereby obtaining a semiconductor device. The semiconductor device thus obtained is expressed as a semiconductor device D.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
（実施の形態２）
　次に、via-Firstにおいて貫通電極を形成した積層半導体装置の実施例に関して説明する。デバイス領域と最初のメタル配線（Ｍ１）を形成する手前まで半導体装置を作製した後、層間膜上から電気導通のある貫通電極用の穴を開口し、この貫通電極穴の内壁にCVD酸化膜で側壁絶縁膜を堆積させる。この時の貫通電極深さは31μmである。シード層（Ta/Cu）をスパッタで形成し、Cuメッキにて貫通電極穴内にCuを埋め込んだ後、余分なCuをCMPにて除去および平坦化することで、貫通電極同士を電気的に独立させた。この後、メタル配線層を形成する。この際、この貫通電極と配線層は電気的に繋がるので、この貫通電極は電気導通のある貫通電極となる。 (Embodiment 2)
Next, an example of a laminated semiconductor device in which through electrodes are formed in via-first will be described. After manufacturing the semiconductor device to the point before the device region and the first metal wiring (M1) are formed, a hole for the through electrode having electrical continuity is opened from above the interlayer film, and a CVD oxide film is formed on the inner wall of the through electrode hole. A sidewall insulating film is deposited. The penetration electrode depth at this time is 31 μm. A seed layer (Ta / Cu) is formed by sputtering, Cu is embedded in the through-electrode hole by Cu plating, and then excess Cu is removed and planarized by CMP to electrically isolate the through-electrodes. I let you. Thereafter, a metal wiring layer is formed. At this time, since the through electrode and the wiring layer are electrically connected, the through electrode becomes a through electrode having electrical conduction.
　配線層の形成後、デバイス側の最上部に取り出し電極としてAl電極を形成した。このAl電極は、半導体装置面内に均一配置されており、それらの高さは皆同じである。回路設計により、予め内部回路との電気導通があるAl電極と電気導通がないAl電極の両方が形成されている。  After formation of the wiring layer, an Al electrode was formed as an extraction electrode on the uppermost part on the device side. The Al electrodes are uniformly arranged in the semiconductor device surface, and their heights are all the same. According to the circuit design, both an Al electrode having electrical continuity with the internal circuit and an Al electrode having no electrical continuity are formed in advance.
　続いて、Al電極上に金属バンプを形成する方法を説明する。シードとなる金属をスパッタで堆積させ、レジスト塗布後、Al電極領域のみフォトリソ工程で開口し、その後メッキにより開口部に金属を成長させる。この後、金属バンプ高さを揃えるために、金属バンプ上端を平坦化している。平坦化後、レジストを除去し、ウェットエッチングにてシード金属を取り除くことで、Al金属上にのみ金属バンプを形成した。 Subsequently, a method of forming metal bumps on the Al electrode will be described. A metal to be a seed is deposited by sputtering, and after applying a resist, only the Al electrode region is opened by a photolithography process, and then metal is grown in the opening by plating. Thereafter, in order to align the metal bump height, the upper end of the metal bump is flattened. After planarization, the resist was removed, and the seed metal was removed by wet etching to form metal bumps only on the Al metal.
　デバイス面側にバンプが形成されているので、バンプ面を保護テープで保護した状態で半導体装置を平均厚さ32μmになるまで薄厚化する。半導体装置の薄厚化は、一般的なバックグラインディング装置を用いて行ない、研磨面はストレスリリーフ処理を行っている。この段階では、貫通電極端は露出していない（図７(1)の18）。 Since bumps are formed on the device surface side, the semiconductor device is thinned to an average thickness of 32 μm with the bump surface protected by a protective tape. The semiconductor device is thinned by using a general back grinding apparatus, and the polished surface is subjected to stress relief processing. At this stage, the end of the through electrode is not exposed (18 in FIG. 7 (1)).
　次に、上記半導体装置の裏面から電気導通のない電極を形成する方法を説明する。薄厚化した半導体装置は、自重保持できないのでサポート基板に貼り付けてある。はじめに、半導体装置裏面に電気導通のない電極用の穴を形成するため、酸化膜を用いてハードマスクを形成する。200℃以下の低温で成膜可能なCVD酸化膜を用いた。 Next, a method for forming an electrode without electrical conduction from the back surface of the semiconductor device will be described. Since the thinned semiconductor device cannot hold its own weight, it is attached to the support substrate. First, a hard mask is formed using an oxide film in order to form a hole for an electrode having no electrical continuity on the back surface of the semiconductor device. A CVD oxide film that can be formed at a low temperature of 200 ° C. or lower was used.
　ハードマスク用のフォトリソ工程後、ドライエッチングにて電気導通のない電極穴用のハードマスク加工を行う。電気導通のない電極穴内部に側壁絶縁膜を堆積させた後、シード層（Ta/Cu）をスパッタで形成した。その後、電気導通のない電極穴をCuメッキにて埋め込み、余分なCuをCMPにて除去し平坦化した。 After the photolithography process for hard mask, hard mask processing for electrode holes without electrical conduction is performed by dry etching. After depositing a sidewall insulating film inside the electrode hole without electrical conduction, a seed layer (Ta / Cu) was formed by sputtering. After that, electrode holes without electrical continuity were filled with Cu plating, and excess Cu was removed by CMP to flatten it.
　電気導通のある貫通電極端を露出させるため、既に露出している電気導通のない電極ごと半導体装置裏面を薄厚化した。この薄厚化により、基板の平均厚さは30μmになった。 In order to expose the end of the through electrode with electrical continuity, the back surface of the semiconductor device was thinned together with the exposed electrode without electrical continuity. With this thinning, the average thickness of the substrate became 30 μm.
　その後、半導体装置裏面に保護膜としてCVD酸化膜を形成し、電気導通のある貫通電極端と電気導通のない電極端の両方を開口させるためのフォトリソ工程とドライエッチングを行った。両電極端を露出させた後、シード層（Ta/Cu）をスパッタで形成し、Cuメッキにより両電極端にCu成長させた後、余分なCuをCMPにて除去し平坦化した。 Thereafter, a CVD oxide film was formed as a protective film on the back surface of the semiconductor device, and a photolithography process and dry etching were performed to open both the through-electrode end having electrical continuity and the electrode end having no electrical continuity. After exposing both electrode ends, a seed layer (Ta / Cu) was formed by sputtering, and Cu was grown on both electrode ends by Cu plating. Then, excess Cu was removed by CMP and planarized.
　次に、裏面の電極端に金属バンプを形成する方法を説明する。デバイス側に形成した方法と同じ方法で作成する。シードとなる金属をスパッタで形成し、レジスト塗布後、貫通電極の領域のみをフォトリソ工程で開口し、その後メッキにより開口部に金属を成長させる。レジストを除去した後、ウェットエッチングにてシード金属を除去し、貫通電極端にのみ金属バンプを形成し、デバイス面側と半導体装置裏面側の両方にバンプが形成された積層半導体装置を得た。 Next, a method for forming metal bumps on the electrode ends on the back surface will be described. It is created by the same method as that formed on the device side. A metal to be a seed is formed by sputtering, and after applying a resist, only the region of the through electrode is opened by a photolithography process, and then the metal is grown in the opening by plating. After removing the resist, the seed metal was removed by wet etching, metal bumps were formed only at the end of the through electrode, and a laminated semiconductor device having bumps formed on both the device surface side and the semiconductor device back surface side was obtained.
　デバイス面側と半導体装置裏面側の両方にバンプが形成された積層半導体装置２２を、サポート基板から取り外し、ダイシングにて各チップに分離することで、両面バンプ付き電極チップ２２を得た（図１１）。 The laminated semiconductor device 22 having bumps formed on both the device surface side and the back surface side of the semiconductor device was removed from the support substrate and separated into each chip by dicing to obtain an electrode chip 22 with double-sided bumps (FIG. 11). ).
　チップに分離された両面バンプ付き電極チップ２２を積層する方法は、前述の通りである。 The method of laminating the electrode chip 22 with double-sided bumps separated into chips is as described above.
　これより得られた積層半導体装置をＥと表現する。 The multilayer semiconductor device obtained from this is expressed as E.
　得られた前記積層半導体装置Ｅを一定数使用して、温度サイクルを-25℃～125℃まで変えてデバイス動作を繰り返し、この温度サイクル時のバンプ接続信頼性試験を実施した。このバンプ接続信頼性試験の結果を100%とした場合の、下記比較例４および５および６に対する相対結果を表２に示す。 Using a certain number of the obtained stacked semiconductor devices E, the temperature cycle was changed from -25 ° C. to 125 ° C. and the device operation was repeated, and a bump connection reliability test at this temperature cycle was performed. Table 2 shows the relative results for the following Comparative Examples 4, 5 and 6 when the result of the bump connection reliability test is 100%.
（比較例４）
　実施の形態２において、電気導通のない電極を形成しない以外は、全て同様の操作を行って積層半導体装置を得た。これにより得られた半導体装置を半導体装置Ｆと表現する。 (Comparative Example 4)
In the second embodiment, a stacked semiconductor device was obtained by performing the same operation except that an electrode without electrical conduction was not formed. The semiconductor device thus obtained is expressed as a semiconductor device F.
（比較例５）
　実施の形態２において電気導通のない電極を形成せず、さらに電気導通のある貫通電極以外の領域に金属バンプを形成しない以外は、全て同様の操作を行って半導体装置を得た。これにより得られた半導体装置を半導体装置Ｇと表現する。 (Comparative Example 5)
A semiconductor device was obtained in the same manner as in Embodiment 2 except that no electrode without electrical conduction was formed and metal bumps were not formed in regions other than through electrodes with electrical conduction. The semiconductor device thus obtained is expressed as a semiconductor device G.
（比較例６）
　実施の形態２において、デバイス面側に金属バンプを形成せず、さらに、半導体装置裏面側に金属バンプを形成しない以外は、全て同様の操作を行って半導体装置を得た。これにより得られた半導体装置を半導体装置Ｈと表現する。 (Comparative Example 6)
In the second embodiment, the same operation was performed except that the metal bumps were not formed on the device surface side and the metal bumps were not formed on the back surface side of the semiconductor device to obtain a semiconductor device. The semiconductor device thus obtained is expressed as a semiconductor device H.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　電気導通のある貫通電極とは別に電気導通のない電極を形成することで、制御性よく信頼性の高い接続技術と熱伝導率の向上の両立が可能である。 ¡By forming an electrode without electrical continuity separately from the through electrode with electrical continuity, it is possible to achieve both controllable and reliable connection technology and improved thermal conductivity.
　この電極が形成された半導体装置同士を積層することで得られる積層半導体装置を製造する条件のもとでは、電極端に形成された金属パッドや金属バンプの高さが同じで、かつ面内に均一に存在するので、接続時に加えられる圧力により不均一な応力が発生しにくく、接続不良が低減できる。また、電極が均一に分布しているので基板の熱伝導率が高く、積層半導体装置から発生する熱を効率よく発散（冷却）できる。 Under the conditions for manufacturing a laminated semiconductor device obtained by laminating semiconductor devices having electrodes formed thereon, the metal pads and metal bumps formed at the electrode ends have the same height and are in-plane. Since it exists uniformly, non-uniform stress is unlikely to occur due to the pressure applied at the time of connection, and connection failure can be reduced. Further, since the electrodes are uniformly distributed, the thermal conductivity of the substrate is high, and the heat generated from the laminated semiconductor device can be efficiently dissipated (cooled).
　このことから、前記半導体装置を使用して得られた積層半導体装置は高い信頼性を示す。 For this reason, the stacked semiconductor device obtained using the semiconductor device exhibits high reliability.
１　基板
２　デバイス領域
３　プロテクト膜
４　取り出し電極（デバイス側）
５　電気導通のある貫通電極（断面）
６　貫通電極のある領域
７　貫通電極のない領域
８　デバイス側の金属パッドまたは金属バンプ
９　半導体装置裏面側の金属パッドまたは金属バンプ
１０　貫通電極ない領域に形成した金属パッドまたは金属バンプ
１１　電気導通のある貫通電極端（平面）
１２　電気導通のない電極端（平面）
１３　半導体装置
１４　配線層
１５　電気導通のある貫通電極穴
１６　電極内の側壁絶縁膜
１７　電極内の埋め込み電極
１８　貫通電極露出面
１９　電気導通のない電極穴
２０　電気導通のない電極（断面）
２１　ＣＶＤ酸化膜
２２　両面バンプ付き電極チップ
２３　インターフェースチップ
２４　積層半導体装置
２５　実装基板
２６　アンダーフィル剤
２７　ハンダバンプ 1 Substrate 2 Device area 3 Protective film 4 Extraction electrode (device side)
5 Electrically penetrating electrode (cross section)
6 region with through-electrode 7 region without through-electrode 8 metal pad or metal bump 9 on the device side metal pad or metal bump 10 on the back side of the semiconductor device 10 metal pad or metal bump 11 formed in the region without through-electrode Through electrode end (plane)
12 Electrode end without electrical continuity (plane)
DESCRIPTION OF SYMBOLS 13 Semiconductor device 14 Wiring layer 15 Through-electrode hole 16 with electric conduction Side wall insulating film 17 in electrode Embedded electrode 18 in electrode Through-electrode exposed surface 19 Electrode hole without electric conduction 20 Electrode without electric conduction (cross section)
21 CVD oxide film 22 Electrode chip with double-sided bump 23 Interface chip 24 Multilayer semiconductor device 25 Mounting substrate 26 Underfill agent 27 Solder bump

Claims (20)

  1. 　電気導通のある貫通電極と電気導通のない電極を備えた半導体装置を複数積層したことを特徴とする積層半導体装置。 A stacked semiconductor device comprising a plurality of stacked semiconductor devices each having a through electrode having electrical continuity and an electrode having no electrical continuity.
  2. 　請求項１に記載の積層半導体装置において、前記両電極の電極端に金属パッドまたは金属バンプを形成したことを特徴とする積層半導体装置。 2. The laminated semiconductor device according to claim 1, wherein metal pads or metal bumps are formed at the electrode ends of the two electrodes.
  3. 　請求項２に記載の積層半導体装置において、前記金属パッドまたは金属バンプをデバイス面側か半導体装置裏面側のいずれか一方に形成したことを特徴とする積層半導体装置。 3. The laminated semiconductor device according to claim 2, wherein the metal pad or the metal bump is formed on either the device surface side or the semiconductor device back side.
  4. 　請求項２に記載の積層半導体装置において、前記金属パッドまたは金属バンプをデバイス面側と半導体装置裏面側の両方に形成したことを特徴とする積層半導体装置。 3. The laminated semiconductor device according to claim 2, wherein the metal pads or metal bumps are formed on both the device surface side and the semiconductor device back side.
  5. 　請求項１に記載の積層半導体装置において、前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内に均一に配置したことを特徴とする積層半導体装置。 2. The stacked semiconductor device according to claim 1, wherein the through electrodes having electrical continuity and the electrodes having no electrical continuity are uniformly arranged in the semiconductor device.
  6. 　請求項５に記載の積層半導体装置において、前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内の少なくともデバイス領域に格子状に均一に配置したことを特徴とする積層半導体装置。 6. The stacked semiconductor device according to claim 5, wherein the through electrodes having electrical continuity and the electrodes having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device. .
  7. 　請求項２に記載の積層半導体装置において、前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内に均一に配置したことを特徴とする積層半導体装置。 3. The stacked semiconductor device according to claim 2, wherein the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in the semiconductor device.
  8. 　請求項７に記載の積層半導体装置において、前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内の少なくともデバイス領域に格子状に均一に配置したことを特徴とする積層半導体装置。 8. The stacked semiconductor device according to claim 7, wherein the through electrodes having electrical continuity and the electrodes having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device. .
  9. 　請求項３に記載の積層半導体装置において、前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内に均一に配置したことを特徴とする積層半導体装置。 4. The stacked semiconductor device according to claim 3, wherein the through electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in the semiconductor device.
  10. 　請求項９に記載の積層半導体装置において、前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内の少なくともデバイス領域に格子状に均一に配置したことを特徴とする積層半導体装置。 10. The stacked semiconductor device according to claim 9, wherein the through electrodes having electrical continuity and the electrodes having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device. .
  11. 　請求項４に記載の積層半導体装置において、前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内に均一に配置したことを特徴とする積層半導体装置。 5. The stacked semiconductor device according to claim 4, wherein the through-electrode having electrical continuity and the electrode having no electrical continuity are uniformly arranged in the semiconductor device.
  12. 　請求項１１に記載の積層半導体装置において、前記電気導通のある貫通電極と前記電気導通のない電極を前記半導体装置内の少なくともデバイス領域に格子状に均一に配置したことを特徴とする積層半導体装置。 12. The stacked semiconductor device according to claim 11, wherein the through electrodes having electrical continuity and the electrodes having no electrical continuity are uniformly arranged in a lattice shape at least in a device region in the semiconductor device. .
  13. 　(a)半導体基板のデバイス面側とは反対側の基板裏面を研磨する工程、
    　(b)前記基板裏面から電気導通のない電極穴を加工する工程、
    　(c)前記基板裏面から電気導通のある貫通電極穴を加工する工程
    　(d)前記両電極穴中に側壁絶縁膜を堆積、加工し、さらに電極材を埋め込んで電極を形成する工程、
    　(e)前記両電極端の平坦化を行い半導体装置を形成する工程、
    　(f)前記(a)～(e)の工程で得られた半導体装置を複数積層する工程を有することを特徴とする積層半導体装置の製造方法。     (a) polishing the back surface of the substrate opposite to the device surface side of the semiconductor substrate;
    (b) a step of machining an electrode hole without electrical conduction from the back surface of the substrate;
    (c) a step of processing a through-electrode hole having electrical continuity from the back surface of the substrate (d) a step of depositing and processing a sidewall insulating film in both the electrode holes, and further embedding an electrode material to form an electrode;
    (e) a step of flattening both electrode ends to form a semiconductor device;
    (f) A method of manufacturing a laminated semiconductor device, comprising a step of laminating a plurality of semiconductor devices obtained in the steps (a) to (e).
  14. 　請求項１３に記載の積層半導体装置の製造方法において、
    　(g)前記半導体基板上のデバイス面側に金属パッドまたは金属バンプを形成する工程と、
    　(h)前記半導体基板上の前記貫通電極側に金属パッドまたは金属バンプを形成する工程から選ばれる少なくとも一つの工程をさらに有することを特徴とする積層半導体装置の製造方法。     In the manufacturing method of the laminated semiconductor device according to claim 13,
    (g) forming a metal pad or metal bump on the device surface side of the semiconductor substrate;
    (h) The method for manufacturing a laminated semiconductor device, further comprising at least one step selected from a step of forming a metal pad or a metal bump on the through electrode side on the semiconductor substrate.
  15. 　請求項１３に記載の積層半導体装置の製造方法において、
    　前記側壁絶縁膜の加工は、電極内に堆積させた絶縁膜の穴底絶縁膜を除去すると同時にデバイス面側の電極面まで加工することを特徴とする積層半導体装置の製造方法。     In the manufacturing method of the laminated semiconductor device according to claim 13,
    The method for manufacturing a laminated semiconductor device is characterized in that the side wall insulating film is processed to the electrode surface on the device surface side simultaneously with removal of the hole bottom insulating film of the insulating film deposited in the electrode.
  16. 　(a)半導体基板のデバイス面側とは反対側の基板裏面を研磨する工程、
    　(i)前記基板裏面にマスク材を堆積させる工程、
    　(j)電気導通のない電極穴を加工するためのマスクを作成し、加工する工程、
    　(k)電気導通のある貫通電極穴を加工するためのマスクを作成し、加工する工程、
    　(d)前記両電極穴中に側壁絶縁膜を堆積、加工し、さらに電極材を埋め込んで電極を形成する工程、
    　(e)前記両電極端の平坦化を行い半導体装置を形成する工程、
    　(f)前記(a)～(e)の工程で得られた半導体装置を複数積層する工程を有することを特徴とする積層半導体装置の製造方法。     (a) polishing the back surface of the substrate opposite to the device surface side of the semiconductor substrate;
    (i) a step of depositing a mask material on the back surface of the substrate;
    (j) creating and processing a mask for processing an electrode hole without electrical conduction;
    (k) creating and processing a mask for processing a through-electrode hole with electrical continuity;
    (d) depositing and processing a sidewall insulating film in both the electrode holes, further embedding an electrode material to form an electrode,
    (e) a step of flattening both electrode ends to form a semiconductor device;
    (f) A method of manufacturing a laminated semiconductor device, comprising a step of laminating a plurality of semiconductor devices obtained in the steps (a) to (e).
  17. 　請求項１６に記載の積層半導体装置の製造方法において、
    　(g)前記半導体基板上のデバイス面側に金属パッドまたは金属バンプを形成する工程と、
    　(h)前記半導体基板上の前記貫通電極側に金属パッドまたは金属バンプを形成する工程から選ばれる少なくとも一つの工程をさらに有することを特徴とする積層半導体装置の製造方法。     In the manufacturing method of the laminated semiconductor device according to claim 16,
    (g) forming a metal pad or metal bump on the device surface side of the semiconductor substrate;
    (h) The method for manufacturing a laminated semiconductor device, further comprising at least one step selected from a step of forming a metal pad or a metal bump on the through electrode side on the semiconductor substrate.
  18. 　請求項１６に記載の積層半導体装置の製造方法において、前記側壁絶縁膜の加工は、電極内に堆積させた絶縁膜の穴底絶縁膜を除去すると同時にデバイス面側の電極面まで加工することを特徴とする積層半導体装置の製造方法。 17. The method of manufacturing a laminated semiconductor device according to claim 16, wherein the processing of the sidewall insulating film includes processing to the electrode surface on the device surface side simultaneously with removing the hole bottom insulating film of the insulating film deposited in the electrode. A method for manufacturing a laminated semiconductor device.
  19. 　(l)半導体基板の一方の面に電極材を埋め込んで電気導通のある貫通電極を形成する工程、
    　(m)半導体基板のもう一方の面を研磨して電気導通のある貫通電極を露出する工程、
    　(b’)前記露出面を保護しながら前記露出面と同じ方向の面から電気導通のない電極穴を加工する工程、
    　(d’)前記電気導通のない電極穴中に電極材を埋め込んで電極を形成する工程、
    　(e)前記両電極端の平坦化を行い半導体装置を形成する工程、
    　(f’)前記(l)～(e)の工程で得られた半導体装置を複数積層する工程を有することを特徴とする積層半導体装置の製造方法。     (l) a step of forming an electrically conductive through electrode by embedding an electrode material on one surface of a semiconductor substrate;
    (m) a step of polishing the other surface of the semiconductor substrate to expose a conductive through electrode,
    (b ′) a step of machining an electrode hole without electrical conduction from a surface in the same direction as the exposed surface while protecting the exposed surface;
    (d ′) a step of forming an electrode by embedding an electrode material in the electrode hole without electrical conduction;
    (e) a step of flattening both electrode ends to form a semiconductor device;
    (f ′) A method for manufacturing a stacked semiconductor device, comprising a step of stacking a plurality of semiconductor devices obtained in the steps (l) to (e).
  20. 　請求項１９に記載の積層半導体装置の製造方法において、
    　(g)前記半導体基板上のデバイス面側に金属パッドまたは金属バンプを形成する工程と、
    　(h)前記半導体基板上の前記電極側に金属パッドまたは金属バンプを形成する工程から選ばれる少なくとも一つの工程をさらに有することを特徴とする積層半導体装置の製造方法。     In the manufacturing method of the laminated semiconductor device according to claim 19,
    (g) forming a metal pad or metal bump on the device surface side of the semiconductor substrate;
    (h) The method for manufacturing a laminated semiconductor device, further comprising at least one step selected from a step of forming a metal pad or a metal bump on the electrode side on the semiconductor substrate.
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