TW201640976A - Stacked electronic device and method for fabricating the same - Google Patents

Stacked electronic device and method for fabricating the same Download PDF

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Publication number
TW201640976A
TW201640976A TW104114669A TW104114669A TW201640976A TW 201640976 A TW201640976 A TW 201640976A TW 104114669 A TW104114669 A TW 104114669A TW 104114669 A TW104114669 A TW 104114669A TW 201640976 A TW201640976 A TW 201640976A
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Taiwan
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substrate
insulating layer
electronic device
stacked electronic
layer
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TW104114669A
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Chinese (zh)
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焦佑鈞
詹東義
林晨曦
何家驊
詹孟璋
周信宏
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華邦電子股份有限公司
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Priority to TW104114669A priority Critical patent/TW201640976A/en
Publication of TW201640976A publication Critical patent/TW201640976A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

The disclosure provides a method for fabricating a stacked electronic device. A first three-dimensional (3D) printing is performed to form a first insulating layer and a plurality of first redistribution layers (RDLs) on a first substrate. A second 3D printing is performed to form a second substrate and a plurality of through substrate vias (TSVs) on the first insulating layer, wherein the plurality of TSVs is electrically connected to the first RDLs. A third 3D printing is performed to form a second insulating layer and a plurality of second RDLs on the second substrate, wherein the plurality of second RDLs is electrically connected to the plurality of TSVs. A plurality of contacts of a third substrate is bonded to the second RDLs, such that the third substrate is mounted onto the second insulating layer. The disclosure also provides a stacked electronic device formed by such a method.

Description

堆疊電子裝置及其製造方法 Stacked electronic device and method of manufacturing same

本發明係關於一種半導體技術,且特別是關於一種利用三維列印技術製造堆疊電子裝置的方法。 This invention relates to a semiconductor technology, and more particularly to a method of fabricating a stacked electronic device using three dimensional printing techniques.

由於半導體技術的向上發展,因此積體電路的集積度(integration)或是電子元件(例如,電晶體、二極體、電阻、電容等等)的密度得以不斷提升。為了提升積體電路的集積度,目前已開始發展出三維積體電路(3DIC)。一般來說,三維積體電路可透過基底通孔電極(through substrate via,TSV)作為電性連接路徑,以實現晶圓或晶片堆疊結構,進而達到提升集積度的目的。 Due to the advancement of semiconductor technology, the integration of integrated circuits or the density of electronic components (eg, transistors, diodes, resistors, capacitors, etc.) is increasing. In order to increase the integration of integrated circuits, three-dimensional integrated circuits (3DIC) have been developed. Generally, the three-dimensional integrated circuit can be used as an electrical connection path through a through-substrate via (TSV) to realize a wafer or wafer stack structure, thereby achieving the purpose of increasing the accumulation degree.

在三維積體電路製程中,晶片與基底(例如,晶片、晶圓或印刷電路板)或晶圓與基底彼此接合,且在每一晶片/晶圓與基底上的接點之間形成電性連接。再者,一般的基底通孔電極的製造是以乾蝕刻或雷射方式在基底(例如,晶圓或晶片)內形成鑽孔(via hole)並以導電材料填入鑽孔內。接著,將基底與其他晶圓/晶片以及承載基底進行堆疊並以化學機械研磨(CMP)進行基底薄化製程,使上述鑽孔變成通孔(through hole)並露出填入的導電材料而形成基底通孔電極。最後將承載基底移除而構成三維堆疊電子裝置。相較於傳統利 用打線接合的電子裝置而言,具有基底通孔電極的三維堆疊電子裝置可縮短內部電性連接路徑,進而增加裝置的傳輸速度、降低雜訊及提升裝置效能。 In a three-dimensional integrated circuit process, a wafer and a substrate (eg, a wafer, a wafer, or a printed circuit board) or a wafer and a substrate are bonded to each other, and electrical properties are formed between each wafer/wafer and a contact on the substrate. connection. Moreover, a typical via via electrode is fabricated by dry etching or laser forming a via hole in a substrate (eg, a wafer or wafer) and filled with a conductive material into the bore. Next, the substrate is stacked with other wafers/wafers and carrier substrates, and a substrate thinning process is performed by chemical mechanical polishing (CMP) to make the holes become through holes and expose the filled conductive material to form a substrate. Through hole electrode. Finally, the carrier substrate is removed to form a three-dimensional stacked electronic device. Compared to traditional In the case of wire-bonded electronic devices, a three-dimensional stacked electronic device having a substrate via electrode can shorten the internal electrical connection path, thereby increasing the transmission speed of the device, reducing noise, and improving device performance.

然而,如上所述,基底通孔電極的製造包括鑽孔製作、鑽孔充填導電材料、基底薄化以及移除承載基底等步驟,因而無法有效縮短製造時間、簡化製程步驟及降低製造成本。因此,有必要尋求一種堆疊電子裝置之製造方法,其可改善上述的問題。 However, as described above, the fabrication of the via via electrodes includes the steps of drilling, drilling the conductive material, thinning the substrate, and removing the carrier substrate, thereby failing to effectively shorten the manufacturing time, simplify the process steps, and reduce the manufacturing cost. Therefore, it is necessary to find a manufacturing method of a stacked electronic device which can improve the above problems.

本發明一實施例提供一種堆疊電子裝置之製造方法,包括:提供一第一基底;進行一第一三維列印,以於第一基底上形成一第一絕緣層以及複數第一重佈線層,其中第一重佈線層嵌入於第一絕緣層內;進行一第二三維列印,以於第一絕緣層上形成一第二基底以及複數基底通孔電極,其中基底通孔電極貫穿第二基底且電性連接至第一重佈線層;進行一第三三維列印,以於第二基底上形成一第二絕緣層以及複數第二重佈線層,其中第二重佈線層嵌入於第二絕緣層內且電性連接至基底通孔電極;以及將一第三基底的複數接點接合至第二重佈線層,使第三基底裝設於第二絕緣層上。 An embodiment of the present invention provides a method of manufacturing a stacked electronic device, including: providing a first substrate; performing a first three-dimensional printing to form a first insulating layer and a plurality of first redistributing layers on the first substrate, The first redistribution layer is embedded in the first insulating layer; performing a second three-dimensional printing to form a second substrate and a plurality of substrate via electrodes on the first insulating layer, wherein the substrate via electrodes penetrate the second substrate And electrically connecting to the first redistribution layer; performing a third three-dimensional printing to form a second insulating layer and a plurality of second redistribution layers on the second substrate, wherein the second redistribution layer is embedded in the second insulation And electrically connecting to the substrate via electrode; and bonding the plurality of contacts of the third substrate to the second redistribution layer to mount the third substrate on the second insulation layer.

本發明另一實施例提供一種堆疊電子裝置,包括:一第一基底;一第一絕緣層以及複數第一重佈線層,設置於第一基底上,其中第一重佈線層嵌入於第一絕緣層內;一第二基底以及複數基底通孔電極,設置於第一絕緣層上,其中基底通孔電極貫穿第二基底且電性連接至第一重佈線層;一第二 絕緣層以及複數第二重佈線層,設置於第二基底上,其中第二重佈線層嵌入於第二絕緣層內且電性連接至基底通孔電極;以及一第三基底,裝設於第二絕緣層上,其中第三基底具有複數接點接合至第二重佈線層。第一絕緣層、第一重佈線層、第二基底、基底通孔電極、第二絕緣層及第二重佈線層係透過三維列印所使用的材料所構成。 Another embodiment of the present invention provides a stacked electronic device including: a first substrate; a first insulating layer and a plurality of first redistribution layers disposed on the first substrate, wherein the first redistribution layer is embedded in the first insulation a second substrate and a plurality of substrate via electrodes disposed on the first insulating layer, wherein the substrate via electrodes penetrate the second substrate and are electrically connected to the first redistribution layer; The insulating layer and the plurality of second redistribution layers are disposed on the second substrate, wherein the second redistribution layer is embedded in the second insulating layer and electrically connected to the substrate via electrode; and a third substrate is mounted on the On the two insulating layers, wherein the third substrate has a plurality of contacts bonded to the second redistribution layer. The first insulating layer, the first redistribution layer, the second substrate, the base via electrode, the second insulating layer, and the second redistribution layer are formed by a material used for three-dimensional printing.

10‧‧‧三維列印機 10‧‧‧3D printer

10a‧‧‧第一列印噴頭 10a‧‧‧First print head

10b‧‧‧第二列印噴頭 10b‧‧‧Second print head

20‧‧‧第一三維列印 20‧‧‧ first three-dimensional printing

20’‧‧‧第二三維列印 20’‧‧‧Second 3D printing

20”‧‧‧第三三維列印 20"‧‧‧ Third 3D printing

100‧‧‧第一基底 100‧‧‧ first base

102‧‧‧第一絕緣層 102‧‧‧First insulation

104‧‧‧第一重佈線層 104‧‧‧First redistribution layer

106‧‧‧第二基底 106‧‧‧Second substrate

108‧‧‧基底通孔電極 108‧‧‧Based through hole electrode

110‧‧‧第二絕緣層 110‧‧‧Second insulation

112‧‧‧第二重佈線層 112‧‧‧Second red wiring layer

200‧‧‧堆疊電子裝置 200‧‧‧Stacked electronic devices

300‧‧‧方法 300‧‧‧ method

301、303、305、307、309‧‧‧步驟 301, 303, 305, 307, 309‧ ‧ steps

第1A至1D圖係繪示出根據本發明一實施例之堆疊電子裝置之製造方法剖面示意圖。 1A to 1D are cross-sectional views showing a method of manufacturing a stacked electronic device according to an embodiment of the present invention.

第2圖係繪示出根據本發明一實施例之堆疊電子裝置之製造方法流程圖。 2 is a flow chart showing a method of fabricating a stacked electronic device in accordance with an embodiment of the present invention.

以下說明本發明實施例之堆疊電子裝置之製造方法。然而,可輕易了解本發明所提供的實施例僅用於說明以特定方法製作及使用本發明,並非用以侷限本發明的範圍。 Hereinafter, a method of manufacturing a stacked electronic device according to an embodiment of the present invention will be described. However, the present invention is to be understood as being limited to the details of the present invention.

請參照第1D圖,其繪示出根據本發明一實施例之堆疊電子裝置剖面示意圖。堆疊電子裝置200包括:一第一基底100、一第一絕緣層102、複數第一重佈線層(redistribution layer,RDL)104、一第二基底106、複數基底通孔電極108、一第二絕緣層110、複數第二重佈線層112以及一第三基底130。在一實施例中,第一基底100可為一印刷電路板、一晶圓、一晶片或其組合。 Please refer to FIG. 1D, which is a cross-sectional view of a stacked electronic device according to an embodiment of the invention. The stacked electronic device 200 includes a first substrate 100, a first insulating layer 102, a plurality of first redistribution layers (RDLs) 104, a second substrate 106, a plurality of substrate via electrodes 108, and a second insulation. The layer 110, the plurality of second redistribution layers 112, and a third substrate 130. In an embodiment, the first substrate 100 can be a printed circuit board, a wafer, a wafer, or a combination thereof.

第一絕緣層102以及第一重佈線層104設置於第一 基底100上,其中第一重佈線層104嵌入於第一絕緣層102內且電性連接至第一基底100的接點(未繪示)。第一基底100的接點可包括接墊、焊料凸塊、導電柱或其組合。此處為簡化圖式,僅以二個單層導電結構表示第一重佈線層104。然而,需注意的是第一重佈線層104可為單層或多層導電結構,且第一重佈線層104的數量可取決於設計需求而不局限於第1D圖所示。 The first insulating layer 102 and the first redistribution layer 104 are disposed at the first On the substrate 100, the first redistribution layer 104 is embedded in the first insulating layer 102 and electrically connected to the contacts (not shown) of the first substrate 100. The contacts of the first substrate 100 may include pads, solder bumps, conductive pillars, or a combination thereof. Here, for the simplified drawing, the first redistribution layer 104 is represented by only two single-layer conductive structures. However, it should be noted that the first redistribution layer 104 may be a single layer or a plurality of layers of conductive structures, and the number of the first redistribution layers 104 may be limited to the design requirements and is not limited to the 1D diagram.

在本實施例中,第一絕緣層102以及第一重佈線層104係透過三維列印所使用的材料所構成。舉例來說,第一絕緣層102包括適用於三維列印技術的陶瓷材料、高分子材料、樹脂材料或介電材料。再者,第一重佈線層104包括適用於三維列印技術的導電金屬,例如鋁、銅、金、無鉛銲錫或其合金或其他金屬合金。 In the present embodiment, the first insulating layer 102 and the first redistribution layer 104 are formed by a material used for three-dimensional printing. For example, the first insulating layer 102 includes a ceramic material, a polymer material, a resin material, or a dielectric material suitable for three-dimensional printing technology. Furthermore, the first redistribution layer 104 comprises a conductive metal suitable for three-dimensional printing techniques, such as aluminum, copper, gold, lead-free solder or alloys thereof or other metal alloys.

第二基底106以及基底通孔電極108設置於第一絕緣層104上,其中基底通孔電極108貫穿第二基底106且電性連接至第一重佈線層104。此處為簡化圖式,僅繪示出二個基底通孔電極108。然而,需注意的是基底通孔電極108的數量可取決於設計需求而不局限於第1D圖所示。 The second substrate 106 and the substrate via electrode 108 are disposed on the first insulating layer 104 , wherein the substrate via electrode 108 penetrates the second substrate 106 and is electrically connected to the first redistribution layer 104 . Here, for the simplified drawing, only two base via electrodes 108 are shown. However, it should be noted that the number of substrate via electrodes 108 may depend on design requirements and is not limited to that shown in FIG. 1D.

在本實施例中,第二基底106內不具有任何主動或被動元件。再者,第二基底106以及基底通孔電極108係透過三維列印所使用的材料所構成。舉例來說,第二基底106包括適用於三維列印技術的模塑成型(molding compound)材料、陶瓷材料、高分子材料、樹脂材料或介電材料。再者,基底通孔電極108包括適用於三維列印技術的導電金屬,例如鎢、鋁、銅、金、無鉛銲錫或其合金或其他金屬合金。在其他實施例中, 第二基底106可包括半導體材料,例如矽或矽鍺。在此情形中,堆疊電子裝置200更包括一絕緣間隔層(spacer),以電性隔離第二基底106與基底通孔電極108。絕緣間隔層包括適用於三維列印技術的陶瓷材料、高分子材料、樹脂材料或介電材料。 In this embodiment, there are no active or passive components within the second substrate 106. Furthermore, the second substrate 106 and the substrate via electrode 108 are formed by a material used for three-dimensional printing. For example, the second substrate 106 includes a molding compound material, a ceramic material, a polymer material, a resin material, or a dielectric material suitable for three-dimensional printing technology. Further, the substrate via electrode 108 includes a conductive metal suitable for three-dimensional printing techniques, such as tungsten, aluminum, copper, gold, lead-free solder or alloys thereof, or other metal alloys. In other embodiments, The second substrate 106 can comprise a semiconductor material such as tantalum or niobium. In this case, the stacked electronic device 200 further includes an insulating spacer to electrically isolate the second substrate 106 from the substrate via electrode 108. The insulating spacer layer comprises a ceramic material, a polymer material, a resin material or a dielectric material suitable for three-dimensional printing technology.

第二絕緣層110以及第二重佈線層112設置於第二基底106上,其中第二重佈線層112嵌入於第二絕緣層110內且電性連接至基底通孔電極108。此處為簡化圖式,僅以二個單層導電結構表示第二重佈線層112。然而,需注意的是第二重佈線層112可為單層或多層導電結構,且第二重佈線層112的數量可取決於設計需求而不局限於第1D圖所示。 The second insulating layer 110 and the second redistribution layer 112 are disposed on the second substrate 106 , wherein the second redistribution layer 112 is embedded in the second insulating layer 110 and electrically connected to the substrate via electrode 108 . Here, to simplify the drawing, the second redistribution layer 112 is represented by only two single-layer conductive structures. However, it should be noted that the second redistribution layer 112 may be a single layer or a plurality of layers of conductive structures, and the number of the second redistribution layers 112 may be limited to the design requirements and is not limited to the 1D diagram.

在本實施例中,第二絕緣層110以及第二重佈線層112係透過三維列印所使用的材料所構成。舉例來說,第二絕緣層110包括適用於三維列印技術的陶瓷材料、高分子材料、樹脂材料或介電材料。再者,第二重佈線層112包括適用於三維列印技術的導電金屬,例如鋁、銅、金、無鉛銲錫或其合金或其他金屬合金。 In the present embodiment, the second insulating layer 110 and the second redistribution layer 112 are formed by a material used for three-dimensional printing. For example, the second insulating layer 110 includes a ceramic material, a polymer material, a resin material, or a dielectric material suitable for three-dimensional printing technology. Furthermore, the second redistribution layer 112 comprises a conductive metal suitable for three-dimensional printing techniques, such as aluminum, copper, gold, lead-free solder or alloys thereof or other metal alloys.

第三基底130裝設於第二絕緣層110上。在本實施例中,第三基底130可為一晶圓、一晶片或其組合。再者,第三基底130具有複數接點120接合至第二重佈線層112。接點120可包括接墊、焊料凸塊、導電柱或其組合,且此處係以焊料凸塊作為範例。 The third substrate 130 is mounted on the second insulating layer 110. In this embodiment, the third substrate 130 can be a wafer, a wafer, or a combination thereof. Furthermore, the third substrate 130 has a plurality of contacts 120 bonded to the second redistribution layer 112. Contact 120 can include pads, solder bumps, conductive posts, or a combination thereof, and solder bumps are exemplified herein.

接下來,請參照第1A至1D圖及第2圖,其中第1A至1D圖係繪示出根據本發明一實施例之堆疊電子裝置之製造方法剖面示意圖,且第2圖係繪示出根據本發明一實施例之堆 疊電子裝置之製造方法300流程圖。在本實施例中,方法300開始於步驟301,提供一第一基底100,如第1A圖所示。在一實施例中,第一基底100可為一印刷電路板、一晶圓、一晶片或其組合。第一基底100可具有複數接點(未繪示),例如接墊、焊料凸塊、導電柱或其組合。 1A to 1D and FIG. 2, wherein FIGS. 1A to 1D are schematic cross-sectional views showing a method of manufacturing a stacked electronic device according to an embodiment of the present invention, and FIG. 2 is a diagram showing Heap of an embodiment of the invention A flow chart of a method 300 of manufacturing an electronic device. In the present embodiment, the method 300 begins in step 301 by providing a first substrate 100 as shown in FIG. 1A. In an embodiment, the first substrate 100 can be a printed circuit board, a wafer, a wafer, or a combination thereof. The first substrate 100 can have a plurality of contacts (not shown), such as pads, solder bumps, conductive posts, or a combination thereof.

接著,仍請參照第1A及2圖,進行步驟303,透過一三維列印機10進行一第一三維列印20,以於第一基底100上形成一第一絕緣層102以及複數第一重佈線層104,其中第一重佈線層104嵌入於第一絕緣層102內,且電性連接至第一基底100的接點(未繪示)。在本實施例中,三維列印機10可具有多重列印噴頭,以在進行第一三維列印20之後,可同時形成第一絕緣層102以及第一重佈線層104。舉例來說,在進行第一三維列印20期間,三維列印機10沿著平行於第一基底100的方向來回移動,利用第一列印噴頭10a來形成第一絕緣層102,而利用第二列印噴頭10b來形成第一重佈線層104。在本實施例中,第一絕緣層102包括陶瓷材料、高分子材料、樹脂材料或介電材料。再者,第一重佈線層104包括導電金屬,例如鋁、銅、金或其合金或其他金屬合金。 Then, referring to FIGS. 1A and 2, step 303 is performed to perform a first three-dimensional printing 20 through a three-dimensional printer 10 to form a first insulating layer 102 and a plurality of first weights on the first substrate 100. The wiring layer 104 is embedded in the first insulating layer 102 and electrically connected to the contacts (not shown) of the first substrate 100. In the present embodiment, the three-dimensional printer 10 may have multiple print heads to form the first insulating layer 102 and the first redistribution layer 104 simultaneously after the first three-dimensional printing 20 is performed. For example, during the first three-dimensional printing 20, the three-dimensional printer 10 moves back and forth along a direction parallel to the first substrate 100, and the first insulating layer 102 is formed by the first printing head 10a, and the first insulating layer 102 is used. The print head 10b is printed in two to form the first redistribution layer 104. In the present embodiment, the first insulating layer 102 includes a ceramic material, a polymer material, a resin material, or a dielectric material. Further, the first redistribution layer 104 includes a conductive metal such as aluminum, copper, gold or an alloy thereof or other metal alloy.

接著,請參照第1B及2圖,進行步驟305,透過三維列印機10進行相似於第一三維列印20的一第二三維列印20’,以於第一絕緣層102上形成一第二基底106以及複數基底通孔電極108,其中基底通孔電極108貫穿第二基底106且電性連接至第一重佈線層104。在本實施例中,在進行第二三維列印20’之後,可同時形成第二基底106以及基底通孔電極108。 舉例來說,在進行第二三維列印20’期間,三維列印機10利用第一列印噴頭10a來形成第二基底106,而利用第二列印噴頭10b來形成基底通孔電極108。在本實施例中,第二基底106包括模塑成型材料、陶瓷材料、高分子材料、樹脂材料或介電材料。再者,基底通孔電極108包括導電金屬,例如鎢、鋁、銅、金、無鉛銲錫或其合金或其他金屬合金。在本實施例中,可透過調整第二三維列印20’的時間,使形成的第二基底106具有所需的厚度。再者,形成的基底通孔電極108因貫穿第二基底106而露出於其表面。因此,無須再藉由任何研磨製程(例如,CMP)來調整第二基底106的厚度來形成基底通孔電極108。 Next, referring to FIGS. 1B and 2, step 305 is performed to perform a second three-dimensional printing 20' similar to the first three-dimensional printing 20 through the three-dimensional printing machine 10 to form a first insulating layer 102. The second substrate 106 and the plurality of substrate via electrodes 108, wherein the substrate via electrodes 108 penetrate the second substrate 106 and are electrically connected to the first redistribution layer 104. In the present embodiment, after the second three-dimensional printing 20' is performed, the second substrate 106 and the substrate via electrode 108 can be simultaneously formed. For example, during the second three-dimensional printing 20', the three-dimensional printer 10 utilizes the first print head 10a to form the second substrate 106, and the second print head 10b forms the base via electrode 108. In the present embodiment, the second substrate 106 includes a molding material, a ceramic material, a polymer material, a resin material, or a dielectric material. Furthermore, the via via electrode 108 comprises a conductive metal such as tungsten, aluminum, copper, gold, lead-free solder or alloys thereof or other metal alloys. In the present embodiment, the formed second substrate 106 can have a desired thickness by adjusting the time of the second three-dimensional printing 20'. Furthermore, the formed via via electrode 108 is exposed on the surface thereof through the second substrate 106. Therefore, the substrate via electrode 108 is formed without adjusting the thickness of the second substrate 106 by any polishing process (for example, CMP).

在其他實施例中,第二基底106可包括適用於三維列印技術的半導體材料,例如矽或矽鍺。在此情形中,三維列印機10可包括至少三個列印噴頭,且第二三維列印20’更包括形成一絕緣間隔層,以電性隔離第二基底106與基底通孔電極108。絕緣間隔層包括陶瓷材料、高分子材料、樹脂材料或介電材料。 In other embodiments, the second substrate 106 can comprise a semiconductor material suitable for three-dimensional printing techniques, such as tantalum or niobium. In this case, the three-dimensional printer 10 can include at least three printing heads, and the second three-dimensional printing 20' further includes forming an insulating spacer to electrically isolate the second substrate 106 from the substrate via electrodes 108. The insulating spacer layer includes a ceramic material, a polymer material, a resin material, or a dielectric material.

接著,請參照第1C及2圖,進行步驟307,透過三維列印機10進行相似於第一三維列印20的一第三三維列印20”,以於第二基底106上形成一第二絕緣層110以及複數第二重佈線層112,其中第二重佈線層112嵌入於第二絕緣層110內且電性連接至基底通孔電極108。在本實施例中,在進行第三三維列印20”之後,可同時形成第二絕緣層110以及第二重佈線層112。舉例來說,在進行第三三維列印20”期間,三維列印機10利用第一列印噴頭10a來形成第二絕緣層110,而利用第二列 印噴頭10b來形成第二重佈線層112。在本實施例中,第二絕緣層110可包括相同或不同於第一絕緣材料102的材料。再者,第二重佈線層112可包括相同或不同於第一重佈線層104的材料。 Next, referring to FIGS. 1C and 2, step 307 is performed to perform a third three-dimensional printing 20" similar to the first three-dimensional printing 20 through the three-dimensional printing machine 10 to form a second on the second substrate 106. The insulating layer 110 and the plurality of second redistribution layers 112, wherein the second redistribution layer 112 is embedded in the second insulating layer 110 and electrically connected to the substrate via electrode 108. In this embodiment, the third three-dimensional column is performed. After the stamp 20", the second insulating layer 110 and the second redistribution layer 112 may be simultaneously formed. For example, during the third three-dimensional printing 20", the three-dimensional printer 10 uses the first printing head 10a to form the second insulating layer 110, and utilizes the second column. The head 10b is printed to form the second redistribution layer 112. In the present embodiment, the second insulating layer 110 may include the same or different material than the first insulating material 102. Furthermore, the second redistribution layer 112 may include the same or different material than the first redistribution layer 104.

接著,請參照第1D及2圖,進行步驟309,將一第三基底130的複數接點120接合至第二重佈線層112,使第三基底130裝設於第二絕緣層110上。在本實施例中,第三基底130可為一晶圓、一晶片或其組合。再者,接點120可包括接墊、焊料凸塊、導電柱或其組合。舉例來說,第三基底130為一晶片且接點120為焊料凸塊。再者,透過覆晶(flip chip)技術,將接點120接合至第二重佈線層112。 Next, referring to FIGS. 1D and 2, step 309 is performed to bond the plurality of contacts 120 of the third substrate 130 to the second redistribution layer 112, and the third substrate 130 is mounted on the second insulating layer 110. In this embodiment, the third substrate 130 can be a wafer, a wafer, or a combination thereof. Further, the contacts 120 can include pads, solder bumps, conductive posts, or a combination thereof. For example, the third substrate 130 is a wafer and the contacts 120 are solder bumps. Further, the contact 120 is bonded to the second redistribution layer 112 by a flip chip technique.

根據上述實施例,由於第一絕緣層102及第一重佈線層104、第二基底106及基底通孔電極108以及第二絕緣層110及第二重佈線層112係依序透過三維列印製作而成,因此可有效縮短堆疊電子裝置的製造時間。另外,利用三維列印製作基底通孔電極可排除因深寬比所引起的填洞困難度(gap-filling difficulty),因而獲得高可靠度的基底通孔電極。再者,相較於傳統的基底通孔電極的製造,利用三維列印製作基底通孔電極無須額外進行鑽孔製作、鑽孔充填導電材料、基底薄化以及移除承載基底等步驟,因此可有效簡化製程步驟及降低製造成本,同時排除上述額外步驟所引起的技術問題。 According to the above embodiment, the first insulating layer 102 and the first redistribution layer 104, the second substrate 106 and the via via electrodes 108, and the second insulating layer 110 and the second redistribution layer 112 are sequentially printed through three-dimensional printing. Therefore, the manufacturing time of the stacked electronic device can be effectively shortened. In addition, the use of three-dimensional printing to fabricate the via-hole electrode eliminates the gap-filling difficulty caused by the aspect ratio, thereby obtaining a highly reliable substrate via electrode. Furthermore, compared with the conventional substrate via electrode fabrication, the use of three-dimensional printing to form the substrate via electrode does not require additional steps of drilling, drilling the conductive material, thinning the substrate, and removing the carrier substrate. It effectively simplifies the process steps and reduces manufacturing costs while eliminating the technical problems caused by the above additional steps.

雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

300‧‧‧方法 300‧‧‧ method

301、303、305、307、309‧‧‧步驟 301, 303, 305, 307, 309‧ ‧ steps

Claims (14)

一種堆疊電子裝置之製造方法,包括:提供一第一基底;進行一第一三維列印,以於該第一基底上形成一第一絕緣層以及複數第一重佈線層,其中該等第一重佈線層嵌入於該第一絕緣層內;進行一第二三維列印,以於該第一絕緣層上形成一第二基底以及複數基底通孔電極,其中該等基底通孔電極貫穿該第二基底且電性連接至該等第一重佈線層;進行一第三三維列印,以於該第二基底上形成一第二絕緣層以及複數第二重佈線層,其中該等第二重佈線層嵌入於該第二絕緣層內且電性連接至該等基底通孔電極;以及將一第三基底的複數接點接合至該等第二重佈線層,使該第三基底裝設於該第二絕緣層上。 A method for manufacturing a stacked electronic device includes: providing a first substrate; performing a first three-dimensional printing to form a first insulating layer and a plurality of first redistribution layers on the first substrate, wherein the first a redistribution layer is embedded in the first insulating layer; performing a second three-dimensional printing to form a second substrate and a plurality of substrate via electrodes on the first insulating layer, wherein the substrate via electrodes penetrate the first a second substrate and electrically connected to the first redistribution layer; performing a third three-dimensional printing to form a second insulating layer and a plurality of second redistribution layers on the second substrate, wherein the second weight a wiring layer is embedded in the second insulating layer and electrically connected to the substrate via electrodes; and a plurality of contacts of a third substrate are bonded to the second redistribution layers, and the third substrate is mounted on the second substrate On the second insulating layer. 如申請專利範圍第1項所述之堆疊電子裝置之製造方法,其中該第一基底包括:一印刷電路板、一晶圓、一晶片或其組合。 The method of manufacturing a stacked electronic device according to claim 1, wherein the first substrate comprises: a printed circuit board, a wafer, a wafer, or a combination thereof. 如申請專利範圍第1項所述之堆疊電子裝置之製造方法,其中該第一絕緣層及該第二絕緣層包括陶瓷材料、高分子材料、樹脂材料或介電材料。 The method of manufacturing a stacked electronic device according to claim 1, wherein the first insulating layer and the second insulating layer comprise a ceramic material, a polymer material, a resin material or a dielectric material. 如申請專利範圍第1項所述之堆疊電子裝置之製造方法,其中該等第一重佈線層及該等第二重佈線層包括鋁、銅、金或其合金。 The method of manufacturing a stacked electronic device according to claim 1, wherein the first redistribution layer and the second redistribution layer comprise aluminum, copper, gold or an alloy thereof. 如申請專利範圍第1項所述之堆疊電子裝置之製造方法,其 中該第二基底包括模塑成型材料、陶瓷材料、高分子材料、樹脂材料或介電材料。 A method of manufacturing a stacked electronic device according to claim 1, wherein The second substrate includes a molding material, a ceramic material, a polymer material, a resin material, or a dielectric material. 如申請專利範圍第1項所述之堆疊電子裝置之製造方法,其中該第二基底包括半導體材料,且該製造方法更包括形成一絕緣間隔層,以電性隔離該第二基底與該等基底通孔電極。 The method of manufacturing a stacked electronic device according to claim 1, wherein the second substrate comprises a semiconductor material, and the manufacturing method further comprises forming an insulating spacer layer to electrically isolate the second substrate from the substrates Through hole electrode. 如申請專利範圍第1項所述之堆疊電子裝置之製造方法,其中該等基底通孔電極包括鎢、鋁、銅、金、無鉛銲錫或其合金。 The method of manufacturing a stacked electronic device according to claim 1, wherein the substrate via electrodes comprise tungsten, aluminum, copper, gold, lead-free solder or alloys thereof. 如申請專利範圍第1項所述之堆疊電子裝置之製造方法,其中用以進行該第一三維列印、該第二三維列印及該第三三維列印的一三維列印機具有至少二個列印噴頭,使每一三維列印進行期間同時形成至少二種不同的材料。 The method for manufacturing a stacked electronic device according to claim 1, wherein the three-dimensional printer for performing the first three-dimensional printing, the second three-dimensional printing, and the third three-dimensional printing has at least two The print heads are printed such that at least two different materials are simultaneously formed during each three-dimensional print. 一種堆疊電子裝置,包括:一第一基底;一第一絕緣層以及複數第一重佈線層,設置於該第一基底上,其中該等第一重佈線層嵌入於該第一絕緣層內;一第二基底以及複數基底通孔電極,設置於該第一絕緣層上,其中該等基底通孔電極貫穿該第二基底且電性連接至該等第一重佈線層;一第二絕緣層以及複數第二重佈線層,設置於該第二基底上,其中該等第二重佈線層嵌入於該第二絕緣層內且電性連接至該等基底通孔電極;以及一第三基底,裝設於該第二絕緣層上,其中該第三基底具 有複數接點接合至該等第二重佈線層;其中該第一絕緣層、該等第一重佈線層、該第二基底、該等基底通孔電極、該第二絕緣層及該等第二重佈線層係透過三維列印所使用的材料所構成。 A stacked electronic device includes: a first substrate; a first insulating layer and a plurality of first redistribution layers disposed on the first substrate, wherein the first redistribution layer is embedded in the first insulating layer; a second substrate and a plurality of substrate via electrodes are disposed on the first insulating layer, wherein the substrate via electrodes penetrate the second substrate and are electrically connected to the first redistribution layer; a second insulating layer And a plurality of second redistribution layers disposed on the second substrate, wherein the second redistribution layers are embedded in the second insulating layer and electrically connected to the substrate via electrodes; and a third substrate, Mounted on the second insulating layer, wherein the third substrate has Bonding a plurality of contacts to the second redistribution layer; wherein the first insulating layer, the first redistribution layer, the second substrate, the substrate via electrodes, the second insulating layer, and the The double wiring layer is formed by the materials used for three-dimensional printing. 如申請專利範圍第9項所述之堆疊電子裝置,其中該第一絕緣層及該第二絕緣層包括陶瓷材料、高分子材料、樹脂材料或介電材料。 The stacked electronic device of claim 9, wherein the first insulating layer and the second insulating layer comprise a ceramic material, a polymer material, a resin material or a dielectric material. 如申請專利範圍第9項所述之堆疊電子裝置,其中該等第一重佈線層及該等第二重佈線層包括鋁、銅、金、無鉛銲錫或其合金。 The stacked electronic device of claim 9, wherein the first redistribution layer and the second redistribution layer comprise aluminum, copper, gold, lead-free solder or alloys thereof. 如申請專利範圍第9項所述之堆疊電子裝置,其中該第二基底包括模塑成型材料、陶瓷材料、高分子材料、樹脂材料或介電材料。 The stacked electronic device of claim 9, wherein the second substrate comprises a molding material, a ceramic material, a polymer material, a resin material or a dielectric material. 如申請專利範圍第9項所述之堆疊電子裝置,其中該第二基底包括半導體材料,且該堆疊電子裝置更包括一絕緣間隔層,以電性隔離該第二基底與該等基底通孔電極。 The stacked electronic device of claim 9, wherein the second substrate comprises a semiconductor material, and the stacked electronic device further comprises an insulating spacer to electrically isolate the second substrate from the substrate via electrodes . 如申請專利範圍第9項所述之堆疊電子裝置,其中該等基底通孔電極包括鎢、鋁、銅、金、無鉛銲錫或其合金。 The stacked electronic device of claim 9, wherein the substrate via electrodes comprise tungsten, aluminum, copper, gold, lead-free solder or alloys thereof.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI692062B (en) * 2018-11-01 2020-04-21 華邦電子股份有限公司 Circuit structure and method of manufacturing the same
TWI733331B (en) * 2020-02-11 2021-07-11 華邦電子股份有限公司 Semiconductor device and method of manufacturing the same
US11309267B2 (en) 2020-07-15 2022-04-19 Winbond Electronics Corp. Semiconductor device including uneven contact in passivation layer and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI692062B (en) * 2018-11-01 2020-04-21 華邦電子股份有限公司 Circuit structure and method of manufacturing the same
TWI733331B (en) * 2020-02-11 2021-07-11 華邦電子股份有限公司 Semiconductor device and method of manufacturing the same
US11309267B2 (en) 2020-07-15 2022-04-19 Winbond Electronics Corp. Semiconductor device including uneven contact in passivation layer and method of manufacturing the same

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