TWI692062B - Circuit structure and method of manufacturing the same - Google Patents

Abstract

Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends from a top surface of the conductive layer upward. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided.

Description

Circuit structure and its manufacturing method

The invention relates to a semiconductor structure and a manufacturing method thereof, and particularly relates to a circuit structure and a manufacturing method thereof.

In recent years, the semiconductor industry has grown rapidly due to the increasing accumulation of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). This increase in accumulation is mostly due to the continuous reduction in the minimum feature size, which allows more components to be integrated in a specific area.

Compared with the conventional packaging structure, these smaller electronic components have a smaller area, so a smaller packaging structure is required. For example, semiconductor wafers or die have more and more input/output (I/O) pads, and a redistribution layer (RDL) can replace the original I/O pads of the semiconductor wafer or die The position is relocated around the semiconductor wafer or die to increase the number of I/O.

However, in the traditional wafer-level packaging process, the redistribution layer structure and the copper pillar bumps are repeatedly used in sputtering, electroplating, lithography, etching and other processes to form a multilayer structure. In addition to the cumbersome steps in the multi-process, the yield loss between each process step, The waste of materials and the diversification of machines will cause high manufacturing costs. In addition, there is a problem of adhesion between layers in the multilayer structure, and intermetallic compounds (IMC) are also easily generated between different metal materials. Therefore, the interface between the traditional redistribution layer structure and the copper pillar bumps often suffers from peeling and cracking during reliability testing.

The invention provides a circuit structure, including: a substrate, a pad, a dielectric layer, a conductive layer, an adhesive layer and a conductive bump. The pad is arranged on the substrate. The dielectric layer is disposed on the substrate and exposes some pads. The conductive layer contacts the pad and extends from the pad to cover the top surface of the dielectric layer. The adhesive layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends upward from the top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed.

The invention provides a method for manufacturing a circuit structure, the steps of which are as follows. A pad is formed on the substrate. A dielectric layer is formed on the substrate. The dielectric layer has an opening that exposes a portion of the pad. An adhesive layer is formed on the dielectric layer. The adhesive layer covers the sidewall of the opening and extends to cover the top surface of the dielectric layer. The circuit layer is formed by the first 3D printing technology. The circuit layer includes: a conductive layer and a conductive bump. The conductive layer contacts the pad and extends from the pad along the first direction to cover the top surface of the adhesive layer. The conductive bump extends from the first top surface of the conductive layer on the adhesive layer along the second direction. The first direction is different from the second direction. A passivation layer is formed on the circuit layer. The passivation layer covers the second top surface of the conductive layer and covers part of the side walls of the conductive bumps. A solder layer is formed on the conductive bump.

Based on the above, the present invention uses 3D printing technology to form a circuit layer (which includes Conductive layer and conductive bump), so that the conductive layer and the conductive bump are integrally formed. That is to say, the conductive layer and the conductive bump are formed in the same process steps and in the same material, thereby avoiding the problems of adhesion and IMC between different materials. In this way, the present invention can greatly increase the structural strength between the conductive layer and the conductive bumps in the circuit structure, thereby improving product reliability. In addition, the manufacturing method of the circuit structure of the present invention also has the advantage of simple process steps, thereby enhancing the commercial competitiveness of the product.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

100: base

102: pad

102t: the top surface of the pad

104: dielectric layer

104t: the top surface of the dielectric layer

105: opening

105s: open side wall

106: Adhesive layer

106t: top surface of the adhesive layer

108: part

110: line layer

112: conductive layer

112a: Part One

112b: Part Two

112c: Part III

112t, 112t’: the top surface of the conductive layer

113: Virtual interface

114: conductive bump

114s: part of the side wall of the conductive bump

115: conductive particles

116: Passivation layer

118: solder layer

202, 212, 222, 232: nozzle

204, 224: Insulating ink

214, 234: conductive ink

D1: First direction

D2: Second direction

1A to 1E are schematic cross-sectional views of a manufacturing process of a circuit structure according to an embodiment of the invention.

FIG. 2 is an enlarged cross-sectional view of a portion of the line structure of FIG. 1C.

The invention is explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms, and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar element reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1A to 1E are schematic cross-sectional views of a manufacturing process of a circuit structure according to an embodiment of the invention. 2 is a cross-section of a portion of the circuit structure of FIG. 1C Zoom in. Here, the circuit structure illustrated in this embodiment may be a redistribution layer (RDL) structure, but the invention is not limited thereto. In other embodiments, the circuit structure may also be an interconnect structure in a back-end-of-line (BEOL) process, a circuit structure in a circuit board, or the like.

Referring to FIG. 1A, this embodiment provides a method for manufacturing a circuit structure, and the steps are as follows. First, the substrate 100 is provided. In one embodiment, the substrate 100 includes semiconductor material. Specifically, the substrate 100 may be formed of at least one semiconductor material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. In this embodiment, the substrate 100 may be a silicon substrate. In addition, the substrate 100 may also include a silicon substrate on the insulator. Although FIG. 1A does not show any components disposed in the substrate 100, the substrate 100 of this embodiment may have active components (such as transistors, diodes, etc.), passive components (such as capacitors, inductors, Resistors, etc.), or a combination thereof. In other embodiments, the substrate 100 may have, for example, logic elements, memory elements, or a combination thereof.

Next, the pad 102 is formed on the substrate 100. In an embodiment, the material of the pad 102 includes a metal material, which may be, for example, copper, aluminum, gold, silver, nickel, palladium, or a combination thereof. The forming method of the pad 102 includes physical vapor deposition (PVD), plating, or a combination thereof. Although only one pad 102 is shown in FIG. 1A, the invention is not limited thereto. In other embodiments, the number of pads 102 can be adjusted according to needs. In one embodiment, the pads 102 can be electrically connected to elements (not shown) in the substrate 100.

After that, the dielectric layer 104 is formed on the substrate 100. The dielectric layer 104 covers the interface The side wall of the pad 102 also covers a part of the top surface of the pad 102. As shown in FIG. 1A, the dielectric layer 104 has an opening 105. The opening 105 exposes another part of the top surface 102t of the pad 102. In an embodiment, the material of the dielectric layer 104 includes a dielectric material, which may be, for example, silicon oxide, silicon nitride, silicon oxynitride, polyimide, or a combination thereof. The method for forming the dielectric layer 104 includes PVD, chemical vapor deposition (CVD), or a combination thereof.

1B, the adhesive layer 106 is formed by three-dimensional (3D) printing technology. In one embodiment, the 3D printing technology includes an ink jet printing process (Ink Jet Printing process), an aerosol spray printing process (Aerosol Jet Printing process), or a combination thereof. Taking the aerosol spray printing process as an example, it uses an aerosol jet deposition head (aerosol jet deposition head) to form an outer sheath flow (outer sheath flow) and an inner aerosol-containing carrier flow (inner aerosol- laden carrier flow). In the ring-shaped aerosol spraying process, aerosol streams of materials to be deposited are concentrated and deposited on the surface to be formed. The above step may be referred to as Maskless Mesoscale Material Deposition (M3D), that is, it may be deposited without using a mask.

In the present embodiment, as shown in FIG. 1B, the nozzle 202 of the 3D printing device ejects the insulating ink 204 onto the dielectric layer 104 along the first direction D1. In one embodiment, the insulating ink 204 includes an insulating material and a solvent. For example, the insulating material may be polyimide, polyurethane (PU), or similar insulating materials. And the solvent may be N-methylpyrrolidone (N-Methyl-2-pyrrolidone, NMP), Propylene glycol monomethyl ether (PGME), ethylene glycol and other similar solvents. After the curing step, the insulating ink 204 is cured into the adhesive layer 106. In an alternative embodiment, the curing step includes heating or illuminating to evaporate and cure the solvent in the insulating ink 204. In this case, as shown in FIG. 1B, the adhesive layer 106 covers the side wall 105 s of the opening 105 and extends to cover the top surface 104 t of the dielectric layer 104. In one embodiment, the adhesive layer 106 includes an insulating polymer, which may be, for example, polyimide, polyurethane, epoxy resin (SU-8), adhesive, or a combination thereof. In this embodiment, the adhesive layer 106 can increase the adhesion between the dielectric layer 104 and the subsequently formed conductive layer 112 (as shown in FIG. 1C). In another embodiment, the minimum thickness of the adhesive layer 106 may be between 0.8 μm and 3 μm. However, the present invention is not limited to this. In other embodiments, the thickness of the adhesive layer 106 can be increased by printing a layer.

1C, the circuit layer 110 is formed by 3D printing technology. The circuit layer 110 includes a conductive layer 112 and a conductive bump 114. In detail, the nozzle 212 of the 3D printing device ejects the conductive ink 214 onto the adhesive layer 106 along the first direction D1 to form the conductive layer 112, and then ejects the conductive ink 214 onto the conductive layer 112 along the second direction D2 To form the conductive bump 114. In this case, as shown in FIG. 1C, the conductive layer 112 extends from the pad 102 along the first direction D1 to cover the top surface 106 t of the adhesive layer 106. Specifically, the conductive layer 112 may include a first portion 112a, a second portion 112b, and a third portion 112c. The first portion 112a covers and contacts the top surface 102t of the pad 102. The second portion 112b covers and contacts the top surface 106t of the adhesive layer 106. The third portion 112c is located between the first portion 112a and the second portion 112b. In other words, the third The portion 112c can be regarded as a connecting portion or an inclined portion to connect the first portion 112a and the second portion 112b. In addition, the conductive bump 114 extends along the second direction D2 from the top surface 112t (considered to be the first top surface) of the conductive layer 112 on the adhesive layer 106. That is, the conductive bump 114 extends upward from the top surface 112t of the second portion 112b. In one embodiment, the first direction D1 is different from the second direction D2. For example, the first direction D1 and the second direction D2 are perpendicular or orthogonal to each other.

In an embodiment, the minimum thickness of the conductive layer 112 may be between 0.5 μm and 5 μm; and the minimum height of the conductive bump 114 is between 20 μm and 30 μm. However, the present invention is not limited to this. In other embodiments, the thickness of the conductive layer 112 or the height of the conductive bump 114 can be increased by printing a layer.

In one embodiment, the conductive ink 214 includes a plurality of conductive particles 115 and a solvent. The solvent includes N-methylpyrrolidone, propylene glycol methyl ether, ethylene glycol and the like. Furthermore, please refer to the enlarged view 2 of a portion 108 of the circuit layer 110 of FIG. 1C. After the curing step, the circuit layer 110 (which includes the conductive layer 112 and the conductive bump 114) is composed of a plurality of conductive particles in contact with each other 115 constituted. In an embodiment, the conductive particles 115 include a plurality of metal nano particles, which may be, for example, silver nano particles, copper silver nano particles, copper nano particles, or a combination thereof. In another embodiment, the average particle diameter of the conductive particles 115 may be between 5 nm and 1000 nm. The standard deviation of the particle size distribution of the conductive particles 115 may be between 4.55 and 43. In some embodiments, the circuit layer 110 tightly connects spherical conductive particles 115 with a uniform particle size to achieve uniform conduction. In other embodiments, the conductive particles 115 may also have different particle sizes.

On the other hand, as shown in FIG. 2, the conductive layer 112 and the conductive bump 114 share at least one or more of the conductive particles 115. That is, at least one or more of the conductive particles 115 span the virtual interface 113 between the conductive layer 112 and the conductive bump 114. It should be noted that there is actually no interface between the conductive layer 112 and the conductive bump 114. The virtual interface 113 described herein is defined to clearly define that the conductive layer 112 and the conductive bump 114 are integrally formed. The so-called integral molding can be regarded as being formed by the same process and using the same material. For example, the conductive layer 112 and the conductive bump 114 are formed by the same 3D printing technology and the same conductive ink 214. Since the conductive layer 112 and the conductive bump 114 are integrally formed, this embodiment can avoid the problems of adhesion and IMC between different materials. Therefore, this embodiment can greatly increase the structural strength between the conductive layer 112 and the conductive bump 114, thereby improving product reliability. In other words, compared with the conventional RDL structure, the adhesion between the conductive layer 112 and the conductive bump 114 in this embodiment is strong, and it is not easy to peel off or break.

Referring to FIG. 1D, a passivation layer 116 is formed by 3D printing technology. Specifically, the nozzle 222 of the 3D printing device ejects the insulating ink 224 onto the conductive layer 112 along the first direction D1. In one embodiment, the insulating ink 224 includes an insulating material and a solvent. The insulating material includes polyimide, polyurethane and other similar insulating materials. The solvent includes N-methylpyrrolidone, propylene glycol methyl ether, ethylene glycol and the like. After the curing step, the insulating ink 224 is cured into the passivation layer 116. In an alternative embodiment, the curing step includes heating or illuminating to evaporate and cure the solvent in the insulating ink 224. In this case, as shown in FIG. 1D, the passivation layer 116 The top surface 112t' of the conductive layer 112 which is not covered by the conductive bump 114 (which can be regarded as a second top surface) and covers a part of the side wall 114s of the conductive bump 114. In one embodiment, the passivation layer 116 includes an insulating polymer, which may be, for example, polyimide, an adhesive, or a combination thereof. In this embodiment, the passivation layer 116 can protect the conductive layer 112 from oxygen or moisture. In another embodiment, the minimum thickness of the passivation layer 116 may be between 0.7 μm and 4 μm. However, the present invention is not limited to this. In other embodiments, the thickness of the passivation layer 116 can be increased by printing a build-up layer.

1E, the solder layer 118 is formed by 3D printing technology. In detail, the conductive ink 234 is ejected onto the conductive bump 114 by the nozzle 232 of the 3D printing device to form the solder layer 118. In one embodiment, the conductive ink 234 includes conductive particles and a solvent. The conductive particles include a plurality of metal nanoparticles, which may be, for example, silver nanoparticles, copper silver nanoparticles, copper nanoparticles, or a combination thereof. The solvent includes N-methylpyrrolidone, propylene glycol methyl ether, ethylene glycol and the like. In another embodiment, the minimum thickness of the solder layer 118 may be between 0.7 μm and 4 μm. However, the present invention is not limited to this. In other embodiments, the thickness of the solder layer 118 can be increased by repeated stacking. In alternative embodiments, the solder layer 118 and the circuit layer 110 may be the same material or different materials. For example, the material of the circuit layer 110 includes copper-silver alloy; and the material of the solder layer 118 includes tin-silver alloy.

In summary, the present invention forms a circuit layer (which includes a conductive layer and a conductive bump) by 3D printing technology, so that the conductive layer and the conductive bump are integrally formed. That is to say, the conductive layer and the conductive bump are formed in the same process steps and in the same material, thereby avoiding the problems of adhesion and IMC between different materials. As a result, this issue Clearly, the structural strength between the conductive layer and the conductive bumps in the circuit structure can be greatly increased, thereby improving product reliability. In addition, the manufacturing method of the circuit structure of the present invention also has the advantage of simple process steps, thereby enhancing the commercial competitiveness of the product.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100: base

102: pad

104: dielectric layer

106: Adhesive layer

110: line layer

112: conductive layer

114: conductive bump

116: Passivation layer

118: solder layer

232: nozzle

234: conductive ink

Claims (9)

A circuit structure includes: a pad arranged on a substrate; a dielectric layer arranged on the substrate and exposing a part of the pad; a conductive layer contacting the pad and extending from the pad to cover A top surface of the dielectric layer; an adhesive layer, disposed between the dielectric layer and the conductive layer; a passivation layer, disposed on the conductive layer; and conductive bumps, from the top of the conductive layer The surface protrudes upward from the top surface of the passivation layer, wherein the conductive bump and the conductive layer are integrally formed. The circuit structure as described in item 1 of the patent application range, wherein the conductive layer and the conductive bump are composed of a plurality of conductive particles in contact with each other. The line structure as described in item 2 of the patent application range, wherein the conductive layer and the conductive bump share at least one of the plurality of conductive particles. The circuit structure as described in item 2 of the patent application range, wherein the plurality of conductive particles include a plurality of metal nanoparticles, and the plurality of metal nanoparticles include silver nanoparticles, copper silver nanoparticles, copper nanoparticles Rice granules or combinations thereof. The circuit structure as described in item 1 of the patent application scope, wherein the conductive layer does not have an interface between the conductive bumps. The circuit structure according to item 1 of the patent application scope, wherein the adhesive layer includes an insulating polymer, and the insulating polymer includes polyimide, polyurethane, epoxy resin, adhesive, or a combination thereof. The circuit structure as described in item 1 of the patent application scope further includes a solder layer disposed on the conductive bump. A method of manufacturing a circuit structure includes: forming a pad on a substrate; forming a dielectric layer on the substrate, the dielectric layer having an opening that exposes a portion of the pad; by first 3D printing Technology forms an adhesive layer on the dielectric layer, the adhesive layer covers the side wall of the opening and extends to cover the top surface of the dielectric layer; the circuit layer is formed by the second 3D printing technology, the circuit layer The method includes: a conductive layer contacting the pad and extending from the pad along the first direction to cover the top surface of the adhesive layer; and a conductive bump from the first of the conductive layer on the adhesive layer The top surface extends along a second direction, wherein the first direction is different from the second direction; a passivation layer is formed on the circuit layer by a third 3D printing technology, the passivation layer covers the conductive layer A second top surface of and covering part of the side wall of the conductive bump; and forming a solder layer on the conductive bump by a fourth 3D printing technique. The method for manufacturing a circuit structure as described in item 8 of the patent application range, wherein the formation of the circuit layer by the second 3D printing technology includes the use of conductive ink, the conductive ink including a plurality of metal nanoparticles, so The plurality of metal nanoparticles include silver nanoparticles, copper silver nanoparticles, copper nanoparticles, or a combination thereof.

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