JP5873323B2 - 半導体デバイスパッケージを製作するための方法 - Google Patents
半導体デバイスパッケージを製作するための方法 Download PDFInfo
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- JP5873323B2 JP5873323B2 JP2011277812A JP2011277812A JP5873323B2 JP 5873323 B2 JP5873323 B2 JP 5873323B2 JP 2011277812 A JP2011277812 A JP 2011277812A JP 2011277812 A JP2011277812 A JP 2011277812A JP 5873323 B2 JP5873323 B2 JP 5873323B2
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- Prior art keywords
- metal layer
- patterned
- layer
- vias
- interconnect
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Classifications
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- Manufacturing & Machinery (AREA)
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Description
110 第2の金属層
111 第2の金属層内面
112 第2の金属層外面
120 誘電体膜
121 誘電体膜内面
122 誘電体膜外面
130 第1の金属層
131 第1の金属層内面
132 第1の金属層外面
140 パターン形成済みの第2の金属層
141 パターン形成済みの第2の金属層領域
142 第2の金属層外面
143 パターン形成済みの第2の金属層領域
145 パターン形成済みの第2の金属層領域
150 ビア
151 ビア
152 ビア内面
153 ビア
155 ビア
160 接着剤
180 導電層
190 相互接続層
192 パターン形成済み相互接続層
194 上部相互接続領域
196 ビア相互接続領域
200 デバイス
202 デバイスの活性表面
204 デバイスの反対面
210 接触パッド
220 接触パッド
230 ドレイン端子
300 半導体デバイスパッケージ
Claims (5)
- 半導体デバイスパッケージを製作する方法であって、
第1の金属層と第2の金属層との間に挿入された誘電体膜を含む積層体を用意するステップであり、前記積層体が第1の金属層外面および第2の金属層外面を有する、ステップと、
所定のパターンに従って前記第2の金属層をパターン形成して、パターン形成済みの第2の金属層を形成するステップと、
所定のパターンに従って前記積層体を通って延在する複数のビアを形成するステップと、
1つまたは複数の半導体デバイスを前記パターン形成済みの第2の金属層の一部分の前記第2の金属層外面に取り付けるステップと、
前記第1の金属層外面および1つまたは複数のビアの内面に導電層を配置して、前記第1の金属層および前記導電層を含む相互接続層を形成するステップと、
所定の回路構成に従って前記相互接続層をパターン形成して、パターン形成済み相互接続層を形成するステップであり、前記パターン形成済み相互接続層の一部分が、1つまたは複数のビアを通って延在し、前記半導体デバイスとの電気接点を形成する、ステップと、
を含み、
前記パターン形成済みの第2の金属層が、1つまたは複数のビアと整列する1つまたは複数のフィードスルー構造体をさらに含み、前記パターン形成済み相互接続層の一部分が、前記1つまたは複数のビアを通って延在し、前記1つまたは複数のフィードスルー構造体との電気接点を形成する、
方法。 - 前記複数のビアを形成する前に前記所定のビアパターンに従って前記第1の金属層をパターン形成するステップをさらに含む、請求項1に記載の方法。
- 前記パターン形成済みの第2の金属層が複数のパターン形成済み領域をさらに含み、少なくとも2つのパターン形成済み領域が互いに異なる厚さを有する、請求項1または2に記載の方法。
- 複数の半導体デバイスを前記パターン形成済みの第2の金属層に取り付けるステップをさらに含み、少なくとも2つの半導体デバイスが互いに異なる厚さを有する、請求項1から3のいずれかに記載の方法。
- 誘電体膜に配置された第1の金属層を含む積層体と、
所定のパターンに従って前記積層体を通って延在する複数のビアと、
半導体デバイスが1つまたは複数のビアと接触するように前記誘電体膜に取り付けられた1つまたは複数の半導体デバイスと、
前記誘電体膜に配置され、前記第1の金属層および導電層の1つまたは複数のパターン形成済み領域を含むパターン形成済み相互接続層であって、一部分が1つまたは複数のビアを通って延在し、前記半導体デバイスとの電気接点を形成するパターン形成済み相互接続層と、
を備え、
前記パターン形成済み相互接続層が、上部相互接続領域およびビア相互接続領域を含み、前記上部相互接続領域が、前記ビア相互接続領域の厚さよりも大きい厚さを有し、
前記積層体は、前記誘電体膜の前記第1の金属層とは反対側に配置されたパターン形成済みの第2の金属層をさらに備え、
前記パターン形成済みの第2の金属層が、1つまたは複数のビアと整列する1つまたは複数のフィードスルー構造体をさらに含み、前記パターン形成済み相互接続層の一部分が、前記1つまたは複数のビアを通って延在し、前記1つまたは複数のフィードスルー構造体との電気接点を形成する、
半導体デバイスパッケージ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/975,466 US8114712B1 (en) | 2010-12-22 | 2010-12-22 | Method for fabricating a semiconductor device package |
US12/975,466 | 2010-12-22 |
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JP2012134500A JP2012134500A (ja) | 2012-07-12 |
JP2012134500A5 JP2012134500A5 (ja) | 2015-02-12 |
JP5873323B2 true JP5873323B2 (ja) | 2016-03-01 |
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US (2) | US8114712B1 (ja) |
EP (1) | EP2469591B1 (ja) |
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CN102593046B (zh) | 2015-08-26 |
EP2469591B1 (en) | 2021-01-27 |
CA2762470A1 (en) | 2012-06-22 |
CA2762470C (en) | 2019-01-15 |
CN102593046A (zh) | 2012-07-18 |
JP2012134500A (ja) | 2012-07-12 |
US20120161325A1 (en) | 2012-06-28 |
EP2469591A3 (en) | 2018-01-31 |
BRPI1105202A2 (pt) | 2013-04-09 |
US8114712B1 (en) | 2012-02-14 |
EP2469591A2 (en) | 2012-06-27 |
US8334593B2 (en) | 2012-12-18 |
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