JP2019047115A - 半導体パッケージ基板の製造方法及びそれを用いて製造された半導体パッケージ基板 - Google Patents
半導体パッケージ基板の製造方法及びそれを用いて製造された半導体パッケージ基板 Download PDFInfo
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- 229910052802 copper Inorganic materials 0.000 description 11
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- TVZPLCNGKSPOJA-UHFFFAOYSA-N copper zinc Chemical compound [Cu].[Zn] TVZPLCNGKSPOJA-UHFFFAOYSA-N 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
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- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L23/49822—Multilayer substrates
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
10a 上面
10b 下面
10c トレンチ
11 ポスト
14 下部回路配線
20 樹脂
30 導電体
34 上部回路配線
50 メッキ層または有機コーティング層
Claims (10)
- 伝導性素材のベース基板の上面をエッチングしてトレンチ及びポストを形成する段階と、
前記トレンチを樹脂で充填する段階と、
前記ポストの上面と前記樹脂の上面とが同一レベルを形成するように、前記トレンチの外部に露出された樹脂を除去する段階と、
前記ポストの上面及び前記樹脂の上面全体に導電層を形成する段階と、
前記導電層及び前記ベース基板の下面を同時にパターニングして、上部回路配線及び下部回路配線を含む回路配線を形成する段階と、を含む、半導体パッケージ基板の製造方法。 - 前記導電層は、第1導電層及び第2導電層が積層されて形成され、
前記第1導電層の厚さは、第2導電層の厚さよりも薄い、請求項1に記載の半導体パッケージ基板の製造方法。 - 前記第1導電層はスパッタリング法を用いて形成される、請求項2に記載の半導体パッケージ基板の製造方法。
- 前記第1導電層は、スパッタリング法を用いて形成され、前記第2導電層は、電気メッキ法を用いて形成される、請求項2に記載の半導体パッケージ基板の製造方法。
- 前記導電層を形成する段階以前に、前記樹脂に表面処理を行う段階をさらに含む、請求項1に記載の半導体パッケージ基板の製造方法。
- 前記回路配線を形成する前に、前記ベース基板の下面全体をエッチングする段階をさらに含む、請求項1に記載の半導体パッケージ基板の製造方法。
- 前記回路配線を形成した後、前記回路配線の少なくとも一部に回路保護層を形成する段階をさらに含む、請求項1に記載の半導体パッケージ基板の製造方法。
- 前記樹脂及び前記回路保護層は、感光性樹脂で形成される、請求項7に記載の半導体パッケージ基板の製造方法。
- 前記回路保護層の形成後、露出された回路パターン上にメッキ層または有機コーティング層を形成する段階をさらに含む、請求項7に記載の半導体パッケージ基板の製造方法。
- 樹脂が充填された半導体パッケージ基板において、
前記樹脂の上面に配置された上部回路配線と、
前記樹脂の下面に配置された下部回路配線と、
前記樹脂を貫通するものであって、前記上部回路配線と前記下部回路配線とを連結するポストと、を含み、
前記上部回路配線は、前記ポストと別途に備えられ、前記下部回路配線の少なくとも一部は、前記ポストと一体に備えられた、半導体パッケージ基板。
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KR1020170111038A KR102069659B1 (ko) | 2017-08-31 | 2017-08-31 | 반도체 패키지 기판 제조방법 및 이를 이용하여 제조된 반도체 패키지 기판 |
KR10-2017-0111038 | 2017-08-31 |
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US (2) | US10811302B2 (ja) |
JP (1) | JP2019047115A (ja) |
KR (1) | KR102069659B1 (ja) |
CN (1) | CN109427598A (ja) |
TW (1) | TWI772480B (ja) |
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KR102119142B1 (ko) | 2019-10-01 | 2020-06-05 | 해성디에스 주식회사 | 웨이퍼 레벨 패키지의 캐리어를 리드 프레임으로 제작하는 방법 |
KR102535353B1 (ko) * | 2020-12-09 | 2023-05-23 | 해성디에스 주식회사 | 반도체 패키지 기판, 이의 제조방법, 반도체 패키지 및 이의 제조방법 |
KR102531703B1 (ko) * | 2021-09-15 | 2023-05-12 | 해성디에스 주식회사 | 반도체 패키지 기판 및 반도체 패키지 기판의 제조방법, 반도체 패키지 |
KR102574456B1 (ko) * | 2021-09-28 | 2023-09-06 | 해성디에스 주식회사 | 반도체 패키지 기판용 조성물, 이를 포함하는 반도체 패키지 기판 및 이의 제조방법 |
CN118412304B (zh) * | 2024-07-03 | 2024-09-03 | 四川蓝辉先进新材料科技有限公司 | 一种半导体材料封装用衬底制备装置 |
Citations (7)
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US11876012B2 (en) | 2024-01-16 |
US10811302B2 (en) | 2020-10-20 |
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TW201913915A (zh) | 2019-04-01 |
TWI772480B (zh) | 2022-08-01 |
KR20190024243A (ko) | 2019-03-08 |
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US20200411362A1 (en) | 2020-12-31 |
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