JP4890959B2 - 配線基板及びその製造方法並びに半導体パッケージ - Google Patents
配線基板及びその製造方法並びに半導体パッケージ Download PDFInfo
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- JP4890959B2 JP4890959B2 JP2006168083A JP2006168083A JP4890959B2 JP 4890959 B2 JP4890959 B2 JP 4890959B2 JP 2006168083 A JP2006168083 A JP 2006168083A JP 2006168083 A JP2006168083 A JP 2006168083A JP 4890959 B2 JP4890959 B2 JP 4890959B2
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L2924/01013—Aluminum [Al]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01033—Arsenic [As]
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- H01L2924/01079—Gold [Au]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
2;レジストパターン
3;導体配線層
4;エッチング容易層
5;エッチングバリア層
6;配線本体
7;基体絶縁膜
7a;凹部
8、38;内部導体
10、30、74、94;ヴィアホール
11;上層配線
12、32;ソルダーレジスト層
13、23、33、43、53、97;配線基板
14、24;バンプ
15、25;半導体デバイス
16;アンダーフィル
17;モールディング
18;はんだボール
19、29、39、49;半導体パッケージ
31;中間配線
37;中間絶縁層
26;マウント材
27;ワイヤ
28;接続ヴィア
41;保護膜
42;開口部
70、85;ビルドアッププリント基板
71、83;スルーホール
72、73、81、92、95;導体配線
73;ベースコア基板
75、93;層間絶縁膜
82;プリプレグ
84;導体ペースト
86;ランドパターン
91;支持板
96;支持体
Claims (16)
- 厚さが20乃至100μmで、その一方の面に凹部が形成された基体絶縁膜と、前記基体絶縁膜の前記凹部内に形成された第1の配線と、前記基体絶縁膜の他方の面上に形成された第2の配線と、前記基体絶縁膜に形成され前記第1の配線と前記第2の配線とを相互に接続するヴィアホールと、を有し、前記基体絶縁膜は耐デスミア性の異なる複数の層により構成されており、前記ヴィアホールの前記基体絶縁膜の厚さ方向における断面が樽型形状であることを特徴とする配線基板。
- 前記基体絶縁膜はアラミド繊維又はガラスクロスを樹脂に含浸させた材料であることを特徴とする請求項1に記載の配線基板。
- 前記基体絶縁膜の前記他方の面上に、複数の絶縁膜が積層された積層構造を有し、前記各絶縁膜間には夫々中間配線が形成されており、前記絶縁膜に形成されたヴィアホールが、前記基体絶縁膜の前記第2の配線と前記絶縁膜の下層に形成された前記配線同士及び前記絶縁膜の上層及び下層に形成された配線同士を相互に接続することを特徴とする請求項1又は2に記載の配線基板。
- 前記ヴィアホールを介して相互に接続されている2つの配線の接続界面が、前記ヴィアホールの前記基体絶縁膜の厚さ方向における中央部分に存在していることを特徴とする請求項1乃至3のいずれか1項に記載の配線基板。
- 前記第1の配線の表面と、前記基体絶縁膜の一方の面との間に0.5乃至10μmの段差が形成されていることを特徴とする請求項1乃至4のいずれか1項に記載の配線基板。
- 前記第1の配線の表面と前記基体絶縁膜の一方の面とが同一平面上に位置していることを特徴とする請求項1乃至4のいずれか1項に記載の配線基板。
- 前記基体絶縁膜の一方の面及び前記第1の配線上には保護膜が形成されており、この保護膜における前記第1の配線上に形成された部分の少なくとも一部には開口部が設けられており、前記開口部において前記第1の配線の表面が露出していることを特徴とする請求項6に記載の配線基板。
- 前記基体絶縁膜の他方の面及び前記第2の配線上にはソルダーレジスト層が形成されており、このソルダーレジスト層における前記第2の配線上に形成された部分の少なくとも一部には開口部が設けられており、前記開口部において前記第2の配線の表面が露出していることを特徴とする請求項1又は2に記載の配線基板。
- 前記絶縁膜の上層に形成された配線上にはソルダーレジスト層が形成されており、このソルダーレジスト層における前記配線上に形成された部分の少なくとも一部には開口部が設けられており、前記開口部において前記配線の表面が露出していることを特徴とする請求項3に記載の配線基板。
- 前記基体絶縁膜の他方の面にも凹部が形成されており、前記第2の配線はこの凹部内に形成されていることを特徴とする請求項1乃至9のいずれか1項に記載の配線基板。
- 前記絶縁膜の厚さが20乃至100μmであることを特徴とする請求項3に記載の配線基板。
- 厚さが20乃至100μmで、その一方の面に凹部が形成された基体絶縁膜と、前記基体絶縁膜の前記凹部内に形成された第1の配線と、前記基体絶縁膜の他方の面上に形成された第2の配線と、前記基体絶縁膜に形成され前記第1の配線と前記第2の配線とを相互に接続するヴィアホールとを有する配線基板の製造方法であって、前記基体絶縁膜の一部を薬液によるデスミヤ処理することにより、前記ヴィアホールの前記基体絶縁膜の厚さ方向における断面を樽型形状、釣り鐘形状又は蛇腹形状にする工程を有することを特徴とする配線基板の製造方法。
- 請求項1乃至11のいずれか1項に記載の配線基板と、この配線基板上に搭載された1又は複数の半導体デバイスと、を有することを特徴とする半導体パッケージ。
- 前記半導体デバイスは、前記配線基板の第1の配線に接続されていることを特徴とする請求項13に記載の半導体パッケージ。
- 前記半導体デバイスは、前記配線基板の第2の配線に接続されていることを特徴とする請求項13又は14に記載の半導体パッケージ。
- 更に、前記第1の配線又は前記第2の配線に接続されており、外部素子に接続される接続用端子を有することを特徴とする請求項13乃至15のいずれか1項に記載の半導体パッケージ。
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JP2006168083A JP4890959B2 (ja) | 2005-06-17 | 2006-06-16 | 配線基板及びその製造方法並びに半導体パッケージ |
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JP2005178415 | 2005-06-17 | ||
JP2005178415 | 2005-06-17 | ||
JP2006168083A JP4890959B2 (ja) | 2005-06-17 | 2006-06-16 | 配線基板及びその製造方法並びに半導体パッケージ |
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JP2011248227A Division JP5451719B2 (ja) | 2005-06-17 | 2011-11-14 | 配線基板及び半導体パッケージ |
JP2011248228A Division JP5331958B2 (ja) | 2005-06-17 | 2011-11-14 | 配線基板及び半導体パッケージ |
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JP2007027706A JP2007027706A (ja) | 2007-02-01 |
JP4890959B2 true JP4890959B2 (ja) | 2012-03-07 |
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Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2009022461A1 (ja) * | 2007-08-10 | 2009-02-19 | Sanyo Electric Co., Ltd. | 回路装置及びその製造方法、携帯機器 |
JP5439713B2 (ja) * | 2007-08-10 | 2014-03-12 | 三洋電機株式会社 | 回路装置及びその製造方法、携帯機器 |
JP5442192B2 (ja) * | 2007-09-28 | 2014-03-12 | 三洋電機株式会社 | 素子搭載用基板、半導体モジュール、および、素子搭載用基板の製造方法 |
JP5577760B2 (ja) * | 2009-03-09 | 2014-08-27 | 新光電気工業株式会社 | パッケージ基板および半導体装置の製造方法 |
JP5675443B2 (ja) | 2011-03-04 | 2015-02-25 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
TWI557855B (zh) * | 2011-12-30 | 2016-11-11 | 旭德科技股份有限公司 | 封裝載板及其製作方法 |
JP2013229524A (ja) * | 2012-04-26 | 2013-11-07 | Ngk Spark Plug Co Ltd | 多層配線基板及びその製造方法 |
KR20170067426A (ko) | 2015-12-08 | 2017-06-16 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지의 제조 방법 및 이를 이용한 반도체 패키지 |
KR102019355B1 (ko) | 2017-11-01 | 2019-09-09 | 삼성전자주식회사 | 반도체 패키지 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH03136298A (ja) * | 1989-10-20 | 1991-06-11 | Fujitsu Ltd | プリント回路基板の製造方法 |
JPH04154187A (ja) * | 1990-10-18 | 1992-05-27 | Mitsubishi Materials Corp | スルーホール配線板の構造及びその製造方法 |
JP3651027B2 (ja) * | 1994-08-29 | 2005-05-25 | 株式会社村田製作所 | 多層配線基板の製造方法 |
JP2000223810A (ja) * | 1999-02-01 | 2000-08-11 | Kyocera Corp | セラミックス基板およびその製造方法 |
JP3841079B2 (ja) * | 2002-11-12 | 2006-11-01 | 日本電気株式会社 | 配線基板、半導体パッケージ、基体絶縁膜及び配線基板の製造方法 |
JP4479180B2 (ja) * | 2003-07-25 | 2010-06-09 | 凸版印刷株式会社 | 多層回路板の製造方法 |
JP2004274071A (ja) * | 2004-04-20 | 2004-09-30 | Nec Toppan Circuit Solutions Inc | 半導体装置用基板並びに半導体装置及びそれらの製造方法 |
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