TW201034142A - Integrated circuit micro-module - Google Patents

Abstract

Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.

Description

201034142 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to a package of an integrated circuit (1C). More specifically, the present invention relates to an integrated circuit micromodule. [Prior Art] There are several conventional methods for packaging an integrated circuit (IC) die. Some packaging technologies create electronic modules for incorporating multiple electronic devices (eg, 'integrated circuits; passive devices' such as inductors, capacitors, resistors, or ferromagnetic materials; etc.) into a single package. Among them. A package incorporating more than one integrated circuit die is often referred to as a multi-wafer module. Some multi-chip modules include a substrate or interposer (in terp〇Ser) to support various devices' while other multi-chip modules use lead frames, dies or other structures to support various other packaged devices. . Several, multi-chip module packaging techniques have been identified, for example, to integrate multiple interconnect layers into a package using a laminated film or a multi-stack wafer carrier, although for packaging electronic molds. The existing arrangement and method of the group are not correct. However, it is still necessary to strive to develop improved packaging technology, and use θ to save money in order to meet the needs of a variety of different packaging applications. SUMMARY OF THE INVENTION One of the points of the moon is related to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered by a light-emitting epoxy layer. The integrated circuit is disposed in a cavity 8 in the top surface of the substrate. The epoxy layer is formed on the top surface of the substrate. 201034142 The interconnect layer is formed in the epoxy electrical interface. When the extra integrated circuit, the surface and the active surface of the integrated circuit are above. Above the resin layer and with the integrated circuit, if necessary or suitable for a particular application, the interconnect layer and/or the epoxy layer may be stacked above the substrate. The substrate and epoxy layer may comprise a wide variety of devices, active and passive devices such as: sensors, inductors, capacitors, resistors, heat pipes, photovoltaic cells, and the like.

The substrate may have a wide variety of features, depending on the needs of a particular application. For example, the substrate may be a doped enamel wafer that is electrically grounded and electrically and thermally coupled to one or more buried integrated circuits and/or contacts. In one embodiment, the substrate is at least partially transparent and the optical devices within the substrate are capable of communicating via the substrate. Yet another embodiment includes an integrated circuit in a cavity of the substrate that separates an air gap from the sidewall of the cavity. This arrangement can help reduce stress on the integrated circuit as it expands due to temperature changes. Additional embodiments of the present invention are directed to methods for forming the aforementioned integrated circuit packages. [Embodiment] In one of the aspects, the present invention is generally related to an integrated circuit (IC) package and, more specifically, to an IC micromodule technology. This point includes a micromodule composed of a plurality of layers made of a dielectric material, which is preferably photoimageable and easily planarized. The micromodule may contain a wide variety of devices including one or more integrated circuits, interconnect layers, heat sinks, conductor vias, passive devices, MEMS devices, sensors, heat pipes, ... 5 201034142 et al. . The various devices can be arranged in a variety of different ways and stacked within the micromodule. The various layers and devices of the micromodule can be deposited and processed using various conventional wafer level processing techniques, such as spin coating techniques, spray coating techniques, lithography, and/or electroplating techniques. Another aspect of the present invention is directed to wafer level fabrication techniques and structures that integrate multiple active and/or passive devices into a single, low cost, high performance package. Shown in Figure 1 is a package in accordance with an embodiment of the present invention. In the embodiment shown in the figures, the multi-layer package 100 comprises: a substrate 〇2, a heat sink 104, a plurality of stacked dielectric layers 〇6, an integrated circuit 114, and a passive device (in the figure Not shown), interconnect layer 122, channel 125, and external contact (4) m. The heat sink 104 will be formed over the substrate 1〇2, and the dielectric layers 106 will be stacked on top of the heat sink. If necessary, a plurality of interconnect layers are interposed between adjacent dielectric layers (10). The integrated circuits are buried in the -packed dielectric layer 1 () 6, and it is possible that the appropriate lines of & 122 and channel 125 are electrically connected to other devices, for example, other 1C, Passive device, external contact pad 120, stupid. In the embodiment shown in the figures, one of the integrated circuits (114a, a) is effectively placed over the dipstick i04 to provide a good heat dissipation. ... The dielectric M 1G6 can be made of any suitable dielectric material. In various preferred embodiments, the dielectric layer 106 is made of a two-piece material that is easily flattened and/or photoimageable. In a particularly preferred embodiment, the layers are made of photoimageable, planarized SU-8, although other suitable 7 gauge materials can be used. In some designs, the dielectric used for layer 1〇6 201034142 is very viscous when it is just coated, and then partially or fully cured during the photolithography process. The layers 106 can be applied using a variety of suitable techniques, including spin coating techniques and spray coating techniques. The thickness of the various dielectric layers can vary widely depending on the needs of the particular application' and the different layers need not be of the same thickness (although they may also have the same thickness). The integrated circuit 114 within the package 100 can be arranged in a wide variety of ways 10 and can be placed at almost any location within the package. For example, different integrated circuits 114 can be disposed in substrate 1 〇 2, in different photoimageable layers, and/or in the same layer. In various embodiments, the equal-integrated circuits 114 can be stacked, side-by-side disposed, placed closely adjacent one another, and/or separated by a substantial distance based on the overall size of the package. The integrated circuits disposed in the different layers may be disposed directly or partially above each other, or they may be separated so that they do not overlap each other. The integrated circuit 114 may also have a variety of different shapes _ factors, architectures, and configurations. For example, they may be in the form of relatively bare grains (for example, unpackaged grains, flip-chips, etc.), partially and/or fully encapsulated in the form of grains (for example, BGA, lgA, QFN, etc.). ... The electrical interconnects inside the package 100 can also be arranged in a variety of different ways. The embodiment shown in Figure 1 includes two interconnect (line) layers 122. There may be more or fewer interconnect layers in different implementations. Each interconnect layer will typically have at least one (but usually there will be many) lines 123 that will be used to assist the transmission of electrical signals between the different devices of the package. The interconnect layers 122 are typically formed at the top of the associated layer in the planarized layers 106. The circuit layer is then buried or covered by a different dielectric layer. Therefore, interconnect layers such as shaws typically extend in a plane parallel to the dielectric f layers and buried within the dielectric layers. Because the interconnect layers (and other possible devices of the package) are turned on at the top of the dielectric layer, it is desirable that the dielectric layers have a very flat and hard surface. The device (for example, a line, a passive device, etc.) may be formed thereon or a discrete device (for example, 1C) may be disposed. SU-8 is particularly suitable for this application because it can be easily automatically planarized when applied by conventional spin technology and spin coating techniques, and it will be very stiff after being cured. More specifically, the rotated SU-8 can be used to form a hard, flat surface without the need for any additional flatness prior to forming a high quality interconnect layer thereon using conventional sputtering/plating techniques. Chemical action (for example, chemical mechanical polishing). A dielectric material that can be coated in this manner to form a very flat surface is referred to herein as a planarizing dielectric. Conductive vias 125 are provided to electrically connect devices resident at different layers of the package (e.g., IC/line/contact/passive device, etc.). The channels 125 are arranged to extend through an associated dielectric layer 106. For example, the channels 125 can be used to couple lines from two different interconnect layers together, attaching a die or another device to an interconnect layer' to couple a contact to A line, die or other device. Etc. As explained in more detail below, a plurality of metallization channels can be formed simultaneously, and 201034142 can thereby deposit an associated interconnect layer by filling the via openings previously formed in an associated dielectric layer 106. 122. Package 1 may contain many other types of devices than those shown in FIG. In the embodiment shown in the figure, only a few integrated circuits and interconnect layers are shown. However, package 1 may also contain almost any number of active and/or passive devices. Examples of such active and/or passive devices include resistors, capacitors, magnetic cores, MEMS devices, sensors, batteries ( For example, capsular lithium battery or other battery), integrated thin film battery structure, inductor, etc. The devices can be arranged and/or stacked in various locations within the package 1〇〇. These devices may be in the form of discrete devices fabricated in advance or may be formed in the field. One of the advantages of the lithography-based process for creating packages is that these and other devices can be formed in the field during the layered formation of the package. That is, discrete devices can be placed almost anywhere in the package after being fabricated in advance, and the device can be directly applied using any suitable technique (eg, conventional sputtering and/or plating). It is fabricated on any photoimageable layer 1〇6. Due to this process characteristics, superior matching, accuracy, and control can be achieved, and low stress packages can be achieved on a variety of die and/or substrate sizes, including medium and large die and/or substrates. Effect. Substrate 102 may be made of any suitable material, including: tantalum, glass, steel, quartz, GW-FR4, any other FR4 family epoxy, ... and the like. Depending on the needs of the particular application, the substrate may be electrically conductive, electrically insulating and/or light transmissive. In some embodiments, the substrate is only used as a carrier during fabrication and thus will be removed prior to completion of the package. 201034142 In other embodiments, the substrate will remain as an integrally formed part of the package. If desired, the substrate 102 can also be thinned after assembly by back grinding techniques or other suitable techniques. Again, in other embodiments, the substrate may be omitted altogether. In some embodiments, the substrate 102 may incorporate one or more sensors (not shown). This approach achieves the goal of integrating the sensor device without having to package and without the reliability issues typically associated with the necessary conditions of the sensor to be exposed to the environment. The sensor can be placed on either side of the substrate 102 and can be embedded or exposed to the environment via an etched window or microchannel. Examples of suitable sensors include, but are not limited to, biosensors, gas sensors, chemical sensors' electromagnetic sensors, acceleration sensors, vibration sensors, temperature sensors , humidity sensor, .., etc. One such way is to integrate a sensing element to the back side of the substrate 1〇2. The sensing element can be built into the interior of the substrate 102 that has been etched away from the back side of the substrate 102. For example, the sensing element may be a capacitor made of a plurality of plated Cu fingers. The capacitor container can be connected to the contact pads on the front side of the substrate 1 2 via a microchannel. A package 100 can be formed over the contact pads such that the capacitor is electrically interfaced with at least a portion of the electrical devices and interconnect layers within the package 100. The sensing elements inside the cavity created on the back side of the wafer may be filled with gas sensitive material and may be automatically exposed to the environment, while the active circuitry on the front side of the substrate 1〇2 may utilize conventional encapsulation techniques. (For example: as discussed below in conjunction with Figure 5E) to protect. 10 201034142 Package 1〇〇 also contains a device for dissipating internal heat generated tubes and heat sinks, for example: ..... System's package (10) may play a role in the performance of the system °, ^ _ The role of the key, because of the high power and multi-embedded device package can be from the inside + private • will have a good cooling effect to function properly. The heat pipes and fins are typically formed substantially simultaneously with the interconnect layer = to mb and using the same techniques. These heat pipes can pass through and/or bypass through - or exchange multiple interconnect layers and/or illuminate

G image layer. Any single...continuous heat pipe, line, and/or channel can be split into a plurality of other lines and/or channels at almost any point of the location and can extend in more than one direction of the package, such as : Horizontal and / or vertical. The heat transfer tubes are in fact capable of thermally coupling any of the devices within the package (10) to one or more heat sink pads and/or heat sinks external to the package 100. The heat sink 104 may have a variety of different architectures. In the embodiment shown in the figures, the heat sink 104 will constitute a layer covering a range that substantially matches the coverage of the photoimageable layer of the package. Alternatively, package 10A may include one or more heat sinks whose dimensions at least partially match the dimensions of the active device (e.g., integrated circuit) above or below. In the embodiment shown in the figures, the heat sink may have the form of a layer or sheet 104 formed over the substrate and which will form the substrate of dielectric layer 〇6. If desired, the integrated circuit 114 can be placed directly on the heat sink layer as shown by integrated circuit 114(a). Alternatively, a thermally conductive channel (not shown) may be used to improve the thermal path between a buried integrated circuit and the heat sink as shown by integrated circuit 114(b). In some embodiments, 201034142 the (etc.) heat sink or heat sink layer may be exposed on the top or bottom surface of the package. In other embodiments, a substrate or other layer may cover the heat sink or heat sink layer, such that the heat sink acts as a heat spreader. The heat sink 104 may be suitable for various types. The conductor material (for example, copper) is made and can be constructed in the same way as the interconnect layer.

Various embodiments of package 100 may also incorporate a wide variety of other features. For example, package 100 may incorporate high voltage (HVh) isolation and embedded inductive Jaffany functionality. It may be characterized by a wireless interface, for example, RF antennas for wireless system 10, EM power collection (Em p〇wer scavenging), RF shielding for EMI sensitive applications, etc. In various embodiments, package 100 may include a power management subsystem, for example, a supercharger, an integrated photovoltaic system, etc. The package 100T is formed over a wafer and encapsulated, for example, as shown in Figure 5E. Sensing surfaces and materials can be integrated into the package 1〇〇 and

As above and in conjunction with Figures 5A to 5H, 6-8 to 6C, and 7A to 7 (: other processing steps of the wafer in question. Next, an embodiment for forming a product according to an embodiment of the present invention will be described with reference to FIG. The wafer level method of the bulk circuit package 100. The steps of the method 2 are illustrated in the figure from 3 to 3. The steps of the method 2 can be repeated and/or in a different order from that shown in the figure. It should be noted that the process shown in method 200 can be used to form many other structures than those shown in the figures (f). 12 201034142 Initially, in step 202 Φ m Z of Figure 2 The pattern m(4) is to be guided over the substrate (10) by any of a variety of suitable techniques. (4) HH. For example, 'using conventional plating after sputtering a seed layer is very suitable. Of course, it can also be utilized. Other suitable conductor layer forming techniques. The conductor layer 104 acts as a heat sink and can be made of various materials such as copper or other suitable metal or metal layer stack. The substrate 1〇2 may be a wafer and may be composed of a variety of suitable materials For example: 矽, ❾ G10-FR4, steel, glass, plastic, etc. In Figure 3B, a flattened, photoimageable epoxy resin is deposited over the heat sink 1〇4. 6 (Step 2〇4 of Figure 2.) This can be done using a variety of techniques, such as spin coating, spray coating or sheet lamination. In the embodiment shown, the ring The oxy-resin layer 106a is SU-8, however, other suitable dielectric materials can also be used. SU-8 is very suitable for applications using conventional spin coating techniques. SU-8 has various superior characteristics "It is a high Viscous, photoimageable, chemically inert polymer, for example, which can be cured when exposed to UV radiation during photolithography. ^ SU-8 provides a machine that is larger than some other known photoresists. Strength 'is resistant to excessive grinding and mechanically stable and thermally stable at temperatures up to at least 300 C. It is easy and uniform to use spin coating for certain other photoimageable materials (eg BCB) Flattening, which makes it easy to use as a Manufacture of interconnects or substrates for passive devices, and on which integrated circuits or other passive devices can be placed. They can be easily used to create dielectric layers with thicknesses ranging from 1 micron to 250 microns, and Thinner or thicker layers of 13 201034142 can be made. In a particular embodiment, multiple openings having a large aspect ratio (for example 'about 5: 1 or greater) can be formed in SU-8 It helps to form devices with large aspect ratios, such as conductive channels or other structures. For example, a 7:1 aspect ratio can be easily achieved compared to many other materials, using SU- The 8 layers are able to achieve better control, accuracy and matching, which can result in higher density and improved performance. It is also possible to use other suitable dielectric materials having one or more of the above features in place of SU-8. In step 206 of FIG. 2, the epoxy layer 106g is patterned using conventional photolithography techniques. In one embodiment, a mask is used to selectively expose the epoxy layer. Multiple parts in 6a. The baking will be carried out after the exposure. These operations enable cross-linking of the exposed portion of the epoxy resin layer 6a. During the photolithography process, the exposed portion of the epoxy layer 10a may be cured 'partially cured (for example, 'B order) or may be modified or hardened relative to the unexposed portion. To help remove the unexposed portion of the epoxy later. In step 208 of Figures 2 and 3C, the unexposed portions of the epoxy layer 1 〇 6a are removed to form one or more openings 306 in the epoxy layer 1 〇 6a. This removal process can be implemented in a variety of ways. For example, the epoxy layer 1_' can be developed in a developer solution to cause the (4) 106a towel to be undissolved. Hard baking may be performed after the development work. In step 210 of Figures 2 and 3D, the open bar circuit 114a is placed 306 and placed over the heat sink 104 by the ampoules. The 201034142 circuit 114a can be used in a variety of ways to the ligand circuit 114a, the furnace can be used, w β, the case does not say 'the product b day or granular crystal, or it may have BGA, LGA And/or other appropriate external ^ ^ 匕. And the external pin configuration. In the embodiment shown in the figure, the thickness of the integrated circuit on the Panyu & will be greater than the thickness of the epoxy layer (10) which is buried at the beginning; however, in other embodiments, i θ θ is also This and the epoxy resin in which it is initially buried. Having substantially the same or a thin thickness. Integrated circuit "牦 active surface

〇, up or down. In a particular embodiment, the integrated circuit 114 can be attached to the heat sink by an adhesive. μ after the integrated circuit ll4a has been disposed in the opening 3 () 6 and attached to the heat sink, '- the second epoxy layer secret is applied to the integrated circuit 114a and the j-oxygen The upper side of the resin layer 1〇6a (step 2〇4 of Fig. 2)' is as shown in Fig. 3E. As with the first epoxy resin layer 1〇6&, the second ring can be deposited by any convenient method (e.g., money method), and the resin layer 1 is sounded. In the embodiment shown in the figures, the epoxy layer is located directly above the integrated circuit 114a and the epoxy layer 1 , and is closely adjacent to the integrated circuit 114a and the epoxy layer 1〇6a. / or directly contact the integrated circuit 114a and the epoxy layer 1 〇 6a; however, other arrangements may also be employed. The epoxy layer 106b may completely or partially cover the active surface of the integrated circuit U4a. After the epoxy layer 16b has been applied, it can be patterned and developed using any suitable technique (steps 2〇6 and 2〇8), which are usually used for patterning. An epoxy resin layer 1〇6a is the same technique. In the embodiment shown in the figures, a plurality of channel openings 312 are formed over the integrated circuit 114a by the shape 15 201034142 to expose the I/O solder contact pads on the active surface of the integrated circuit. Not shown). The resulting structure is as shown in Figure 3F. After any suitable via openings 3丨2 have been formed, a seed layer 319 is deposited over openings 312 and epoxy layers 1〇6b, as shown in Figure 3G. The seed layer 319 may be made of any suitable material (which includes a stack of a plurality of sequentially applied sub-layers (for example, Ti, Cu, and Ti)) and may utilize a wide variety of materials. The process is deposited (for example, by sputtering a thin metal layer on the exposed surfaces). A feature of the foregoing description is that the sputtered seed layer has a tendency to coat all exposed surfaces that include the sidewalls and bottom of the passage opening 312. The deposition of the seed layer 319 may also be limited to only a portion of the exposed surfaces. In Figure 3H, a photoresist 315 is applied over the seed layer 319. The photoresist 315 may be either positive or negative, which will cover the seed layer 319 and fill the opening 3 12 . In Fig. 31, the photoresist is patterned and developed to form an open region 317 where the seed layer 319 is exposed. These open areas will be patterned to reflect the desired layout of the interconnect layers, including any desired conductor tracks and heat pipes, as well as any desired channels in the underlying epoxy layer 1〇6(b). After the desired open areas have been formed, the exposed portions of the seed layer are then electroplated to form the desired interconnect layer structure. In some embodiments, the portion of the seed layer (e.g., Ti) is left in place prior to electroplating. During electroplating, a voltage is applied to the seed layer 3 19 to help electrically bond a conductor material (e.g., copper) to the open areas $317. After the interconnect layer 16 201034142 has been formed, the photoresist 315 and seed layer 319 in the field will then be stripped. Thus, the interconnect layer 122a will be formed over the epoxy layer 106b as shown in Figure 3J (step 212). The plating operation described above for filling the opening of the passage with metal thereby forming a metal passage 3 13 in a space defined before the opening of the passages, the metal passages 313 being arranged to be electrically coupled I/O pads of integrated circuit 114a and corresponding lines 316 of interconnect layer 122a. Since the seed layer 319 has been deposited on both the sidewalls and the bottom of the crucible opening 312, the conductor material will accumulate substantially simultaneously on the sidewalls and the bottoms, thereby causing the filling speed of the opening 312 to The seed layer is only applied over the bottom of the opening Η]. Although not shown in the epoxy layers 1〇6a and 1〇6b; however, the germanium channels may also be formed through one or more epoxy layers for devices (for example, Lines, passive devices, external contact pads, 1C, ..., etc.) are coupled together. Moreover, in other arrangements, a plurality of conductor paths may be formed between a surface of the bottom (or other) surface of the φ body circuit and the heat sink layer 104 to achieve current even without metallization. The carrying function still provides a good thermal path to the heat sink. In general, interconnect layer 122a will have any number of associated traces and metal vias and will wrap the conductors in any manner suitable for the associated packaged devices used to electrically couple them. It should be noted that although this article has described a special sputtering/electrodeposition process which is very suitable for forming a line in an associated & epoxy layer and forming a channel therein at substantially the same time; , 201034142 It should be understood that a variety of other conventional or newly developed processes can be used to separate or form the channels and lines together. After the interconnect layer 122a has been formed, it is generally suitable to form an additional epoxy layer, an interconnect layer, and a suitable device for placing or embedding a suitable device therein or thereon. Steps 204, 206, 208, 210, and/or 212 are repeated in any order to form a particular package 100, such as the package shown in FIG. 3K. For example, in the embodiment shown in the figures, additional layers of epoxy 106c to 106f will be applied over the layer (which will actually repeat the steps as necessary). The integrated circuit U4b and the core are embedded in the epoxy layer and the layer 6e (steps 2〇6, 2〇8, and 21〇). Another interconnect layer 12 hole will be formed in the top epoxy layer 1〇6f (steps 2〇6, 2〇8, and 2 12 ), and so on. It should be understood that the integrated circuitry and interconnect layers in package 100 can be arranged in a variety of ways, depending on the needs of the particular application. For example, in the embodiment shown in the figures, the active faces of some integrated circuits are stacked directly above each other (for example, integrated power $ nh and ◎ 114b). Some integrated circuits are embedded in the same epoxy layer or multiple identical epoxy layers (for example, Integrated &" & Servants & ^14c). The integrated circuit may be buried in an epoxy layer different from the ring #树月曰 layer in which the interconnect layer is buried (for example, the interconnect layer 3 18 a electrical circuits 114a and 114b). ("Different" epoxy tree layer is referred to as each layer of the multilayer and other layers are sequentially deposited in a single adhesive coating, such as epoxy layer l〇6a To the case of l〇6e 18 201034142.) Integrated circuits may be stacked on top of each other and/or in close proximity to each other. The integrated circuit can also be electrically connected through electrical interconnect layers, vias and/or lines that extend substantially to the nearest or outer contour of any single integrated circuit (for example, integrated circuits 14b and 14c) ).

In step 214 of Figures 2 and 3L, additional external contact pads 12 may be added to the top surface of the package. The external contact pads 120 can be placed over other surfaces and formed in a variety of ways. For example, the top epoxy layer 106f can be patterned and developed using the techniques described above to expose a portion of the electrical interconnect layer 122b. Any suitable metal (e.g., copper) can be plated into the holes in the epoxy layer 10f to form conductor vias and external contact pads 120. Accordingly, at least some of the external contact pads 12A can be electrically coupled to the electrical interconnect layers 122a-122b and/or the integrated circuits 114& to n4c. The feature elements of the package can be modified in a variety of ways. For example, it may contain more or fewer integrated circuits and/or interconnect layers. It may also contain a number of additional devices such as: sensors, (10) devices, resistors, capacitors, thin film cell structures, photovoltaic cells, wireless antennas and/or inductors. In some embodiments, the substrate 1〇2 may be concealed or disposed of. The substrate 1〇2 may have any suitable thickness. For example, a thickness in the range of about 1 GG i 25 G microns is extremely suitable for many applications where the thickness of the package 100 may vary widely. For example, the sensitivity of centimeter ranging from about 0,5 to 1 mm is well suited for many applications. The thickness of the electrical interconnect layer and the coffee maker may also vary widely with the needs of a particular application. For example, it is believed that a thickness of about 5 microns is ideal for many applications in 201034142. Figure 4A is a plan view showing another embodiment of the present invention. It is the same as the package 100 of Fig. 1. 'Fig. 4Α's Fengshang 4 璜 褂 3 3 3 integrated circuits 401 and 403, rolled tree raft layer 410, and a plurality of mutual 〇〇 ^ package cuts are also included in the package Some additional non-essential features that are not visible. For example, the special heat dissipation of the package 400. In a, the circuit of the Zhao circuit will be hot (4) Miscellaneous... In the example, some dimensions of the heat sink 4〇2 are substantially the same as those in the thermally coupled device, 1旳 dimension Thunder. In the special embodiment 2=片The 402 may be larger or smaller than the lower surface of the integrated circuit 401. The heat sink is "situated on the top surface or the bottom surface of the integrated body (four) 401 to directly contact the top surface or the bottom surface of the integrated circuit 401. It may be directly adjacent to an outer surface of the package (in the case of the embodiment shown in the figure or may pass through - or a plurality of hot channels are connected to the outer surface. The heat sink 402 is thermally coupled to a conductor layer, For example, the layer 1〇4 of Fig. i. In the preferred embodiment in which the epoxy layer 41 is made of _8, a heat sink 4〇2 is particularly present directly below the integrated circuit 401. Help, because heat is not completely conducted through SU-8. Package 400 features a variety of passive devices such as inductors 4〇6 and 408, resistors 4〇4, and capacitors 4〇6. These passive devices may be located Encapsulating any epoxy layer or location within 400. They can be formed using a variety of suitable techniques, depending on the needs of the particular application. For example, inductor winding 4丨2 and inductor core 4丨〇a and 41〇b may be formed by depositing a conductor material and a ferromagnetic material respectively over at least one of the epoxy resin layers 41. The thin film resistor 201034142 may be by such Epoxy layer 4 〇 or coated Any convenient power 'by sputtering ⑽ above) is formed. Capacitance such as: dream chrome, chrome and chrome, or the omnipotent layer above the chrome epoxy layer is formed by depositing a thin dielectric layer between the deposited metal plates or plates. . The pre-fabricated resistors s (1) are purchased in a layer and the capacitors can be placed in a plurality of inductive states and capacitors. Above. conductor

Any suitable method known in the art can be used, for example, by electron microscopy or organic mining. Package 400 also contains

The type contacts the non-essential BGA above the front surface 416. Since the position of the contact pad 41 is 414 can be set by various materials, the substrate G1〇-FR4, steel and glass. In a particular embodiment where the etc. contact pads are located on the back surface 418, the base LLV can be made of (4) and is characterized by a through passage that is electrically connectable to the contact contacts. In another embodiment, the substrate is primarily used as a build platform for forming the package 400 and will eventually be removed. Figure 4B shows another embodiment of the invention having a number of features S shown in Figure 4a. This embodiment includes 'additional devices, including: precision adjustable capacitor 430 and resistor 432, micro-relay 43 low-cost configurable precision passive feedback network 436, fr_4 base 438 and photovoltaic cells 440. The battery 44 may be covered by a layer of transparent material (eg, transparent SU-8). In other embodiments, photovoltaic cell 440 can be replaced by a window glass sensor, a wireless phase antenna array, a heat sink, or another suitable device. The package 4 may contain additional external structures for the heat of the inductor array, the RF-enabled package 400, which include: a power antenna, a heat pipe, and a dissipating contact pad. ❹ Figure 4C shows a further embodiment of a heat transfer tube shown in Figure 4D. Figure 4C illustrates a crucible 479 comprising an integrated circuit embedded in a multi-layer planarized, photoimageable epoxy resin 48. Multiple: The interconnecting wires 484 meet the solder contact pads on the active surface of the integrated circuit (not shown). The back side of the integrated circuit will be placed over the heat pipe 488. The heat pipe includes the heat conducting line 4 and the heat conducting channel 488b. The heat pipe 488 is made of any suitable material that will properly conduct heat, such as copper. As shown by the virtual 'line 489, the heat from the integrated circuit damage is transmitted through the back side of the integrated circuit 486, flowing near the heat conducting line 488a and passing upward through the heat conducting channel 48, so that the heat will pass to the package 479. The top of the outer surface. The embodiment shown in Figure 4B can be fabricated using a variety of techniques, such as the techniques discussed in conjunction with Figures 3A through 3D.

Figure 4D shows another embodiment of the present invention. This embodiment includes an integrated circuit 114a whose bottom surface is thermally and thermally coupled to heat conduction f 47 。. The heat pipe 470 is made of a heat conductive material (e.g., copper) and transfers heat from the integrated circuit U4a to the external heat transfer portion of the jacket. For packages with multiple integrated circuits and high power density, & dissipation can cause problems. The heat pipe 470 capable of being connected to the inside of the package (10) or a plurality of devices allows internal generated heat to be transferred to the surface of the one or more outer ports P of the package. In Fig. 4C, for example, heat is conducted away from the integrated circuit 22 201034142 and flows to the top surface of the package 100, the bottom surface, and the heat flux portion 472 on the plurality of side surfaces. Multiple fins may also be placed on the top surface, bottom surface, side surfaces, and/or almost any exterior surface of the package. In the embodiment shown in the figures, for example, the heat dispersing plate 1 2 located on the bottom surface of the package 1 is thermally coupled to the heat pipe 47 and dissipates heat to the entire bottom surface area of the package 100. In one embodiment, all of the heat pipes in the package 10100, which are thermally coupled to a plurality of embedded integrated circuits, are also thermally coupled to the heat spreader plate i 02. In a variation of this embodiment, some of the heat pipes are also coupled to heat sinks on the top surface of the package. The heat pipe 470 can be formed using a process similar to that used to fabricate the interconnect layer 122. They may couple multiple passive and/or active devices within the package 1 and can extend in almost any direction within the package. In the embodiment shown in the figures, for example, the heat pipe 470 will extend in a direction parallel and perpendicular to certain planes in the plane formed by the photoimageable layers 1〇6. As shown in FIG. 4C, the heat pipe 470 may include thermally conductive lines 470b and 470d and/or channels 470a and 470c that pass through one or more interconnect layers 122 and/or photoimageable layers 1〇6. The heat pipes 470 are configured to dissipate heat, conduct electrical signals, or both. In one embodiment, an interconnect layer for transmitting electrical signals and a heat pipe unsuitable for transmitting electrical signals are embedded in the same epoxy layer. Another embodiment of the invention is illustrated in Figure 4E. Package arrangement 450 includes a microsystem 452 formed on top surface 46 of substrate 456. Micro 23 201034142 System 452 may contain multiple dielectric-X- « layered, active and/or passive devices, and may have a package 100 and/or Figure 4

Any of the feature elements described. The surface paste of micro (4) (5) and substrate W will be encapsulated in a material that can be molded into a molding material, such as: 敎^, ”, U to plastic. Multiple metals=W will be electrically Μ The bottom (4) of the bottom of the microsystem 452 (not shown) and the bottom surface (6) of the substrate 456. The channels 458 terminate the necessary material 462, which may be made of various conductor materials. In other words, solder balls 462 can be placed over the printed circuit board to provide electrical connections between the microsystem 452 and various external components. Figures 5A through 5B show the arrangement for establishing and ordering 4d. A cross-sectional view of a wafer-level process of the same package. Figure 5 shows a wafer 5 (10) having a top surface plate and a bottom surface pass. Only a small portion of the wafer 5 。 is shown. Shown is the projected cutting line. In the embodiment shown in the figures, the base may be made of a variety of suitable materials, such as: 矽. Ο In Figure 5B, wafer 500 The top surface 5〇2 will be etched away to form the hole (5) 506. The ', for example, electric (four) engraving technique is implemented using a variety of techniques. Metals are then deposited in the two holes to form an electrical system. This deposition can utilize any method of syndicating For example, a plating method (for example, a seed layer (not shown) may be deposited on the top surface 5〇2 of the wafer 5〇〇. Then, a metal may be utilized ( For example: copper) calls the seed layer. The electroplating process produces a metal pass 24 201034142 track 510 and a contact pad 5丨2 on the top surface 5〇2 of the wafer 500. In Figure 5D, the microsystem 513 utilizes The step of +镪夂 from the main 3L" which is identical to the above is formed on the top surface 5〇2 of the wafer 5〇〇. In our embodiment, the microsystem 513 1 does not have an external contact pad formed on its face 515 because the top surface 515 will be overmolded during operation. In another embodiment, an external contact pad may be formed on the top surface 515 for wafer level functional testing prior to in-light cladding molding. The microsystems (1) have external contact contacts on their bottom surface 517 which will contact the contact 512 on the top surface 502 of the crucible. This facilitates an electrical connection between the satellite channel 510 and the interconnect layers within the microsystems M3. In Fig. 5Et, a suitable mold forming material 520 is applied over the top surfaces of the microsystems 513 and the wafer. This _ Chengli process is enough to implement with a variety of appropriate technologies and materials. The result is a structure of a pound-molded wafer. In some designs, the molding material 520 will completely cover and encapsulate the microsystem (1) and the entire top surface of the domain 502 ° the molding of the molding material 52 可以 can provide additional mechanical support for the microsystem 513, when the microsystem This may be quite practical when the 513 is very big. Shown in Figure 5F is a cast s-day circle structure 522 after the bottom surface of the crystal IU 5 crucible is removed using any of a variety of suitable techniques (e.g., back grinding techniques). As a result, a portion of the metal channel 5 will be exposed in Figure 5G, and the solder balls 524 will be applied to the portions of the bare metal channel 25 201034142 510. In Fig. 5H, the molded line structure 522 is then formed by the cut line 508 that has been projected, H # π v ^, to create a plurality of individual package arrangements 526. The singulation process can be carried out using a variety of suitable methods (e.g., cutting or laser cutting).

Figures 6A through 6C are cross-sectional views showing a wafer leveling process for establishing a package in accordance with another embodiment of the present invention. Shown in Fig. 2 is a substrate _ in which a plurality of perforations 602 have been fabricated in advance. Shown in Figure 6B is the deposition of metal in the holes 602 to form a plurality of metal channels 6〇4. The deposition of metals can be carried out using any suitable technique (eg, m technique). In some embodiments, the substrate 600 will be fabricated with perforations 6〇2 and/or metal channels 604 in advance, thereby omitting one or more processing steps. In Figure 6C, a plurality of microsystems 606 are formed over the metal vias 604 and the substrate 600 using any of the foregoing techniques. Then, the embossing operation and the singulation can be carried out as shown in Figs. 5G and 5H. The embodiment shown in the figures may contain the same various features as those described in connection with Figures 5A through 5H. 7A through 7C are cross-sectional views showing a wafer leveling process for establishing a package in accordance with another embodiment of the present invention. A substrate 700 is initially provided. A plurality of copper contact pads 702 are then formed over the top surface of the substrate 7A. In Figure 7B, a plurality of microsystems 704 are formed over the copper contact pads 702 and the substrate 700 using any of the foregoing techniques. The microsystems 7〇4 and the top surface of the substrate 700 are then encapsulated in a suitable mold forming material 706. Next, in Figure 7C, the substrate 700 will be completely removed or removed. A plurality of solder bumps are then attached to the copper contact pads 702. The embodiment shown in Fig. 26 201034142 may contain the same various features as those described in connection with Figs. 5A through 5H. Additional embodiments of the invention are illustrated in Figures 8 through 1(R). These embodiments are directed to integrated circuit packages that embed one or more integrated circuits in a substrate (e.g., a germanium substrate). The buried integrated circuit is covered by a photoimageable epoxy layer. An interconnect layer will be formed over the epoxy layer and electrically coupled to the integrated circuit via one or more of the epoxy layers.埋 Embedding one or more integrated circuits in a substrate provides many advantages. For example, embodiments of the present invention include a buried integrated circuit that uses the substrate as a heat sink, an electrical conductor, and/or a medium for optical communication. When a wafer is used as the substrate, the same thermal expansion of the embedded integrated circuit and the tantalum substrate can reduce the risk of delamination. Embedding the integrated circuit in the substrate rather than the epoxy layer in certain modes of operation can help minimize the thickness of the epoxy layer and reduce the size of the package. φ Various examples of an integrated circuit package including a substrate having one or more buried integrated circuits will now be described with reference to Figs. 8A and 8B. 8A is an integrated circuit package 800 comprising: a substrate 804, an integrated circuit 802, an epoxy layer 806, and an interconnect layer 8丨2. Substrate 804 is preferably a lithographic wafer that is readily handled by existing semiconductor packaging equipment. However, depending on the intended use of the package 800, other suitable materials (e.g., glass, quartz, ..., etc.) may be used. The integrated circuit 802 is disposed inside the cavity 808 in the top surface of the substrate 8〇4. The active surface of the integrated circuit 802 and the top surface of the substrate 8〇4 are covered by an epoxy layer 806 of 201034142. The epoxy layer 8〇6 is made of a planarized, photoimageable epoxy resin (for example, su_8). The interconnect layer M2 will be formed over the epoxy layer 806. The interconnect layer 812 includes conductor traces 812b and conductor vias 812a that extend to the epoxy resin layer (4) σ 810 and electrically dissipate I/O (4) on the active side of the integrated circuitry 8〇2. The dielectric layer can be applied over the interconnect layer 812 without regard to the various implementations of adding more epoxy layers, integrated circuitry, and electrical devices. Solder contact pads may be formed on the outside of the package 800, and they may be connected to the integrated circuit 802 and the interconnect layer 812 via openings in the dielectric layer. Figure 8B shows another embodiment of the present invention comprising the provision of an additional layer of epoxy, integrated circuitry, and interconnects over substrate 8A4. The integrated circuit package 8〇1 includes a plurality of adjacent epoxy resin layers M2, interconnect layers 818, and integrated circuits 816, which are stacked on the interconnect layer η], the epoxy layer 806, and the integrated circuit. 802 and the top of the substrate 8〇4. Each of the integrated circuits 816 is disposed in at least one of the epoxy layers 822. The interconnect layer 818 is interspersed between the respective integrated circuits 816 ° and the epoxy layer 822. The interconnect layers 818 electrically connect the respective integrated circuits 802 and 816 to each other and electrically connect the integrated circuits 8〇2 and 816 to 1/(> formed on the top surface of the integrated circuit package 8〇1. Contact pad 824 ° It should be understood that Figures 8 and 8B represent particular embodiments from which many variations can be made. For example, there may be one or almost any number of integrated circuits disposed on the substrate. Inside or above 8〇4. 28 201034142 The arrangement of the interconnection layers t and lines, the placement and dimensions of the cavities and/or

with. In addition, the oxygen distribution of the ring: the thickness of the layer is W

It is also possible to combine any of the features and arrangements described in Figures 至/ to 7C with almost any point of view or with almost any point of view in 8B. Come to ^正图8A

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An exemplary method for forming the eight-eight 8B bulk circuit package of FIG. 8 will now be described with reference to FIGS. 9A through 9G. In Figure 9 "will provide - substrate - in a preferred embodiment, 'the substrate 9 〇 2 is a enamel wafer, as this can help maximize the operation of the Figure 9 and the semiconductor wafer Based on the compatibility of processing equipment. In an alternative embodiment, the substrate 9〇2 may be made of a wide variety of materials including: tantalum, glass, steel, G丨, quartz, ..., etc., depending on the needs of the particular application. . In FIG. 9A, a plurality of cavities 904 are formed in the substrate 9A2. Cavity 904 can be formed using wet or plasma etching, although other suitable techniques can be utilized. The chemical used in the etching process and the crystalline structure of the germanium in the substrate 902 can help control the angle of the sidewalls of the cavity 9〇4. For example, it has been discovered that the germanium crystal structure of [110] can help more straight sidewalls and/or help form a sidewall that is approximately perpendicular to the bottom surface of its corresponding cavity. A die attach adhesive 903 is applied to the bottom of the cavity 904 to help adhere the integrated circuit 906 to the bottom surface of the cavity 904 as shown in Figure 9C. In an alternate embodiment, the die attach adhesive 903 is first applied to the integrated body in an individual manner or in the wafer level prior to placing the integrated circuit 906 in the cavity 904. The back surface of circuit 906. Depending on the needs of the particular application, the die attaches to the adhesive 29 201034142

Ui or non-conductive. In some embodiments, the shank type of adhesive will be used simultaneously in the same package. The integrated circuit will electrically connect a conductive substrate via its bottom surface: the other will be electrically insulated from the substrate (below In the discussion of the conductive substrate, "the flattened, photoimageable epoxy layer 9" 8 in FIG. 9D will be accumulated in the cavities, the substrate 9 () 2, and the integrated circuits 9 Above the 〇6. Θ Epoxy layer _ preferably S SU-8, however, other suitable materials can also be used. The epoxy layer can extend over the active surface of the integrated circuit 〇9〇6 and The active surface of the integrated circuit 906 is directly contacted and can be filled into the cavity 904 in the substrate 902. As previously mentioned, one of the advantages of photoimageable epoxy (e.g., su_8) is utilized. A better degree of control can be achieved compared to its use of photolithography. In Figure 9E, one or more openings 91 are formed in the epoxy layer 908. The openings 91 can be familiar with A variety of ways known to those skilled in the art of semiconductor processing are produced. In this case, the epoxy layer 908 may be patterned by photolithography and a portion of the epoxy layer 908 may be dissolved by a developer solution 。. The openings 910 can be exposed to be buried in the epoxy layer. The I/O pads on the active surface of the integrated circuit 906 in 908. Figure 9F shows the formation of the interconnect layer 912, which can be implemented using various suitable techniques known in the art. One of the similar steps to the step of 3J includes: depositing a seed layer and a photoresist layer; patterning the photoresist layer; and electrically bonding a metal to form a conductor line in the openings 91 〇 30 201034142 912a and conductor channel 912b. In various embodiments, the interconnect layer 912 electrically connects a plurality of integrated circuit dies 906 embedded in the substrate 902. Then an additional epoxy layer 918, integrated Circuitry 922 and/or interconnect layer 916 can be formed over substrate 902, integrated circuit 906, epoxy layer 908, and interconnect layer 912. The layers and devices can be arranged in a variety of ways. And can be used in conjunction with Figures 1 to 7C Any arrangement and features are discussed to modify any of the aspects of the embodiments shown in the figures. For example, the one or more interconnect layers 912 and/or 916 can be used to electrically connect the substrate 902. The integrated circuit 906 and any or all of the integrated circuits 922 embedded in the epoxy layer 918. The heat transfer tubes suitable or unsuitable for transmitting electrical signals will be from the substrate-based integrated circuit crystals. The pellets 906 extend to any outer surface of the integrated circuit package 921. As previously described, various passive and active devices, heat pipes, heat sinks, sensors, etc. can be formed or placed in the integrated circuit. The package 921 is in almost any position (for example, in the substrate 9〇2, above the substrate 902, embedded between the epoxy layers 918, etc.). The s-substrate 902 may also be subjected to back grinding or any other operation suitable for reducing the thickness of the substrate 902. Figure 9G shows Figure 9F after an additional epoxy layer, interconnect layer, and integrated circuitry are applied over substrate 〇2, integrated circuit 906, epoxy layer 908, and interconnect layer 912. An example of an integrated circuit package. Shown in Figures 10A through 1D are additional embodiments of the present invention, each of which also includes a substrate having one or more buried integrated circuits. 31 201034142 FIG. 10A shows an integrated circuit package 1000 including a conductive and thermally conductive substrate 1002' having a buried integrated circuit 1〇〇4; a planarized, photoimageable epoxy layer 1006 And an interconnect layer 1〇〇8. The integrated circuit package 1000 can be formed using any of the techniques described in connection with Figures 9A through 9F. The integrated circuit 1 〇〇 4b is placed on the bottom surface of the ten-cavity 1〇〇5 of the substrate 1002 using the conductive adhesive 丨〇丨2t>. Therefore, the integrated circuit 1〇〇4b can electrically couple the substrate 1002 and/or can dissipate heat to the outer surface of the package using the substrate 1〇〇2. Some embodiments also include an integrated circuit 1004a that is electrically isolated from the conductor substrate ❹ 1002 by a non-conductive adhesive 1 〇 12a. In the embodiment shown in the figures, only two integrated circuits are shown; however, fewer or more integrated circuits may be disposed in the substrate 1〇〇2, each of which is electrically coupled to the respective ones. The substrate 1〇〇2 is either electrically insulated from the substrate 1002. In various embodiments, substrate 1 可 2 can serve as a conduit for achieving an electrical ground connection. The package 1000 includes a ground interconnection 1 〇 2 〇 which is formed over the epoxy layer 1006 and extends through the epoxy layer 1006 and is electrically coupled to one of the substrates 1 〇〇 2 Ground contact zone 〇 1014. The ground interconnect 1 2 is made of a conductive material (e.g., copper) and may have been formed at least partially during formation of the interconnect layer 1 08 as previously described in connection with Figure 9F. The ground contact regions 1〇14 and other portions of the substrate 1002 in the substrate 1002 are made of tantalum and may be doped to improve their conductivity. To facilitate electrical connection between the substrate 1002 and the ground interconnect 1020, the doping concentration of the ground contact region 1014 is substantially higher than a 32 201034142 or portions of the substrate 1〇〇2. In various implementations, the substrate 1〇〇2 is made of a p-type semiconductor material and the ground contact region 1014 is a p++ doped region; however, any suitable one known to those skilled in the art can also be utilized. The substrate and/or concentration are doped to the substrate 1〇〇2 and the ground contact region 1〇14. Thus, when the ground interconnect 1020 is electrically grounded, the integrated circuit 1004b, the substrate 1002, and the ground contact region 1〇14 are electrically coupled to the ground interconnect 1020 and are also electrically grounded. Figure 10B provides an enlarged view of a region 1010 of Figure a, in accordance with one embodiment of the present invention. The figure includes a substrate 1〇〇2 having a lower surface: a ground contact region 1014, an interlayer dielectric 1〇16, a passivation layer 1018, a conductive plug 1〇22, electrical interconnections 1024 and 1020, an epoxy layer 1006, and Ground interconnect 1020. Techniques known to those skilled in the art of semiconductor fabrication can be used to deposit, pattern, and/or develop interlayer dielectrics 16 and passivation layers 1018, and to form plugs 1022 and electrical interconnects 1024. Plug 1022 and electrical interconnect 1024 may be made of a variety of suitable conductive materials, including tungsten and aluminum, respectively. The epoxy layer 10 〇 6 and the interconnect 1 〇 2 〇 can be formed using various techniques including the techniques described in conjunction with Figures 9D through 9F. The technique for forming the interlayer dielectric 1 〇 16 and the passivation layer 1018 of Fig. 10B can be integrated into the technique for forming the cavity 1 〇〇 5 of Fig. 1A. For example, during formation of cavity 1005, interlayer dielectric 1μμ will be deposited across top surface 1003 of substrate 1002. The interlayer dielectric will be patterned and etched, not only to create the plugs. The space of 1 〇 22 is also used to form a reticle to form the cavity 1 〇〇 5 in the substrate 1002. This approach can help reduce the number of processing steps 33 201034142 used to fabricate integrated circuit packages. Another embodiment of the invention is illustrated in Figure 1c. Figure 1A includes an integrated circuit package 1030 that forms an integrated circuit, a planarized photoimageable epoxy layer, and an interconnect layer on both sides of a substrate. In the embodiment shown in the drawing, the integrated circuit 1036, the epoxy layer 1 〇 4 〇 and the interconnect layer 1038 are formed over the top end surface 1 〇 34 of the substrate 1 〇 32. The integrated circuit 1042, the epoxy layer 1 〇 44, and the interconnect layer 1 〇 46 are formed over the reverse bottom surface 1 〇 46 of the substrate 1032. One of the ways to form the integrated circuit package 1030 is to apply the techniques discussed in connection with Figures 9-8 to 9F on both the top and bottom surfaces of the substrate 〇32. One particular implementation of the integrated circuit package 1030 includes arranging a plurality of integrated circuits to optically communicate with one another via a light transmissive substrate. In the embodiment shown in the figures, for example, the integrated circuits 1036a and 1042a are vertically aligned with each other and include a plurality of optical devices, such as laser diodes, optical detectors, etc. (again, in In another embodiment, a plurality of optical devices (eg, optical sensors, optical detectors, lightning diodes, etc.) may be used in place of integrated circuits 1036a and/or 1042a). Portions 1034 of the substrate at least between the integrated circuits 1036a and 1042a are transmissive and are arranged to allow optical communication between the integrated circuits 310a and 1042a. The light transmissive substrate may be made of various materials including glass and quartz. Some modes of operation include a substrate 1032 that is completely argon and/or has a uniform composition from a single light transmissive material. Another way includes a substrate 1 〇 32 made of tantalum. The enamel substrate 34 201034142 1032 can electrically insulate the integrated circuits 310a and 1042a; however, for example, they are allowed to communicate optically using ultraviolet light (which can travel through the stone eve). Further, another embodiment of the present invention is illustrated in Fig. 10D. Illustrated in Figure 1A is an integrated circuit package 1050 having features for mitigating stresses embedded in one or more integrated circuits 1 〇 54 within the package substrate 1052. The integrated circuit package 1 〇 5 〇 includes a substrate φ 1052 having a lower surface: a cavity 1 〇 6 〇, an integrated circuit 1 〇 54, a photoimageable epoxy layer ι 56, and an interconnect layer 1058. Each cavity 1060 includes an air gap 1062 between the side wall 1064 of the cavity 1 〇 6 及 and the integrated circuit 1054. During the test and operation, the integrated circuit 1054 and the package 1 50 are subjected to temperature cycling. The increase in temperature may cause the integrated circuit 1〇54 to expand with other devices in the package 1050, and if the integrated circuit 1〇54 is encapsulated in a resilient material, the expansion may be Additional stress is imposed on the integrated circuit 1054. The air gap 1 〇 62 can provide space for the integrated circuit 1054 to expand and thereby help to reduce this stress. Accordingly, the epoxy layer 1056 covers the cavity 1060 but does not substantially extend into the cavity 1060. There are various ways in which the features of the integrated circuit package 1050 can be formed. For example, forming cavity 1060 in substrate 1052 and placing integrated circuit 1 〇 54 in cavity 1060 can be implemented as previously described in connection with Figures 9A through 9C. A layer of pre-fabricated photoimageable epoxy (e.g., SU-8) can then be applied to cover the cavity 1060 and the substrate 1052. In various embodiments, the epoxy layer 1056 is not sprayed and spin coated over the cavities 1060, but is laminated over the substrate 105 2 . This approach helps to retain the air gap 1 〇 62 between each of the integrated circuits and the side walls 1064 of the corresponding cavity 1060. Next, the formation of an opening in the epoxy resin layer 1056 and the interconnect layer 1 〇 58 can be performed in the same manner as the operation described in connection with Figs. 9E to 9F. For example, photolithography can be utilized to pattern the epoxy layer 1〇56, which can result in curing and/or removal of a portion of the epoxy layer 1056. Although the present invention has been described in detail herein, it should be understood that the invention may be embodied in many other forms without departing from the spirit and scope of the invention. For example, the various embodiments described herein sometimes illustrate unique and distinct features; however, the invention encompasses a wide variety of integrated circuit packages, each of which may contain the features of the 7G described herein. Almost any combination is formed using almost any combination of the processes described herein. Taking the substrate 8〇4 of the integrated circuit package 800 of FIG. 8A including one or more buried integrated circuits 802 as an example, it may further include a plurality of metal vias that pass through the substrate 8〇4 and allow each other. The layer 812 electrically connects the contacts on the outer surface of the substrate 8〇4. These metal channels are described in conjunction with Figure 4E. The process for fabricating the metal vias is as described with respect to Figures 5A through 5H and is equally applicable to the substrate 8A of Figure 8A. Therefore, the embodiments of the present invention should be construed as illustrative and not restrictive, and the invention is not limited to the details set forth herein. Correction ° [Simple Description of the Drawings] 36 201034142 With reference to the above description in conjunction with the accompanying drawings, the present invention and its advantages can be best understood, wherein: Figure 1 shows an implementation in accordance with the present invention. For example, a cross-sectional view of a package containing a plurality of integrated circuits and interconnect layers. 2 is a process flow diagram of a crystalline P-level process for packaging an integrated circuit in accordance with an embodiment of the present invention. 3A to 3L are cross-sectional views showing selected steps in the process of Fig. 2. © Figures 4A through 4E are cross-sectional views of the package in accordance with various alternative embodiments of the present invention. 5A through 5H are selected steps in a wafer level process for packaging integrated circuits in accordance with another embodiment of the present invention. Figures 6A through 6C illustrate selected steps in a wafer level process for packaging integrated circuits in accordance with another embodiment of the present invention. Figures 7A through 7C are selected steps in a wafer leveling process for packaging integrated circuits in accordance with yet another embodiment of the present invention. ® Figures 8A through 8B are cross-sectional views of packages in accordance with various embodiments of the present invention, each package including a substrate having a buried integrated circuit. 9A through 9G show selected steps in a wafer leveling process for forming a package in accordance with another embodiment of the present invention, each of which includes a substrate having a buried integrated circuit. 10A through 10D are cross-sectional views of a package arrangement in accordance with various embodiments of the present invention. In the drawings, the same component symbols are sometimes used to denote the same structural elements. It should also be understood that the greens depicted in the figures are only schematic representations of the drawings, and are not drawn to scale.

Claims (1)

201034142 VII. Patent application scope: 1. An integrated circuit package, comprising: a substrate having a top surface and a reverse bottom surface, wherein a first cavity is formed in the top surface of the substrate; An integrated circuit disposed in the first cavity in the top surface of the substrate; a curved, photoimageable first epoxy layer formed on the top surface of the substrate and the integrated body Above the active surface of the circuit, the first® epoxy layer has a substantially flat top surface; and a first interconnect layer comprising a plurality of interconnect lines formed in the first interconnect layer An active surface of the first integrated circuit is electrically connected to an epoxy layer. 2. The integrated circuit package of claim 1, wherein the substrate is made of at least one of the group consisting of 矽, G10-FR4, steel, copper, quartz, and glass. 3. The integrated circuit package of claim </ RTI> wherein the substrate is made of tantalum and one or more regions of the substrate are doped with a first doping concentration to cause the substrate It has electrical and thermal conductivity to help the integrated circuit transfer heat to the outer surface of the integrated circuit package. 4. The integrated circuit package of claim 3, wherein: the substrate comprises a ground contact region having a second doping concentration substantially greater than the first doping concentration, the ground contact region being disposed in the The top surface of the substrate; the integrated circuit package further comprising an interconnect line formed by a conductive material 39 201034142, the ground interconnect extending completely through the first epoxy layer and electrically connected to the substrate The ground contact region; and the first integrated circuit includes a ground contact electrically coupled to the one or more doped regions in the substrate, wherein the ground interconnect, the substrate The ground contact region, the ground contact on the first integrated circuit, and the one or more doped regions of the substrate are arranged to be electrically grounded and electrically coupled to each other. [5] Integrated circuit package, further packaged Included: a second cavity in the substrate; a second integrated circuit disposed in the second cavity, the second integrated circuit is attached to the non-conductive die attaching adhesive a substrate, wherein the second integrated circuit is electrically insulated from the conductor substrate, wherein the first integrated circuit is attached to the substrate through the conductive die attaching adhesive, thereby electrically (four) the [integrated circuit With the conductor substrate. 6. The integrated circuit package of claim 1, wherein the substrate is at least partially made of a light transmissive material and the first integrated circuit comprises a first optical device, the integrated circuit package further comprising a second cavity in the bottom surface of the substrate; a second integrated circuit disposed in the second cavity, the second integrated circuit disposed in a reverse of the first integrated circuit And comprising a second optical device arranged to optically ventilate the first optical device in the first-stack circuit via a light-transmissive raft of the substrate. 40 201034142 Above the base surface; a second curved layer of epoxy resin, a photoimageable second epoxy layer, an active surface of the second integrated circuit, and a second interconnect layer comprising a plurality of interconnects And a second interconnect layer formed over the second epoxy layer and electrically connected to the active surface of the second integrated circuit. 7. The integrated circuit package of claim 6, wherein the substrate is made of Shi Xi; and the first optical device communicates with the second optical device to facilitate the passage of the dream substrate. Optical communication between the two optical devices. The first optical device of the first aspect of the invention, wherein the sidewall of the first cavity and the second cavity disposed in the first cavity are disposed. There is an air gap between the integrated circuits, so that the first integrated circuit has a space to expand in the first cavity. 9_ The integrated circuit package of claim </ RTI> wherein: the substrate comprises a plurality of cavities; a plurality of integrated circuits are respectively disposed in the plurality of cavities; and the first interconnect layer is electrically coupled One or more of the plurality of integrated circuits are connected. 10. The integrated circuit package of claim 1, further comprising: a plurality of closely adjacent stacked cured, 201034142 planarized, photoimageable epoxy layers formed over the substrate; The interconnect layer, each of the plurality of interconnect layers comprises at least one conductor line and at least one conductive suspension iS, a bitter channel and formed over one of the plurality of epoxy layers The first plurality of integrated circuits are respectively disposed in a plurality of cavities in the substrate; and the second plurality of integrated circuits are arranged in a fine manner. ,, in order to be embedded in one of the related layers of the epoxy layer, the active surface of each of the first plurality of integrated circuits is disposed in the furnace One of the associated layers of the epoxy layer is covered. &quot;If you apply for a patent scope! The integrated circuit package of the item, wherein the substrate comprises at least one of the group consisting of: one or more conductor channels that pass completely through the substrate and terminate on the bottom surface of the substrate - external contact pad and electrically coupled to the first interconnect layer; 2) - photovoltaic cells; 3) a biological) biosensor / 4; a gas sensor; 5) accelerated sensing 6) a vibration sensor; 7) a chemical ❹ sensor...-electromagnetic sensor; 9) a temperature sensor; and... a humidity sensor. 12. The integrated circuit package of claim </RTI> wherein the first epoxy layer is planarized. 〆 13. The integrated circuit package of claim </ RTI> wherein the substrate is a enamel wafer and the epoxy resin is SU-8. I4. A method for packaging an integrated circuit, the method comprising: providing a substrate comprising a top surface and a reverse bottom surface; 42 201034142 Aligning the first plate of the first surface of the cured, photoimageable surface with the active surface of the first integrated circuit; patterning the first epoxy layer by photolithography; Forming one or more open epoxy layers in the resin layer deposited on the substrate, forming a first interconnect layer over the first integrated circuit and inside the first opening, and causing the first opening; and the ring The one interconnect layer of the oxy-resin layer includes at least one conductor line and at least one conductor channel. 15: The method of claim 14, wherein: the substrate is made of at least one of the group consisting of: 矽, G10-FR4, steel, quartz, copper, and glass; The epoxy layer is made of SU-8; and the etching of the substrate comprises one of a group consisting of wet etching and plasma etching. 16. The method of claim 14, further comprising: applying a die attaching an adhesive to the first layer before disposing the first integrator circuit in the first cavity of the substrate. A bottom surface of the Longdian $, the bottom of the fish Adhesive is applied to the bottom of the first cavity in the substrate. 18. The method of claim 14, wherein the forming the one or more openings in the first 43 201034142 ring latex layer comprises dissolving the first epoxy layer in a developer solution t a portion to form the one or more openings in the first epoxy tree layer. 19. The method of claim 14, further comprising: sequentially depositing a second epoxy layer over the substrate to form a plurality of planarized epoxy layers over the substrate, wherein Depositing the second epoxy layer comprises one of a group consisting of spin coating and dip coating; 图 patterning at least some of the second epoxy layers by photolithography a second epoxy layer; after at least some of the second epoxy trees (four) are patterned, and in the next pick-up, the next first epoxy resin Forming a plurality of openings in at least some of the second epoxy layers in the enamel layer of the enamel layer before the layer is deposited; 〇 placing a second integrated circuit Inside the associated opening of the openings, wherein the (four) two-long circuit has a plurality of I/Q solder contacts and at least one of the second layer of the nano-alkaline resin is disposed on the second integrated circuit And then deposited to cover the third integrated circuit; a second-second interconnect layer, wherein each of the second interconnect layers is formed over an associated second epoxy layer; and a plurality of external package contacts are formed, wherein the second integrated body The circuit and the first bank circuit are electrically connected to the plurality of the external package contacts at least in part via the first interconnect layer and the at least one first interconnect layer. The method of claim 14, wherein the substrate at least 44 201034142 comprises a first portion made of a light-emitting material and the first integrated electro-optical sensor, the method further comprising: Etching the bottom surface of the substrate to form a second cavity; placing a second integrated circuit in the second cavity, the first circuit comprising a second optical sensor and being disposed in the first - the opposite of the integrated body '俾 such that the first optical sensor and the second optical sensor are capable of optical communication via a light transmissive portion of the substrate; b 〇 on the substrate and the second product The upper surface of the active surface of the bulk circuit - the second photoimageable epoxy layer '丨, the second epoxy layer is deposited by using a group consisting of spin coating and spray coating π patterning the second epoxy layer by photolithography; forming one or more openings in the second epoxy layer; and above the second integrated circuit and the second ring The openings of the oxyresin layer form a second interconnect layer The second interconnect layer includes at least Φ a conductor line and at least one conductor channel. The method of claim 14 further includes using a thermally conductive and electrically conductive die attach adhesive to a first integrated circuit is attached to the substrate, wherein the substrate is made of tantalum and one or more regions of the substrate are doped with a first doping concentration to make the substrate conductive and thermally conductive And thereby assisting the integrated circuit to transfer heat to the outer surface of the integrated circuit package through the substrate. 22. The method of claim 21, wherein: the substrate comprises a ground contact region having a second doping concentration substantially greater than a doping concentration of the first 45 201034142, the ground contact region being disposed on the substrate Forming the top surface; forming the one or more openings in the first epoxy layer to form a ground interconnect opening directly over the ground contact region in the substrate; and the method further comprising utilizing a Conducting material to fill the ground interconnect opening to form a ground interconnect including a conductor via that extends completely through the first epoxy layer and electrically connected to the ground in the substrate Contact area. 0. The method of claim 22, further comprising: applying an interlayer dielectric to the substrate prior to depositing the first epoxy layer; applying over the interlayer dielectric a purification layer; forming a plurality of openings in the interlayer dielectric and the passivation layer; and filling the openings with one or more conductor materials to form a one that is electrically coupled to a ground contact region in the substrate Or a plurality of electrical contacts, wherein the depositing of the first epoxy layer comprises depositing the first epoxy layer over the interlayer dielectric and the passivation layer, and the top surface of the substrate is money The interlayer dielectric is used as a mask to pattern the substrate and to help form the first cavity in the substrate. 24. The method of claim 14, wherein the deposition of the first epoxy resin layer comprises one of a group consisting of a spray coating method and a spin coating method. 25. The method of claim 14, wherein the first epoxy 46 201034142 tree layer is pre-engineered to produce a first-ring L-shaped workpiece, and wherein the prior epoxy resin is substantially deposited Above the first cavity, the integrated circuit and the first cavity are provided to help trap the gap between the first and the side walls of the first cavity so that the first integrated circuit has &quot ; ' ― Work wind gap, the empty compensation 遛 1: The road has a work room to expand in the first cavity. 26. The method of claim 14, which comprises back grinding the substrate. 27. The method of claim 14, wherein the substrate is made of Shi Xi and has a crystal structure of [1, 1, 〇], and wherein the etching of the substrate is utilized with the stone The crystal structure of the cermet substrate is reacted by a chemical agent that reacts. The method of claim 14, wherein the first epoxy resin layer is planarized. Eight, the pattern: (such as the next page) 47