CN103871914B - 制作层堆叠的方法 - Google Patents

制作层堆叠的方法 Download PDF

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CN103871914B
CN103871914B CN201310678119.XA CN201310678119A CN103871914B CN 103871914 B CN103871914 B CN 103871914B CN 201310678119 A CN201310678119 A CN 201310678119A CN 103871914 B CN103871914 B CN 103871914B
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layer
substrate
thickness
stacked
scope
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CN103871914A (zh
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P.加尼策尔
M.哈里逊
K.马托伊
M.施波恩
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Infineon Technologies AG
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Abstract

制作层堆叠的方法。在一个实施例方法中，第一Ti基层被沉积在衬底上。中间的Al基层被沉积在第一层上，第二NiV基层被沉积在中间层上，并且第三Ag基层被沉积在第二层上。该层堆叠以这样的方式即在包含Ti，Al，Ni和V的组的至少两个金属之间形成至少一个金属间相来被回火。

Description

制作层堆叠的方法
技术领域
本发明涉及在衬底上制作层堆叠的方法、电子模块和层堆叠。
背景技术
焊接是其中两个或更多个部件，例如金属部件，通过熔化和将焊料材料流入接头处而结合到一起的过程。半导体芯片，例如功率半导体芯片可以通过使用焊接方法被安装在衬底或其它半导体芯片上。然而，在焊接期间可以在接头处的任一侧使用的两个或更多个金属材料之间形成金属间相。这些所得到的金属间相可能结果证明具有抗蚀性，其不足够高，使得在最坏的情况下整个焊料连接可能断开。因此，存在对提供稳定的且永久可靠的焊料连接的持续的需要。
附图说明
附图被包括用以提供对实施例的进一步的理解并且被并入和构成该说明书的一部分。这些图示出实施例并且与描述一起用来解释实施例的原理。将容易领会其它实施例和实施例的多个预期的优点，因为参考以下详细描述它们将变得更好理解。这些图的元件不一定相对于彼此按比例。相似的参考数字表示相应的相似部分。
图1示出用于说明根据实施例用于在衬底上制作层堆叠的方法的流程图；
图2A-2D示出用于说明根据实施例在衬底上制作层堆叠的方法的示意截面侧视图表示；和
图3示出根据实施例的电子模块的示意截面侧视图表示。
具体实施方式
现在参照各图描述各方面和实施例，其中从头到尾相似的参考数字通常用来指代相似的元件。在下面的描述中，为了解释的目的，许多特定的细节被阐述以便提供对实施例的一个或多个方面的透彻理解。然而，对于本领域技术人员来说，可以显然的是实施例的一个或多个方面可以以更少程度的特定细节来被实施。在其它实例中，以示意的形式示出已知结构和元件以便便于描述实施例的一个或多个方面。应该理解在不脱离本发明的范围的情况下，可以利用其它实施例并且可以作出结构或逻辑变化。应该进一步注意到各图不是按比例或者不必要按比例。
另外，虽然可以相对于几个实施方式中的仅一个来公开实施例的特定特征或方面，但是在对于任何给定的或特定的应用可以是所需的和有利的时，这样的特征或方面可以与其它实施方式的一个或多个其它特征或者方面相结合。此外，就在详细的描述或者权利要求中使用的术语“包括”，“具有”，“有”或者其其它变体来说，这样的术语以与术语“包含”相似的方式旨在是包括一切的（inclusive）。可以使用术语“耦合”和“连接”以及派生词。应该理解这些术语可以被用来表示两个元件互相协作或互相作用，不管它们是直接物理或电接触，还是它们不是互相直接接触。而且，术语“示例性的”仅意指作为示例，而不是最好的或最佳的。因此，下面详细的描述不是在限制性意义上来进行的，并且本发明的范围被所附权利要求限定。
电子模块的实施例和在衬底上制作层堆叠的方法可以使用各种类型的衬底，尤其是半导体芯片或并入在半导体芯片中的电路，在它们之中有逻辑集成电路，模拟集成电路，混合信号集成电路，传感器电路，MEMS（微机电系统），功率集成电路，具有集成无源器（integrated passives）的芯片等。实施例也可以使用半导体芯片，所述半导体芯片包括MOS晶体管结构或者垂直晶体管结构，比如例如，IGBT（绝缘栅双极晶体管）结构或者通常是其中至少一个电接触焊盘被布置在半导体芯片的第一主面上并且至少一个其它电接触焊盘被布置在与半导体芯片的第一主面相对的半导体芯片的第二主面上的晶体管或其它结构或器件。
在几个实施例中，层或者层堆叠被施加到彼此或者材料被施加或者沉积到层上。应该领会到任何这样的术语如“被施加”或者“被沉积”意味着字面上覆盖将层施加到彼此之上的所有种类和技术。特别地，它们意味着覆盖其中各层作为整体被同时施加的技术，比如，例如层压技术以及其中层以顺序的方式被沉积的技术，比如，例如溅射，电镀，模塑，CVD等。
半导体芯片可以包括在其外表面的一个或多个上的接触元件或接触焊盘，其中接触元件用于电接触半导体芯片。接触元件可以具有任何所需的形式或形状。它们可以例如具有接触面（land）的形式，即在半导体芯片的外表面上的平的接触层。可以由任何导电材料，例如由金属（诸如如铝，金，或铜）或者金属合金，或者导电有机材料，或者导电半导体材料来制成接触元件或者接触焊盘。
在权利要求中并且在下面的描述中，尤其在流程图中，用于制作电子部件的方法的不同实施例被描述为特定顺序的工艺或者测量。应该注意到实施例不应被限制到描述的特定顺序。不同工艺或者测量的特定的一些或者全部也可以同时地或者以任何其它有益的和适当的顺序来进行。
图1示出用于说明根据本公开的第一方面在衬底上制作层堆叠的方法的流程图。方法100包括提供衬底（方框110），在衬底上沉积第一Ti基层（方框120），在第一层上沉积中间的Al基层（方框130），在中间层上沉积第二NiV基层（方框140），在第二层上沉积第三Ag基层（方框150），并且以在包含Ti，Al，Ni，和V的组中的至少两个金属之间形成至少一个金属间相的方式回火（方框160）。
根据第一方面的方法的实施例，第一层通常由纯Ti构成，中间层通常由纯Al构成，第二层通常由纯NiV构成，并且第三层通常由纯Ag构成。
根据第一方面的方法的实施例，以包括Ni和Al形成金属间相的方式来执行回火。
根据第一方面的方法的实施例，衬底可以包括半导体芯片，尤其是硅芯片。半导体芯片可以包括电子器件，该电子器件包括晶体管，功率晶体管，MOS晶体管，SFET晶体管，垂直晶体管，和绝缘栅双极晶体管（IGBT）中的一个或多个。
根据第一方面的方法的实施例，层堆叠被沉积在衬底的主表面的一个上。根据其实施例，层堆叠可以被沉积在衬底的整个主表面上。然而，层堆叠仅被沉积在衬底的主表面的预定部分上也是可能的。预定部分可以由设置在衬底中的电器件的电接触端子，尤其是晶体管的接触端子（比如源极，漏极和栅极接触端子）构成。
根据第一方面的方法的实施例，第一Ti基层被沉积具有在从100nm-400nm的范围中的厚度。
根据第一方面的方法的实施例，第二NiV基层被沉积具有在从200nm-400nm的范围中的厚度。
根据第一方面的方法的实施例，中间层被沉积具有在从30nm-50nm的范围中的厚度。
根据第一方面的方法的实施例，第三层被沉积具有在从200nm-600nm的范围中的厚度。
根据第一方面的方法的实施例，中间层和第一至第三层中的一个或多个通过溅射被沉积，尤其是在同一个反应室内。
根据第一方面的方法的实施例，在从300℃-400℃的温度范围中并且对于在从20分钟-40分钟的范围中的持续时间执行回火。
根据第一方面的方法的实施例，通过使用剥离方法来沉积层堆叠。特别地，牺牲层比如，例如，光致抗蚀剂层可以被沉积在不同于预定部分的部分中的衬底上，该层堆叠可以被沉积在预定部分中的衬底上和牺牲层上，并且然后去除牺牲层以便层堆叠仅保留在预定部分上。
根据第一方面的方法的实施例，层堆叠适用蚀刻工艺，例如湿法蚀刻工艺。首先层堆叠可以被沉积在整个衬底表面上，然后掩模层可以被沉积在预定部分上，其中掩模层原则上可以由包括对衬底表面，尤其对金属表面的良好粘附特性的任何材料制成。掩模层可以例如包括光敏抗蚀剂。然后可以使用蚀刻工艺来去除层堆叠的未掩蔽部分。对于蚀刻工艺，可以使用湿法蚀刻介质，其中使用用于蚀刻层堆叠的不同金属的不同蚀刻介质（例如用于蚀刻Ti的氟化氢）可能是必需的。原则上也可以使用干法蚀刻如，例如用于蚀刻未掩蔽部分的等离子体蚀刻或反应离子蚀刻。
图2A-2D示出示意截面侧视图表示，用于说明根据实施例在衬底上制作层堆叠的方法。图2A示出可以由半导体芯片，尤其是硅芯片构成的衬底10。衬底10可以包括电器件，比如晶体管，功率晶体管，MOS晶体管，SFET晶体管，垂直晶体管和IGB晶体管中的一个或多个。在任何情况下，电器件可以包括在衬底10的主面处的电接触端子10A和10B。电接触端子10A和10B可以由衬底10的掺杂区构成。其旨在将电接触层选择性地沉积在电接触端子10A和10B上。
为了这个目的，如在图2B中所示，牺牲模版层20，尤其是光致抗蚀剂层被沉积在衬底10的表面上并且然后通过在电接触端子10A和10B上面的牺牲层20中蚀刻开孔来在牺牲层20中产生反转图案（inverse pattern）。
然后，如在图2C中所示，层堆叠30被沉积在整个区的上方，从而覆盖电接触端子10A和10B并且也留在那些区域中的牺牲层20的顶部，在那里没有预先蚀刻牺牲层20。层堆叠30由第一Ti基层31，中间Al基层32，第二NiV基层33，和第三Ag基层34构成。第一层的厚度可以在从200nm-400nm的范围中，中间层的厚度可以在从30nm-50nm的范围中，第二层的厚度可以在从200nm-400nm的范围中，并且第三层的厚度可以在从400nm-600nm的范围中。
然后，如在图2D中所示，牺牲层20被冲走。特别地，在光致抗蚀剂作为牺牲层的情况下，适当的溶剂可被用来去除光致抗蚀剂。因此，在牺牲层区域的顶部上的层堆叠的材料被剥离并且与下面的牺牲层一起被冲洗。在剥离之后，层堆叠仅保留在电接触端子10A和10B的区域中。
然后可以在350℃将回火或者退火工艺执行30分钟以便全部或者至少部分的中间层32的Al被转换为金属间相比如，例如Al-Ni金属间相。这些金属间相可以稍后在焊接工艺中用作对Sn的阻挡，其中Sn是被使用的一个或者主要焊接材料。这样可以防止在界面处的腐蚀。
图3示出根据本公开的第二方面的电子模块的示意性截面侧视图表示。电子模块200包括衬底210和布置在衬底210上的层堆叠220。层堆叠220包括设置在衬底210上的第一Ti基层221，设置在层222上的第二NiV基层223，和设置在第二层223上的第三Ag基层224。
根据第二方面的电子模块的实施例，在第一和第二层221和223之间的中间层222包含在包含Ti，Al，Ni，和V的组的至少两个金属之间的至少一个金属间相。根据其实施例，中间层222包含包括Al和Ni的金属间相。
根据第二方面的电子模块的实施例，衬底210包括硅。特别地，衬底210包括半导体芯片比如硅芯片。衬底可以包括在衬底210中或者在衬底210上的电子器件，其中电子器件可以是晶体管，功率晶体管，MOS晶体管，SFET晶体管，垂直晶体管和IGBT晶体管中的一个或多个。衬底厚度可以在从50μm-300μm的范围中。
根据第二方面的电子模块的实施例，衬底210可以包括电接触端子210A和210B，其可以由衬底的掺杂区构成并且其可以由在衬底210中或在衬底210上设置的电器件的电接触端子构成。层堆叠320可以被选择性地设置在电接触区210A和210B上。
根据第二方面的电子模块的实施例，层堆叠220可以被设置在衬底210的整个主表面上面或者上方。然而，层堆叠220也可以被设置在衬底210的主表面的预定部分比如，例如电接触端子210A和210B上面或上方。
虽然已经相对于一个或多个实施方式示出和描述了本发明，但是在不脱离所附权利要求的精神和范围的情况下，可以作出对图示示例的改变和/或修改。尤其关于由上面描述的部件或结构（组件，器件，电路，系统等）所执行的各种功能，除非另外表明，用来描述这种部件的术语（包括对“装置”的引用）旨在对应于执行所描述部件的指定功能的任何部件或结构（例如，其是功能上等同的），即使结构上不等同于执行本发明于此示出的示例性实施方式中的功能的公开结构。

Claims (17)

1.一种制作衬底的层堆叠的方法，所述方法包括：
在衬底上沉积具有在从100nm到400nm的范围中的厚度的第一Ti基层；
在第一层上沉积具有在从30nm到50nm的范围中的厚度的中间的Al基层；
在中间层上沉积具有在从200nm到400nm的范围中的厚度的第二NiV基层；
在第二层上沉积具有在从200nm到600nm的范围中的厚度的第三Ag基层；
其中，中间层中的Al利用选自由Ti，Ni，和V构成的组的金属通过回火部分地被转换成金属间相。
2.根据权利要求1的方法，其中所述衬底包括Si。
3.根据权利要求1的方法，其中所述第一层，第二层，第三层和所述中间层中的一个或多个通过溅射被沉积。
4.根据权利要求1的方法，其中在从300℃—400℃的温度范围中并且对于从20分钟-40分钟的持续时间执行回火。
5.根据权利要求1的方法，其中使用剥离方法沉积层堆叠。
6.根据权利要求1的方法，其中所述层堆叠被沉积在所述衬底的预定部分上。
7.根据权利要求6的方法，进一步包括：
将牺牲材料沉积在不同于所述预定部分的部分中的所述衬底上；
将所述层堆叠沉积在所述预定部分中的所述衬底上和所述牺牲层上；以及
去除所述牺牲层。
8.根据权利要求6的方法，其中所述预定部分包括电器件的电接触端子。
9.根据权利要求1的方法，其中所述层堆叠被沉积在所述衬底的整个表面上。
10.一种电子模块，包括：
衬底；
被设置在所述衬底上的层堆叠；
其中所述层堆叠包括：
第一层，其中所述第一层包含Ti并且具有在从100nm到400nm的范围中的厚度；
沉积在所述第一层上的中间层，其中所述中间层包含Al并且具有在从30nm到50nm的范围中的厚度，其中所述Al利用选自由Ti，Ni，和V构成的组的金属部分地被转换成金属间相；
沉积在所述中间层上的第二层，其中所述第二层包含NiV并且具有在从200nm到400nm的范围中的厚度；以及
沉积在所述第二层上的第三层，其中所述第三层包含Ag并且具有在从200nm到600nm的范围中的厚度。
11.根据权利要求10的电子模块，其中所述衬底包括Si。
12.根据权利要求10的电子模块，进一步包括在所述衬底中或在所述衬底上的至少一个电子器件。
13.根据权利要求12的电子模块，其中所述电子器件包括功率晶体管，MOS晶体管，SFET晶体管，垂直晶体管，和绝缘栅双极（IGB）晶体管中的一个或多个。
14.根据权利要求10的电子模块，其中所述层堆叠仅被布置在所述衬底的主表面的预定部分上。
15.根据权利要求14的电子模块，其中所述预定部分包括电器件的电接触端子。
16.根据权利要求10的电子模块，其中所述层堆叠被布置在所述衬底的整个主面上。
17.一种层堆叠，包括：
第一层，其中所述第一层包含Ti并且具有在从100nm到400nm的范围中的厚度；
设置在所述第一层上的中间层，其中所述中间层包含Al并且具有在从30nm到50nm的范围中的厚度，其中所述Al利用选自由Ti，Ni，和V构成的组的金属部分地被转换成金属间相；
设置在所述中间层上的第二层，其中所述第二层包含NiV并且具有在从200nm到400nm的范围中的厚度；和
设置在所述第二层上的第三层，其中所述第三层包含Ag并且具有在从200nm到600nm的范围中的厚度。
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