CN102037370A - 制造和测试集成电路的方法 - Google Patents

制造和测试集成电路的方法 Download PDF

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CN102037370A
CN102037370A CN2009801183492A CN200980118349A CN102037370A CN 102037370 A CN102037370 A CN 102037370A CN 2009801183492 A CN2009801183492 A CN 2009801183492A CN 200980118349 A CN200980118349 A CN 200980118349A CN 102037370 A CN102037370 A CN 102037370A
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pad
integrated circuit
conductive
path part
layer
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罗曼·科菲
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STMicroelectronics Grenoble 2 SAS
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STMicroelectronics Grenoble 2 SAS
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Abstract

一种制造和测试集成电路的方法，包括步骤：在集成电路(1)的上部上面形成钝化层(19)，该钝化层在集成电路的最终互连叠层的金属路径(17)的位置包含有开口；在开口中形成第一垫(11)，第一垫通过导电路径部分连接到形成在钝化层上的第二垫(13)，第一垫是为了集成电路的连接而设置的；通过使测试头接触第二垫测试集成电路；并且去除至少一个导电路径部分的至少一部分。

Description

制造和测试集成电路的方法
技术领域
本发明涉及一种制造和测试集成电路的方法，更具体地，涉及一种直接在半导体晶片上测试集成电路并且为封装这些集成电路作准备的方法。
背景技术
通常，形成在半导体晶片上的集成电路直接在晶片上进行第一次测试。此测试通过放置在集成电路的接触垫上并且可以电性测试该电路的测试头来进行。然后，连接元件(例如，其上形成有导电凸块的导电结合层)被形成在接触垫上。在此之后，集成电路被切割成芯片并且有缺陷的芯片被淘汰。最后，集成电路被放置在支承体上并且封装好。在此封装步骤之后通常进行第二次测试。
在这里考虑属于表面贴装元件(SMC)类的，更具体地，属于倒装集成电路芯片组件类的集成电路。
在对尚未切割的晶片进行测试时，测试头被按压在形成于集成电路一个表面上的接触垫上。这样的按压有缺点，即在接触垫上形成刮痕，而刮痕可能导致形成在接触垫上的连接元件产生可靠性问题。当集成电路的尺寸减小从而分配给接触垫的尺寸也减小的情况下，此问题会格外严重。
为了克服这个问题，已经提出了应用由两部分构成的接触垫。第一部分，这里称为测试垫，用作为测试头按压区域，另一部分，这里称为连接垫，提供给将要与支承体上的集成电路芯片连接的连接元件组件。这样，由测试头按压形成的刮痕位于测试垫位置，这些测试垫此后不再用。因此，在连接垫位置，芯片和连接元件之间的接触得到了保证。
然而，由两个单体垫(elementary pads)构成的接触垫具有相对较大的表面积，应用这样的接触垫在考虑到射频电路(即工作于800MHz以上频率的电路或具有高切换频率的电路时)是个问题。
确实，与连接垫被偏置于同一电压的测试垫，形成了天线，或者至少与集成电路中紧邻接触垫或在所述垫下层的元件形成了寄生电容和电感。
为了避免在电路中形成寄生元件的问题，有一个解决办法即当探测结束后使测试垫和连接垫分离。日本专利申请JP 02241046提出了这一解决办法，测试垫和连接垫在探测后被“割开”，然而，这样的切割需要额外的制作步骤，例如激光切割。较为理想的是不增加制作步骤的数目即能实现这样的分离。
发明内容
因此需要一种能避免上述问题的集成电路制造和测试方法。
为达此目的，本发明的一个实施例提供了一旦在集成电路晶片上实施了测试即使测试垫从连接垫分离。
更具体地，本发明的一个实施例提供了一种将测试垫和连接垫分离的具体方法，此方法相对于已知方法来说不需要增加所实施步骤的数目，此方法特别适用于集成电路芯片通过导电凸块连接于支承体的情况。
因此，本发明的一个实施例提供了一种制造和测试集成电路的方法，包括步骤：在集成电路的上部上面形成钝化层，该钝化层在集成电路的最终互连叠层的金属路径的位置包含开口；在开口中形成第一垫，第一垫通过导电路径部分连接到形成在钝化层上的第二垫，第一垫是为了集成电路的连接而设置的；通过使测试头接触第二垫测试集成电路；去除至少一个导电路径部分的至少一部分。
根据一个实施例，去除至少一个导电路径部分的至少一部分包括步骤：在结构上沉积多层导电叠层；并且蚀刻该多层叠层，但不蚀刻第一垫的上方，所述蚀刻也移除了导电路径部分的材料，由此第一垫和第二垫被分离。
根据一实施例，在蚀刻多层导电叠层的步骤之后，该方法进一步还包括，在多层叠层的余留部分上形成导电凸块的步骤，其后还有将集成电路切割成芯片的步骤。
根据一实施例，第一垫和第二垫由多层形成，第二垫的所述层中至少一层与导电路径部分的材料在不同时间移除。
根据一实施例，导电路径部分以及与连接垫接触的多层叠层的第一层由铝形成。
根据一实施例，多层叠层由三层构成。
根据一实施例，与第一垫接触的多层叠层的第一层由选自铝、钛、钛钨合金、铬、钽、银和金构成的组的材料形成，多层叠层的第二层由选自钒/镍、氮化钛、氮化钽、镍、钒、铬和铜构成的组的材料形成，并且多层叠层的第三层由选自铜、钯、金和银构成的组的材料形成。
根据一实施例，第一垫的形状是六边形。
根据一实施例，钝化层的材料选自BCB(苯并环丁烯)、氮化硅和PI(聚酰亚胺)构成的组。
本发明的一个实施例进一步提供了一种集成电路，该集成电路包括上部，在该上部中形成有金属路径、并且在上部上形成有在金属路径上方包含有开口的钝化层，该集成电路还包括形成在开口中、金属路径上的第一垫，以及形成在钝化层上的第二垫，第一垫和第二垫通过导电路径部分连接，其中至少一个导电路径部分的至少一部分不存在。
另一实施例提供了一种系统，其包括至少一个如上所述的集成电路以及至少一个其它电子元件。
根据一实施例，该系统集成在手机里。
本发明的前述目的、特性和优点将结合附图在以下对具体实施例的非限制性描述中详细论述。
附图说明
附图1是集成电路芯片和支承体之间的连接的一个例子的截面图；
附图2是例如像附图1中的集成电路芯片倒装之前的顶视图；
附图3是由两部分形成的接触垫的顶视图；
附图4是示出了附图3的接触垫上形成连接元件之后得到的结构的截面图；
附图5A到5G是示出了根据本发明的实施例测试集成电路的步骤的截面图，附图5B是附图5A的一部分的放大图；并且
附图6示出了根据本发明实施例的系统。
具体实施方式
为了清楚起见，不同附图中的同样的部件用同样的附图标记标注，并且，按照对集成电路的惯常表示法，各附图并非按规定比例绘制。
附图1是集成电路芯片和封装支承体之间的连接的一个例子的截面图。
在倒装型集成电路芯片1的接触垫上形成有很多连接元件3，即，示例中的球。芯片1通过设在支承体5的接触垫上的连接元件3连接于支承体5。包围不同的连接元件3的密封层7形成在集成电路芯片1和支承体5之间，密封层7使得这些元件彼此绝缘，同时还避免了湿气到达连接元件3。
附图2是例如像附图1中这种集成电路芯片倒装在基板5上之前的顶视图。
在附图2中，示出了芯片表面的连接元件的一种可能的排列。在芯片1上形成有很多接触垫，这些接触垫将要承接使芯片和支承体接触的连接元件3。在附图2的例子中，两排接触垫形成在芯片外围。接触垫的排列方式可能有多种。例如，可以在集成电路芯片1的整个表面都形成接触垫，或者在芯片表面的外围形成单排接触垫。
附图3是由两部分形成的接触垫的例子的顶视图。
形成在集成电路1上的接触垫包括两部分，其上将要形成连接元件的连接垫11，以及在电测试中测试头将要按压在其上的测试垫13。连接垫和测试垫通过导电路径15相连。在附图3所示的例子中，连接垫11是六边形的，测试垫13是矩形的。应该了解，连接垫和测试垫可以具有任何合适的形状，这里示出的例子只是作为例证说明。还应该了解，连接垫11以合适的方式连接到形成在下层互连层中的金属路径。
附图4是示出了附图3的接触垫上形成连接元件之后得到的结构的截面图。
其上要形成接触的金属路径17被形成在集成电路1的上部。绝缘钝化层19被形成在电路和金属路径17上。钝化层19在连接元件将要形成的位置包括开口21，其位于金属路径17之上。接触垫形成在钝化层19上以及开口21中，该接触垫包括连接垫11、测试垫13以及连接垫11和13的导电路径部分15。连接垫11在开口21中的路径17上延伸，测试垫13和路径部分15在钝化层19上延伸。测试垫13、连接垫11和导电路径部分15结构相同。
在开口21中，其上形成有导电凸块31的多层导电叠层23形成在连接垫11的底部和侧壁。多层叠层23使得连接垫11和导电凸块31之间形成良好的结合和电接触。举例来说，多层叠层23可以包括三层25、27和29。
本发明的一个实施例提供了一种在集成电路的接触垫上形成连接元件的方法，其中包括一旦晶片上的测试完成就使得连接垫和测试垫分离开的步骤。这样就避免了测试垫与形成在集成电路里的元件之间的干扰，特别是当集成电路工作于射频状态时。
附图5A到5G是根据本发明的一个实施例的截面图，其描述了测试集成电路以及在集成电路的连接垫上制造连接元件的步骤，附图5B是附图5A的一部分的放大图。
在附图5A中，示出了其中形成有大量电子元件的集成电路晶片的上部1。金属路径17形成在上部1中，在电路的最后一层互连层中。
钝化层19在上部1上延伸。举例来说，钝化层19可以由氮化硅、BCB(苯并环丁烯)或PI(聚酰亚胺)形成。通过合适的掩模，开口21被形成在钝化层19中，在将要在金属路径17上实施接触的位置。
顶视图形状与附图3中的接触垫相同的接触垫在钝化层19上和开口21中延伸。该接触垫由以下几部分形成：形成在开口21位置的、将要承接连接元件的连接垫11，其上将放置测试头的、在钝化层19上延伸的测试垫13，以及连接垫11和垫13的导电路径部分33。
附图5B是附图5A中在导电路径部分33位置的局部放大图。
根据本发明的一个实施例，导电路径部分33具有与连接垫11和测试垫13不同的结构。连接垫11和测试垫13由多个导电层的叠层构成，而导电路径部分由这些导电路径中的一个或仅几个构成。
举例来说，并且如附图5B所示，连接垫11和测试垫13可以由四层导电层的叠层构成，导电路径部分33可由这些导电路径中的一个构成。例如，形成测试垫和连接垫的层可以是用于保护钝化层19的层以及能与测试头和连接元件都具有良好电接触的层。导电路径部分33由形成连接垫和测试垫的叠层中的一层或多层形成。在示例中，形成导电路径部分33的层是形成测试垫和连接垫的叠层中的最后一层导电层。
请注意，附图5B中的例子只是导电路径部分33的众多可能变形中的一种。导电路径部分33可由形成连接垫和测试垫的叠层中的任一适合的层构成。
为了得到这样的结构，应用第一掩模来形成连接垫和测试垫的层，该层不在导电路径部分中，应用第二掩模来形成导电路径部分以及连接垫和测试垫剩下的层。作为一个非限制性的举例，导电路径部分可由铝、铜或钛形成。
在附图5C所示的步骤，形成在晶片中的集成电路被测试。为达此目的，测试头35被放置与测试垫13相接触。
在附图5D所示的步骤，多层导电叠层37(称为凸块下金属或UBM叠层)被形成在附图5C中的结构上。举例来说，这一叠层可以包括三个导电路径39、41和43。层39被称为结合层，层41为阻挡层，层43为可湿层(wettable layer)。举例来说，结合层39可由铝、钛、钛钨合金、铬、钽、银或金形成，阻挡层41可由钒/镍、氮化钛、氮化钽、镍、钒、铬或铜形成，可湿层43可由铜、钯、金或银形成。
应该理解，可以应用不同结构的导电叠层37。例如，导电叠层37可以包含少于或多于三层，进一步地，如果导电路径部分33的材料是铝，则结合层39的材料优选为铝。
在附图5E所示的步骤，掩模45被形成在导电路径37上，在连接垫11上方。
在附图5F所示的步骤，导电叠层37的没有被掩模45所保护的部分被一次或多次蚀刻。蚀刻操作被实施以移除测试垫和路径部分33上方的层39、41和43，这些蚀刻操作还要移除导电路径部分33。在导电路径部分33和结合层39都是由铝形成的情况下，或者在导电路径部分33和导电叠层37的其中一层是由两种可同时被蚀刻的材料形成的情况下，同一蚀刻过程即可蚀刻路径部分和导电叠层的相应层。在导电路径部分33和互连叠层37的层是由不能同时被蚀刻的材料形成的情况下，将提供额外的蚀刻以移除导电路径部分33的金属。在导电路径部分33是由形成测试垫和连接垫的叠层的上层形成的情况下，请注意，不同的蚀刻操作也将除去测试垫13的上部。然后，移除掩模45。
这样就得到了连接垫11和测试垫13分离的结构，导电路径部分33被去除。这样，测试垫13没有被偏置在连接垫11的电压。当工作在射频状态时，这样就能避免由于测试垫13的偏置而产生的寄生电容或电感。
在附图5G所示的步骤，导电凸块47被形成在叠层37的余留部分上，在连接垫11上方。导电凸块47由本领域技术人员公知的任何方法形成。举例来说，导电凸块47可由锡/铜、锡/银或锡/铅合金形成。
这样，所述方法使得一旦晶片上的测试完成就使测试垫13从连接垫11分离。此方法相对于已知方法来说，具有不增加步骤数目就能实施的优点。实际上，最好是导电路径部分33由一种或多种与导电叠层37的其中一层同时被蚀刻的材料形成。进一步地，因为导电路径部分37是由能在连接垫11和测试垫13中找到的一层或多层构成，因此相对于已知方法来说，形成路径部分不需要额外的沉积步骤。
应该理解，附图5A到5G所揭示的步骤是在将晶片切割为芯片之前，同时实施在集成电路晶片的多个接触垫上、或者在所有的接触垫上。
附图6说明了系统的一个实施例，该系统包含电路，其中至少一个接触垫的导电路径部分不存在。
此系统包含集成电路ICA(51)，其接触垫按照上述方法形成，即，所述接触垫由连接垫、测试垫以及至少一部分已被去除的导电路径部分所构成。该系统还包括另一电子元件ICB(53)，其可以是任何已知的电子元件并且通过连接55与集成电路互相。元件ICB本身也可以是电路，其中至少一个接触垫的导电路径部分不存在。这样的一个系统，例如，可包含在手机中。
上面已经描述了本发明的详细实施例。本领域的技术人员可以做各种变动和修改。要特别注意的是，测试垫13可以具有和路径部分33同样的结构。这样，在附图5F的蚀刻步骤中，测试垫13的金属可以完全被去除。
进一步地，所述方法也可用于下述情况，即集成电路将通过与此处揭示的不同的连接元件连接到支承体上。例如，此处所述方法也可适用于这种情况，即集成电路芯片的接触垫和芯片支承体的垫之间的连接是通过引线来保证(引线键合)。在这种情况下，下述步骤将被实施：
-在集成电路上形成钝化层，该钝化层在将要进行连接的位置包含开口；
-形成接触垫，接触垫由开口中的连接垫以及钝化层上的测试垫构成，连接垫和测试垫通过导电路径部分连接；
-通过按压测试头于测试垫上对电路进行电测试；
-至少在连接垫上方形成掩模；
-去除导电路径部分；
-移除掩模；
-切割集成电路芯片；并且
-在连接垫上以及在芯片支承体表面提供的垫上连接键合引线。

Claims (8)

1.一种制造和测试集成电路的方法，其包括以下步骤：
在集成电路(1)的上部上面形成钝化层(19)，该钝化层在集成电路的最终互连叠层的金属路径(17)的位置包含开口(21)；
在开口中形成第一垫(11)，该第一垫通过导电路径部分(33)连接到形成在钝化层上的第二垫(13)，第一垫是为了集成电路的连接而设置的；
通过使测试头(35)接触第二垫测试集成电路；
在结构上沉积用来与导电凸块连接的多层导电叠层(37)；并且
蚀刻该多层叠层，但不蚀刻该第一垫的上方，所述路径部分选择的材料能使所述蚀刻也移除了所述路径部分，由此第一垫和第二垫被分离。
2.如权利要求1所述的方法，在蚀刻多层导电叠层的步骤之后，还包括，在多层叠层的余留部分上形成导电凸块(47)的步骤，其后还有将集成电路切割成芯片的步骤。
3.如权利要求1或2所述的方法，其中，第一垫和第二垫由多层形成，第一垫(11)的所述层中的至少一层与导电路径部分(33)的材料不同时移除。
4.如权利要求1到3中任一项所述的方法，其中，导电路径部分(33)以及与连接垫(11)接触的多层叠层(37)的第一层(39)由铝形成。
5.如权利要求1到4中任一项所述的方法，其中，多层叠层(37)包括三层。
6.如权利要求1到5中任一项所述的方法，其中，与第一垫(11)接触的多层叠层(37)的第一层(39)由选自铝、钛、钛钨合金、铬、钽、银和金构成的组的材料形成，多层叠层的第二层(41)由选自钒/镍、氮化钛、氮化钽、镍、钒、铬和铜构成的组的材料形成，并且多层叠层的第三层(43)由选自铜、钯、金和银构成的组的材料形成。
7.如权利要求1到6中任一项所述的方法，其中，第一垫(11)的形状是六边形。
8.如权利要求1到7中任一项所述的方法，其中，钝化层(19)的材料选自BCB(苯并环丁烯)、氮化硅和PI(聚酰亚胺)构成的组。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681558A (zh) * 2012-09-03 2014-03-26 矽品精密工业股份有限公司 半导体封装件中的连接结构
CN103871914A (zh) * 2012-12-14 2014-06-18 英飞凌科技股份有限公司 制作层堆叠的方法
CN106409798A (zh) * 2015-07-27 2017-02-15 英飞凌科技股份有限公司 半导体器件和用于制造半导体器件的方法
CN117497483A (zh) * 2023-12-27 2024-02-02 日月新半导体(昆山)有限公司 集成电路制造方法以及集成电路装置

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2931586B1 (fr) 2008-05-22 2010-08-13 St Microelectronics Grenoble Procede de fabrication et de test d'un circuit electronique integre
US8093106B2 (en) * 2009-09-23 2012-01-10 Chipmos Technologies Inc. Method for manufacturing packaging structure
US8558229B2 (en) 2011-12-07 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation layer for packaged chip
CN102723311B (zh) * 2012-06-29 2014-11-05 京东方科技集团股份有限公司 阵列基板制作方法
US9082626B2 (en) * 2013-07-26 2015-07-14 Infineon Technologies Ag Conductive pads and methods of formation thereof
US9691686B2 (en) 2014-05-28 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Contact pad for semiconductor device
DE102018124497B4 (de) 2018-10-04 2022-06-30 Infineon Technologies Ag Halbleitervorrichtung und Verfahren zum Bilden einer Halbleitervorrichtung
TWI738193B (zh) * 2020-01-22 2021-09-01 復格企業股份有限公司 晶片封裝的製程內測試方法及裝置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02241046A (ja) * 1989-03-15 1990-09-25 Nec Corp 半導体集積回路の製造方法
US5593903A (en) * 1996-03-04 1997-01-14 Motorola, Inc. Method of forming contact pads for wafer level testing and burn-in of semiconductor dice
JP2000232127A (ja) * 1999-02-09 2000-08-22 Mitsubishi Electric Corp 半導体装置
TW430935B (en) * 1999-03-19 2001-04-21 Ind Tech Res Inst Frame type bonding pad structure having a low parasitic capacitance
US6667195B2 (en) * 2001-08-06 2003-12-23 United Microelectronics Corp. Laser repair operation
JP2003249534A (ja) * 2002-02-25 2003-09-05 Matsushita Electric Ind Co Ltd 高周波回路、高周波回路装置
US20040010404A1 (en) * 2002-07-09 2004-01-15 Stone Cheng Method for replacing language of user interface without having to restart application
US6762503B2 (en) * 2002-08-29 2004-07-13 Micron Technology, Inc. Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same
US6825541B2 (en) * 2002-10-09 2004-11-30 Taiwan Semiconductor Manufacturing Co., Ltd Bump pad design for flip chip bumping
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
JP4415747B2 (ja) * 2004-04-30 2010-02-17 ソニー株式会社 半導体装置の製造方法
DE102004041961B3 (de) * 2004-08-31 2006-03-30 Infineon Technologies Ag Integrierte Halbleiterschaltung mit integrierter Kapazität zwischen Kontaktanscluss und Substrat und Verfahren zu ihrer Herstellung
FR2931586B1 (fr) 2008-05-22 2010-08-13 St Microelectronics Grenoble Procede de fabrication et de test d'un circuit electronique integre

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681558A (zh) * 2012-09-03 2014-03-26 矽品精密工业股份有限公司 半导体封装件中的连接结构
CN103681558B (zh) * 2012-09-03 2017-11-24 矽品精密工业股份有限公司 半导体封装件中的连接结构
CN103871914A (zh) * 2012-12-14 2014-06-18 英飞凌科技股份有限公司 制作层堆叠的方法
CN103871914B (zh) * 2012-12-14 2017-07-14 英飞凌科技股份有限公司 制作层堆叠的方法
CN106409798A (zh) * 2015-07-27 2017-02-15 英飞凌科技股份有限公司 半导体器件和用于制造半导体器件的方法
CN117497483A (zh) * 2023-12-27 2024-02-02 日月新半导体(昆山)有限公司 集成电路制造方法以及集成电路装置
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