CN104916623A - 半导体封装和制造半导体封装基底的方法 - Google Patents

半导体封装和制造半导体封装基底的方法 Download PDF

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CN104916623A
CN104916623A CN201510108355.7A CN201510108355A CN104916623A CN 104916623 A CN104916623 A CN 104916623A CN 201510108355 A CN201510108355 A CN 201510108355A CN 104916623 A CN104916623 A CN 104916623A
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substrate
semiconductor packages
conductive
frequency unit
radio
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CN104916623B (zh
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许文松
于达人
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MediaTek Inc
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MediaTek Inc
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种半导体封装和用于制造半导体封装基底的方法。半导体封装包括基底。所述基底具有装置连接面。射频(RF)装置被嵌入所述基底中。所述RF装置靠近所述装置连接面。本发明提供的半导体封装及其方法能够获得更好的品质因数。

Description

半导体封装和制造半导体封装基底的方法
技术领域
本发明涉及一种半导体封装和用于制造半导体封装基底的方法，特别地，涉及一种用于半导体封装的基底，所述基底具有嵌入其中的射频(RF)装置。
背景技术
在高速应用中(例如射频(RF)应用)，常规的RF装置包括几个安装在RF主管芯上的分立的RF芯片和其它有源或无源装置(如电感器，天线，滤波器，功率放大器(PA)，去耦或匹配电路)。然而，常规的RF装置的在片(on-wafer)电感器由铝(Al)形成，并且在片电感器的厚度受限于常规的RF装置的制造工艺。因此，常规的RF装置的电感器(也被称为在片电感器)会具有占据面积大和品质因数(Q-因数)低的不良品质。此外，无法减小常规RF装置的RF主管芯尺寸和每个晶片上管芯的数量。
因此，需要一种新的RF装置封装。
发明内容
为了解决上面的品质因数不高的问题，本发明特提供一种半导体封装和用于制造半导体封装基底的方法。
一个实施例中，半导体封装包括具有装置连接面的基底。射频装置被嵌入基底之中，所述射频装置靠近装置连接面。
另一个实施例中，半导体封装包括射频装置，所述射频装置具有连接到基底的底面和侧壁。半导体装置通过导电结构安装在RF装置上。
另一个实施例中,用于制造半导体封装基底的方法包括,提供载体，所述载体的顶面和底面具有导电种子层。射频装置分别形成于导电种子层之上。第一基底材料层和第二基底材料层分别层压在导电种子层之上，覆盖所述射频装置。第一基底材料层和第二基底材料层(其上包含RF装置)与载体分离以形成第一基底和第二基底。
另一个实施例中,用于制造半导体封装基底的方法包括提供基底。至少一个射频装置在基底上形成。附加绝缘材料形成于基底之上，并且进一步限定所述附加绝缘材料上的图案，其中所述图案形成于所述RF装置之上。
本发明提供的半导体封装能够具有更高的品质因数。
以下实施例和相关附图中给出了详细说明。
附图说明
通过参照附图来阅读随后的详细说明和实例可以更全面地理解本发明，其中：
图1显示半导体封装的一个典型实施例的俯视图，特别是示出用于半导体封装的基底，该基底具有嵌入其中的射频装置。
图2显示沿图1中线A-A'截取的局部横截面，其示出半导体封装的一个典型实施例，特别是示出了用于半导体封装的基底，该基底具有嵌入其中的射频装置。
图3显示本发明半导体封装的另一典型实施例的局部横截面图，特别是示出了用于半导体封装的基底，该基底具有嵌入其中的射频装置。
图4A到4E是横截面图，该横截面示出了用于制造本发明半导体封装基底方法的一个典型实施例，该基底具有RF装置。
具体实施方式
以下描述是用于实现本发明的方式。该描述是为了说明本发明的一般原理而不应被视为具有限制意义。本发明的范围最好参考所附的权利要求来确定。只要可能，附图和说明书中使用相同的附图标记来表示相同或相似的部分。
本发明将根据特定实施例并参考特定附图进行描述，但本发明不限于此，而是仅由权利要求所限制。所描述的附图仅是示意性和非限制性的。在附图中，出于展示目的，一些元件的尺寸可能被夸大并且未按比例绘制。该尺寸和相对尺寸与本发明实施中的实际尺寸并不一致。
图1显示半导体封装500a的一个实施例的俯视图，特别显示了具有嵌入基底中的射频(RF)装置的半导体封装的基底。在本实施例中，半导体封装可以是使用导电结构(例如铜柱凸块焊盘)将半导体装置连接到基底的覆晶封装。替代地，半导体封装可以是使用引线接合技术将半导体装置连接到基底的封装。图2示出沿图1中线A-A'截取的局部截面图，其示出了本发明半导体封装500a的一个典型实施例。请参阅图1和2，其中，半导体封装500a包括基底200，该基底200具有装置连接面214和与装置连接面214相对的焊球连接面213。在一个实施例中，基底200(例如印刷电路板(PCB))可以由聚丙烯(PP)形成。还应当注意到，基底200可以是单层或多层结构。在本实施例中，所形成的射频(RF)装置240嵌入基底200之中，射频装置240靠近装置连接面214。在一个实施例中，RF装置240可以包括电感器，天线，滤波器，功率放大器(PA)，去耦或匹配电路。在本实施例中，RF装置240是电感器240。在本实施例中，RF装置240具有用作焊盘区域248和250的两个端部248和250，所述两个端部248和250连接到直接安装在基底200上的半导体装置300。在本实施例中，射频装置240具有多个装置部分，例如，装置部分240-1和240-2。该RF装置240的装置部分240-1和240-2可以被设计成具有大于5μm的宽度W1和约为10-12μm的最小间隔S1。但是，应当注意到，这并非是对RF装置240的装置部分240-1和240-2的宽度W1和最小间隔S1的限制。
可替代地，多个第一导电迹线202a也可以设计成被嵌入基底200，所述第一导电迹线202a靠近装置连接面214。在一个实施例中，第一导电迹线202a可包括信号迹线段或接地迹线段，其用于直接安装在基底200上的半导体装置300的输入/输出(I/O)连接。因此，每个所述第一导电迹线202a具有用作基底200的焊盘区域的部分。在本实施例中，第一导电迹线202A被设计为具有大于5μm的宽度W2和约10-12μm的最小间隔S2。但是，应该注意到，这并非是对导电迹线宽度的限制。对于不同的设计，导电迹线的宽度可以根据需求而小于5μm。
在如图2所示的一个实施例中，第二导电迹线202b也可被设计为布置在基底200的焊球连接面213上。在本实施例中，焊球结构252也可以被设计为布置在第二导电迹线202b上。
半导体装置300被安装在基底200的装置连接面214上，半导体装置300的有源表面通过粘结工艺(bonding process)而面向基底200。在一个实施例中，半导体装置300可以包括管芯，封装，或晶片级封装。在本实施例中，半导体装置300是覆晶封装。如图2所示，半导体装置300可以包括主体301，其上覆盖半导体主体301的金属焊盘304，以及覆盖金属焊盘304的绝缘层302。半导体装置300的电路被布置在有源表面上，金属焊盘304被布置在电路的顶部。半导体装置300的电路通过多个布置在半导体装置300有源表面的导电结构222互连到嵌入基底200内的RF装置240和第一导电迹线202a，然而，应当注意到，图2所示的导电结构222仅为示例，并非对本发明的限制。
如图2图所示，导电结构222可以包括导电凸块结构，如铜凸块或焊料凸块结构、导线结构或导电胶结构。在本实施例中，导电结构222可以由金属叠层组成，所述金属叠层包括UBM(凸点下金属)层306，铜层216(例如镀铜层)的，导电缓冲层218，以及焊料帽220。在一个实施例中，该UBM层306可通过沉积法(如溅射法或镀覆法)和随后的各向异性刻蚀工艺在开口内暴露的金属焊盘304上形成。所述各向异性刻蚀工艺在形成导电柱后执行。该UBM层306还可以延伸到绝缘层302的顶面之上。在本实施例中，该UBM层306可以包括钛，铜，或它们的组合。铜层216(例如电镀铜层)可以形成于该UBM层306上。所述开口可被铜层216和UBM层306填充，且所述开口内的铜层216和UBM层306可以形成导电结构222的完整插头。铜层216的形成位置是由干膜光致抗蚀剂或液体光致抗蚀剂的图案来定义(未示出)。
在一个实施例中，底部填充材料或底部填料230可以被引入半导体装置300和基底200之间的间隙。在一个实施例中，底部填料230可以包括毛细型底部填充(CUF)，模塑型底部填充(MUF)，或者它们的组合。
在一个实施例中，RF装置240和第一导电迹线202a可以具有布置在基底表面的上面、下面或对准该基底表面的顶面，以改善高密度半导体封装的布线(routing)能力。如图2所示，RF装置240具有布置为对准到基底200的装置连接面214的顶面242a。也就是说，RF装置240的底面246a和至少一个侧壁244a被设计为完全连接到基底200。可替代地，所述第一导电迹线202a可以具有连接到RF装置240的类似配置。例如，第一导电迹线202a具有布置为对准到基底200的装置连接面214的顶面212a。另外，导电迹线202a的底面206a和侧壁204a被设计成完全连接到基底200。在本实施例中，导电结构222的焊料帽220被布置为与基底200的一部分相接触并连接到所述RF装置240的顶面242a和所述第一导电迹线202a的顶面212a。归因于RF装置的顶面和与基底200的装置连接面214共面(coplanar)的第一导电迹线，所述凸块与迹线之间的空间被增大，并且凸块到迹线的桥接问题可以被有效避免。
图3显示本发明半导体封装500b的另一实施例的局部横截面，特别是示出了用于半导体封装的基底200a，该基底具有嵌入其中的射频(RF)装置。可替换地，基底200a可以包括多层结构。在本实施例中，多层基底200a可以具有允许所述RF装置240被嵌入其中的基底部分201。另外，该多层基底200a进一步包括绝缘层208，所述绝缘层208具有布置在基底部分204上的开口并借此开口靠近基底部分204的装置连接面214。在本实施例中，基底部分201和绝缘层208共同用作多层基底200a。在本实施例中，RF装置240和第一导电迹线202a嵌入基底201中。RF装置240的顶面242a和第一导电迹线202a的顶面212a可以对准到基底部分204的装置连接面214。在本实施例中，嵌入基底部分201中的RF装置240和第一导电迹线202a可以在绝缘层208的开口内露出。
图4A到4E是横截面图，其显示了用于制造本发明两个半导体封装基底200c和200d方法的一个实施例，该基底具有RF装置。在本实施例中，用于制造半导体封装基底的方法也称为双面基底制造工艺。该实施例的元件与先前根据附图1-3所描述的元件相同或相似，为简便起见在下文中不再重复。如图4A所示，提供具有导电种子层402a和402b的载体400，所述导电种子层402a和402b位于顶面401和底面403上。在一个实施例中，载体400可包括FR4玻璃环氧树脂或不锈钢。另外，导电种子层402a和402b被作为种子层，该种子层用于随后在载体400的顶面401和底面403上形成互连的基底的导电迹线。在一个实施例中，导电种子层402a和402b可以包括铜。
然后，如图4B所示，RF装置440a、440b和第一导电迹线404a、404b同时形成于载体400的顶面401和底面403上。RF装置440a、440b的底端部分和第一导电迹线404a和404b连接到导电种子层402a和402b的顶端部分。在一个实施例中，RF装置440a、440b和第一导电迹线404a、404b可以通过电镀工艺和各向异性刻蚀工艺形成。所述电镀工艺和各向异性刻蚀工艺在载体400的顶面401和底面403上同时执行。在一个实施例中，电镀工艺可以包括电气电镀工艺。在一个实施例中，RF装置440a、440b和第一导电迹线404a、404b可以包括铜(Cu)。在一个实施例中，RF装置440A，440B可用作电感器440a，440b。在一个实施例中，RF装置440a，440b的宽度W1和最小间隔S1或第一导电迹线404a，404b的宽度W2和最小间距S2可归因于形成工艺(例如各向异性刻蚀工艺)而得到精确控制。在本实施例中，RF装置440a，440b可以被设计为具有大于5μm的宽度W1和约为10-12μm的最小间隔S1。在本实施例中，第一导电迹线404a，404b可以被设计为具有大于5μm的宽度W2和约10-12μm的最小间隔S2。但是，应当注意到，这并非是对RF装置和第一导电迹线的宽度W1，W2和最小间隔S1，S2的限制。对于不同的设计，宽度W1和W2可以根据需要而小于5μm。因此，相比于常规的在片电感器的匝数，嵌入基底的所得到的电感器440a，440b的匝数可以得到增加。另外，归因于形成工艺(例如电镀工艺)，相比于常规的在片电感器，所得到的电感器440a，440b的厚度得到显着增加。此外，电感器440a，440b由铜(Cu)形成，并且电感器的电阻相比于由铝(Al)形成的常规的在片电感器而言得到减小。
然后，如图4C所示，执行层压工艺从而将第一基底材料层406a和第二基底材料层406b分别布置在载体400的顶面401和底面403上，其中，第一基底材料层406a和第二基底材料层406b分别覆盖所述RF装置440a，440b和第一导电迹线404a和404b。在本实施例中，第一基底材料层406a和第二基底材料层406b的层压工艺在载体400的顶面401和底面403上同时执行。在一个实施例中，第一基底材料层406a和第二基底材料层406b可以包括聚丙烯(PP)。
接下来，请再次参考图4C，其中执行钻孔工艺以形成通过第一基底材料层406a和第二基底材料层406b的开口(未示出)，以界定随后所形成的通孔408a，408b，448a和448b的形成位置。在一个实施例中，钻孔工艺可以包括激光钻孔工艺，蚀刻钻孔工艺，或机械钻孔工艺。然后，执行电镀工艺以将导电材料填充到开口中从而形成通孔448a和448b，所述通孔448a和448b用于将RF装置440a，440b互连到随后的第二导电迹线450a和450b。另外，同时执行电镀工艺以将导电材料填充到开口从而形成通孔408a和408b，所述通孔408a和408b用于将所述第一导电迹线404a和404b互连到随后的第二导电迹线410a和410b。在本实施例中，钻孔工艺和电镀工艺分别在第一基底材料层406a和第二基底材料层406b上同时执行。
接下来，请再次参考图4C，其中多个第二导电迹线410a，410b，450a和450b分别形成于第一基底材料层406a的第一表面412和第二基底材料层406b的第一表面414上。如图4C所示，第一基底材料层406a的第一表面412和第二基底材料层406b的第一表面414分别远离载体400的顶面401和底面403。第二导电迹线410a，410b，450a和450b通过电镀工艺和各向异性刻蚀工艺而形成。所述电镀工艺和各向异性刻蚀工艺在第一基底材料层406a的第一表面412和第二基底材料层406b的第一表面414上同时执行。在一个实施例中，电镀工艺可以包括电气电镀工艺。在一个实施例中，第二导电迹线410a，410b，450a和450b可以包括铜。在一个实施例中，第二导电迹线410a，410b，450a和450b被设计为具有大于5μm的宽度W2和约10-12μm的最小间隔S2。但是，应当注意到，这并非是对导电迹线的宽度的限制。对于不同的设计，第二导电迹线410a，410b，450a和450b的宽度可根据需要而小于5μm。在本实施例中，各向异性刻蚀工艺可精确地控制所述第二导电迹线410a，410b，450a和450b的宽度。
然后，如图4D和4E所示，第一基底材料层406a包括嵌入其中的RF装置440a和第一导电迹线404a以及位于其上的第二导电迹线410a和450a；第二基底材料层406b包括嵌入其中的RF装置440b和第一导电迹线404b以及位于其上的第二导电迹线410b和450b，第一基底材料层406a和第二基底材料层406b分别与载体400的顶面401和底面403分离，以形成相互分离的第一基底200c和第二基底200d。然后，再次如图4D和4E所示，导电种子层402a和402b分别从第一基底200c和第二基底200d移除。
如图4D和4E所示，RF装置440a，440b和第一导电迹线404a，404b被分别对准第一和第二基底200c和200d的第二表面416和418，所述第二表面416和418位于所述第一表面412和414的对面。在本实施例中，第一基底200c和第二基底200d通过双面基底制造工艺在相对的表面上(顶面401和底面403)同时制造。
然后，执行粘结工艺以在分离工艺之后通过导电结构(例如，如图2所示的导电性结构222)将半导体装置(例如，如图2所示的半导体装置300)安装在第一基底200c/第二基底200d上。如图4D和4E所示，在粘结处理之后，导电结构与射频装置440a/440b和第一导电迹线404a，404b的顶面接触。然后，底部填充材料或底部填料(例如，如图2所示的底部填料230)可以被引入所述半导体装置和第一基底200c/第二基底200d之间的空隙。最后，如图4D和4E所示的第一基底200c/第二基底200d，RF装置440a/440b，导电迹线404a/404b，第二导电迹线410a/410b，450a/450b，以及半导体装置(例如，如图2所示的半导体装置300)和导电结构(例如，如图2所示的导电结构222)可以共同形成半导体封装(例如，如图2所示的半导体封装500a)。
可替换地，如图4D和4E所示的第一基底200c和第二基底200d分离之后，具有开口的两个钝化或绝缘层(例如，如图3中所示的绝缘层208)可选择地分别形成于第一基底200c的第二表面416和第二基底200d的第二表面418上。在本实施例中，第一和第二基底200c，200d中的RF装置440a，440b和第一导电迹线404a和404b的端部在开口内露出。另外，在本实施例中，第一基底200c/第二基底200d和其上的绝缘层共同用作多层基底。执行粘结工艺和底部填充材料/底部填料引入工艺之后，如图4D和4E所示的第一基底200c/第二基底200d，RF装置440a/440b，导电迹线404a/404b，第二导电迹线410a/410b，450a/450b，以及半导体装置(例如，如图2所示的半导体装置300)和导电结构(例如,如图2所示的导电结构222)可以共同形成半导体封装(例如，如图3所示的半导体封装500b)。
实施例提供一种半导体封装和用于制造半导体封装基底的方法。半导体封装被设计为包括嵌入诸如印刷电路板(PCB)的基底中RF装置(例如，电感器)。RF装置可以具有布置在基底表面的上面，下面或对准基底表面的顶面，以改善高密度半导体封装的工艺路线能力。此外，RF装置被设计为具有大于5μm的宽度以及约为10-12μm的最小间隔。进一步地，基底可以包括单层结构或多层结构。典型实施例中还提供用于制造半导体封装基底的方法。在一个实施例中，该方法可以在载体的两侧同时制造两个基底，所述基底具有嵌入其中的RF装置(例如电感器)。进一步地，RF装置可以通过电镀工艺和各向异性刻蚀工艺形成，各向异性刻蚀工艺可以精确地控制RF装置的宽度和最小间隔。因此，相比于常规的在片电感器的匝数，嵌入基底的电感器的匝数可以得到增加。相应地，安装在基底上的半导体装置的尺寸(或管芯尺寸)可以减小，并且每个晶片上的管芯数量可以得到增加。此外，一个实施例中，归因于形成工艺(例如在电镀工艺)，相比于常规的在片电感器而言，嵌入基底的电感器的厚度得到显著增加。进一步地，一个实施例中，嵌入基底的电感器由铜(Cu)形成，并且相比于由铝(Al)形成的常规的在片电感器而言，该电感器的电阻得到减小。因此，一个典型实施例中，嵌入基底的电感器可以具有比常规的在片电感器更高的品质因数(Q-因数)。可替代地，该方法可以制造包括单层结构或多层结构的基底以改善设计性能。
虽然本发明已经通过示例和优选实施例的方式得到描述，但应当理解为本发明不局限于所公开的实施例。相反地，它旨在覆盖各种修改和类似配置(由于其对本领域技术人员来说是显而易见的)。因此，所附权利要求的范围应被赋予最为宽泛的解释，以使其涵盖所有这些修改和类似。

Claims (24)

1.一种半导体封装，包括：
具有装置连接面的基底；以及
嵌入所述基底的射频装置，所述射频装置靠近所述装置连接面。
2.如权利要求1所述的半导体封装，其特征在于，所述半导体封装进一步包括：
嵌入所述基底的第一导电迹线，所述第一导电迹线靠近所述装置连接面；以及通过第一导电结构安装在所述第一导电迹线上的半导体装置。
3.如权利要求2所述的半导体封装，其特征在于，所述半导体封装进一步包括：
布置在所述基底的焊球连接面上的第二导电迹线，其中所述焊球连接面位于所述装置连接面的对面；以及
布置在所述第二导电迹线上的焊球结构。
4.如权利要求2所述的半导体封装，其特征在于，所述射频装置具有顶面，所述顶面位于基底表面的上面，下面或对准所述基底表面。
5.如权利要求2所述的半导体封装，其特征在于，所述半导体封装进一步包括：
绝缘层，所述绝缘层具有布置在所述基底的所述装置连接面上的开口，所述绝缘层位于所述射频装置的顶面的上面，其中，所述射频装置部分在所述开口内被露出。
6.如权利要求2所述的半导体封装，其特征在于，所述第一导电结构接触所述射频装置。
7.如权利要求2所述的半导体封装，其特征在于，所述第一导电结构包括导电柱结构，导线结构或导电胶结构。
8.如权利要求7所述的半导体封装，其特征在于，所述导电柱结构由金属叠层组成，所述金属叠层包括凸块下金属层，铜层和焊料帽。
9.如权利要求8所述的半导体封装，其特征在于，所述导电柱结构进一步包括位于所述铜层和所述焊料帽之间的导电缓冲层。
10.如权利要求2所述的半导体封装，其特征在于，所述半导体装置包括管芯，封装，或晶片级封装。
11.如权利要求2所述的半导体封装，其特征在于，所述第二导电结构包括铜凸块或焊料凸块结构。
12.如权利要求1中所述的半导体封装，其特征在于，所述射频装置的宽度大于5μm，其中所述射频装置具有多个装置部分，并且其中被所述基底的一部分隔开的相邻装置部分具有大约10-12μm的最小间隔。
13.如权利要求1所述的半导体封装，其特征在于，所述基底包括单层结构或多层结构。
14.一种半导体封装，包括：
射频装置，所述射频装置具有连接到基底的底面和侧壁；以及
通过导电结构安装在所述射频装置上的半导体装置。
15.一种用于制造半导体封装基底的方法，包括：
提供载体，所述载体的顶面和底面具有导电种子层；
分别在所述导电种子层上形成射频装置；
分别在所述导电种子层上层压第一基底材料层和第二基底材料层，所述第一基底材料层和所述第二基底材料层覆盖所述射频装置；以及
由所述载体分离所述第一基底材料层与所述第二基底材料层以形成第一基底和第二基底，所述第一基底材料层与第二基底材料层包含其上的所述射频装置。
16.如权利要求15所述的用于制造半导体封装基底的方法，其特征在于，所述方法进一步包括：
在所述导电种子层上分别层压所述第一基底材料层和所述第二基底材料层之前，在所述导电种子层上形成第一导电迹线；以及
在所述第一基底材料层的第一表面和所述第二基底材料层的第一表面分别形成第二导电迹线，其中，由所述载体分离所述第一基底材料层和所述第二基底材料层之前，所述第一基底材料层的第一表面和所述第二基底材料层的第一表面分别远离所述载体的顶面和底面。
17.如权利要求16所述的用于制造半导体封装基底的方法，其特征在于，所述方法进一步包括：
执行钻孔工艺以形成通过所述第一基底材料层和所述第二基底材料层的开口；以及
在形成所述第二导电迹线之前，执行电镀工艺将导电材料填充到所述开口以形成将所述射频装置或所述第一导电迹线互连到所述第二导电迹线的通孔。
18.如权利要求17所述的用于制造半导体封装基底的方法，其特征在于，所述钻孔工艺包括激光钻孔工艺，蚀刻钻孔工艺，或机械钻孔工艺，电镀工艺包括电气电镀工艺。
19.如权利要求16所述的用于制造半导体封装基底的方法，其特征在于，所述射频装置，所述第一导电迹线，和所述第二导电迹线通过电镀工艺和各向异性刻蚀工艺形成。
20.如权利要求16所述的用于制造半导体封装基底的方法，其特征在于，所述方法进一步包括：
在所述第一基底和所述第二基底上分别形成具有开口的绝缘层，其中，所述射频装置的部分以及所述第一基底和所述第二基底的所述第一导电迹线的部分在所述开口内露出。
21.如权利要求15所述的用于制造半导体封装基底的方法，其特征在于，所述方法进一步包括：
从所述第一基底和所述第二基底移除所述导电种子层。
22.如权利要求15所述的用于制造半导体封装基底的方法，其特征在于，所述射频装置以及所述第一基底和所述第二基底的所述第一导电迹线对准所述第一基底和所述第二基底的第二表面，并且其中所述第二表面分别在所述第一基底和所述第二基底的第一表面的对面。
23.如权利要求15所述的用于制造半导体封装基底的方法，其特征在于，每个所述射频装置具有大于5μm的宽度，其中每个所述射频装置具有多个装置部分，并且其中通过所述基底的一部分隔开的相邻装置部分具有大约10-12μm的最小间隔。
24.一种用于制造半导体封装的方法，包括：
提供基底；
在所述基底上形成至少一个射频装置；
在所述基底上形成附加绝缘材料；以及
在所述附加绝缘材料上限定图案，其中所述图案形成于所述射频装置上。
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