CN101416308A - 使用薄的管芯和金属衬底的半导体管芯封装 - Google Patents

使用薄的管芯和金属衬底的半导体管芯封装 Download PDF

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Publication number
CN101416308A
CN101416308A CNA2007800117691A CN200780011769A CN101416308A CN 101416308 A CN101416308 A CN 101416308A CN A2007800117691 A CNA2007800117691 A CN A2007800117691A CN 200780011769 A CN200780011769 A CN 200780011769A CN 101416308 A CN101416308 A CN 101416308A
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semiconductor element
die package
conductive structure
metal substrate
semiconductor die
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CNA2007800117691A
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H·耶尔马兹
S·萨普
王�琦
励敏华
J·J·墨菲
J·R·迪柔
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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Publication of CN101416308A publication Critical patent/CN101416308A/zh
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Abstract

公开了一种半导体管芯封装。该半导体管芯封装包括：金属衬底；及包括第一表面、第二表面、及至少一个孔的半导体管芯，所述第一表面包括第一电气端子，所述第二表面包括第二电气端子。该金属衬底与该第二表面附连。多个导电结构在该半导体管芯上，并包括置于至少一个孔内的至少一个导电结构。可将其他导电结构置于该半导体管芯的第一表面上。

Description

使用薄的管芯和金属衬底的半导体管芯封装
发明背景
因为功率半导体器件已经发展且导通电阻已经减小，所以半导体管芯中的衬底层对总的电阻的影响增大。一种进一步减小功率半导体器件中的导通电阻的方法是使用更薄的半导体管芯。此外，薄的半导体管芯相比较厚的半导体管芯能更好地散热。
由Qi Wang等人于2005年7月25日提交的，题为“SemiconductorStructures Formed On Substrates And Methods of Manufacturing The Same”(在衬底上形成的半导体结构及其制造方法)的美国专利申请No.11/189,163描述了一种生产薄的半导体管芯的方法。所描述的方法包括将薄的经掺杂的衬底层转移至带氧化物介入层的操作晶片(handle wafer)。可以用包括外延沉积的标准方法来对该薄的衬底层(1-3微米)进行加工。最终用厚的金属衬底来代替操作晶片以消除正常半导体衬底对所形成的器件的导通态电阻的影响。然后可将该所得结构分割成可结合到常规半导体管芯封装内的芯片。
本发明的各实施例提供特别适于与上述半导体管芯一起使用的半导体管芯封装。然而，本发明的各实施例不需专门与上述半导体管芯一起使用。如以下将更详细地描述的，根据本发明的各实施例的半导体管芯封装可提供相比常规半导体封装更低的导通电阻特性和更好的散热特性。
本发明的各实施例单独地和共同地解决了上述问题及其它问题。
发明概要
本发明的各实施例涉及半导体管芯封装及其制造方法。
本发明的一个实施例涉及半导体管芯封装。该半导体管芯封装包括：金属衬底；以及包括第一表面、第二表面、及至少一个孔的半导体管芯，所述第一表面包括第一电气端子，所述第二表面包括第二电气端子。该金属衬底被附连到第二表面。多个导电结构在该半导体管芯上，并包括置于至少一个孔内的至少一个导电结构。其他导电结构可置于该半导体管芯的第一表面上。
本发明的另一实施例涉及一种用于形成半导体管芯封装的方法。该方法包括获得包括第一表面、以及第二表面的半导体管芯，所述第一表面包括第一电气端子，所述第二表面包括第二电气端子。金属衬底被附连到该半导体管芯的第二表面，且至少一个孔在该半导体管芯内形成，从而暴露该金属衬底的表面的一部分。至少一个导电结构被沉积在该至少一个孔中，其中至少一个导电结构与该金属衬底电气连通。
本发明的其他各个实施例涉及结合根据本发明的各实施例的半导体管芯封装的电气组件，及用于形成这些电气组件的各种方法。
以下将更详细地描述本发明的这些及其它各实施例。
附图简述
图1(a)到图1(c)示出根据本发明一实施例的半导体管芯封装在其形成时的横截面。图1(c)具体示出包括焊料凸点的具体的半导体管芯封装实施例。
图1(d)示出安装到印刷电路板上的在图1(c)中示出的封装。
图2示出具有增强机械层的根据本发明另一实施例的另一半导体管芯封装的横截面侧视图。
图3示出具有多个电镀金属层的根据本发明另一实施例的另一半导体管芯封装的横截面侧视图。
图4示出包括两个半导体管芯的根据本发明另一实施例的另一半导体管芯封装的横截面侧视图。该半导体管芯封装可用在同步降压转换器电路中。
图5示出根据本发明一实施例的半导体管芯封装的横截面侧视图。在此示例中，该封装包括分别连接到半导体管芯中的器件的输入端和输出端的第一金属层和第二金属层。该第一金属层和第二金属层重叠。
图6示出图5所示的半导体管芯封装的俯视图。
图7示出另一半导体管芯封装实施例的横截面侧视图。该半导体管芯封装实施例具有金属衬底，它用作两个附连到该金属衬底的半导体管芯的公共输出。这两个半导体管芯可或可不是同一类型的。他们可具有不同的性能特性，其中他们的组合会提供最期望的效果。
以下将参考详细描述对本发明的这些及其它实施例进行更详细地描述。此外，为了清楚例示，在附图中的一些部件可能不是按比例绘制的。
详细描述
本发明的各实施例涉及半导体管芯封装及制造半导体管芯封装的方法。在一个实施例中，根据本发明一实施例的半导体管芯封装包括：金属衬底；以及包括第一表面、第二表面、及至少一个孔的半导体管芯，所述第一表面包括第一电气端子，且所述第二表面包括第二电气端子。该第一和第二端子可分别是输入(例如源极或栅极)端子或输出(例如漏极)端子。该金属衬底附连至该半导体衬底的第二表面。包括第一导电结构和第二导电结构的导电结构在该半导体管芯上。至少一个第一导电结构置于该半导体管芯中的至少一个孔内。至少一个第二导电结构置于该半导体管芯的第一表面上的。该第一导电结构和第二导电结构可包括相同或不同类型的导电材料。
可参考图1(a)到图1(c)对本发明的一些实施例进行描述。在这些实施例中，完成的超薄晶片器件(UTW)是根据美国专利申请No.11/189,163中描述的方法生产的，该专利申请的内容为所有目的通过引用完整结合于此。在该工艺流程的适当时候，附加的加工从半导体管芯的顶部发生，以除去覆盖在该半导体管芯之下并与其附连的相对较厚的金属衬底的半导体管芯的一部分。(该半导体管芯通常与其他半导体管芯存在于半导体晶片的阵列中。)结果，一个或多个孔在该半导体管芯中形成。在加工之后，该金属衬底的表面可通过孔暴露。
在该半导体管芯中形成一个或多个孔之后，将焊球或其他导电结构(例如铜钉)沉积于该半导体管芯的表面上及该一个或多个孔内。此提供如图1(c)所示的顶面到背面金属衬底的连接。
该所得封装是完成的功率半导体管芯封装，且可具有类似于金属氧化物半导体场效应晶体管球栅阵列(MOSFET BGA)型半导体管芯封装(参见例如美国专利No.6,133,634)的构造。然而，与常规MOSFET BGA型半导体封装不同，在本发明实施例中的金属衬底在包含该半导体管芯的晶片的加工期间与半导体管芯附连。这降低了与处理各个半导体管芯并封装它们相关联的成本。此外，该半导体衬底电阻被消除，以使性能提高，且所形成的封装甚至比常规MOSFET BGA型半导体封装更小。以下参考图1(a)到图1(c)提供进一步的细节。
图1(a)示出包括半导体管芯107的中间结构700。该中间结构700可通过美国专利申请No.11/189,163中所述的工艺来形成，该专利申请的内容为所有目的通过引用完整结合于此。为了清楚例示而示出一个中间结构700。可以理解，在图1(a)中所示的中间结构700可以是正在加工的单个半导体晶片中的半导体管芯阵列中的许多中间结构中的一个。
该半导体管芯107具有第一表面107(a)和第二表面107(b)。该半导体管芯107的第二表面107(b)附连到金属衬底118。该金属衬底118可先前已层叠到半导体管芯107。或者，该金属衬底118可通过一些其他工艺(例如气相沉积、电镀及低温热接合)沉积到该半导体管芯上。
金属层116在该半导体管芯107的第一表面107(a)上。该金属层116可包括任何适合的材料。例如，该金属层116可包括诸如凸点下金属层组合的可焊的金属材料。凸点下金属层组合是用在焊料凸点加工中的金属叠层。该叠层可包括粘附层、扩散阻挡层、浸润层、及氧化保护层中的至少两层。该金属层116也可具有任何适合的厚度。该金属层116可使用包括气相沉积、电镀等适合的工艺来形成。
该半导体管芯107可具有任何适合的厚度。例如，在本发明一些实施例中，该半导体管芯107可具有小于约50微米，且优选小于约30微米(例如，10到30微米厚)的厚度。如上所释，较薄半导体管芯提供较低的导通电阻特性及较好的散热特性。
该半导体管芯107的第一表面107(a)可与第一电气端子重合，且该半导体管芯107的第二表面107(b)可与第二电气端子重合。该第一电气端子可以是输入端子，而该第二电气端子可以是输出端子。例如，在该第一表面107(a)处的第一电气端子可以是在功率MOSFET中的源极端子S或栅极端子G，而在第二表面107(b)处的该第二端子可以是在功率MOSFET内的漏极端子D。在该第一和第二表面107(a)、107(b)处可以有除第一和第二端子以外的附加端子。
在图1(a)中，栅极结构702在半导体管芯107中示出。该栅极结构702可以是经填充的沟槽的形式，且该沟槽可以用诸如掺杂多晶硅或金属之类的导电材料来填充，且可具有与该半导体管芯107的第一表面107(a)重合的相应的栅极端子G。
第一端子和第二端子还可在功能半导体器件中形成端子。适合的半导体器件包括含有功率MOSFET、绝缘栅双极型晶体管(IGBT)、双极型功率晶体管等的垂直器件。其他包括功率射频横向扩散MOS(RF LDMOS)器件、单片微波集成电路(MMIC)、及其他IC器件(依赖于低的接地回路电感和电阻)的器件可从通过提供直接连接到接地平面的互连的封装概念中获益。RFLDMOS器件尤其为此目的利用源极到衬底的互连。这种互连可由到接地的直接互连代替，从而改进在射频功率传输应用中的此类器件的性能。
该金属衬底118可具有任何适合的特性，且可具有任何适合的构造。例如，该金属衬底118可包括诸如铜、铝、贵金属、及其合金之类的金属。该金属衬底118相对该半导体管芯107优选是厚的。例如，该金属衬底118的厚度在某些实施例中可大于约5微米，且优选大于约100微米厚(例如，100微米到200微米厚)。如这些示例所示，该金属衬底优选比半导体管芯107厚。
如图1(b)所示，在获得如图1(a)所示的中间结构700之后，该半导体管芯107被蚀刻以在预选位置形成孔904。孔904可具有任何适合的尺寸，或形状，且可使用包括蚀刻(湿法或干法)、研磨等的任何已知的材料去除工艺来形成。在半导体管芯107中形成孔904后，金属衬底118的表面的至少一部分通过孔904暴露。任何适合数量的孔904可在该半导体管芯107中形成。
如图1(c)所示，将导电结构900沉积在金属衬底118和半导体管芯107上。导电结构900包括至少一个第一导电结构900(a)及至少一个第二导电结构900(b)。
该导电结构900可包括任何适合的材料，且可以是任何适合的形状(例如，柱形、球形、及具有平的和/或圆的表面的结构)。适合的材料包括焊料(铅基和无铅)及诸如铜之类的导电金属。如果导电结构900包括焊料，则可使用本领域已知的焊料回流工艺。
导电结构900还可使用任何适合的工艺形成。
例如，丝网印刷工艺、气相沉积工艺、电镀工艺、拾取贴装工艺等可用来形成导电结构900。
如图1(d)所示，一旦形成图1(c)中所示的半导体管芯封装，就可将其翻转并安装到电路板990上以形成电气组件。该电路板990包括电介质层991以及导电焊盘992(a)、992(b)。适合的电路板在本领域是已知的，且可包括任何数目的导电焊盘、线路和层、以及任何数目的电介质层。
该半导体管芯107的第一表面107(a)可面向电路板990，而第二表面107(b)背离该电路板。在该电气组件中，该第一导电结构900(a)对半导体管芯107中的半导体器件(例如功率MOSFET)起输入连接的作用，而该第二导电结构900(b)可对该半导体器件起输出连接的作用。输入电流可从电路板990上的导电焊盘992(a)流向第一导电结构900(a)，然后流向管芯107。输出电流可从该半导体管芯107的第二表面107(b)流到金属衬底118，到第二导电结构900(b)，然后到电路板990上的导电焊盘992(b)。该金属衬底118和较薄的半导体管芯107提供具有较低的导通电阻特性和较好的散热特性的所得半导体管芯封装。
在其他各实施例中，图1(c)所示的封装不需翻转并安装到电路板上。例如，可将该封装安装成使金属衬底118附连到电路板990并面向它。在该封装另一侧上的导电结构900可使用导线、引线框、或其他导体与该电路板上的导电焊盘电气耦合。
图2示出本发明另一实施例。在图1(c)和图2中，相同的附图标记指示相同的元件。图2所示的构造与图1(c)所示的构造类似。然而，在图2中，金属衬底118比图1(c)所示的衬底118薄(例如，厚度小于10微米，或厚度在5-10微米之间)。此外，附加的机械层119是在该金属衬底118上。机械层119机械地支撑半导体管芯107和金属衬底118。可选择该机械层119的CTE(热膨胀系数)以使其基本匹配该半导体管芯107的CTE。
该机械层119可具有任何适合的、预定的热特性、电特性、及机械特性。例如，该机械层可包括具有高的热导率的绝缘材料(例如陶瓷)。如需要，还可将散热片直接附连到机械层119。
图2所示的半导体管芯封装具有许多优点。
例如，该半导体管芯封装是硬而薄的，以减小该封装的总厚度。此外，因为该金属衬底118具有减小的厚度，所以相对图1(c)所示的实施例还可降低成本。
图3示出本发明的另一实施例。在图1(c)和图3中，相同的附图标记指示相同的元件。图3所示的封装可通过导线接合、夹片、或带状连接器与外部引线连接，或者可将其翻转并安装到电路板或类似物上。
在图3所示的实施例中，顶面金属(例如铝)层116在半导体管芯107上。电镀金属910代替如在图1(c)的实施例中的焊料填充孔904。可焊的顶面外涂层912(a)、912(b)与顶面金属层116及电镀金属910接触并置于它们之上。如需要，则该可焊的顶面外涂层912(a)、912(b)、及/或顶面金属层116和电镀金属910还可使用常规技术(例如CMP或化学机械抛光)进行平坦化。该电镀金属910可替换地使用诸如化学气相沉积(CVD)、物理气相沉积(PVD)等的其他沉积工艺来形成。该电镀金属910还可包括含有铜、铝、钨、其合金等的任何适合的金属。此外，虽然在图3中只示出了两个电镀金属通孔，但需要时本发明的各实施例可具有更多通孔。
在图3所示的实施例中，到金属衬底118的电气连接可通过在该孔904内电镀或另外沉积金属来形成。在将该封装安装到电路板时，可将电镀金属910与焊球或金属钉结合，用于将该封装接合到电路板。
图4示出根据本发明一实施例的另一半导体管芯封装。该半导体管芯封装可供在同步降压转换器应用中的单个封装解决方案。在美国专利No.6,806,580中描述了同步降压转换器系统，该专利的内容为了所有目的通过引用完整结合于此。该半导体管芯封装在需要时还可附连到散热片(未示出)。图4所示的封装可表征为具有“H桥”构造。
在图4所示的半导体管芯封装实施例中，有置于金属衬底118(a)、118(b)上的第一和第二半导体管芯177(a)、177(b)。该第一和第二半导体管芯177(a)、177(b)可具有各自的第一表面177(a)-1、177(b)-1，和第二表面177(a)-2、177(b)-2。与先前各实施例一样，金属层116(a)、116(b)可置于该第一和第二半导体管芯177(a)、177(b)的第一表面177(a)-1、177(b)-1上。该金属层116(a)、116(b)可包括可焊的金属。单个机械层119可支撑金属衬底118(a)和118(b)两者。
图4所示的半导体管芯封装包括在该第一和第二半导体管芯177(a)、177(b)上的多个导电结构940。该多个导电结构940包括第一多个导电结构940(a)、至少一个第二导电结构940(b)、多个第三导电结构940(c)、以及至少一个第四导电结构940(d)。该第一、第二、第三、及第四导电结构940(a)-(d)可包括任何适合的材料，且可使用任何适合的工艺形成。以上已对示例性材料和工艺作了描述。
图4所示的半导体管芯封装还包括多个电介质层960(a)、960(b)、960(c)。该第一电介质层906(a)可使第一多个导电结构940(a)所在区域与相邻导体隔离。该第二电介质层906(b)可使第二导电结构940(b)与在该第二半导体管芯177(b)以及该第二金属衬底118(b)中流动的漏极电流电气隔离。第三电介质层960(c)可使第三和第四导电结构940(c)、940(d)相互隔离并与其他导体隔离。
该第一、第二、及第三电介质层960(a)、960(b)、960(c)可包括任何适合的电介质材料，可具有任何适合的厚度，且可使用任何适合的工艺(例如连同本领域已知的适合的光刻工艺一起的化学气相沉积、旋涂及固化等)形成。例如，电介质层960(a)、960(b)、960(c)可包括诸如聚酰亚胺之类的绝缘的、可图案化的聚合材料。
一旦形成图4所示的半导体管芯封装，就可将其翻转并安装到电路板或类似物上以形成电气组件。在该电气组件中，该第一多个导电结构940(a)可用作至第一半导体管芯177(a)(栅极输入未示出)的第一表面177(a)-1处的源极端子的源极输入。来自第一半导体管芯177(a)的第二表面177(a)-2的漏极电流可流到第一金属衬底118(a)、到第二导电结构940(b)、再到使第二导电结构940(b)与第三导电结构940(c)电气耦合的电路板上的焊盘(未示出)。该电流然后经由第三导电结构940(c)流到该第二半导体管芯177(b)的第一表面177(b)-1处的源极端子。来自该第二半导体管芯177(b)的漏极电流然后流到该第二金属衬底118(b)、到第四导电结构940(d)、再到该电路板上的输出导电焊盘(未示出)。
如果该第一和第二半导体管芯177(a)、177(b)包括高侧MOSFET和低侧MOSFET(通常在同步降压转换器电路中)，则该第二导电结构940(b)可起在一个MOSFET中的漏极与另一MOSFET中的源极之间的连接的作用。(到第一和第二半导体管芯177(a)、177(b)的栅极连接未在图4中示出。)
图5和图6示出根据本发明另一实施例的另一半导体管芯封装。如图5和图6所示，可通过减小到背面金属/机械层的顶部金属连接的尺寸并增加连接的数量来进一步减小半导体管芯封装的大小(横向尺寸)。与先前各实施例一样，制造至该背面金属/机械层的“通孔”。然后可在绝缘电介质膜上的顶部金属层上制造到背面的连接，该绝缘电介质膜在半导体管芯上。此减小了该半导体管芯封装的大小。还可改变通孔的大小和数量以满足电流需要。通过具有多个连接，增大了到该半导体管芯封装的连接的可靠性。
参考图5，与先前各实施例一样，半导体管芯708附连到金属衬底706上。孔715如前所述地在该半导体管芯708上形成。第二金属层718(a)在该半导体管芯708上的第一金属层718(b)上形成，且第二可焊的金属层704(a)在第二金属层718(b)上形成。电介质层710也在该半导体管芯708和该第一金属层718(b)上形成。该电介质层710可由聚酰亚胺或类似物形成。导电通孔714在孔715中形成，并将第二顶部金属层718(a)连接到金属衬底706。第一可焊的金属层704(b)还可在第一金属层718(b)上形成。
与先前各实施例一样，多个导电结构702在该半导体管芯708上。该多个导电结构702包括与金属衬底706电气耦合的第一多个导电结构702(a)以及与半导体管芯708的顶部电气耦合的第二多个导电结构702(b)。该第一多个导电结构702(a)可对半导体管芯708中的MOSFET提供漏极输出，而第二多个导电结构702(b)可对该半导体管芯702中的MOSFET提供源极输入。
如所示，第一多个导电结构702(a)与半导体管芯708的一部分重叠，从而减小了所形成的封装的横向尺寸，并为该半导体封装提供了大量的输入端子和/或输出端子。
图6示出图6所示的半导体管芯封装的俯视图。示出了通孔714。如所示，第二可焊的金属层704(a)覆盖在第一可焊的金属层704(b)上。在图6中，与在图5中一样，第一金属层718(a)通过通孔714与金属机械层706连接。在图6中，未示出第一金属层718(a)和金属机械层706。
在各优选实施例中，任何可焊的层的涂覆可被延迟到任何底部导电(铝)层处于适当位置之后。
图7示出本发明的另一实施例。在图7中，构造与图1(c)所示的构造类似，然而，在图7中，背面金属衬底504可用作公共漏极双管芯应用的公共导线管。如所示，两个半导体管芯502(a)、502(b)被安装在金属衬底504上。该衬底504可形成半导体管芯502(a)、502(b)中的半导体器件的公共输出(例如公共漏极)端子。该半导体管芯502(a)、502(b)被如前所述地加工，且该导电结构505如前所述地在该半导体管芯502(a)、502(b)上形成。然而，代替在晶片切片工艺期间将各个管芯锯开以使它们相互分离，该锯开工艺被修改成得到通过公共金属层连接在一起的各管芯对。在其他各实施例中，切片工艺可用研磨工艺代替。
本发明的各个实施例具有许多优点。第一，根据本发明各实施例的半导体管芯封装是小的且可用于芯片级封装(CSP)。第二，因为该封装可使用薄的半导体管芯形成，所以该封装具有低的导通电阻和电感特性及好的散热特性。第三，因为该封装形成工艺发生在管芯存在于半导体晶片中时，所以成本因不需为封装单独操作各个管芯而降低。
以上描述是说明性的而非限制性的。本发明的许多变体对本领域的技术人员在仔细查看本发明内容后将是显而易见的。因此，本发明的范围不应参照以上说明来确定，而应该参照所附权利要求及其全部范围或等效方案来确定。
任一实施例的一个或多个特征可在不背离本发明范围的情况下与任一其他实施例的一个或多个特征进行组合。例如，机械层和金属衬底组合在图2中示出。此组合可用在本申请的其他附图所示的各实施例的任何一个中。
“一”、“一个”或“该”的叙述旨在表示“一个或多个”，除非具体指定为相反意思。此外，诸如“在...之上”，“在...之下”等术语是用来描述如附图中所示的部件的，且可或可不指的是在制造或使用根据本发明各实施例的半导体管芯封装时的绝对位置。
为了所有目的将以上提及的所有专利、专利申请、公开、及说明通过引用完整结合于此。没有一项被认为属于现有技术。

Claims (21)

1.一种半导体管芯封装，包括：
金属衬底；
包括第一表面、第二表面、及至少一个孔的半导体管芯，所述第一表面包括第一电气端子，所述第二表面包括第二电气端子，其中所述金属衬底被附连到所述第二表面；以及
在所述半导体管芯上的多个导电结构，其中所述多个导电结构包括置于所述半导体管芯的第一表面上的至少一个第一导电结构、以及置于所述至少一个孔内的至少一个第二导电结构，
其中所述至少一个第二导电结构与在所述半导体管芯的第二表面处的所述第二端子电气连通。
2.如权利要求1所述的半导体管芯封装，其特征在于，进一步包括附连到所述金属衬底的机械层，其中所述金属衬底在所述机械层与所述半导体衬底之间。
3.如权利要求1所述的半导体管芯封装，其特征在于，所述半导体管芯包括功率晶体管，其中所述第一电气端子是输入端子且所述第二电气端子是输出端子。
4.如权利要求1所述的半导体管芯封装，其特征在于，所述半导体管芯具有小于约50微米的厚度，且其中所述金属衬底具有大于约50微米的厚度。
5.如权利要求1所述的半导体管芯封装，其特征在于，所述导电结构是焊料凸点。
6.如权利要求1所述的半导体管芯封装，其特征在于，所述导电结构是电镀金属层。
7.如权利要求6所述的半导体管芯封装，其特征在于，进一步包括在所述电镀金属层上的焊料。
8.如权利要求1所述的半导体管芯封装，其特征在于，所述半导体管芯是第一半导体管芯，且其中所述半导体管芯封装包括第二半导体管芯，其中所述第二半导体管芯附连到所述金属衬底。
9.如权利要求1所述的半导体管芯封装，其特征在于，进一步包括在所述半导体管芯的第一表面上的第一金属层以及与所述第一金属层重叠的第二金属层，其中所述第二金属层和所述第一金属层相互电气隔离，且其中所述第一金属层与所述至少一个第二导电结构电气耦合。
10.如权利要求1所述的半导体管芯封装，其特征在于，所述半导体管芯包括功率MOSFET，其中所述第一端子是在所述功率MOSFET中的源极端子，且所述第二端子是在所述功率MOSFET中的漏极端子，且其中所述半导体管芯的第一表面包括栅极端子。
11.一种电气组件，包括：
如权利要求1所述的半导体管芯封装；以及
电路板，其中所述半导体管芯封装安装于所述电路板上。
12.一种方法，包括：
获得包括第一表面、第二表面的半导体管芯，所述第一表面包括第一电气端子，所述第二表面包括第二电气端子，其中金属衬底被附连到所述半导体管芯的第二表面；
在所述半导体管芯中形成至少一个孔，从而使所述金属衬底的表面的一部分暴露；以及
在所述至少一个孔中沉积至少一个导电结构，其中所述至少一个导电结构与所述金属衬底电气连通。
13.如权利要求12所述的方法，其特征在于，进一步包括使机械层附连到所述金属衬底上，其中在附连之后，所述金属衬底在所述机械层与所述半导体衬底之间。
14.如权利要求12所述的方法，其特征在于，所述半导体管芯包括功率晶体管，其中所述第一端子是输入端子且所述第二端子是输出端子。
15.如权利要求12所述的方法，其特征在于，所述半导体管芯具有小于约50微米的厚度，且其中所述金属衬底具有大于约50微米的厚度。
16.如权利要求12所述的方法，其特征在于，所述导电结构是焊料凸点。
17.如权利要求12所述的方法，其特征在于，进一步包括在所述半导体管芯的第一表面上沉积至少一个导电结构，所述至少一个导电结构与所述第一端子电气连通。
18.如权利要求12所述的方法，其特征在于，所述形成至少一个孔包括蚀刻所述半导体管芯。
19.如权利要求12所述的方法，其特征在于，所述沉积至少一个导电结构包括电镀。
20.如权利要求12所述的方法，其特征在于，在沉积之后，形成半导体管芯封装，且所述方法包括：
将所述半导体管芯封装安装到电路板上。
21.一种方法，包括：
获得包括第一表面、第二表面的半导体管芯，所述第一表面包括源极端子，所述第二表面包括漏极端子，其中金属衬底被附连到所述半导体管芯的第二表面，且其中所述半导体管芯具有小于约50微米的厚度；
在所述半导体管芯中形成至少一个孔，从而使所述金属衬底的表面的一部分暴露；以及
在所述至少一个孔中沉积至少一个导电结构，其中所述至少一个导电结构与所述金属衬底电气连通。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102655134A (zh) * 2009-06-08 2012-09-05 万国半导体有限公司 功率半导体器件封装及制造方法
CN102800703A (zh) * 2011-05-23 2012-11-28 半导体元件工业有限责任公司 半导体装置

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7446374B2 (en) * 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US7944048B2 (en) * 2006-08-09 2011-05-17 Monolithic Power Systems, Inc. Chip scale package for power devices and method for making the same
US20080166837A1 (en) * 2007-01-10 2008-07-10 Tao Feng Power MOSFET wafer level chip-scale package
US7951688B2 (en) * 2007-10-01 2011-05-31 Fairchild Semiconductor Corporation Method and structure for dividing a substrate into individual devices
US20090194857A1 (en) * 2008-02-01 2009-08-06 Yong Liu Thin Compact Semiconductor Die Packages Suitable for Smart-Power Modules, Methods of Making the Same, and Systems Using the Same
US8101996B2 (en) * 2008-04-15 2012-01-24 Fairchild Semiconductor Corporation Three-dimensional semiconductor device structures and methods
US8237195B2 (en) * 2008-09-29 2012-08-07 Fairchild Semiconductor Corporation Power MOSFET having a strained channel in a semiconductor heterostructure on metal substrate
TWI456738B (zh) * 2010-09-02 2014-10-11 Sinopower Semiconductor Inc 整合轉換器之半導體元件及其封裝結構
CN102447383B (zh) * 2010-10-08 2014-08-27 大中积体电路股份有限公司 整合转换器的半导体组件及其封装结构
US8553420B2 (en) * 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US8614488B2 (en) * 2010-12-08 2013-12-24 Ying-Nan Wen Chip package and method for forming the same
US8487371B2 (en) 2011-03-29 2013-07-16 Fairchild Semiconductor Corporation Vertical MOSFET transistor having source/drain contacts disposed on the same side and method for manufacturing the same
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8304881B1 (en) 2011-04-21 2012-11-06 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US9059306B2 (en) * 2011-10-11 2015-06-16 Maxim Integrated Products, Inc. Semiconductor device having DMOS integration
US9984968B2 (en) * 2016-06-30 2018-05-29 Semiconductor Components Industries, Llc Semiconductor package and related methods
WO2018231045A1 (en) * 2017-06-15 2018-12-20 Jabil Inc. System, apparatus and method for utilizing surface mount technology on metal substrates
CN109473362B (zh) * 2018-10-29 2020-04-21 上海朕芯微电子科技有限公司 一种功率器件的csp封装方法
CN111146157A (zh) * 2018-11-02 2020-05-12 尼克森微电子股份有限公司 功率芯片封装结构
US11769768B2 (en) * 2020-06-01 2023-09-26 Wolfspeed, Inc. Methods for pillar connection on frontside and passive device integration on backside of die

Family Cites Families (168)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617826A (en) 1967-11-14 1971-11-02 Sony Corp An integrated transistor with a polycrystalline contact to a buried collector region
US3761782A (en) 1971-05-19 1973-09-25 Signetics Corp Semiconductor structure, assembly and method
US4205099A (en) 1978-04-14 1980-05-27 Sprague Electric Company Method for making terminal bumps on semiconductor wafers
JPS5691478A (en) 1979-12-26 1981-07-24 Hitachi Ltd Manufacture of punch-through type diode
US4416054A (en) 1980-07-01 1983-11-22 Westinghouse Electric Corp. Method of batch-fabricating flip-chip bonded dual integrated circuit arrays
JPS5773956A (en) 1980-10-27 1982-05-08 Hitachi Ltd Glass coated semiconductor device
US4680613A (en) 1983-12-01 1987-07-14 Fairchild Semiconductor Corporation Low impedance package for integrated circuit die
US4751199A (en) 1983-12-06 1988-06-14 Fairchild Semiconductor Corporation Process of forming a compliant lead frame for array-type semiconductor packages
US4772935A (en) 1984-12-19 1988-09-20 Fairchild Semiconductor Corporation Die bonding process
US4890153A (en) 1986-04-04 1989-12-26 Fairchild Semiconductor Corporation Single bonding shelf, multi-row wire-bond finger layout for integrated circuit package
US4720396A (en) 1986-06-25 1988-01-19 Fairchild Semiconductor Corporation Solder finishing integrated circuit package leads
US4791473A (en) 1986-12-17 1988-12-13 Fairchild Semiconductor Corporation Plastic package for high frequency semiconductor devices
US4839717A (en) 1986-12-19 1989-06-13 Fairchild Semiconductor Corporation Ceramic package for high frequency semiconductor devices
US4731701A (en) 1987-05-12 1988-03-15 Fairchild Semiconductor Corporation Integrated circuit package with thermal path layers incorporating staggered thermal vias
US5256893A (en) 1987-07-22 1993-10-26 Hitachi, Ltd. Semiconductor integrated circuit device with power MOSFET incorporated
US4796080A (en) 1987-07-23 1989-01-03 Fairchild Camera And Instrument Corporation Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate
US5130316A (en) * 1988-07-29 1992-07-14 Du Pont Merck Pharmaceutical Company Aminomethyloxooxazlidinyl arylbenzene derivatives useful as antibacterial agents
JPH0267731A (ja) 1988-09-02 1990-03-07 Toshiba Corp はんだバンプ形半導体装置とその製造方法
US5342797A (en) 1988-10-03 1994-08-30 National Semiconductor Corporation Method for forming a vertical power MOSFET having doped oxide side wall spacers
IT1224606B (it) 1988-10-10 1990-10-04 Eniricerche Spa Sensore chimico monolitico a membrana ione selettiva di tipo chemfet eprocedimento per la sua realizzazione
US5156989A (en) 1988-11-08 1992-10-20 Siliconix, Incorporated Complementary, isolated DMOS IC technology
EP0409226A3 (en) 1989-07-21 1993-01-13 Hitachi, Ltd. Power supply control system
US5023196A (en) 1990-01-29 1991-06-11 Motorola Inc. Method for forming a MOSFET with substrate source contact
US5134448A (en) 1990-01-29 1992-07-28 Motorola, Inc. MOSFET with substrate source contact
US5155562A (en) 1990-02-14 1992-10-13 Fuji Electric Co., Ltd. Semiconductor device equipped with a conductivity modulation misfet
US5994739A (en) 1990-07-02 1999-11-30 Kabushiki Kaisha Toshiba Integrated circuit device
US5216278A (en) 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
US5241133A (en) 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
US5856695A (en) 1991-10-30 1999-01-05 Harris Corporation BiCMOS devices
US5416351A (en) 1991-10-30 1995-05-16 Harris Corporation Electrostatic discharge protection
IT1254799B (it) 1992-02-18 1995-10-11 St Microelectronics Srl Transistore vdmos con migliorate caratteristiche di tenuta di tensione.
US5592025A (en) 1992-08-06 1997-01-07 Motorola, Inc. Pad array semiconductor device
US5352926A (en) 1993-01-04 1994-10-04 Motorola, Inc. Flip chip package and method of making
US5327325A (en) 1993-02-08 1994-07-05 Fairchild Space And Defense Corporation Three-dimensional integrated circuit package
JP2790033B2 (ja) * 1993-04-07 1998-08-27 松下電器産業株式会社 半導体装置
US5355283A (en) 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5396403A (en) * 1993-07-06 1995-03-07 Hewlett-Packard Company Heat sink assembly with thermally-conductive plate for a plurality of integrated circuits on a substrate
JP3015679B2 (ja) 1993-09-01 2000-03-06 株式会社東芝 半導体装置およびその製造方法
US5734201A (en) 1993-11-09 1998-03-31 Motorola, Inc. Low profile semiconductor device with like-sized chip and mounting substrate
US5539254A (en) * 1994-03-09 1996-07-23 Delco Electronics Corp. Substrate subassembly for a transistor switch module
US5467253A (en) 1994-06-30 1995-11-14 Motorola, Inc. Semiconductor chip package and method of forming
EP0706208B1 (en) 1994-10-03 2002-06-12 Kabushiki Kaisha Toshiba Method of manufacturing of a semiconductor package integral with semiconductor chip.
US5841197A (en) 1994-11-18 1998-11-24 Adamic, Jr.; Fred W. Inverted dielectric isolation process
US5455190A (en) 1994-12-07 1995-10-03 United Microelectronics Corporation Method of making a vertical channel device using buried source techniques
US5583376A (en) 1995-01-03 1996-12-10 Motorola, Inc. High performance semiconductor device with resin substrate and method for making the same
US5591655A (en) 1995-02-28 1997-01-07 Sgs-Thomson Microelectronics, Inc. Process for manufacturing a vertical switched-emitter structure with improved lateral isolation
JP2679681B2 (ja) 1995-04-28 1997-11-19 日本電気株式会社 半導体装置、半導体装置用パッケージ及びその製造方法
US5777362A (en) 1995-06-07 1998-07-07 Harris Corporation High efficiency quasi-vertical DMOS in CMOS or BICMOS process
JPH0945692A (ja) 1995-07-27 1997-02-14 Sharp Corp 縦型構造トランジスタ及びその製造方法、並びに半導体装置
US5844168A (en) 1995-08-01 1998-12-01 Minnesota Mining And Manufacturing Company Multi-layer interconnect sutructure for ball grid arrays
KR0157899B1 (ko) 1995-09-22 1998-12-01 문정환 기판에 반도체 장치를 부착시키기 위한 연결구조
DE19543540C1 (de) 1995-11-22 1996-11-21 Siemens Ag Vertikal integriertes Halbleiterbauelement mit zwei miteinander verbundenen Substraten und Herstellungsverfahren dafür
US5674785A (en) 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
JPH09213753A (ja) 1995-11-30 1997-08-15 Ricoh Co Ltd 半導体装置とプリント基板との接続構造体
US5578841A (en) 1995-12-18 1996-11-26 Motorola, Inc. Vertical MOSFET device having frontside and backside contacts
US5646446A (en) 1995-12-22 1997-07-08 Fairchild Space And Defense Corporation Three-dimensional flexible assembly of integrated circuits
US5866939A (en) 1996-01-21 1999-02-02 Anam Semiconductor Inc. Lead end grid array semiconductor package
US5731709A (en) 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US5865695A (en) * 1996-05-17 1999-02-02 Mahala; Robert Training device for basketball players for developing proper shooting technique
KR100231276B1 (ko) 1996-06-21 1999-11-15 황인길 반도체패키지의 구조 및 제조방법
US5841166A (en) 1996-09-10 1998-11-24 Spectrian, Inc. Lateral DMOS transistor for RF/microwave applications
US5807783A (en) 1996-10-07 1998-09-15 Harris Corporation Surface mount die by handle replacement
US5814884C1 (en) 1996-10-24 2002-01-29 Int Rectifier Corp Commonly housed diverse semiconductor die
US5866949A (en) 1996-12-02 1999-02-02 Minnesota Mining And Manufacturing Company Chip scale ball grid array for integrated circuit packaging
WO1998034285A1 (fr) 1997-01-31 1998-08-06 Matsushita Electronics Corporation Element electroluminescent, dispositif electroluminescent a semiconducteur, et leur procede de production
US5889332A (en) 1997-02-21 1999-03-30 Hewlett-Packard Company Area matched package
US6462976B1 (en) 1997-02-21 2002-10-08 University Of Arkansas Conversion of electrical energy from one form to another, and its management through multichip module structures
JPH10256574A (ja) 1997-03-14 1998-09-25 Toko Inc ダイオード装置
US6125448A (en) 1997-05-02 2000-09-26 3Com Corporation Power subsystem for a communication network containing a power bus
US6117299A (en) 1997-05-09 2000-09-12 Mcnc Methods of electroplating solder bumps of uniform height on integrated circuit substrates
JPH10335567A (ja) 1997-05-30 1998-12-18 Mitsubishi Electric Corp 半導体集積回路装置
US5869875A (en) 1997-06-10 1999-02-09 Spectrian Lateral diffused MOS transistor with trench source contact
US6395582B1 (en) * 1997-07-14 2002-05-28 Signetics Methods for forming ground vias in semiconductor packages
US5831832A (en) 1997-08-11 1998-11-03 Motorola, Inc. Molded plastic ball grid array package
US5965930A (en) 1997-11-04 1999-10-12 Motorola, Inc. High frequency bipolar transistor and method of forming the same
EP0926723B1 (en) 1997-11-26 2007-01-17 STMicroelectronics S.r.l. Process for forming front-back through contacts in micro-integrated electronic devices
US6075290A (en) 1998-02-26 2000-06-13 National Semiconductor Corporation Surface mount die: wafer level chip-scale package and process for making the same
US6373100B1 (en) 1998-03-04 2002-04-16 Semiconductor Components Industries Llc Semiconductor device and method for fabricating the same
US6048772A (en) 1998-05-04 2000-04-11 Xemod, Inc. Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection
JPH11354631A (ja) 1998-06-11 1999-12-24 Nec Kansai Ltd 半導体装置
US6064088A (en) 1998-06-15 2000-05-16 Xemod, Inc. RF power MOSFET device with extended linear region of transconductance characteristic at low drain current
US6133634A (en) 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
US6424035B1 (en) 1998-11-05 2002-07-23 Fairchild Semiconductor Corporation Semiconductor bilateral switch
US6608494B1 (en) 1998-12-04 2003-08-19 Advanced Micro Devices, Inc. Single point high resolution time resolved photoemission microscopy system and method
SG82591A1 (en) * 1998-12-17 2001-08-21 Eriston Technologies Pte Ltd Bumpless flip chip assembly with solder via
US6255852B1 (en) 1999-02-09 2001-07-03 Micron Technology, Inc. Current mode signal interconnects and CMOS amplifier
JP3813758B2 (ja) 1999-04-12 2006-08-23 エルピーダメモリ株式会社 半導体記憶装置
US6198166B1 (en) 1999-07-01 2001-03-06 Intersil Corporation Power semiconductor mounting package containing ball grid array
KR100335480B1 (ko) 1999-08-24 2002-05-04 김덕중 칩 패드가 방열 통로로 사용되는 리드프레임 및 이를 포함하는반도체 패키지
KR100462980B1 (ko) * 1999-09-13 2004-12-23 비쉐이 메저먼츠 그룹, 인코포레이티드 반도체장치용 칩 스케일 표면 장착 패키지 및 그 제조공정
KR100335481B1 (ko) 1999-09-13 2002-05-04 김덕중 멀티 칩 패키지 구조의 전력소자
US6483327B1 (en) 1999-09-30 2002-11-19 Advanced Micro Devices, Inc. Quadrant avalanche photodiode time-resolved detection
US6521982B1 (en) 2000-06-02 2003-02-18 Amkor Technology, Inc. Packaging high power integrated circuit devices
US6720642B1 (en) 1999-12-16 2004-04-13 Fairchild Semiconductor Corporation Flip chip in leaded molded package and method of manufacture thereof
TW516984B (en) 1999-12-28 2003-01-11 Toshiba Corp Solder material, device using the same and manufacturing process thereof
JP4646284B2 (ja) 2000-02-10 2011-03-09 インターナショナル レクティフィアー コーポレイション 単一表面上のバンプコンタクトを有する垂直伝導フリップチップ半導体デバイス
US6949822B2 (en) 2000-03-17 2005-09-27 International Rectifier Corporation Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance
CN1284421C (zh) 2000-03-22 2006-11-08 国际整流器公司 栅极驱动器多芯片模块
US6392290B1 (en) * 2000-04-07 2002-05-21 Siliconix Incorporated Vertical structure for semiconductor wafer-level chip scale packages
US6989588B2 (en) 2000-04-13 2006-01-24 Fairchild Semiconductor Corporation Semiconductor device including molded wireless exposed drain packaging
US6556750B2 (en) 2000-05-26 2003-04-29 Fairchild Semiconductor Corporation Bi-directional optical coupler
JP2001351929A (ja) 2000-06-09 2001-12-21 Hitachi Ltd 半導体装置およびその製造方法
KR100370231B1 (ko) 2000-06-13 2003-01-29 페어차일드코리아반도체 주식회사 리드프레임의 배면에 직접 부착되는 절연방열판을구비하는 전력 모듈 패키지
US6661082B1 (en) 2000-07-19 2003-12-09 Fairchild Semiconductor Corporation Flip chip substrate design
US6391687B1 (en) 2000-10-31 2002-05-21 Fairchild Semiconductor Corporation Column ball grid array package
KR100403608B1 (ko) 2000-11-10 2003-11-01 페어차일드코리아반도체 주식회사 스택구조의 인텔리젠트 파워 모듈 패키지 및 그 제조방법
US6525372B2 (en) 2000-11-16 2003-02-25 Silicon Wireless Corporation Vertical power devices having insulated source electrodes in discontinuous deep trenches
JP3415581B2 (ja) 2000-11-29 2003-06-09 Ｎｅｃエレクトロニクス株式会社 半導体装置
US6437981B1 (en) 2000-11-30 2002-08-20 Harris Corporation Thermally enhanced microcircuit package and method of forming same
TW577152B (en) 2000-12-18 2004-02-21 Hitachi Ltd Semiconductor integrated circuit device
KR100374629B1 (ko) 2000-12-19 2003-03-04 페어차일드코리아반도체 주식회사 얇고 작은 크기의 전력용 반도체 패키지
JP2002217416A (ja) 2001-01-16 2002-08-02 Hitachi Ltd 半導体装置
US6469384B2 (en) 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
US6570259B2 (en) 2001-03-22 2003-05-27 International Business Machines Corporation Apparatus to reduce thermal fatigue stress on flip chip solder connections
US6664841B1 (en) 2001-03-23 2003-12-16 Conexant Systems, Inc. Method and apparatus for conditioning an analog signal
US6930397B2 (en) 2001-03-28 2005-08-16 International Rectifier Corporation Surface mounted package with die bottom spaced from support board
US6891257B2 (en) 2001-03-30 2005-05-10 Fairchild Semiconductor Corporation Packaging system for die-up connection of a die-down oriented integrated circuit
JP2002359345A (ja) * 2001-03-30 2002-12-13 Toshiba Corp 半導体装置及びその製造方法
US6645791B2 (en) 2001-04-23 2003-11-11 Fairchild Semiconductor Semiconductor die package including carrier with mask
US6893901B2 (en) 2001-05-14 2005-05-17 Fairchild Semiconductor Corporation Carrier with metal bumps for semiconductor die packages
US7061080B2 (en) 2001-06-11 2006-06-13 Fairchild Korea Semiconductor Ltd. Power module package having improved heat dissipating capability
US6683375B2 (en) 2001-06-15 2004-01-27 Fairchild Semiconductor Corporation Semiconductor die including conductive columns
US6449174B1 (en) 2001-08-06 2002-09-10 Fairchild Semiconductor Corporation Current sharing in a multi-phase power supply by phase temperature control
US6582990B2 (en) 2001-08-24 2003-06-24 International Rectifier Corporation Wafer level underfill and interconnect process
JP3697184B2 (ja) 2001-08-27 2005-09-21 株式会社ルネサステクノロジ 電圧調整モジュール（ｖｒｍ）
JP3868777B2 (ja) 2001-09-11 2007-01-17 株式会社東芝 半導体装置
US6462621B1 (en) 2001-09-27 2002-10-08 Microchip Technology Incorporated Operational amplifier that is configurable as a progammable gain amplifier of a general purpose amplifier
US6774465B2 (en) 2001-10-05 2004-08-10 Fairchild Korea Semiconductor, Ltd. Semiconductor power package module
JP4387076B2 (ja) 2001-10-18 2009-12-16 株式会社ルネサステクノロジ 半導体装置
US6891256B2 (en) 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
US6642738B2 (en) 2001-10-23 2003-11-04 Fairchild Semiconductor Corporation Method and apparatus for field-effect transistor current sensing using the voltage drop across drain to source resistance that eliminates dependencies on temperature of the field-effect transistor and/or statistical distribution of the initial value of drain to source resistance
US6674157B2 (en) 2001-11-02 2004-01-06 Fairchild Semiconductor Corporation Semiconductor package comprising vertical power transistor
US6676310B2 (en) * 2001-11-15 2004-01-13 Hewlett-Packard Development Company, L.P. Check writing system and method
US6566749B1 (en) 2002-01-15 2003-05-20 Fairchild Semiconductor Corporation Semiconductor die package with improved thermal and electrical performance
US6830959B2 (en) 2002-01-22 2004-12-14 Fairchild Semiconductor Corporation Semiconductor die package with semiconductor die having side electrical connection
US6867489B1 (en) 2002-01-22 2005-03-15 Fairchild Semiconductor Corporation Semiconductor die package processable at the wafer level
JP2003258192A (ja) 2002-03-01 2003-09-12 Hitachi Ltd 半導体装置およびその製造方法
JP2003258197A (ja) * 2002-03-07 2003-09-12 Seiko Instruments Inc 半導体装置
JP3757881B2 (ja) 2002-03-08 2006-03-22 株式会社日立製作所 はんだ
DE10392377T5 (de) 2002-03-12 2005-05-12 FAIRCHILD SEMICONDUCTOR CORP. (n.d.Ges.d. Staates Delaware) Auf Waferniveau beschichtete stiftartige Kontakthöcker aus Kupfer
US6649961B2 (en) 2002-04-08 2003-11-18 Fairchild Semiconductor Corporation Supporting gate contacts over source region on MOSFET devices
US6641254B1 (en) 2002-04-12 2003-11-04 Hewlett-Packard Development Company, L.P. Electronic devices having an inorganic film
US6943056B2 (en) * 2002-04-16 2005-09-13 Renesas Technology Corp. Semiconductor device manufacturing method and electronic equipment using same
US6836023B2 (en) 2002-04-17 2004-12-28 Fairchild Semiconductor Corporation Structure of integrated trace of chip package
US6798180B2 (en) 2002-06-17 2004-09-28 Hitachi, Ltd. Power-supply device
US6664848B1 (en) 2002-06-26 2003-12-16 Sun Microsystems, Inc. On-chip power supply noise reduction
JP4601892B2 (ja) * 2002-07-04 2010-12-22 ラムバス・インコーポレーテッド 半導体装置および半導体チップのバンプ製造方法
US6946740B2 (en) 2002-07-15 2005-09-20 International Rectifier Corporation High power MCM package
US7061077B2 (en) 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die
US6777800B2 (en) 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US6943434B2 (en) 2002-10-03 2005-09-13 Fairchild Semiconductor Corporation Method for maintaining solder thickness in flipchip attach packaging processes
US7045884B2 (en) * 2002-10-04 2006-05-16 International Rectifier Corporation Semiconductor device package
US6731000B1 (en) 2002-11-12 2004-05-04 Koninklijke Philips Electronics N.V. Folded-flex bondwire-less multichip power package
US6882170B2 (en) 2002-12-05 2005-04-19 Intel Corporation Device speed alteration by electron-hole pair injection and device heating
US6969909B2 (en) 2002-12-20 2005-11-29 Vlt, Inc. Flip chip FET device
US6806580B2 (en) 2002-12-26 2004-10-19 Fairchild Semiconductor Corporation Multichip module including substrate with an array of interconnect structures
US7038917B2 (en) 2002-12-27 2006-05-02 Vlt, Inc. Low loss, high density array interconnection
US6771052B2 (en) 2003-01-03 2004-08-03 Astec International Limited Programmable multiple output DC-DC isolated power supply
JP3708082B2 (ja) 2003-02-27 2005-10-19 株式会社ルネサステクノロジ 電力半導体装置
US7129577B2 (en) * 2003-02-27 2006-10-31 Power-One, Inc. Power supply packaging system
US6867481B2 (en) 2003-04-11 2005-03-15 Fairchild Semiconductor Corporation Lead frame structure with aperture or groove for flip chip in a leaded molded package
JP2005217072A (ja) * 2004-01-28 2005-08-11 Renesas Technology Corp 半導体装置
US6900650B1 (en) 2004-03-01 2005-05-31 Transmeta Corporation System and method for controlling temperature during burn-in
US7507638B2 (en) 2004-06-30 2009-03-24 Freescale Semiconductor, Inc. Ultra-thin die and method of fabricating same
JP4153932B2 (ja) * 2004-09-24 2008-09-24 株式会社東芝 半導体装置および半導体装置の製造方法
US20060252262A1 (en) * 2005-05-03 2006-11-09 Rockwell Scientific Licensing, Llc Semiconductor structures having via structures between planar frontside and backside surfaces and methods of fabricating the same
US7635637B2 (en) 2005-07-25 2009-12-22 Fairchild Semiconductor Corporation Semiconductor structures formed on substrates and methods of manufacturing the same
US8018056B2 (en) * 2005-12-21 2011-09-13 International Rectifier Corporation Package for high power density devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102655134A (zh) * 2009-06-08 2012-09-05 万国半导体有限公司 功率半导体器件封装及制造方法
CN102800703A (zh) * 2011-05-23 2012-11-28 半导体元件工业有限责任公司 半导体装置
CN102800703B (zh) * 2011-05-23 2015-03-25 半导体元件工业有限责任公司 半导体装置

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Application publication date: 20090422