CN1284421C - 栅极驱动器多芯片模块 - Google Patents

栅极驱动器多芯片模块 Download PDF

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CN1284421C
CN1284421C CNB018069436A CN01806943A CN1284421C CN 1284421 C CN1284421 C CN 1284421C CN B018069436 A CNB018069436 A CN B018069436A CN 01806943 A CN01806943 A CN 01806943A CN 1284421 C CN1284421 C CN 1284421C
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power
module
substrate
chip module
mosfet
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CN1419798A (zh
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D·豪雷吉
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Infineon science and technology Americas
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International Rectifier Corp USA
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
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Abstract

一种多芯片模块MCM(2)，提供计算机主板(4)上的电源电路，密封在一个尺寸减小了的封装内，但性能没有降低。该MCM将关键的电源电路组件共同封装在一个球栅阵列(BGA)基片上。在该BGA基片上生成的两个功率MOSFET(8和10)在输入电压与地之间连接成半桥电路。MOSFET栅极驱动器(12)电气连接到两个功率MOSFET(8和10)相应的栅极输入端，交替开关两个功率MOSFET，以便在所述两个功率MOSFET之间的一个公共输出节点处产生交流输出电压。在BGA基片上生成至少一个肖特基二极管(16，18)，连接在所述公共输出节点与地之间，使得在空载导通期间，损耗达到最小。电路的输入电容器(C4)包括在MCM外壳内，靠近MOSFET，以减小电路中的杂散电感。MCM封装(2)很薄，其面积大约1cm×1cm或更小。

Description

栅极驱动器多芯片模块
发明领域
本发明涉及一种多芯片模块(MCM)。更具体地说，本发明涉及一种用于计算机主板的MCM电源电路。
背景技术
电源电路一般在计算机主板上占据一个不小的面积。因此，需要在不牺牲性能的前提下缩小电源电路的尺寸。
发明内容
本发明提供一种MCM，包括一个MOSFET栅极驱动器、两个功率MOSFET、以及相关的无源元件，所述无源元件中包括一个电容器，所有的这些元件都固定在一个球栅阵列(BGA)基片上，并密封在单个芯片中。
本发明的MCM的功率MOSFET在输入电压与地之间连接成半桥电路。MOSFET的栅极驱动器分别连接在两个功率MOSFET的栅极输入端，交替地开关这些功率MOSFET以便在两个功率MOSFET之间的公共输出节点产生交流输出电压。在上述BGA基片上至少生成一个肖特基二极管，连接在一个公共节点与地之间，以使空载导通期间的损耗最小。
无源电路组件包括连接在输入电压与地之间的输入电容器，为变换器提供输入电容。优选地，该输入电容器在物理上靠近所有其它组件。附加的组件为栅极控制器提供良好的偏置。所有的组件都密封在一种模塑料内从而形成上述MCM封装。
通过将上述输入电容器固定在靠近其它组件的位置并且是在很小的封装内，可以得到下述多种好处：
首先，在输入电容器与MOSFET之间的杂散电感很低，这样会减小在包括MOSFET寄生电容Coss和杂散电感L的电路内引起的“振荡”。减小电感就可以减小电路振荡。
其次，输入电容器在MCM封装内的位置使得主板可以独立布局，该主板不必再包括所述的电容器(在距离MCM封装内的MOSFET一定距离处)。
第三，电容器作为旁路通过封装内的一个MOSFET的体二极管(用较高的di/dt)导通不期望的电流，并帮助稳定MOSFET的QRR(反相恢复充电)。
模块最好密封在边界尺寸为大约11mm×11mm(即大约1cm×1cm)或更小的封装内。因此，输入电容器距离MOSFET的距离小于1cm。
本发明的MCM的优点在于其大小减小了50％，但性能没有降低，并且与印刷电路板(PCB)是独立的。封装的优点是比离散的方案性能更好。
本发明的其它特征和优点将通过下面结合附图所做的说明而更加清楚。
附图简述
图1是本发明的MCM内共同封装的有源和无源组件的平面布置图。
图2是根据本发明的MCM的正视图。
图3是根据本发明的MCM的电路原理图。
图3A是图3所示电路的部分等效电路图。
图4是根据本发明的MCM的时序图。
具体实施方式
参照图1，示出了本发明的MCM 2的优选的布置图。MCM 2包括六个固定在BGA基片4上的电路小片。在基片4的上表面布置有多个焊接区6。
电路小片8和10是功率MOSFET，最好分别是IRFC7811A和IRFC7809A功率MOSFET，布置为半桥电路。电路小片12是MOSFET栅极驱动器，最好是Semtech SC1405高速同步功率MOSFET智能驱动器。电路小片14、16和18是肖特基二极管，最好是SKM863二极管，如图3所示的电路原理图的方式连接。在基片4上表面固定的有源组件使用导线接头20电气连接到相应的焊接区6。
图1所示的无源组件包括电阻R1、电容器C1、C2、C3、C4，也如图3所示的电路原理图的方式连接。图中示出这些无源组件被直接连接到相应的焊接区6。显然，电容器C4靠近MOSFET8和10。
参考图2，示出本发明的MCM2的正视图。在基片4的下表面布置有多个焊球22。在完成的封装内，基片4上表面上的组件被密封在模塑料24内，如Nitto HC100。外壳2的尺寸约为1cm×1cm，因此在主板上所占的空间很小。
参考图3，示出电源MCM 2的电路原理图。功率MOSFET8和10连接成半桥形式，串联在输入电压VIN与接地PGND之间。外部电路电容CEXT连接到VIN。MOSFET栅极驱动器12的高电平侧输出栅极驱动TG连接到高电平侧功率MOSFET8的栅极输入端19。MOSFET栅极驱动器12的低电平侧输出栅极驱动BG连接到低电平侧功率MOSFET10的栅极输入端21。栅极驱动器12交替开关两个功率MOSFET，以便在所述功率MOSFET之间的一个公共输出节点SW NODE上产生交流输出电压。
肖特基二极管16和18连接在公共输出节点SW NODE与地之间，使得在空载导通阶段的损耗达到最小。输入电容器C4连接在输入电压VIN与地PGND之间。采用两个并联的二极管16和18帮助保持组件布置的对称性。通常将一个输出电感30连接到SW NODE和输出电压端子VOUT。输出电容器COUT也在输出电路中。
电源电压VDD在引线VCC提供给MOSFET栅极驱动器12。提供一个自举电路，包括肖特基二极管14和连接在该自举电路引线BST和DRN引线之间的电阻器R1/电容器C1，以产生高电平侧MOSFET8的空载自举电压。
在导线DRV_IN上提供一个TTL电平输入信号给MOSFET驱动器引线CO。该设备的工作通过在MOSFET驱动器12的使能端子EN上提供最小2.0V电压而使能。状态端子PRDY指示+5V电源电压的状态。当该电源电压低于4.4V时，该输出被置高。该输出具有10mA电源和10μA容量。当PRDY为低时，驱动器12内置的欠电压电路保证两个驱动器输出TG和BG都为低。
参考图4，示出MCM 2的时序图。在信号输入DRV_IN与MCM 2的输出SW NODE之间存在典型地为63ns的导通延迟tD(ON)。在信号输入DRV_IN与MCM 2的输出SW NODE之间存在典型地为26ns的关断延迟tD(OFF)。该延迟的一部分是驱动器12所固有的。
电源电压的范围可以是4.2V-6.0V。5V-12V之间的输入电压都可以使用，产生的输出电压的范围为0.9-1.2V。输出电流典型地是15A。设备的工作频率为300-1000kHz。
通过将输入电容器C4与MOSFET10之间的距离缩短，图3所示电路的工作得到显著的加强。
首先，从主板上去掉电容器C4增加了主板设计的灵活性。
其次，在主板上，由于电容器C4非常靠近MOSFET 8和10，电路中的杂散电感与电容器C4位于芯片之外时相比得以减小。该近距离(约1cm或更少)显著减小了电路中的“振荡”。更具体地说，如图3所示，MOSFET10具有寄生电容Coss。该电路包括杂散电感L和Coss，往往在谐振频率处发生振荡。通过减小L，就可以减小所述振荡。
电容器C4的第三个优点是它保持MOSFET10的QRR(反相恢复充电)稳定，并保持从模块2到主板的电流的高di/dt。更具体地说，图3A是图3所示电路的部分等效电路，特别示出MOSFET10的体二极管。在空载期间，即MOSFET8和10都关断期间，通过图3所示的肖特基二极管16和18导通，不过，“残余”电流还通过MOSFET10的体二极管导通。当MOSFET8在MOSFET10导通期间导通时，将会有一个反相恢复电流以很高的di/dt从外部电容器CEXT馈送。但是，电容器C4将作为该高di/dt的旁路。图3所示的电容器C4的功能与此类似。
虽然以上结合具体的实施例对本发明进行了阐述，但是对本发明的普通技术人员来说，其它各种变化和改动将是显而易见的。

Claims (19)

1.一种多芯片模块，用于在计算机主板上提供电源电路，包括：
球栅阵列基片；
在所述球栅阵列基片上生成的两个功率MOSFET，在输入电压与地之间连接成半桥电路；
在所述球栅阵列基片上生成的一个MOSFET栅极驱动器，电气连接到两个功率MOSFET的对应栅极输入端，用来交替开关所述功率MOSFET，以便在所述两个功率MOSFET之间的一个公共输出节点处产生交流输出电压；和
在所述球栅阵列基片上生成的至少一个二极管，连接在所述公共输出节点与地之间，使得在空载导通期间，损耗达到最小；以及
在所述球栅阵列基片上生成的一个输入电容器，连接在输入电压与地之间。
2.权利要求1的模块，还包括另一个二极管，与公共输出节点与地之间连接的二极管并联连接。
3.权利要求1的模块，其中，所述基片的面积大约为1厘米×1厘米或更小。
4.权利要求1的模块，其中，所述输入电容器与MOSFET间的距离小于1厘米。
5.权利要求1的模块，其中，所述输入电容器邻近所述两个功率MOSFET。
6.权利要求1的模块，还包括封装所述基片、MOSFET、栅极驱动器和至少一个二极管的绝缘外壳，所述球栅阵列通过该外壳的底部暴露出来，以固定在主板上。
7.权利要求6的模块，其中，所述外壳的面积大约为1厘米×1厘米或更小。
8.权利要求6的模块，其中，所述输入电容器邻近所述两个功率MOSFET。
9.权利要求5的模块，其中输入电容器与MOSFET的间距小于1厘米。
10.权利要求8的模块，其中输入电容器与MOSFET的间距小于1厘米。
11.一种多芯片模块，包括：
具有第一表面和相对的第二表面的基片；
功率输入连接；
接地连接；
两个功率开关器件，设置在所述基片的所述第一表面上，并且依照半桥布置串联连接在所述功率输入连接和所述接地连接之间；以及
输入电容器，连接在所述功率输入连接和所述接地连接之间，
其中所述输入电容器设置在所述基片的所述第一表面上并且与所述两个功率开关器件的间距不超过1厘米，且其中所述输入电容器和所述功率开关器件肩并肩地放置。
12.根据权利要求11的多芯片模块，其中所述功率开关器件是MOSFET。
13.根据权利要求11的多芯片模块，其中所述基片是球栅阵列。
14.根据权利要求11的多芯片模块，其中所述半桥连接包括位于所述两个功率开关器件之间的输出节点，还包括至少一个连接在所述输出节点和所述接地连接之间的肖特基二极管。
15.根据权利要求14的多芯片模块，还包括连接在所述输出节点和所述接地连接之间的另一肖特基二极管。
16.根据权利要求11的多芯片模块，还包括设置在所述基片上的控制器，用于选择性控制所述两个功率开关器件的操作。
17.根据权利要求11的多芯片模块，其中所述多芯片模块是1厘米×1厘米或者更小的。
18.根据权利要求11的多芯片模块，其中所述输入电容器减小了杂散电感，从而减少了由所述两个功率开关器件的所述至少一个中的共振引起的振荡。
19.根据权利要求11的多芯片模块，其中所述输入电容器设置在所述基片上并且与所述半桥布置中的下侧功率开关器件的间距不超过1厘米。
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