CN103681558A - 半导体封装件中的连接结构 - Google Patents

半导体封装件中的连接结构 Download PDF

Info

Publication number
CN103681558A
CN103681558A CN201210337060.3A CN201210337060A CN103681558A CN 103681558 A CN103681558 A CN 103681558A CN 201210337060 A CN201210337060 A CN 201210337060A CN 103681558 A CN103681558 A CN 103681558A
Authority
CN
China
Prior art keywords
layer
thickness
nickel dam
syndeton
metal level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201210337060.3A
Other languages
English (en)
Other versions
CN103681558B (zh
Inventor
林长甫
蔡和易
姚进财
何瑞忠
洪静慧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN103681558A publication Critical patent/CN103681558A/zh
Application granted granted Critical
Publication of CN103681558B publication Critical patent/CN103681558B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05584—Four-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05616—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16501—Material at the bonding interface
    • H01L2224/16503—Material at the bonding interface comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/365—Metallurgical effects
    • H01L2924/3651—Formation of intermetallics

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

一种半导体封装件中的连接结构，其设于基板的连接垫上，其包括凸块底下金属层以及一焊锡材料，且该凸块底下金属层依序为形成于该连接垫上的钛层、铜层、镍层及金属层，而该金属层为金层、银层、铅层或铜层的其中一者，又该金属层的厚度为0.5至5微米，所以当回焊该焊锡材料以形成焊锡凸块后，该焊锡凸块与该金属层之间不会产生锡镍化合物，以避免于该凸块底下金属层与该焊锡凸块之间发生凸块脱落的问题。

Description

半导体封装件中的连接结构
技术领域
本发明涉及一种连接结构，尤指一种半导体封装件中的连接结构。
背景技术
随电子产品朝多功能、高性能的发展，半导体封装件对应开发出不同的封装结构型态。其中一种半导体封装件主要将半导体组件借由焊锡凸块放置并电性连接至一封装基板(package substrate)上，再将封装基板连同半导体组件进行封装。因此，现有半导体组件与封装基板上均具有连接垫，以供该封装基板与半导体组件借由焊锡凸块相互对接与电性连接。
如图1所示，一基板30（如半导体芯片）具有多个铝材的连接垫300（于此仅以单一连接垫300即可表示全部连接垫300的情况），且该基板30上形成有外露该连接垫300的一绝缘保护层301；接着，于该连接垫300的外露表面上依序形成一钛层11、一铜层12及一镍层13，以作为凸块底下金属层（Under Bump Metallurgy,UBM）；之后，于该镍层13上形成焊锡材料15以构成连接结构1，再回焊（reflow）该焊锡材料15，以形成焊锡凸块，且该焊锡凸块与镍层13之间的接口上会形成接口合金共化物（Inter Metallic Compound,IMC）13’。
然而，现有接口合金共化物13’的成分为锡镍化合物（NixSny），如锡化镍（Ni3Sn4），其因脆性较强而易损及该焊锡凸块的机械强度、寿命及疲劳强度(Fatigue Strength)，所以当信赖性测试后，于该UBM与该焊锡凸块的接口容易发生凸块碎裂（bump crack）或脱落，导致产品的良率降低。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷，本发明的主要目的在于提供一种半导体封装件中的连接结构，以避免于该UBM与该焊锡凸块之间发生凸块脱落的问题。
本发明的半导体封装件包含一具有连接垫的基板，供该连接结构设于该连接垫上，该连接结构包括：镍层，其形成于该连接垫上；以及金属层，其形成于该镍层上，且该金属层为金层、银层、铅层或铜层的其中一者，又该金属层的厚度为0.5至5微米。
前述的连接结构中，该镍层的厚度为3微米。
前述的连接结构中，还包括钛层，其形成于该连接垫与该镍层之间，且该镍层的厚度大于该钛层的厚度，例如，该钛层的厚度为0.3微米。
前述的连接结构中，还包括铜层，其形成于该连接垫与该镍层之间，且该镍层的厚度大于该铜层的厚度，例如，该铜层的厚度为0.3微米。
前述的连接结构中，还包括形成于该连接垫与该镍层之间的钛层、及形成于该钛层与该镍层之间的铜层，该镍层的厚度大于该钛层的厚度，且镍层的厚度也大于该铜层的厚度。
前述的连接结构中，还包括形成于该金属层上的焊锡材料。
由上可知，本发明的连接结构借由于该镍层上形成不为镍层或焊锡层的金属层，以阻隔该镍层与该焊锡材料，可避免于回焊工艺后产生锡镍化合物，所以相比于现有技术，本发明的连接结构能有效避免于该UBM与该焊锡凸块之间发生凸块碎裂或脱落的问题。
附图说明
图1为现有半导体封装件的连接结构的剖视示意图；以及
图2为本发明半导体封装件的连接结构的剖视示意图。
主要组件符号说明
1,2连接结构
11,21钛层
12,22铜层
13,23镍层
13’,24’接口合金共化物
15,25焊锡材料
24金属层
30基板
300连接垫
301绝缘保护层。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2为本发明的半导体封装件中的连接结构2的剖面示意图。
如图2所示，该半导体封装件包含一具有至少一连接垫300的基板30，该连接结构2设于该连接垫300上，且该连接结构2包括：一钛层21、一铜层22、一镍层23、一金属层24以及一焊锡材料25。
所述的基板30为半导体芯片且还具有外露该连接垫300的一绝缘保护层301，以令该连接垫300的外露表面上可形成凸块底下金属层（Under Bump Metallurgy,UBM）。于本实施例中，形成该连接垫300的材质为铝，且该凸块底下金属层包含该钛层21、该铜层22、该镍层23及该金属层24。
所述的钛层21形成于该连接垫300上，且该钛层21的厚度约为0.3微米。
所述的铜层22形成于该钛层21上，且该铜层22的厚度约为0.3微米。
所述的镍层23形成于该铜层22上，该镍层23的厚度大于该钛层21的厚度，且镍层23的厚度也大于该铜层22的厚度。于本实施例中，该镍层23的厚度约为3微米。
所述的金属层24形成于该镍层23上，且该金属层24不为另一镍层或焊锡层。于本实施例中，该金属层24为另一铜层，也就是该铜层22可称为第一铜层，而材质为铜的金属层24为第二铜层，且该金属层24的厚度为0.5至5微米。
所述的焊锡材料25形成于该金属层24上。于本实施例中，该焊锡材料25采用无铅工艺环境中的锡银(SnAg)合金，而于其它实施例中，该焊锡材料25也可为锡银铜（SAC）无铅锡膏。
当回焊该焊锡材料25成为焊锡凸块时，该金属层24的铜材将消耗于该焊锡材料25中，使该焊锡材料25与金属层24之间的接口上所形成的接口合金共化物（Inter Metallic Compound,IMC）24’的成分为锡铜化合物（CuxSny），如Cu6Sn5，而无任何锡化镍成分，且该焊锡凸块的材质为类似无铅的锡银铜合金。
本发明的接口合金共化物24’为锡铜化合物，所以其硬度低于现有IMC（NixSny材）的硬度，约降低5至10%，且相比于现有IMC的破裂韧性，本发明的接口合金共化物24’的破裂韧性可提高30至40%。
因此，本实施例的连接结构2主要借由形成另一铜层（即该金属层24）于该镍层23上，以于回焊工艺后，使该金属层24与该焊锡材料25之间的接口上形成良好的接口合金共化物（即锡铜化合物），且该锡铜化合物因结合性较佳，而不会影响焊锡凸块的机械强度、寿命及疲劳强度，所以可避免发生凸块碎裂或脱落等问题，因而有效提升产品的可靠度。
另外，于其它实施例中，该金属层24也可为金层、铅层或银层。若该金属层24为金层或铅层，当回焊该焊锡材料25时，该金材或铅材会溶入该焊锡材料25中，而不会形成IMC；若该金属层24为银层，因银材为该焊锡材料25的成分，所以该金属层24可视为焊锡材料，因而当回焊该焊锡材料25时，并不会形成IMC，因此，不会影响焊锡凸块的品质。
综上所述，本发明的连接结构，主要借由于该镍层上形成如铜层、金层、铅层或银层的金属层，以避免于回焊工艺后产生锡镍化合物，所以能有效避免发生凸块碎裂或脱落的问题，以达到提升产品良率的目的。
上述实施例用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (11)

1.一种半导体封装件中的连接结构，该半导体封装件包含一具有连接垫的基板，供该连接结构设于该连接垫上，该连接结构包括：
镍层，其形成于该连接垫上；以及
金属层，其形成于该镍层上，且该金属层为金层、银层、铅层或铜层的其中一者，又该金属层的厚度为0.5至5微米。
2.根据权利要求1所述的连接结构，其特征在于，该镍层的厚度为3微米。
3.根据权利要求1所述的连接结构，其特征在于，该结构还包括形成于该连接垫与该镍层之间的钛层。
4.根据权利要求3所述的连接结构，其特征在于，该镍层的厚度大于该钛层的厚度。
5.根据权利要求3所述的连接结构，其特征在于，该钛层的厚度为0.3微米。
6.根据权利要求1所述的连接结构，其特征在于，该结构还包括形成于该连接垫与该镍层之间的铜层。
7.根据权利要求6所述的连接结构，其特征在于，该镍层的厚度大于该铜层的厚度。
8.根据权利要求6所述的连接结构，其特征在于，该铜层的厚度为0.3微米。
9.根据权利要求1所述的连接结构，其特征在于，该结构还包括形成于该连接垫与该镍层之间的钛层、及形成于该钛层与该镍层之间的铜层。
10.根据权利要求9所述的连接结构，其特征在于，该镍层的厚度大于该钛层的厚度，且镍层的厚度也大于该铜层的厚度。
11.根据权利要求1所述的连接结构，其特征在于，该结构还包括形成于该金属层上的焊锡材料。
CN201210337060.3A 2012-09-03 2012-09-12 半导体封装件中的连接结构 Active CN103681558B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW101131977A TWI490994B (zh) 2012-09-03 2012-09-03 半導體封裝件中之連接結構
TW101131977 2012-09-03

Publications (2)

Publication Number Publication Date
CN103681558A true CN103681558A (zh) 2014-03-26
CN103681558B CN103681558B (zh) 2017-11-24

Family

ID=50186360

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210337060.3A Active CN103681558B (zh) 2012-09-03 2012-09-12 半导体封装件中的连接结构

Country Status (3)

Country Link
US (1) US9013042B2 (zh)
CN (1) CN103681558B (zh)
TW (1) TWI490994B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106898582A (zh) * 2015-12-18 2017-06-27 株洲南车时代电气股份有限公司 一种半导体器件金属薄膜结构及其制作方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI612632B (zh) * 2014-05-09 2018-01-21 矽品精密工業股份有限公司 封裝結構、晶片結構及其製法
TWI548011B (zh) * 2014-05-13 2016-09-01 矽品精密工業股份有限公司 封裝基板及其製法
KR102430984B1 (ko) 2015-09-22 2022-08-09 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR101942737B1 (ko) * 2017-08-04 2019-01-29 삼성전기 주식회사 반도체 패키지 연결 시스템
US10903151B2 (en) * 2018-05-23 2021-01-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040104484A1 (en) * 2002-10-25 2004-06-03 William Tze-You Chen [under-ball-metallurgy layer]
CN1753159A (zh) * 2004-09-22 2006-03-29 日月光半导体制造股份有限公司 整合打线及倒装封装的芯片结构及制程
CN101090099A (zh) * 2006-06-12 2007-12-19 中芯国际集成电路制造(上海)有限公司 焊料凸块及其制造方法
US20080277784A1 (en) * 2007-05-07 2008-11-13 Sony Corporation Semiconductor chip and manufacturing method thereof
US7915741B2 (en) * 2009-02-24 2011-03-29 Unisem Advanced Technologies Sdn. Bhd. Solder bump UBM structure
CN102024769A (zh) * 2009-09-14 2011-04-20 台湾积体电路制造股份有限公司 集成电路元件
CN102037370A (zh) * 2008-05-22 2011-04-27 意法半导体（格勒诺布尔）公司 制造和测试集成电路的方法
US20110127668A1 (en) * 2006-02-07 2011-06-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Bump Structure with Multi-Layer UBM Around Bump Formation Area
CN102148211A (zh) * 2010-02-09 2011-08-10 台湾积体电路制造股份有限公司 半导体组件、半导体元件及其制法
CN102148201A (zh) * 2010-02-04 2011-08-10 台湾积体电路制造股份有限公司 半导体元件、封装结构、及半导体元件的形成方法
CN102290379A (zh) * 2010-06-18 2011-12-21 台湾积体电路制造股份有限公司 半导体结构及半导体装置的制造方法
CN102403290A (zh) * 2010-09-10 2012-04-04 台湾积体电路制造股份有限公司 半导体组件及制造半导体组件的方法
CN102437135A (zh) * 2011-12-19 2012-05-02 南通富士通微电子股份有限公司 圆片级柱状凸点封装结构
CN102496603A (zh) * 2011-12-19 2012-06-13 南通富士通微电子股份有限公司 一种芯片级封装结构
CN102496604A (zh) * 2011-12-19 2012-06-13 南通富士通微电子股份有限公司 高可靠芯片级封装结构

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2943805B1 (ja) * 1998-09-17 1999-08-30 日本電気株式会社 半導体装置及びその製造方法
US7095121B2 (en) * 2002-05-17 2006-08-22 Texas Instrument Incorporated Metallic strain-absorbing layer for improved fatigue resistance of solder-attached devices
TWI259572B (en) * 2004-09-07 2006-08-01 Siliconware Precision Industries Co Ltd Bump structure of semiconductor package and fabrication method thereof
TW200733270A (en) * 2005-10-19 2007-09-01 Koninkl Philips Electronics Nv Redistribution layer for wafer-level chip scale package and method therefor
TW201203403A (en) * 2010-07-12 2012-01-16 Siliconware Precision Industries Co Ltd Semiconductor element and fabrication method thereof

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040104484A1 (en) * 2002-10-25 2004-06-03 William Tze-You Chen [under-ball-metallurgy layer]
CN1753159A (zh) * 2004-09-22 2006-03-29 日月光半导体制造股份有限公司 整合打线及倒装封装的芯片结构及制程
US20110127668A1 (en) * 2006-02-07 2011-06-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Bump Structure with Multi-Layer UBM Around Bump Formation Area
CN101090099A (zh) * 2006-06-12 2007-12-19 中芯国际集成电路制造(上海)有限公司 焊料凸块及其制造方法
US20080277784A1 (en) * 2007-05-07 2008-11-13 Sony Corporation Semiconductor chip and manufacturing method thereof
CN102037370A (zh) * 2008-05-22 2011-04-27 意法半导体（格勒诺布尔）公司 制造和测试集成电路的方法
US7915741B2 (en) * 2009-02-24 2011-03-29 Unisem Advanced Technologies Sdn. Bhd. Solder bump UBM structure
CN102024769A (zh) * 2009-09-14 2011-04-20 台湾积体电路制造股份有限公司 集成电路元件
CN102148201A (zh) * 2010-02-04 2011-08-10 台湾积体电路制造股份有限公司 半导体元件、封装结构、及半导体元件的形成方法
CN102148211A (zh) * 2010-02-09 2011-08-10 台湾积体电路制造股份有限公司 半导体组件、半导体元件及其制法
CN102290379A (zh) * 2010-06-18 2011-12-21 台湾积体电路制造股份有限公司 半导体结构及半导体装置的制造方法
CN102403290A (zh) * 2010-09-10 2012-04-04 台湾积体电路制造股份有限公司 半导体组件及制造半导体组件的方法
CN102437135A (zh) * 2011-12-19 2012-05-02 南通富士通微电子股份有限公司 圆片级柱状凸点封装结构
CN102496603A (zh) * 2011-12-19 2012-06-13 南通富士通微电子股份有限公司 一种芯片级封装结构
CN102496604A (zh) * 2011-12-19 2012-06-13 南通富士通微电子股份有限公司 高可靠芯片级封装结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106898582A (zh) * 2015-12-18 2017-06-27 株洲南车时代电气股份有限公司 一种半导体器件金属薄膜结构及其制作方法
CN106898582B (zh) * 2015-12-18 2019-05-31 株洲南车时代电气股份有限公司 一种半导体器件金属薄膜结构及其制作方法

Also Published As

Publication number Publication date
CN103681558B (zh) 2017-11-24
TW201411794A (zh) 2014-03-16
US20140061928A1 (en) 2014-03-06
US9013042B2 (en) 2015-04-21
TWI490994B (zh) 2015-07-01

Similar Documents

Publication Publication Date Title
CN103681558A (zh) 半导体封装件中的连接结构
CN100468674C (zh) 半导体器件及其制造方法、线路板及其制造方法、半导体封装件和电子装置
CN100565859C (zh) 具有改进的机械可靠性和热可靠性的半导体装置
CN103811449B (zh) 焊球凸块结构及其形成方法
US20070182006A1 (en) Semiconductor device with an improved solder joint
US20100084765A1 (en) Semiconductor package having bump ball
CN1930672A (zh) 允许使用高含锡量焊块的凸块下金属化层
CN103299406A (zh) 用于改善耐脆性断裂的焊接方法及相关器件
US20100127047A1 (en) Method of inhibiting a formation of palladium-nickel-tin intermetallic in solder joints
JP5636122B1 (ja) 半導体構造およびその製造方法
CN101924088A (zh) 一种集成电路结构
CN100392850C (zh) 一种引线框架以及具有所述引线框架的半导体器件
CN104099653A (zh) 半导体结构及其制造方法
CN103187324A (zh) 一种焊点制备方法及其结构
TWI242866B (en) Process of forming lead-free bumps on electronic component
CN103050466B (zh) 半导体封装件及其制法
CN201829475U (zh) 半导体芯片互连结构及应用其的半导体封装件
TWI336516B (en) Surface structure of package substrate and method for manufacturing the same
CN103958120A (zh) 锡基焊球和包含它的半导体封装
CN101989587A (zh) 电路板的电性连接结构及电路板装置
CN103811442A (zh) 基板的连接结构及其制法
CN104810344A (zh) 堆叠组及其制法与基板结构
KR101009192B1 (ko) 반도체 장치의 범프 구조물 및 그 제조방법
CN102487049B (zh) 半导体基板及其制法
TWI305403B (en) Lead-free conductive jointing bump

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant