TWI490994B - 半導體封裝件中之連接結構 - Google Patents

半導體封裝件中之連接結構 Download PDF

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TWI490994B
TWI490994B TW101131977A TW101131977A TWI490994B TW I490994 B TWI490994 B TW I490994B TW 101131977 A TW101131977 A TW 101131977A TW 101131977 A TW101131977 A TW 101131977A TW I490994 B TWI490994 B TW I490994B
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Taiwan
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layer
thickness
nickel
connection structure
copper
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TW101131977A
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English (en)
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TW201411794A (zh
Inventor
林長甫
蔡和易
姚進財
何瑞忠
洪靜慧
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矽品精密工業股份有限公司
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Priority to TW101131977A priority Critical patent/TWI490994B/zh
Priority to CN201210337060.3A priority patent/CN103681558B/zh
Priority to US13/677,861 priority patent/US9013042B2/en
Publication of TW201411794A publication Critical patent/TW201411794A/zh
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Publication of TWI490994B publication Critical patent/TWI490994B/zh

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/365—Metallurgical effects
    • H01L2924/3651—Formation of intermetallics

Description

半導體封裝件中之連接結構
本發明係有關一種連接結構，尤指一種半導體封裝件中之連接結構。
隨電子產品朝多功能、高性能的發展，半導體封裝件係對應開發出不同的封裝結構型態。其中一種半導體封裝件主要係將半導體元件藉由銲錫凸塊放置並電性連接至一封裝基板(package substrate)上，再將封裝基板連同半導體元件進行封裝。因此，習知半導體元件與封裝基板上均具有連接墊，以供該封裝基板與半導體元件藉由銲錫凸塊相互對接與電性連接。
如第1圖所示，一基板30(如半導體晶片)係具有複數鋁材之連接墊300(於此僅以單一連接墊300即可表示全部連接墊300之情況)，且該基板30上形成有外露該連接墊300之一絕緣保護層301；接著，於該連接墊300之外露表面上依序形成一鈦層11、一銅層12及一鎳層13，以作為凸塊底下金屬層(Under Bump Metallurgy,UBM)；之後，於該鎳層13上形成銲錫材料15以構成連接結構1，再回銲(reflow)該銲錫材料15，以形成銲錫凸塊，且該銲錫凸塊與鎳層13之間的介面上會形成介面合金共化物(Inter Metallic Compound,IMC)13’。
惟，習知介面合金共化物13’之成分係為錫鎳化合物(Nix Sny )，如錫化鎳(Ni3 Sn4 )，其因脆性較強而易損及 該銲錫凸塊之機械強度、壽命及疲勞強度(Fatigue Strength)，故當信賴性測試後，於該UBM與該銲錫凸塊之介面容易發生凸塊碎裂(bump crack)或脫落，導致產品之良率降低。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件中之連接結構，該半導體封裝件包含一具有連接墊之基板，供該連接結構設於該連接墊上，該連接結構係包括：鎳層，係形成於該連接墊上；以及金屬層，係形成於該鎳層上，且該金屬層係為金層、銀層、鉛層或銅層之其中一者，又該金屬層之厚度係為0.5至5微米。
前述之連接結構中，該鎳層之厚度係為3微米。
前述之連接結構中，復包括鈦層，係形成於該連接墊與該鎳層之間，且該鎳層之厚度係大於該鈦層之厚度，例如，該鈦層之厚度係為0.3微米。
前述之連接結構中，復包括銅層，係形成於該連接墊與該鎳層之間，且該鎳層之厚度係大於該銅層之厚度，例如，該銅層之厚度係為0.3微米。
前述之連接結構中，復包括形成於該連接墊與該鎳層之間的鈦層、及形成於該鈦層與該鎳層之間的銅層，該鎳層之厚度係大於該鈦層之厚度，且鎳層之厚度亦大於該銅層之厚度。
前述之連接結構中，復包括形成於該金屬層上之銲錫材料。
由上可知，本發明之連接結構係藉由於該鎳層上形成不為鎳層或銲錫層之金屬層，以阻隔該鎳層與該銲錫材料，可避免於回銲製程後產生錫鎳化合物，故相較於習知技術，本發明之連接結構能有效避免於該UBM與該銲錫凸塊之間發生凸塊碎裂或脫落的問題。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2圖係為本發明之半導體封裝件中之連接結構2的剖面示意圖。
如第2圖所示，該半導體封裝件包含一具有至少一連接墊300之基板30，該連接結構2設於該連接墊300上，且該連接結構2係包括：一鈦層21、一銅層22、一鎳層23、一金屬層24以及一銲錫材料25。
所述之基板30係為半導體晶片且復具有外露該連接墊300之一絕緣保護層301，以令該連接墊300之外露表面上可形成凸塊底下金屬層(Under Bump Metallurgy,UBM)。於本實施例中，形成該連接墊300之材質係為鋁，且該凸塊底下金屬層係包含該鈦層21、該銅層22、該鎳層23及該金屬層24。
所述之鈦層21係形成於該連接墊300上，且該鈦層21之厚度係約為0.3微米。
所述之銅層22係形成於該鈦層21上，且該銅層22之厚度係約為0.3微米。
所述之鎳層23係形成於該銅層22上，該鎳層23之厚度係大於該鈦層21之厚度，且鎳層23之厚度亦大於該銅層22之厚度。於本實施例中，該鎳層23之厚度係約為3微米。
所述之金屬層24係形成於該鎳層23上，且該金屬層24不為另一鎳層或銲錫層。於本實施例中，該金屬層24係為另一銅層，亦即該銅層22可稱為第一銅層，而材質為銅的金屬層24為第二銅層，且該金屬層24之厚度係為0.5至5微米。
所述之銲錫材料25係形成於該金屬層24上。於本實 施例中，該銲錫材料25係採用無鉛製程環境中之錫銀(SnAg)合金，而於其它實施例中，該銲錫材料25亦可為錫銀銅(SAC)無鉛錫膏。
當回銲該銲錫材料25成為銲錫凸塊時，該金屬層24之銅材將消耗於該銲錫材料25中，使該銲錫材料25與金屬層24之間的介面上所形成之介面合金共化物(Inter Metallic Compound,IMC)24’之成分係為錫銅化合物(Cux Sny )，如Cu6 Sn5 ，而無任何錫化鎳成分，且該銲錫凸塊之材質係為類似無鉛之錫銀銅合金。
本發明之介面合金共化物24’係為錫銅化合物，故其硬度低於習知IMC(Nix Sny 材)之硬度，約降低5至10%，且相較於習知IMC之破裂韌性，本發明之介面合金共化物24’之破裂韌性可提高30至40%。
因此，本實施例之連接結構2係主要藉由形成另一銅層(即該金屬層24)於該鎳層23上，以於回銲製程後，使該金屬層24與該銲錫材料25之間的介面上形成良好之介面合金共化物(即錫銅化合物)，且該錫銅化合物因結合性較佳，而不會影響銲錫凸塊之機械強度、壽命及疲勞強度，故可避免發生凸塊碎裂或脫落等問題，因而有效提升產品之可靠度。
另外，於其它實施例中，該金屬層24亦可為金層、鉛層或銀層。若該金屬層24為金層或鉛層，當回銲該銲錫材料25時，該金材或鉛材會溶入該銲錫材料25中，而不會形成IMC；若該金屬層24為銀層，因銀材為該銲錫材料 25之成分，故該金屬層24可視為銲錫材料，因而當回銲該銲錫材料25時，並不會形成IMC，因此，不會影響銲錫凸塊之品質。
綜上所述，本發明之連接結構，主要藉由於該鎳層上形成如銅層、金層、鉛層或銀層之金屬層，以避免於回銲製程後產生錫鎳化合物，故能有效避免發生凸塊碎裂或脫落的問題，以達到提升產品良率之目的。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2‧‧‧連接結構
11,21‧‧‧鈦層
12,22‧‧‧銅層
13,23‧‧‧鎳層
13’,24’‧‧‧介面合金共化物
15,25‧‧‧銲錫材料
24‧‧‧金屬層
30‧‧‧基板
300‧‧‧連接墊
301‧‧‧絕緣保護層
第1圖係為習知半導體封裝件之連接結構之剖視示意圖；以及第2圖係為本發明半導體封裝件之連接結構之剖視示意圖。
2‧‧‧連接結構
21‧‧‧鈦層
22‧‧‧銅層
23‧‧‧鎳層
24‧‧‧金屬層
24’‧‧‧介面合金共化物
25‧‧‧銲錫材料
30‧‧‧基板
300‧‧‧連接墊
301‧‧‧絕緣保護層

Claims (11)

  1. 一種半導體封裝件中之連接結構，該半導體封裝件包含一具有連接墊之基板，供該連接結構設於該連接墊上，該連接結構係為凸塊底下金屬層(Under Bump Metallurgy,UBM)，其包括：鎳層，係形成於該連接墊上；以及金屬層，係形成於該鎳層上，且該金屬層係為金層、銀層、鉛層或銅層之其中一者，又該金屬層之厚度係為0.5至5微米。
  2. 如申請專利範圍第1項所述之連接結構，其中，該鎳層之厚度係為3微米。
  3. 如申請專利範圍第1項所述之連接結構，復包括形成於該連接墊與該鎳層之間的鈦層。
  4. 如申請專利範圍第3項所述之連接結構，其中，該鎳層之厚度係大於該鈦層之厚度。
  5. 如申請專利範圍第3項所述之連接結構，其中，該鈦層之厚度係為0.3微米。
  6. 如申請專利範圍第1項所述之連接結構，復包括形成於該連接墊與該鎳層之間的銅層。
  7. 如申請專利範圍第6項所述之連接結構，其中，該鎳層之厚度係大於該銅層之厚度。
  8. 如申請專利範圍第6項所述之連接結構，其中，該銅層之厚度係為0.3微米。
  9. 如申請專利範圍第1項所述之連接結構，復包括形成 於該連接墊與該鎳層之間的鈦層、及形成於該鈦層與該鎳層之間的銅層。
  10. 如申請專利範圍第9項所述之連接結構，其中，該鎳層之厚度係大於該鈦層之厚度，且鎳層之厚度亦大於該銅層之厚度。
  11. 如申請專利範圍第1項所述之連接結構，復包括形成於該金屬層上之銲錫材料。
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