TWI609473B - 半導體裝置及用於製造半導體裝置之方法 - Google Patents

半導體裝置及用於製造半導體裝置之方法 Download PDF

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Publication number
TWI609473B
TWI609473B TW105105050A TW105105050A TWI609473B TW I609473 B TWI609473 B TW I609473B TW 105105050 A TW105105050 A TW 105105050A TW 105105050 A TW105105050 A TW 105105050A TW I609473 B TWI609473 B TW I609473B
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layer
intermetallic compound
copper
solder
semiconductor
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TW105105050A
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TW201633488A (zh
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蕭友享
李秋雯
楊秉豐
林光隆
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日月光半導體製造股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262—Sn as the principal constituent
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
    • B23K35/302—Cu as the principal constituent
    • C—CHEMISTRY; METALLURGY
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    • C22C—ALLOYS
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    • C—CHEMISTRY; METALLURGY
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Description

半導體裝置及用於製造半導體裝置之方法
本發明係關於半導體結構及半導體製程之領域，且更特定而言，係關於半導體覆晶結合裝置及用於製造該半導體覆晶結合裝置之半導體製程。
在習知半導體覆晶結合方法中，鎳(Ni)材料之阻障層塗佈至上部晶粒之銅柱，且焊料形成於鎳阻障層上。接著，上部晶粒置放於底部晶粒或基板上，使得銅柱上之焊料接觸底部晶粒或基板之焊墊。在回焊製程之後，焊料經熔融而連接至焊墊以便形成半導體覆晶結合裝置。
在回焊製程期間，焊料可與底部晶粒或基板之焊墊反應以便形成金屬間化合物(Intermetallic Compound,IMC)。通常，焊料之材料為錫銀合金(例如，SnAg)，焊墊之材料為銅(Cu)，且金屬間化合物之材料因此為錫、銀及銅之組合，諸如銅錫合金(Cu6Sn5或Cu3Sn4)或鎳錫合金(Ni6Sn5、或Ni3Sn4)。金屬間化合物可使焊料與焊墊之間的結合更緊密。然而，若焊墊較薄，則整個焊墊可能會與焊料反應而使得焊墊破裂。另外，由於金屬間化合物為脆性的，因此較厚的金屬間化合物層將減小半導體覆晶結合裝置之剪切強度(Shear Strength)。此外，若焊料極薄(例如，小於30μm)，則金屬間化合物與焊料之體積比可大 於80%，此可導致接合破裂(Joint Crack)。
因此，需要新的半導體裝置及用於控制金屬間化合物之量的半導體製程。
本發明之一態樣係關於半導體裝置及用於製造該半導體裝置之方法。該半導體裝置包括半導體晶粒、半導體元件及焊料層。半導體晶粒包括銅柱。半導體元件包括表面處理層，其中表面處理層之材料為鎳、金及鈀中之至少兩者之組合。焊料層位於銅柱與表面處理層之間。焊料層包括第一金屬間化合物(IMC)及第二金屬間化合物。第一金屬間化合物包括銅、鎳及錫之組合。第二金屬間化合物包括金與錫之組合、鈀與錫之組合或兩者。
本發明之另一態樣係關於半導體裝置。在一實施例中，該半導體裝置包含半導體晶粒、半導體元件及焊料層。半導體晶粒包括銅柱、阻障層及金屬層。阻障層位於銅柱之末端上，且金屬層位於阻障層上。半導體元件包括電性接點及位於該電性接點上之表面處理層。表面處理層之材料為鎳、金及鈀中之兩者或兩者以上之組合。焊料層位於半導體晶粒之金屬層與半導體元件之表面處理層之間。焊料層包括第一金屬間化合物及第二金屬間化合物。第一金屬間化合物包括銅、鎳及錫中之兩者或兩者以上之組合。第二金屬間化合物包括金與錫之組合、鈀與錫之組合或兩者。
本發明之另一態樣係關於用於製造半導體裝置之方法。在一實施例中，該方法包含：(a)提供包含銅柱之半導體晶粒；(b)形成焊料層鄰近於銅柱之末端；(c)將該半導體晶粒置放於半導體元件上，使得焊料層接觸該半導體元件之電性接點上的表面處理層，其中表面處理層之材料為鎳、金及鈀中之兩者或兩者以上之組合；及(d)進行回焊製程以在焊料層中形成第一金屬間化合物及第二金屬間化合物，其中 第一金屬間化合物包含銅、鎳及錫之組合，且第二金屬間化合物包括金與錫之組合、鈀與錫之組合或兩者。
1‧‧‧半導體封裝
10‧‧‧基板
20‧‧‧上部電路層
30‧‧‧下部電路層
32‧‧‧上部保護層
34‧‧‧下部保護層
36‧‧‧外部焊球
38‧‧‧半導體元件
39‧‧‧表面處理層
40‧‧‧第一底膠
42‧‧‧半導體晶體
44‧‧‧焊料層
45‧‧‧主焊料部分
46‧‧‧第二底膠
47‧‧‧第一金屬間化合物
48‧‧‧封膠體
49‧‧‧第二金屬間化合物
50‧‧‧頂部層
52‧‧‧底部層
54‧‧‧外圍保護層
101‧‧‧上部表面
102‧‧‧下部表面
321‧‧‧開口
341‧‧‧開口
381‧‧‧上部表面
382‧‧‧下部表面
383‧‧‧上部電路層
384‧‧‧下部電路層
385‧‧‧導電通道
387‧‧‧下部保護層
388‧‧‧焊球
421‧‧‧主動面
422‧‧‧金屬電路層
423‧‧‧晶種層
424‧‧‧銅柱
425‧‧‧保護層
426‧‧‧阻障層
427‧‧‧銅金屬層
3831‧‧‧焊墊
4251‧‧‧開口
圖1說明根據本發明之一實施例之半導體封裝的橫截面圖。
圖2說明圖1之半導體封裝中之半導體晶粒與半導體元件之間的半導體覆晶結合之區域的放大圖。
圖3說明根據本發明之另一實施例之半導體覆晶結合的橫截面圖。
圖4說明根據本發明之另一實施例之半導體覆晶結合的橫截面圖。
圖5、圖6及圖7說明根據本發明之一實施例之用於製造半導體裝置的方法。
圖8說明根據本發明之另一實施例之用於製造半導體裝置的方法。
參看圖1，說明根據本發明之一實施例之半導體封裝的橫截面圖。半導體封裝1包含基板10、複數個外部焊球36、半導體晶粒42、半導體元件38、第一底膠(Underfill)40、複數個焊料層44、第二底膠46及封膠體(Molding Compound)48。
基板10可為(例如)矽基板、晶圓或玻璃基板。基板10包括上部表面101、下部表面102、上部電路層20、下部電路層30、上部保護層32及下部保護層34。上部電路層20位於基板10之上部表面101上，且下部電路層30位於基板10之下部表面102上。上部保護層32覆蓋基板10之上部電路層20及上部表面101，且界定複數個開口321以曝露上部電路層20之一部分。下部保護層34覆蓋基板10之下部電路層30及下部表面102，且界定複數個開口341以曝露下部電路層30之一部分。在一實 施例中，上部電路層20及下部電路層30之材料為銅，且上部保護層32及下部保護層34為焊料遮罩(Solder Mask)，且其材料為(例如)聚醯亞胺(PI)。外部焊球36位於曝露之下部電路層30上以用於外部連接。
半導體元件38可為(例如)矽基板、晶圓或玻璃基板。在一實施例中，半導體元件為中介層(Interposer)。半導體元件包括上部表面381、下部表面382、上部電路層383、下部電路層384、複數個導電通道(Conductive Via)385、下部保護層387及複數個焊球388。上部電路層383及下部電路層384分別位於半導體元件38之上部表面381及下部表面382上。導電通道385貫穿半導體元件38，且接觸且電連接上部電路層383及下部電路層384。下部保護層387覆蓋半導體元件38之下部電路層384及下部表面382，且界定複數個開口以曝露下部電路層384之一部分。焊球388接觸且電連接半導體元件38之下部電路層384的曝露部分及基板10之上部電路層20的曝露部分。第一底膠40位於半導體元件38與基板10之間以用於保護焊球388。在一實施例中，下部保護層387為焊料遮罩，且其材料為(例如)聚醯亞胺(PI)。
半導體晶粒42藉助於半導體晶粒42上之複數個銅柱424附接於半導體元件38。每一焊料層44位於該等銅柱424之一者與上部電路層383之曝露部分之間，以便將銅柱424結合至上部電路層383。第二底膠46位於半導體晶粒42與半導體元件38之間以用於保護銅柱424及焊料層44。在一些實施例中，除了銅之外，銅柱424包含不同金屬、金屬合金或其他導電材料，且所形成之金屬間化合物的組成將因此不同。
封膠體48位於基板10之上部表面101上以包覆半導體元件38、第一底膠40、半導體晶粒42及第二底膠46。在一些實施例中，可省去第一底膠40及第二底膠46中之一者或兩者。
在圖1之實施例中，半導體覆晶結合裝置包含具有銅柱424之半導體晶粒42、半導體元件38及焊料層44。
參看圖2，說明圖1之半導體覆晶結合裝置之區域A的放大圖。如圖2中之區域A的放大圖所說明，半導體晶粒42包括主動面421，金屬電路層422、晶種層423、銅柱424及保護層425。金屬電路層422位於主動面421上。在一些實施例中，金屬電路層422包括彼此絕緣之複數個區段，且該等區段之材料為(例如)鋁(Al)、銅(Cu)或鋁銅合金(例如，AlCu)。保護層425覆蓋主動面421及金屬電路層422，且界定複數個開口4251以曝露金屬電路層422之部分。在一實施例中，保護層425為包含金屬氧化物之鈍化層。銅柱424鄰設於金屬電路層422，且電連接至金屬電路層422。在圖1及圖2中所說明之實施例中，晶種層423位於開口4251中之金屬電路層422上，且銅柱424位於晶種層423上。亦即，晶種層423之一部分位於每一銅柱424與金屬電路層422之間。然而，可省去晶種層423，且銅柱424可直接位於金屬電路層422上。在一實施例中，晶種層423之材料為鈦合金(例如，TiCu)。
半導體元件38包括用於電連接至半導體晶粒42之電性接點。在所說明之實施例中，上部電路層383之一部分形成焊墊3831，焊墊3831為上文所提及之電性接點。在此實施例中，半導體元件38包括位於焊墊3831上之表面處理層(Surface Finish Layer)39，其中表面處理層39形成於諸如鎳(Ni)、鈀(Pd)及金(Au)或其合金(例如，Ni/Au、Ni/Pd或Ni/Pd/Au)之層的一或多個層中，且焊墊3831之材料為銅(Cu)。舉例而言，表面處理層39之鎳層充當阻障層，其可阻擋自焊墊3831至焊料層44的一些銅擴散，以避免因消耗整個焊墊3831而導致的上部電路層383破裂。另外，位於鎳層上的表面處理層39之金(Au)、鈀(Pd)或鈀金(Pd/Au)層可用於增加焊料層44之可濕潤性(Wettability)，以避免因鎳層之較差可濕性而導致焊料結合不充分。
焊料層44位於銅柱424與表面處理層39之間，且當經製造時，包含主焊料部分45、第一金屬間化合物47及第二金屬間化合物49。在此 實施例中，焊料層44直接接觸銅柱424。主焊料部分45之材料為錫(Sn)或錫銀合金(SnAg)。第一金屬間化合物47及第二金屬間化合物49為在主焊料部分45與銅柱424之間及在主焊料部分45與具有處理層39的焊墊3831之間的金屬相互作用之產物。第一金屬間化合物47為銅(Cu)、鎳(Ni)及錫(Sn)之組合，且第二金屬間化合物49為金(Au)及錫(Sn)之組合(諸如，AuSn4)，鈀(Pd)及錫(Sn)之組合(諸如，PdSn4)或金(Au)及錫(Sn)之組合及鈀(Pd)及錫(Sn)之組合兩者。在一實施例中，第一金屬間化合物47包括(Cu,Ni,Au,Pd)6Sn5(亦即，Cu6Sn5、Ni6Sn5、Au6Sn5或Pd6Sn5中之一或多者)及其他金屬間化合物，且第二金屬間化合物49包括(Au,Pd,Ni)Sn4(亦即，AuSn4、PdSn4或NiSn4中之一或多者)及其他IMC。
第一金屬間化合物47包括由與主焊料部分45進行金屬反應(Metal Reaction)所形成之頂部層50及底部層52。在一實施例中，頂部層50及底部層52為同一材料。由主焊料部分45與銅柱424之相互作用在銅柱424之末端處形成頂部層50，且由焊料層44與表面處理層39之相互作用鄰近於電性接點(亦即，焊墊3831)形成底部層52。在一些實施例中，阻障層可位於(例如，塗佈於)銅柱424及表面處理層39中之一者或兩者上；然而，在圖2中所說明之實施例中，可省去此阻障層。
第二金屬間化合物49亦由金屬反應所形成，且在主焊料部分45中不連續地形成，如圖2中之說明所示。
如所描述，在圖2之實施例中，諸如Ni層之阻障層並不位於銅柱424之末端上。因此，在回焊製程期間，銅柱424中之銅(Cu)及表面處理層39中之鎳(Ni)將快速進入焊料層44，以形成第一金屬間化合物47之頂部層50及底部層52。具體言之，來自銅柱424之一些銅穿過焊料層44且與表面處理層39中之鎳相互作用(反應)以形成底部層52，且來自表面處理層39之一些鎳穿過焊料層44且與銅柱424中之銅相互作用 以形成頂部層50。在一實施例中，金屬相互作用導致第一金屬間化合物47之頂部層50及底部層52包括同一材料。舉例而言，頂部層50及底部層52可皆包括相同的一或多種化合物，該等化合物可為(Cu,Ni,Au,Pd)6Sn5中之一或多者。以類似方式，來自銅柱424及表面處理層39之金屬穿過焊料層44以形成非連續第二金屬間化合物49。
第一金屬間化合物47及第二金屬間化合物49之組合之體積相對於焊料層44之體積的體積比被控制為小於80%，藉此避免接合破裂且增加半導體覆晶結合裝置之機械可靠性(Mechanical Reliability)。在一些實施例中，第一金屬間化合物47相對於焊料層44之體積比大於第二金屬間化合物49相對於焊料層44之體積比。然而，在其他實施例中，歸因於製程公差(Process Tolerance)，表面處理層39之一或多層(例如，金(Au)、鈀(Pd)或鈀金(Pd/Au)層中之一或多者)的厚度可使得第一金屬間化合物47相對於焊料層44之體積比小於第二金屬間化合物49相對於焊料層44之體積比。
可在加工期間藉由控制銅柱424、表面處理層39及焊料層44之厚度來控制第一金屬間化合物47之厚度。此上下文中之「厚度」係指圖2中所展示之定向中的垂直尺寸。因此，給定圖2中之厚度T1、T2及T3(分別為銅柱424、焊料層44及表面處理層39之厚度)，第一金屬間化合物47之頂部層50將形成為T5之厚度，且第一金屬間化合物47之底部層52將形成為T6之厚度。舉例而言，銅柱424之厚度T1為約5微米(μm)至約20μm；焊料層44之厚度T2為約5μm至約30μm；且表面處理層39之厚度T3為約1μm至約15μm；使得頂部層50之所得厚度T5為約2μm至約3μm，且底部層52之所得厚度T6不大於或小於T5，且為約1μm至約2μm。
因此，第一金屬間化合物47之頂部層50及底部層52的組合的厚度為約3μm至約5μm，且可因此控制第一金屬間化合物47，使得其不完 全替換焊料層44。此外，藉由控制T1、T2及T3之厚度，可控制第二金屬間化合物49的厚度，且該厚度可經控制以使得第一金屬間化合物47及第二金屬間化合物49之組合的厚度小於焊料層44之厚度(亦即，不完全替換焊料層44)。在一個實施例中，焊墊3831之厚度T4為約1μm至約10μm；然而，藉由利用表面處理層39阻擋焊墊3831中之銅的遷移，在此實施例中，焊墊3831之厚度並不顯著影響第一金屬間化合物47或第二金屬間化合物49之厚度。
控制金屬間結合(Metallic Bonding)以形成第一金屬間化合物47及第二金屬間化合物49之額外益處為避免焊料層44中之空隙；因此，半導體覆晶結合裝置之壽命增加。
參看圖3，說明根據本發明之另一實施例之半導體覆晶結合裝置的橫截面圖。此實施例之半導體覆晶結合裝置類似於圖2之半導體覆晶結合裝置，且差異為銅柱424具有位於銅柱424之側壁上以包圍銅柱424的外圍保護層54。外圍保護層54之材料為諸如氧化銅之金屬氧化物，其被如下形成：首先，將遮罩層用於覆蓋銅柱424之末端的底部表面。接著，將具有遮罩層之銅柱424置放至氧化氣體中，使得外圍保護層54形成於銅柱424之側壁上。在移除遮罩層之後，將焊料層44形成於銅柱424之末端處。
參看圖4，說明根據本發明之另一實施例之半導體覆晶結合裝置的橫截面圖。此實施例之半導體覆晶結合裝置類似於圖2之半導體覆晶結合裝置，且差異為半導體晶粒42進一步包括阻障層426及金屬層427。阻障層426位於銅柱424之末端上，且金屬層427位於(例如，塗佈於)阻障層426上。在一實施例中，阻障層426之材料為鎳(Ni)，且金屬層427之材料與銅柱424之材料相同，即，皆為銅(Cu)。因此，第一金屬間化合物47之頂部層50直接形成於金屬層427上。在一實施例中，第一金屬間化合物47之頂部層50及底部層52的材料為 (Cu,Ni,Au,Pd)6Sn5中之一或多者，且頂部層50及底部層52可為同一合金。另外，此實施例之銅柱424可包括類似於圖3中所說明之外圍保護層54的外圍保護層。在一實施例中，為了控制第一金屬間化合物47及第二金屬間化合物49之厚度，阻障層426之厚度T7為約1μm至約5μm，且金屬層427之厚度T8為約2μm至約8μm。
參看圖5、圖6及圖7，說明根據本發明之一實施例之用於製造半導體裝置的方法。此實施例用於製造半導體覆晶結合裝置，諸如圖2中所展示之半導體覆晶結合裝置。
參看圖5，提供半導體晶粒42。在此實施例中，半導體晶粒42包括主動面421、金屬電路層422、晶種層423、銅柱424及保護層425。金屬電路層422位於主動面421上。在此實施例中，金屬電路層422包括彼此絕緣之複數個區段，且該等區段之材料為鋁(Al)、銅(Cu)或鋁銅(AlCu)。保護層425覆蓋主動面421及金屬電路層422，且界定複數個開口4251以曝露金屬電路層422之一部分。在一實施例中，保護層425為金屬氧化物之鈍化層。銅柱424鄰設於金屬電路層422，且電連接至金屬電路層422。在此實施例中，晶種層423位於每一開口4251中的金屬電路層422上，且每一銅柱424位於晶種層423上。亦即，晶種層423位於每一銅柱424與金屬電路層422之間。然而，可省去晶種層423，且每一銅柱424可直接位於金屬電路層422上。在一實施例中，晶種層423之材料為鈦銅(TiCu)。
參看圖6，形成焊料層44鄰近於銅柱424之末端。在此實施例中，焊料層44形成於銅柱424之末端處。亦即，不存在位於銅柱424之末端上的阻障層(諸如，鎳層)，使得焊料層44直接接觸銅柱424之末端。焊料層44之材料為錫(Sn)或錫銀(SnAg)。焊料層44之外周邊表面與銅柱424之外周邊表面共面，因此，焊料層44之半徑與銅柱424之半徑實質上相同。
接著，提供半導體元件38。在一實施例中，半導體元件38為中介層，且包括用於電連接至半導體晶粒42之一或多個電性接點。半導體元件38之上部電路層383之一部分形成焊墊3831。在此實施例中，半導體元件38進一步包括位於焊墊3831上之表面處理層39。在一實施例中，表面處理層39之材料為Ni/Au、Ni/Pd或Ni/Pd/Au之組合，且焊墊3831之材料為銅。
在圖6中所說明之實施例中，銅柱424之厚度T1為約5μm至約20μm，焊料層44之厚度T2為約5μm至約30μm，表面處理層39之厚度T3為約1μm至約15μm，且焊墊3831之厚度T4為約1μm至約10μm。
參看圖7，半導體晶粒42置放於半導體元件38上，使得銅柱424上之焊料層44接觸半導體元件38之電性接點(例如，焊墊3831)上的表面處理層39。接著，執行回焊以將銅柱424與焊料層44結合且將焊料層44與表面處理層39結合。此回焊製程在焊料層44中形成第一金屬間化合物47及第二金屬間化合物49，在該等金屬間化合物47,49之間留下主焊料部分45。在一實施例中，主焊料部分45之材料為錫(Sn)或錫銀(SnAg)，第一金屬間化合物47由銅(Cu)、鎳(Ni)及錫(Sn)的組合製成且包括Cu6Sn5，且第二金屬間化合物49為基於AuSn4的(AuSn4 Based)、基於PdSn4的(PdSn4 Based)或其組合。
在圖5至圖7描述之實施例中，諸如Ni層之阻障層不塗佈於銅柱424之末端上；因此，在回焊製程期間，銅柱424中之銅及表面處理層39中之鎳將快速進入焊料層44，以便形成第一金屬間化合物47之頂部層50及底部層52。在一實施例中，頂部層50及底部層52中之每一者之材料包括(Cu,Ni,Au,Pd)6Sn5中之一或多者，且頂部層50及底部層52可為同一材料。根據Gibb能量方程式，若形成能量不同，則將首先形成具有較低之形成能量及較高穩定性的金屬間化合物。因為(Cu,Ni,Au,Pd)6Sn5之形成能量低於(Au,Pd,Ni)Sn4之形成能量，且因為 (Cu,Ni,Au,Pd)6Sn5比(Au,Pd,Ni)Sn4更穩定，所以將首先形成第一金屬間化合物47的頂部層50及底部層52(皆呈(Cu,Ni,Au,Pd)6Sn5形式)。
在一些實施例中，第一金屬間化合物47(包括頂部層50及底部層52)之Cu6Sn5相對於焊料層44之最大體積比為約15%。此外，若焊料層44中之銅的濃度大於1重量百分比(1wt%)，則將抑制AuSn4及/或PdSn4之形成。在諸如關於圖5至圖7描述之實施例中，在阻障層不塗佈於銅柱424之末端上的情況下，來自銅柱424之Cu可抑制第二金屬間化合物49之形成。舉例而言，在回焊製程期間，銅柱424中之銅自由進入焊料層44，焊料層44中之銅首先形成Cu6Sn5，且因此，焊料層44中剩餘之相對大量(例如，大於1wt%)的銅抑制AuSn4及/或PdSn4之形成。因此，在一些實施例中，第一金屬間化合物47相對於焊料層44之體積比將大於第二金屬間化合物49相對於焊料層44之體積比。然而，在其他實施例中，歸因於製程容限，表面處理層39之金(Au)、鈀(Pd)或鈀金(Pd/Au)層的厚度可使得其抵消焊料層44中剩餘之銅的作用，且因此AuSn4及/或PdSn4之形成得不到抑制。在此情況下，第一金屬間化合物47相對於焊料層44之體積比可小於第二金屬間化合物49相對於焊料層44之體積比。然而，第一金屬間化合物47與第二金屬間化合物49之組合相對於焊料層44的體積比可被控制為小於80%，以避免接合破裂且增加半導體覆晶結合裝置之機械可靠性。
參看圖8，說明根據本發明之另一實施例之用於製造半導體裝置的方法。此實施例用於製造半導體覆晶結合裝置，諸如圖4中所展示之半導體覆晶結合裝置。此實施例之方法類似於圖5至圖7之方法，且差異為半導體晶粒42進一步包括阻障層426及金屬層427。在一實施例中，阻障層426之材料為Ni，且阻障層426位於銅柱424之末端上。金屬層427之材料與銅柱424之材料相同，即，皆為銅。金屬層427位於阻障層426上。阻障層426之厚度T7為約1μm至約5μm，且金屬層427 之厚度T8為約2μm至約8μm。焊料層44位於金屬層427上。在此實施例中，焊料層44之外周邊表面與銅柱424及金屬層427之外周邊表面共面，因此，焊料層44之半徑與銅柱424及金屬層427之半徑實質上相同。
在此實施例中，金屬層427之厚度T8與焊料層44之厚度T2之間的關係式為約T8 0.09 T2，其被如下導出。在此實施例中，阻障層426塗佈於銅柱424之末端上，因此，在回焊製程期間，銅柱424中之銅將不進入焊料層44。亦即，焊料層44中之銅僅或主要來自銅金屬層427。
銅金屬層427之厚度T8可視為第一部分與第二部分之組合。銅金屬層427之第一部分的厚度用於控制Cu6Sn5之形成，且銅金屬層427之第二部分的厚度用於抑制AuSn4及/或PdSn4之形成。為方便起見，銅金屬層427之第一部分的厚度在本文中被稱作T81，且銅金屬層427之第二部分的厚度在本文中被稱作T82。
T81係由以下方式所決定。如上文所陳述，在一些實施例中，Cu6Sn5相對於焊料層44之最大體積比為約15%。因此，V1=(0.15)V2，其中V1表示Cu6Sn5之體積，且V2表示焊料層44之體積。因為 Cu6Sn5中之銅(Cu)的體積比為，所以銅(Cu)之體積為 (0.15)V2。在幾何關係中，銅(Cu)之體積為πr2×T81，且焊料層44之體積為V2=πr2×T2，其中r表示焊料層44之半徑(其與銅金屬層427之半徑相同)。如在方程式(1)中，使銅(Cu)之體積的兩個描述相等，且藉由求解方程式(1)，如在方程式(2)中決定厚度T81。
銅金屬層427之第二部分的厚度T82係由以下方式所決定。如上文 所陳述，在一些實施例中，若焊料層44中之銅(Cu)的濃度大於1wt%，則將抑制AuSn4及/或PdSn4之形成。因此，在一些實施例中， 當(亦即，當99 W1W2時)時，抑制發生，其中W1表示 銅(Cu)之重量，且W2表示SnAg之重量。銅(Cu)之重量為W1=πr2×T82×8.96，且焊料層44之重量為W2=πr2×T2×7.31，其中r表示焊料層44之半徑(其與銅金屬層427之半徑相同)，8.96為銅(Cu)之密度，且7.31為SnAg之密度。方程式(3)始於關係式99 W1W2，且在該關係式中代入W1及W2，且在方程式(4)中求解厚度T82。
厚度T8為厚度T81及T82之總和，因此，根據方程式(2)及(4)，T8=T81+T82 0.0818 T2+0.00824 T2 0.09004 T2。亦即，銅金屬層427之厚度T8與焊料層44之厚度T2之間的關係式為約T8 0.09 T2。
仍參看圖8，半導體晶粒42置放於半導體元件38上，使得焊料層44接觸半導體元件38之電性接點(例如，焊墊3831)上的表面處理層39。接著，執行回焊以在焊料層44中形成第一金屬間化合物47及第二金屬間化合物49連同剩餘主焊料部分45，以獲得如圖4中所展示之半導體覆晶結合裝置。在此實施例中，銅金屬層427之厚度T8與焊料層44之厚度T2之間的關係式滿足上文所提及之方程式T8 0.09 T2，因此，第一金屬間化合物47及第二金屬間化合物49相對於焊料層44之體積比小於80%，藉此避免接合破裂且增加半導體覆晶結合裝置之機械可靠性。
如本文中所使用，術語「實質上」及「約」用於描述及解釋較小變化。當與事件或情形相結合使用時，該等術語可指事件或情形精確發生之情況，及事件或情形極近似地發生之情況。舉例而言，該等術 語可指小於或等於±10%，諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%。因此，將一個半徑描述為與另一半徑「實質上相同」指示：一個半徑小於或等於另一半徑之±10%，諸如小於或等於±5%，小於或等於±4%，小於或等於±3%，小於或等於±2%，小於或等於±1%，小於或等於±0.5%，小於或等於±0.1%或小於或等於±0.05%。
另外，有時在本文中按範圍格式呈現量、比率及其他數值。應理解，此類範圍格式係為便利及簡潔起見而使用，且應靈活地理解為不僅包括明確指定為範圍的極限之數值，且亦包括涵蓋於彼範圍內之所有個別數值或子範圍，就如同明確指定每一數值及子範圍一般。
雖然已參考本發明之特定實施例描述並說明本發明，但此等描述及說明並不限制本發明。熟習此項技術者應理解，在不脫離如由所附申請專利範圍界定的本發明之真實精神及範疇的情況下，可作出各種改變且可取代等效物。說明可能未必按比例繪製。歸因於製造製程及容限，本發明中之藝術再現與實際設備之間可存在區別。可存在並未具體說明的本發明之其他實施例。應將本說明書及圖式視為說明性而非限制性的。可作出修改，以使特定情形、材料、物質組成、方法或程序適應於本發明之目標、精神及範疇。所有此等修改意欲在隨附之申請專利範圍之範疇內。雖然已參考按特定次序執行之特定操作描述本文中所揭示的方法，但應理解，在不脫離本發明之教示的情況下，可組合、再分，或重新定序此等操作以形成等效方法。相應地，除非本文中具體指示，否則操作的次序及分組並非本發明之限制。
1‧‧‧半導體封裝
10‧‧‧基板
20‧‧‧上部電路層
30‧‧‧下部電路層
32‧‧‧上部保護層
34‧‧‧下部保護層
36‧‧‧外部焊球
38‧‧‧半導體元件
40‧‧‧第一底膠
42‧‧‧半導體晶體
44‧‧‧焊料層
46‧‧‧第二底膠
48‧‧‧封膠體
101‧‧‧上部表面
102‧‧‧下部表面
321‧‧‧開口
341‧‧‧開口
381‧‧‧上部表面
382‧‧‧下部表面
383‧‧‧上部電路層
384‧‧‧下部電路層
385‧‧‧導電通道
387‧‧‧下部保護層
388‧‧‧焊球
424‧‧‧銅柱

Claims (12)

  1. 一種半導體裝置，其包含：一半導體晶粒，其包含一銅柱；一半導體元件，其包含一電性接點及位於該電性接點上之一表面處理層，其中該表面處理層之材料為鎳、金及鈀中之至少兩者之一組合；及一焊料層，其位於該銅柱與該表面處理層之間，該焊料層包含第一金屬間化合物及第二金屬間化合物，其中該第一金屬間化合物包含銅、鎳及錫中之兩者或兩者以上之一組合，且該第二金屬間化合物包括金與錫之一組合、鈀與錫之一組合或兩者。
  2. 如請求項1之半導體裝置，其中該第一金屬間化合物包含一頂部層及一底部層，該頂部層及該底部層之材料相同，該頂部層接觸該銅柱，且該底部層接觸該表面處理層。
  3. 如請求項1之半導體裝置，其中該半導體元件為一晶粒或一中介層，且該電性接點為一銅焊墊。
  4. 如請求項1之半導體裝置，其中該第一金屬間化合物與該第二金屬間化合物之組合相對於該焊料層之體積比小於80%。
  5. 如請求項1之半導體裝置，其中該第一金屬間化合物包括Cu6Sn5，且該第一金屬間化合物之該Cu6Sn5相對於該焊料層之體積比為約15%。
  6. 如請求項1之半導體裝置，其中該焊料層之厚度為約5μm至約30μm。
  7. 如請求項1之半導體裝置，其中該第一金屬間化合物相對於該焊料層之體積比大於該第二金屬間化合物相對於該焊料層之體積 比。
  8. 一種半導體裝置，其包含：一半導體晶粒，其包含一電路層、一保護層及一晶種層，該保護層曝露該電路層之一部分，該晶種層位於該電路層上被該保護層曝露之該部分；一銅柱，其位於該晶種層上；一半導體元件，其包含一焊墊及位於該焊墊上之表面處理層；一焊料層，其位於該銅柱及該表面處理層之間；一第一金屬間化合物，其介於該焊料層與該銅柱之間；及一第二金屬間化合物，其介於該焊料層及該表面處理層之間，該第一金屬間化合物之體積相加該第二金屬間化合物之體積係小於該焊料層之體積的80%。
  9. 如請求項8之半導體裝置，其中該第一金屬間化合物包含銅、鎳及錫中之兩者或兩者以上之一組合，且該第二金屬間化合物包括金與錫之一組合、鈀與錫之一組合或兩者。
  10. 如請求項8之半導體裝置，進一步包含一基板，其中該半導體晶粒係經由該半導體元件與該基板電連接。
  11. 如請求項10之半導體裝置，進一步包含一封膠體，其包覆該半導體晶粒、該半導體元件及該基板之一表面之一部分。
  12. 如請求項8之半導體裝置，其中該第一金屬間化合物相對於該焊料層之體積比大於該第二金屬間化合物相對於該焊料層之體積比。
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