US20160260677A1 - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
- Publication number
- US20160260677A1 US20160260677A1 US14/639,535 US201514639535A US2016260677A1 US 20160260677 A1 US20160260677 A1 US 20160260677A1 US 201514639535 A US201514639535 A US 201514639535A US 2016260677 A1 US2016260677 A1 US 2016260677A1
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- Prior art keywords
- layer
- imc
- solder
- semiconductor device
- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 136
- 238000000034 method Methods 0.000 title abstract description 28
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 239000010949 copper Substances 0.000 claims abstract description 141
- 229910000679 solder Inorganic materials 0.000 claims abstract description 127
- 229910052802 copper Inorganic materials 0.000 claims abstract description 111
- 229910000765 intermetallic Inorganic materials 0.000 claims abstract description 107
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 101
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 65
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 52
- 239000011135 tin Substances 0.000 claims abstract description 46
- 239000010931 gold Substances 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 38
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 34
- 229910052737 gold Inorganic materials 0.000 claims abstract description 31
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 31
- 229910052718 tin Inorganic materials 0.000 claims abstract description 28
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 22
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 58
- 239000002184 metal Substances 0.000 claims description 58
- 230000004888 barrier function Effects 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 20
- 229910018471 Cu6Sn5 Inorganic materials 0.000 claims description 13
- 150000001875 compounds Chemical class 0.000 claims description 3
- 238000000465 moulding Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 10
- 229910007637 SnAg Inorganic materials 0.000 description 6
- 230000003993 interaction Effects 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- YJLIKUSWRSEPSM-WGQQHEPDSA-N (2r,3r,4s,5r)-2-[6-amino-8-[(4-phenylphenyl)methylamino]purin-9-yl]-5-(hydroxymethyl)oxolane-3,4-diol Chemical compound C=1C=C(C=2C=CC=CC=2)C=CC=1CNC1=NC=2C(N)=NC=NC=2N1[C@@H]1O[C@H](CO)[C@@H](O)[C@H]1O YJLIKUSWRSEPSM-WGQQHEPDSA-N 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 2
- -1 Cu6Sn5 Chemical compound 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910010165 TiCu Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910003306 Ni3Sn4 Inorganic materials 0.000 description 1
- 229910005907 NiSn4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical group [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
- B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
- B23K1/0016—Brazing of electronic components
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
- B23K35/262—Sn as the principal constituent
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
- B23K35/302—Cu as the principal constituent
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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- H01L2225/06503—Stacked arrangements of devices
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- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/30—Technical effects
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- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
Definitions
- the method comprises (a) providing a semiconductor die comprising a copper pillar; (b) forming a solder layer adjacent to a tip of the copper pillar; (c) placing the semiconductor die on a semiconductor element such that the solder layer contacts a surface finish layer on an electrical contact of the semiconductor element, wherein the material of the surface finish layer is a combination of two or more of nickel, gold and palladium; and (d) performing a reflow process to form a first IMC and a second IMC in the solder layer, wherein the first IMC comprises a combination of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.
- FIG. 8 illustrates a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.
- the semiconductor package 1 comprises a substrate 10 , a plurality of external solder balls 36 , a semiconductor die 42 , a semiconductor element 38 , a first underfill 40 , a plurality of solder layers 44 , a second underfill 46 and a molding compound 48 .
- the lower protection layer 387 covers the lower circuit layer 384 and the lower surface 382 of the semiconductor element 38 , and defines a plurality of openings to expose a portion of the lower circuit layer 384 .
- the solder balls 388 contact and electrically connect exposed portions of the lower circuit layer 384 of the semiconductor element 38 and exposed portions of the upper circuit layer 20 of the substrate 10 .
- the first underfill 40 is disposed between the semiconductor element 38 and the substrate 10 for protecting the solder balls 388 .
- the lower protection layer 387 is a solder mask, and the material thereof is, for example, polyimide (PI).
- the molding compound 48 is disposed on the upper surface 101 of the substrate 10 to encapsulate the semiconductor element 38 , the first underfill 40 , the semiconductor die 42 and the second underfill 46 . In some embodiments, one or both of the first underfill 40 and the second underfill 46 may be omitted.
- the solder layer 44 is disposed between the copper pillar 424 and the surface finish layer 39 , and, as manufactured, comprises a main solder portion 45 , a first IMC 47 and a second IMC 49 .
- the solder layer 44 contacts the copper pillar 424 directly.
- the material of the main solder portion 45 is Sn or SnAg.
- the first IMC 47 and the second IMC 49 are a result of the metal interaction between the main solder portion 45 and the copper pillar 424 , and between the main solder portion 45 and the pad 3831 with the finish layer 39 .
- the second IMC 49 is also formed by metal interaction, and is formed discontinuously in the main solder portion 45 , as indicated by the illustration in FIG. 2 .
- a combined thickness of the top layer 50 and the bottom layer 52 of the first IMC 47 is about 3 ⁇ m to about 5 ⁇ m, and the first IMC 47 can therefore be controlled such that it does not replace the solder layer 44 completely.
- a thickness of the second IMC 49 may be controlled, and may be controlled such that the combined thickness of the first IMC 47 and the second IMC 49 is less than the thickness of the solder layer 44 (i.e., the solder layer 44 is not completely replaced).
- An additional benefit of controlling the intermetallic bonding to form the first IMC 47 and the second IMC 49 is that voids in the solder layer 44 are avoided; thus, the lifetime of the semiconductor flip-chip bonded device is increased.
- FIG. 4 a cross-sectional view of a semiconductor flip-chip bonded device according to another embodiment of the present disclosure is illustrated.
- the semiconductor flip-chip bonded device of this embodiment is similar to the semiconductor flip-chip bonded device of FIG. 2 , and the difference is that the semiconductor die 42 further includes a barrier layer 426 and a metal layer 427 .
- the barrier layer 426 is disposed on a tip of the copper pillar 424
- the metal layer 427 is disposed (for example, coated) on the barrier layer 426 .
- the material of the barrier layer 426 is Ni
- the material of the metal layer 427 is the same as that of copper pillar 424 , namely, both are Cu.
- a solder layer 44 is formed adjacent to a tip of the copper pillar 424 .
- the solder layer 44 is formed at the tip of the copper pillar 424 . That is, there is no barrier layer, such as Ni layer, disposed on the tip of the copper pillar 424 , so that the solder layer 44 contacts the tip of the copper pillar 424 directly.
- the material of the solder layer 44 is Sn or SnAg.
- the outer peripheral surface of the solder layer 44 is coplanar with the outer peripheral surface of the copper pillar 424 , thus, the radius of the solder layer 44 is substantially the same as that of the copper pillar 424 .
- a thickness T 1 of the copper pillar 424 is about 5 ⁇ m to about 20 ⁇ m
- the thickness T 2 of the solder layer 44 is about 5 ⁇ m to about 30 ⁇ m
- the thickness T 3 of the surface finish layer 39 is about 1 ⁇ m to about 15 ⁇ m
- the thickness T 4 of the pad 3831 is about 1 ⁇ m to about 10 ⁇ m.
- the maximum volume ratio of the Cu 6 Sn 5 of the first IMC 47 (including the top layer 50 and the bottom layer 52 ) to the solder layer 44 is about 15%. Further, if the concentration of Cu in the solder layer 44 is more than one percent by weight (1 wt %), the formation of AuSn 4 and/or PdSn 4 will be suppressed. In an embodiment such as described with respect to FIGS. 5 to 7 , where no barrier layer is coated on the tip of the copper pillar 424 , the Cu from the copper pillar 424 may suppress formation of the second IMC 49 .
- a thickness of an Au, Pd or Pd/Au layer of the surface finish layer 39 due to process tolerance may be such that it counterbalances the Cu remaining in the solder layer 44 , and thus formation of AuSn 4 and/or PdSn 4 is not suppressed.
- the volume ratio of the first IMC 47 to the solder layer 44 may be less than the volume ratio of the second IMC 49 to the solder layer 44 .
- the volume ratio of the combination of the first IMC 47 and the second IMC 49 to the solder layer 44 may be controlled to be less than 80%, to avoid joint crack and to increase mechanical reliability of the semiconductor flip-chip bonded device.
- FIG. 8 a method for manufacturing a semiconductor device according to another embodiment of the present disclosure is illustrated.
- This embodiment is used to manufacture a semiconductor flip-chip bonded device such as that shown in FIG. 4 .
- the method of this embodiment is similar to the method of FIGS. 5 to 7 , and the difference is that the semiconductor die 42 further includes a barrier layer 426 and a metal layer 427 .
- the material of the barrier layer 426 is Ni, and the barrier layer 426 is disposed on a tip of the copper pillar 424 .
- the material of the metal layer 427 is the same as that of copper pillar 424 , namely, both are Cu.
- the metal layer 427 is disposed on the barrier layer 426 .
- the relationship between the thickness T 8 of the metal layer 427 and the thickness T 2 of the solder layer 44 is about T 8 ⁇ 0.09 T 2 , which is derived as follows.
- the barrier layer 426 is coated on the tip of the copper pillar 424 , thus, during the reflow process, the Cu in the copper pillar 424 will not enter the solder layer 44 . That is, the Cu in the solder layer 44 only, or primarily, comes from the copper metal layer 427 .
- Equation (3) starts with the relationship 99 W1 ⁇ W2 and substitutes in the relationships for W1 and W2, and the thickness T 82 is solved for in equation (4).
- the semiconductor die 42 is placed on the semiconductor element 38 such that the solder layer 44 contacts the surface finish layer 39 on the electrical contact (e.g., the pad 3831 ) of the semiconductor element 38 . Then, reflow is performed to form the first IMC 47 and the second IMC 49 in the solder layer 44 , along with the remaining main solder portion 45 , such that the semiconductor flip-chip bonded device as shown in FIG. 4 is obtained.
- one radius described as “substantially the same” as another radius indicates that the one radius is less than or equal to ⁇ 10% of the other radius, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
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Abstract
Description
- 1. Technical Field
- The present disclosure relates to the field of semiconductor structure and semiconductor process, and more particularly, to semiconductor flip-chip bonded device and semiconductor process for manufacturing the same.
- 2. Description of the Related Art
- In a conventional semiconductor flip-chip bonding method, a barrier layer of nickel (Ni) material is coated to a copper pillar of an upper die, and a solder is formed on the Ni barrier layer. Then, the upper die is placed on a bottom die or a substrate, so that the solder on the copper pillar contacts the pad of the bottom die or the substrate. After a reflow process, the solder is melted to join to the pad so as to form a semiconductor flip-chip bonded device.
- During the reflow process, the solder may react with the pad of the bottom die or the substrate so as to form intermetallic compounds (IMC). Typically, the material of the solder is a tin silver alloy (e.g., SnAg), the material of the pad is copper (Cu), and the material of an IMC is thus a combination of tin, silver and copper, such as Cu6Sn5, Ni6Sn5, Cu3Sn4 or Ni3Sn4. IMCs can make the bonding between the solder and the pad tighter. However, if the pad is thin, the whole pad may react with the solder so that the pad cracks. In addition, a thicker IMC layer will reduce the shear strength of the semiconductor flip-chip bonded device because the IMCs are brittle. Moreover, if the solder is very thin (e.g., less than 30 μm), the volume ratio of the IMCs to the solder can exceed 80%, which can result in joint crack.
- Thus, a new semiconductor device and semiconductor process for controlling amounts of IMCs are desirable.
- An aspect of the present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor die, a semiconductor element and a solder layer. the semiconductor die includes a copper pillar. The semiconductor element includes a surface finish layer, wherein the material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC. The first IMC includes a combination of copper, nickel and tin. The second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.
- Another aspect of the present disclosure relates to a semiconductor device. In an embodiment, the semiconductor device comprises a semiconductor die, a semiconductor element and a solder layer. The semiconductor die includes a copper pillar, a barrier layer and a metal layer. The barrier layer is disposed on a tip of the copper pillar, and the metal layer is disposed on the barrier layer. The semiconductor element includes an electrical contact and a surface finish layer disposed on the electrical contact. The material of the surface finish layer is a combination of two or more of nickel, gold and palladium. The solder layer is disposed between the metal layer of the semiconductor die and the surface finish layer of the semiconductor element. The solder layer includes a first IMC and a second IMC. The first IMC includes a combination of two or more of copper, nickel and tin. The second IMC includes a combination of gold and tin, palladium and tin, or both.
- Another aspect of the present disclosure relates to a method for manufacturing a semiconductor device. In an embodiment, the method comprises (a) providing a semiconductor die comprising a copper pillar; (b) forming a solder layer adjacent to a tip of the copper pillar; (c) placing the semiconductor die on a semiconductor element such that the solder layer contacts a surface finish layer on an electrical contact of the semiconductor element, wherein the material of the surface finish layer is a combination of two or more of nickel, gold and palladium; and (d) performing a reflow process to form a first IMC and a second IMC in the solder layer, wherein the first IMC comprises a combination of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.
-
FIG. 1 illustrates a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. -
FIG. 2 illustrates an enlarged view of an area of a semiconductor flip-chip bond between a semiconductor die and a semiconductor element in the semiconductor package ofFIG. 1 . -
FIG. 3 illustrates a cross-sectional view of a semiconductor flip-chip bond according to another embodiment of the present disclosure. -
FIG. 4 illustrates a cross-sectional view of a semiconductor flip-chip bond according to another embodiment of the present disclosure. -
FIG. 5 ,FIG. 6 andFIG. 7 illustrate a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. -
FIG. 8 illustrates a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. - Referring to
FIG. 1 , a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure is illustrated. Thesemiconductor package 1 comprises asubstrate 10, a plurality ofexternal solder balls 36, asemiconductor die 42, asemiconductor element 38, afirst underfill 40, a plurality ofsolder layers 44, asecond underfill 46 and amolding compound 48. - The
substrate 10 may be, for example, a silicon substrate, a wafer, or a glass substrate. Thesubstrate 10 includes anupper surface 101, alower surface 102, anupper circuit layer 20, alower circuit layer 30, anupper protection layer 32 and alower protection layer 34. Theupper circuit layer 20 is disposed on theupper surface 101 of thesubstrate 10, and thelower circuit layer 30 is disposed on thelower surface 102 of thesubstrate 10. Theupper protection layer 32 covers theupper circuit layer 20 and theupper surface 101 of thesubstrate 10, and defines a plurality ofopenings 321 to expose a portion of theupper circuit layer 20. Thelower protection layer 34 covers thelower circuit layer 30 and thelower surface 102 of thesubstrate 10, and defines a plurality ofopenings 341 to expose a portion of thelower circuit layer 30. In an embodiment, the material of theupper circuit layer 20 and thelower circuit layer 30 is Cu, and theupper protection layer 32 and thelower protection layer 34 are solder masks, and the material thereof is, for example, polyimide (PI). Theexternal solder balls 36 are disposed on the exposedlower circuit layer 30 for external connection. - The
semiconductor element 38 may be, for example, a silicon substrate, a wafer or a glass substrate. In an embodiment, the semiconductor element is an interposer. The semiconductor element includes anupper surface 381, alower surface 382, anupper circuit layer 383, alower circuit layer 384, a plurality ofconductive vias 385, alower protection layer 387 and a plurality ofsolder balls 388. Theupper circuit layer 383 and thelower circuit layer 384 are disposed on theupper surface 381 and thelower surface 382 of thesemiconductor element 38, respectively. Theconductive vias 385 penetrate through thesemiconductor element 38, and contact and electrically connect theupper circuit layer 383 and thelower circuit layer 384. Thelower protection layer 387 covers thelower circuit layer 384 and thelower surface 382 of thesemiconductor element 38, and defines a plurality of openings to expose a portion of thelower circuit layer 384. Thesolder balls 388 contact and electrically connect exposed portions of thelower circuit layer 384 of thesemiconductor element 38 and exposed portions of theupper circuit layer 20 of thesubstrate 10. Thefirst underfill 40 is disposed between thesemiconductor element 38 and thesubstrate 10 for protecting thesolder balls 388. In an embodiment, thelower protection layer 387 is a solder mask, and the material thereof is, for example, polyimide (PI). - The semiconductor die 42 is attached to the
semiconductor element 38 by way of a plurality ofcopper pillars 424 on thesemiconductor die 42. Each of thesolder layers 44 is disposed between one of thecopper pillars 424 and an exposed portion of theupper circuit layer 383 so as to bond thecopper pillars 424 to theupper circuit layer 383. Thesecond underfill 46 is disposed between the semiconductor die 42 and thesemiconductor element 38 for protecting thecopper pillars 424 and the solder layers 44. In some embodiments, rather than being copper,copper pillars 424 comprise a different metal, a metal alloy, or other conductive material, and the composition of the IMCs formed would accordingly be different. - The
molding compound 48 is disposed on theupper surface 101 of thesubstrate 10 to encapsulate thesemiconductor element 38, thefirst underfill 40, the semiconductor die 42 and thesecond underfill 46. In some embodiments, one or both of thefirst underfill 40 and thesecond underfill 46 may be omitted. - In the embodiment of
FIG. 1 , a semiconductor flip-chip bonded device comprises the semiconductor die 42 withcopper pillars 424, thesemiconductor element 38, and the solder layers 44. - Referring to
FIG. 2 , an enlarged view of area A of the semiconductor flip-chip bonded device ofFIG. 1 is illustrated. As illustrated by the enlarged view of area A inFIG. 2 , the semiconductor die 42 includes anactive surface 421, ametal circuit layer 422, aseed layer 423, thecopper pillars 424, and aprotection layer 425. Themetal circuit layer 422 is disposed on theactive surface 421. In some embodiments, themetal circuit layer 422 includes a plurality of segments insulated from each other, and the material of the segments is, for example, aluminum (Al), Cu, or an alloy (e.g., AlCu). Theprotection layer 425 covers theactive surface 421 and themetal circuit layer 422, and defines a plurality ofopenings 4251 to expose portions of themetal circuit layer 422. In an embodiment, theprotection layer 425 is a passivation layer comprised of metal oxide. Thecopper pillars 424 are disposed adjacent to themetal circuit layer 422, and are electrically connected to themetal circuit layer 422. In the embodiment illustrated inFIGS. 1 and 2 , theseed layer 423 is disposed on themetal circuit layer 422 in theopenings 4251, and thecopper pillars 424 are disposed on theseed layer 423. That is, a portion of theseed layer 423 is disposed between each of thecopper pillars 424 and themetal circuit layer 422. However, theseed layer 423 may be omitted, and thecopper pillars 424 may be disposed on themetal circuit layer 422 directly. In an embodiment, the material of theseed layer 423 is a titanium alloy (e.g., TiCu). - The
semiconductor element 38 includes an electrical contact for electrically connecting to the semiconductor die 42. In the illustrated embodiment, a portion of theupper circuit layer 383 forms apad 3831, which is the above-mentioned electrical contact. In this embodiment, thesemiconductor element 38 includes asurface finish layer 39 disposed on thepad 3831, where thesurface finish layer 39 is formed in one or more layers, such as layers of Ni, palladium (Pd), and gold (Au) (e.g. Ni/Au, Ni/Pd or Ni/Pd/Au), and the material of thepad 3831 is Cu. For example, a Ni layer of thesurface finish layer 39 serves as a barrier layer which can block some of the Cu diffusion from thepad 3831 to thesolder layer 44, to avoid a crack of theupper circuit layer 383 due to the consuming of thewhole pad 3831. Additionally, Au, Pd or Pd/Au layer(s) of thesurface finish layer 39 disposed on the Ni layer may be used to increase wettability of thesolder layer 44, to avoid inadequate solder bonding due to poor wettability of the Ni layer. - The
solder layer 44 is disposed between thecopper pillar 424 and thesurface finish layer 39, and, as manufactured, comprises amain solder portion 45, afirst IMC 47 and asecond IMC 49. In this embodiment, thesolder layer 44 contacts thecopper pillar 424 directly. The material of themain solder portion 45 is Sn or SnAg. Thefirst IMC 47 and thesecond IMC 49 are a result of the metal interaction between themain solder portion 45 and thecopper pillar 424, and between themain solder portion 45 and thepad 3831 with thefinish layer 39. Thefirst IMC 47 is a Cu, Ni, Sn combination, and thesecond IMC 49 is an Au, Sn combination such as AuSn4, a Pd, Sn combination such as PdSn4, or both an Au, Sn combination and a Pd, Sn combination. In an embodiment, thefirst IMC 47 includes (Cu, Ni, Au, Pd)6Sn5 (i.e., one or more of Cu6Sn5, Ni6Sn5, Au6Sn5 or Pd6Sn5) and other IMCs, and thesecond IMC 49 includes (Au, Pd, Ni)Sn4 (i.e., one or more of AuSn4, PdSn4 or NiSn4) and other IMCs. - The
first IMC 47 includes atop layer 50 and abottom layer 52 formed by metal interaction with themain solder portion 45. In an embodiment, thetop layer 50 and thebottom layer 52 are the same material. Thetop layer 50 is formed at the tip of thecopper pillar 424 from interaction of themain solder portion 45 and thecopper pillar 424, and thebottom layer 52 is formed adjacent to the electrical contact (i.e., the pad 3831) from interaction of thesolder layer 44 and thesurface finish layer 39. In some embodiments, barrier layers may be disposed (e.g., coated) on one or both of thecopper pillar 424 and thesurface finish layer 39; however, in the embodiment illustrated inFIG. 2 , such barrier layer can be omitted. - The
second IMC 49 is also formed by metal interaction, and is formed discontinuously in themain solder portion 45, as indicated by the illustration inFIG. 2 . - As described, in the embodiment of
FIG. 2 , no barrier layer, such as Ni layer, is disposed on the tip of thecopper pillar 424. Thus, during the reflow process, the Cu in thecopper pillar 424 and the Ni in thesurface finish layer 39 will enter thesolder layer 44 rapidly, so as to form thetop layer 50 and thebottom layer 52 of thefirst IMC 47. Specifically, some of the Cu fromcopper pillar 424 passes throughsolder layer 44 and interacts with the Ni in thesurface finish layer 39 to formbottom layer 52, and some of the Ni from thesurface finish layer 39 passes through thesolder layer 44 and interacts with the Cu in thecopper pillar 424 to formtop layer 50. In an embodiment, the metal interaction results in thetop layer 50 and thebottom layer 52 of thefirst IMC 47 including the same material. For example, thetop layer 50 and thebottom layer 52 may both include the same compound or compounds, which may be one or more of (Cu, Ni, Au, Pd)6Sn5. In similar fashion, metals from thecopper pillar 424 and thesurface finish layer 39 pass through thesolder layer 44 to form the discontinuoussecond IMC 49. - The volume ratio of the combined volume of the
first IMC 47 and thesecond IMC 49 to the volume of thesolder layer 44 is controlled to be less than 80%, thereby avoiding joint crack and increasing mechanical reliability of the semiconductor flip-chip bonded device. In some embodiments, the volume ratio of thefirst IMC 47 to thesolder layer 44 is greater than the volume ratio of thesecond IMC 49 to thesolder layer 44. However, in other embodiments, a thickness of a layer or layers of the surface finish layer 39 (e.g., one or more of an Au, Pd or Pd/Au layer(s)) due to process tolerance may be such that the volume ratio of thefirst IMC 47 to thesolder layer 44 is less than the volume ratio of thesecond IMC 49 to thesolder layer 44. - The thickness of the
first IMC 47 may be controlled during processing by controlling the thicknesses of thecopper pillar 424, thesurface finish layer 39, and thesolder layer 44. “Thickness” in this context indicates a vertical dimension in the orientation shown inFIG. 2 . Thus, given thicknesses T1, T2, and T3 inFIG. 2 (thicknesses of thecopper pillar 424, thesolder layer 44, and thesurface finish layer 39, respectively), thetop layer 50 of thefirst IMC 47 will form to a thickness of T5, and thebottom layer 52 of thefirst IMC 47 will form to a thickness of T6. For example: a thickness T1 of thecopper pillar 424 is about 5 micrometers (μm) to about 20 μm; a thickness T2 of thesolder layer 44 is about 5 μm to about 30 μm; and a thickness T3 of thesurface finish layer 39 is about 1 μm to about 15 μm; such that the resulting thickness T5 of thetop layer 50 is about 2 μm to about 3 μm, and the resulting thickness T6 of thebottom layer 52 is no greater than, or is less than T5, and is about 1 μm to about 2 μm. Therefore, a combined thickness of thetop layer 50 and thebottom layer 52 of thefirst IMC 47 is about 3 μm to about 5 μm, and thefirst IMC 47 can therefore be controlled such that it does not replace thesolder layer 44 completely. Further, by controlling the thicknesses T1, T2, and T3, a thickness of thesecond IMC 49 may be controlled, and may be controlled such that the combined thickness of thefirst IMC 47 and thesecond IMC 49 is less than the thickness of the solder layer 44 (i.e., thesolder layer 44 is not completely replaced). In one embodiment, a thickness T4 of thepad 3831 is about 1 μm to about 10 μm; however, the thickness of thepad 3831 does not significantly affect the thickness of thefirst IMC 47 or thesecond IMC 49 in this embodiment, by using thesurface finish layer 39 to block migration of the Cu inpad 3831. - An additional benefit of controlling the intermetallic bonding to form the
first IMC 47 and thesecond IMC 49 is that voids in thesolder layer 44 are avoided; thus, the lifetime of the semiconductor flip-chip bonded device is increased. - Referring to
FIG. 3 , a cross-sectional view of a semiconductor flip-chip bonded device according to another embodiment of the present disclosure is illustrated. The semiconductor flip-chip bonded device of this embodiment is similar to the semiconductor flip-chip bonded device ofFIG. 2 , and the difference is that thecopper pillar 424 has acircumferential protection layer 54 disposed on the sidewall of thecopper pillar 424 to surround thecopper pillar 424. The material of thecircumferential protection layer 54 is a metal oxide, such as copper oxide, which is formed as follows: first, a mask layer is used to cover the bottom surface of the tip of thecopper pillar 424. Then, thecopper pillar 424 with the mask layer are placed into an oxidizing gas so that thecircumferential protection layer 54 is formed on the sidewall of thecopper pillar 424. After the mask layer is removed, thesolder layer 44 is formed at the tip of thecopper pillar 424. - Referring to
FIG. 4 , a cross-sectional view of a semiconductor flip-chip bonded device according to another embodiment of the present disclosure is illustrated. The semiconductor flip-chip bonded device of this embodiment is similar to the semiconductor flip-chip bonded device ofFIG. 2 , and the difference is that the semiconductor die 42 further includes abarrier layer 426 and ametal layer 427. Thebarrier layer 426 is disposed on a tip of thecopper pillar 424, and themetal layer 427 is disposed (for example, coated) on thebarrier layer 426. In an embodiment, the material of thebarrier layer 426 is Ni, and the material of themetal layer 427 is the same as that ofcopper pillar 424, namely, both are Cu. Therefore, thetop layer 50 of thefirst IMC 47 is formed on themetal layer 427 directly. In an embodiment, the material of thetop layer 50 and thebottom layer 52 of thefirst IMC 47 is one or more of (Cu, Ni, Au, Pd)6Sn5, and thetop layer 50 and thebottom layer 52 may be the same alloy. In addition, thecopper pillar 424 of this embodiment may include a circumferential protection layer similar to thecircumferential protection layer 54 illustrated inFIG. 3 . In an embodiment, for controlling the thickness of thefirst IMC 47 and thesecond IMC 49, a thickness T7 of thebarrier layer 426 is about 1 μm to about 5 μm, and a thickness T8 of themetal layer 427 is about 2 μm to about 8 μm. - Referring to
FIG. 5 ,FIG. 6 andFIG. 7 , a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is illustrated. This embodiment is used to manufacture a semiconductor flip-chip bonded device such as that shown inFIG. 2 . - Referring to
FIG. 5 , asemiconductor die 42 is provided. In this embodiment, the semiconductor die 42 includes anactive surface 421, ametal circuit layer 422, aseed layer 423,copper pillars 424 and aprotection layer 425. Themetal circuit layer 422 is disposed on theactive surface 421. In this embodiment, themetal circuit layer 422 includes a plurality of segments insulated from each other, and the material of the segments is Al, Cu or AlCu. Theprotection layer 425 covers theactive surface 421 and themetal circuit layer 422, and defines a plurality ofopenings 4251 to expose a portion of themetal circuit layer 422. In an embodiment, theprotection layer 425 is a passivation layer of metal oxide. Thecopper pillars 424 are disposed adjacent to themetal circuit layer 422, and are electrically connected to themetal circuit layer 422. In this embodiment, theseed layer 423 is disposed on themetal circuit layer 422 in each of theopenings 4251, and each of thecopper pillars 424 is disposed on theseed layer 423. That is, theseed layer 423 is disposed between each of thecopper pillars 424 and themetal circuit layer 422. However, theseed layer 423 may be omitted, and each of thecopper pillars 424 may be disposed on themetal circuit layer 422 directly. In an embodiment, the material of theseed layer 423 is TiCu. - Referring to
FIG. 6 , asolder layer 44 is formed adjacent to a tip of thecopper pillar 424. In this embodiment, thesolder layer 44 is formed at the tip of thecopper pillar 424. That is, there is no barrier layer, such as Ni layer, disposed on the tip of thecopper pillar 424, so that thesolder layer 44 contacts the tip of thecopper pillar 424 directly. The material of thesolder layer 44 is Sn or SnAg. The outer peripheral surface of thesolder layer 44 is coplanar with the outer peripheral surface of thecopper pillar 424, thus, the radius of thesolder layer 44 is substantially the same as that of thecopper pillar 424. - Then, the
semiconductor element 38 is provided. In an embodiment, thesemiconductor element 38 is an interposer, and includes one or more electrical contact(s) for electrically connecting to the semiconductor die 42. A portion of anupper circuit layer 383 of thesemiconductor element 38 forms apad 3831. In this embodiment, thesemiconductor element 38 further includes asurface finish layer 39 disposed on thepad 3831. In an embodiment, the material of thesurface finish layer 39 is a combination of Ni/Au, Ni/Pd or Ni/Pd/Au, and the material of thepad 3831 is Cu. - In the embodiment illustrated in
FIG. 6 , a thickness T1 of thecopper pillar 424 is about 5 μm to about 20 μm, the thickness T2 of thesolder layer 44 is about 5 μm to about 30 μm, the thickness T3 of thesurface finish layer 39 is about 1 μm to about 15 μm, and the thickness T4 of thepad 3831 is about 1 μm to about 10 μm. - Referring to
FIG. 7 , the semiconductor die 42 is placed on thesemiconductor element 38 such that thesolder layer 44 on thecopper pillar 424 contacts thesurface finish layer 39 on the electrical contact (e.g., the pad 3831) of thesemiconductor element 38. Then, reflow is performed to bond thecopper pillar 424 with thesolder layer 44, and to bond thesolder layer 44 with thesurface finish layer 39. The reflow forms thefirst IMC 47 and thesecond IMC 49 in thesolder layer 44, leaving themain solder portion 45 between. In an embodiment, the material of themain solder portion 45 is Sn or SnAg, thefirst IMC 47 is made of combinations of Cu, Ni, and Sn and includes Cu6Sn5, and thesecond IMC 49 is AuSn4 based, PdSn4 based, or a combination thereof. - In the embodiment described by
FIGS. 5 to 7 , no barrier layer, such as a Ni layer, is coated on the tip of thecopper pillar 424; thus, during the reflow process, the Cu in thecopper pillar 424 and the Ni in thesurface finish layer 39 will enter thesolder layer 44 rapidly, so as to form thetop layer 50 and thebottom layer 52 of thefirst IMC 47. In an embodiment, the material of each of thetop layer 50 and thebottom layer 52 includes one or more of (Cu, Ni, Au, Pd)6Sn5, and both thetop layer 50 and thebottom layer 52 may be the same material. According to the Gibb energy equation, if the energies of formation are different, the intermetallic compound with lower energy of formation and higher stability will be formed first. Because the energy of formation of (Cu, Ni, Au, Pd)6Sn5 is lower that of (Au, Pd, Ni)Sn4, and because (Cu, Ni, Au, Pd)6Sn5 is more stable than (Au, Pd, Ni)Sn4, thetop layer 50 and thebottom layer 52 of the first IMC 47 (both in a form (Cu, Ni, Au, Pd)6Sn5) will be formed first. - In some embodiments, the maximum volume ratio of the Cu6Sn5 of the first IMC 47 (including the
top layer 50 and the bottom layer 52) to thesolder layer 44 is about 15%. Further, if the concentration of Cu in thesolder layer 44 is more than one percent by weight (1 wt %), the formation of AuSn4 and/or PdSn4 will be suppressed. In an embodiment such as described with respect toFIGS. 5 to 7 , where no barrier layer is coated on the tip of thecopper pillar 424, the Cu from thecopper pillar 424 may suppress formation of thesecond IMC 49. For example, during the reflow process, the Cu in thecopper pillar 424 enters thesolder layer 44 freely, the Cu in thesolder layer 44 forms Cu6Sn5 first, and, consequently, the relatively large amount (e.g., greater than 1 wt %) of Cu remaining in thesolder layer 44 suppresses the formation of AuSn4 and/or PdSn4. Thus, in some embodiments, the volume ratio of thefirst IMC 47 to thesolder layer 44 will be greater than the volume ratio of thesecond IMC 49 to thesolder layer 44. However, in other embodiments, a thickness of an Au, Pd or Pd/Au layer of thesurface finish layer 39 due to process tolerance may be such that it counterbalances the Cu remaining in thesolder layer 44, and thus formation of AuSn4 and/or PdSn4 is not suppressed. In such a case, the volume ratio of thefirst IMC 47 to thesolder layer 44 may be less than the volume ratio of thesecond IMC 49 to thesolder layer 44. Nevertheless, the volume ratio of the combination of thefirst IMC 47 and thesecond IMC 49 to thesolder layer 44 may be controlled to be less than 80%, to avoid joint crack and to increase mechanical reliability of the semiconductor flip-chip bonded device. - Referring to
FIG. 8 , a method for manufacturing a semiconductor device according to another embodiment of the present disclosure is illustrated. This embodiment is used to manufacture a semiconductor flip-chip bonded device such as that shown inFIG. 4 . The method of this embodiment is similar to the method ofFIGS. 5 to 7 , and the difference is that the semiconductor die 42 further includes abarrier layer 426 and ametal layer 427. In an embodiment, the material of thebarrier layer 426 is Ni, and thebarrier layer 426 is disposed on a tip of thecopper pillar 424. The material of themetal layer 427 is the same as that ofcopper pillar 424, namely, both are Cu. Themetal layer 427 is disposed on thebarrier layer 426. A thickness T7 of thebarrier layer 426 is about 1 μm to about 5 μm, and a thickness T8 of themetal layer 427 is about 2 μm to about 8 μm. Thesolder layer 44 is disposed on themetal layer 427. In this embodiment, the outer peripheral surface of thesolder layer 44 is coplanar with the outer peripheral surfaces of thecopper pillar 424 and themetal layer 427, thus, the radius of thesolder layer 44 is substantially the same as those of thecopper pillar 424 and themetal layer 427. - In this embodiment, the relationship between the thickness T8 of the
metal layer 427 and the thickness T2 of thesolder layer 44 is about T8≧0.09 T2, which is derived as follows. In this embodiment, thebarrier layer 426 is coated on the tip of thecopper pillar 424, thus, during the reflow process, the Cu in thecopper pillar 424 will not enter thesolder layer 44. That is, the Cu in thesolder layer 44 only, or primarily, comes from thecopper metal layer 427. - The thickness T8 of the
copper metal layer 427 may be considered as a combination of a first portion and a second portion. A thickness of the first portion of thecopper metal layer 427 is used to control the formation of Cu6Sn5, and a thickness of the second portion of thecopper metal layer 427 is used to suppress the formation of AuSn4 and/or PdSn4. For convenience, the thickness of the first portion of thecopper metal layer 427 is referred to herein as T81, and the thickness of the second portion of thecopper metal layer 427 is referred to herein as T82. - T81 is determined as follows. As stated above, in some embodiments, the maximum volume ratio of the Cu6Sn5 to the
solder layer 44 is about 15%. Thus, V1=(0.15) V2, wherein V1 represents the volume of the Cu6Sn5, and V2 represents the volume of thesolder layer 44. Because the volume ratio of Cu in the Cu6Sn5 is 6/11, the volume of Cu is 6/11 V1=( 6/11)(0.15) V2. In geometric terms, the volume of Cu is πr2×T81, and the volume of thesolder layer 44 is V2=πr2×T2, wherein r represents the radius of the solder layer 44 (which is same as the radius of the copper metal layer 427). The two descriptions of volume of Cu are equated as in equation (1), and the thickness T81 determined as in equation (2) by solving equation (1). -
πr 2 ×T 81=( 6/11)(0.15)V 2=( 6/11)(0.15) (πr 2 ×T 2) (1) -
T 81=( 6/11)(0.15)×T 2=0.0818 T 2 (2) - The thickness T82 of the second portion of the
copper metal layer 427 is determined as follows. As stated above, in some embodiments, if the concentration of Cu in thesolder layer 44 is more than 1 wt %, the formation of AuSn4 and/or PdSn4 will be suppressed. Therefore, in some embodiments, suppression occurs when -
- (i.e., when 99 W1≧W2) wherein W1 represents the weight of Cu, and W2 represents the weight of SnAg. The weight of Cu is W1=πr2×T82×8.96, and the weight of the
solder layer 44 is W2=πr2×T2×7.31, wherein r represents the radius of the solder layer 44 (which is same as the radius of the copper metal layer 427), 8.96 is the density of Cu, and 7.31 is the density of SnAg. Equation (3) starts with the relationship 99 W1≧W2 and substitutes in the relationships for W1 and W2, and the thickness T82 is solved for in equation (4). -
99(πr 2 ×T 82×8.96)≧(πr 2 ×T 2×7.31) (3) -
T82≧0.00824 T2 (4) - The thickness T8 is the sum of the thicknesses T81 and T82, thus, from equations (2) and (4), T8=T81+T82≧0.0818 T2+0.00824 T2≧0.09004 T2. That is, the relationship between the thickness T8 of the
copper metal layer 427 and the thickness T2 of thesolder layer 44 is about T8≧0.09 T2. - Still referring to
FIG. 8 , the semiconductor die 42 is placed on thesemiconductor element 38 such that thesolder layer 44 contacts thesurface finish layer 39 on the electrical contact (e.g., the pad 3831) of thesemiconductor element 38. Then, reflow is performed to form thefirst IMC 47 and thesecond IMC 49 in thesolder layer 44, along with the remainingmain solder portion 45, such that the semiconductor flip-chip bonded device as shown inFIG. 4 is obtained. In this embodiment, the relationship between the thickness T8 of thecopper metal layer 427 and the thickness T2 of thesolder layer 44 satisfies the above-mentioned equation, T8≧0.09 T2, therefore, the volume ratio of thefirst IMC 47 and thesecond IMC 49 to thesolder layer 44 is less than 80%, thereby avoiding joint crack and increasing mechanical reliability of the semiconductor flip-chip bonded device. - As used herein, the terms “substantially” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, the terms can refer to less than or equal to ±10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. Thus, one radius described as “substantially the same” as another radius indicates that the one radius is less than or equal to ±10% of the other radius, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.
- Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
- While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.
Claims (21)
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CN201610120953.0A CN105938827B (en) | 2015-03-05 | 2016-03-03 | Semiconductor device and the method for manufacturing semiconductor device |
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US10347602B1 (en) * | 2018-07-23 | 2019-07-09 | Mikro Mesa Technology Co., Ltd. | Micro-bonding structure |
US10388627B1 (en) * | 2018-07-23 | 2019-08-20 | Mikro Mesa Technology Co., Ltd. | Micro-bonding structure and method of forming the same |
US20220336400A1 (en) * | 2021-04-15 | 2022-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connecting structure, package structure and manufacturing method thereof |
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US10763231B2 (en) * | 2018-07-27 | 2020-09-01 | Texas Instruments Incorporated | Bump bond structure for enhanced electromigration performance |
US20230091379A1 (en) * | 2021-09-22 | 2023-03-23 | Intel Corporation | First level interconnect under bump metallizations for fine pitch heterogeneous applications |
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US8592995B2 (en) | 2009-07-02 | 2013-11-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump |
TWI401825B (en) * | 2009-11-27 | 2013-07-11 | Ind Tech Res Inst | A bonding method for led chip and bonded led |
US9142533B2 (en) * | 2010-05-20 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate interconnections having different sizes |
US8810035B2 (en) | 2010-10-22 | 2014-08-19 | Panasonic Corporation | Semiconductor bonding structure body and manufacturing method of semiconductor bonding structure body |
TWI476878B (en) | 2012-05-10 | 2015-03-11 | Univ Nat Chiao Tung | Electric connecting structure comprising preferred oriented cu5sn5 grains and method of fabricating the same |
TWI500129B (en) | 2012-08-03 | 2015-09-11 | Advanced Semiconductor Eng | Semiconductor flip-chip bonding structure and process |
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US9368438B2 (en) * | 2012-12-28 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package (PoP) bonding structures |
US8853071B2 (en) * | 2013-03-08 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical connectors and methods for forming the same |
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US10388627B1 (en) * | 2018-07-23 | 2019-08-20 | Mikro Mesa Technology Co., Ltd. | Micro-bonding structure and method of forming the same |
US20220336400A1 (en) * | 2021-04-15 | 2022-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connecting structure, package structure and manufacturing method thereof |
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