JP2012190939A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of connection reliability between a bump and a pad electrode which is caused by a solder component, such as stannum, penetrating through an under-barrier metal of a bump electrode and reacting with the pad electrode located below the under-barrier metal during the formation of the bump formed of solder or flip-chip mounting.SOLUTION: An under-barrier metal 6 is formed between a pad electrode 3 formed on a semiconductor substrate 1 and a bump 8 formed of solder. The under-barrier metal 6 coats an area ranging from the pad electrode 3 exposed from an opening 5 formed in a protective insulation film 4 to the protective insulation film 4 around the opening 5. However, a bottom surface of the bump 8 is formed so as to be smaller than the under-barrier metal 6, preferably smaller than the opening 5, and be located vertically above an inner region of the opening 5.

Description

  The present invention relates to a semiconductor device in which bumps are provided on a pad electrode in order to enable flip chip mounting, and a method for manufacturing the same.

  One of mounting methods for some electronic components such as semiconductor devices and surface acoustic wave (SAW) filters is a flip chip mounting method. In the flip chip mounting method, basically, bump electrodes are formed on one or both of a pad electrode of a semiconductor integrated circuit device (semiconductor bare chip) and a wiring board on which a wiring pattern is formed, and wiring is performed. In this technique, the surface of the semiconductor integrated circuit is faced down on the surface of the substrate (face-down state) and directly bonded via bumps.

  As described above, the flip-chip mounting method is a method in which both are bonded via a small-sized bump, so that the mounting area and volume are small, enabling high-density mounting and downsizing of electronic devices mounting semiconductor integrated circuits. To do. In addition, this mounting method does not require a long wiring such as a bonding wire, and thus has an advantage that the operation of the electronic device can be speeded up. For these reasons, semiconductor integrated circuit devices that employ bumps as electrodes have been increasing in recent years.

  The electrode portion having the bump is generally a pad electrode formed on the substrate of the semiconductor integrated circuit, a bump-like bump, and an under barrier metal (Under Barrier Metal) provided between the two and under the bump. It is called UBM unless there is The material of the bump is mainly gold or “solder”, and the material of the pad electrode is usually aluminum or an alloy mainly composed of aluminum. However, in devices that handle high-frequency signals and devices that require high reliability in connection parts, pad electrodes having a gold film (for example, a gold plating layer) formed at least on the uppermost layer are used. In UBM, gold or tin (Sn), which is a component element of a bump, diffuses into the pad electrode by heating at the time of bump formation or semiconductor device mounting, and the interface between the bump and the pad electrode is brittle. Used to prevent the adhesion from deteriorating.

  Various bump electrode structures have been proposed to date. Patent Document 1 discloses a bump electrode in which a UBM having a titanium / nickel titanium compound (nickel titanium solid solution) / nickel structure is formed between a Pb—Sn solder bump and an aluminum pad. It has been reported that the above UBM can suppress the diffusion of Sn into the UBM and can prevent breakage of the intermetallic compound formed by the diffusion.

  Patent Document 2 describes a bump electrode including a solder bump made of Pb-5 wt% Sn, an electrode pad made of a Ti-Ni UBM layer, aluminum, an aluminum alloy layer, or the like. Further, Patent Document 3 includes a solder bump mainly composed of Sn, a Ti layer having a function as an adhesive layer, a Ni layer having a function as a barrier layer, and an Au layer having a function for ensuring solder wettability. A bump electrode including an electrode pad mainly composed of UBM and Au is described. Patent Document 4 describes a bump electrode including a gold bump, a UBM layer made of Ti—W, Ti—Pd, Ti—Pt, or the like, and a pad portion containing aluminum. Patent Document 5 describes a bump electrode including a Pb / Sn-based protruding electrode, a UBM made of a Ti layer / Pt layer / Au layer, and a wiring metal made of Ti / Pt / Au.

Japanese Patent Laid-Open No. 9-129647 JP 11-186309 A JP 2006-19550 A JP 2001-77150 A JP-A-6-104262

  As described above, bump electrodes having various structures have been conventionally proposed. When flip-chip mounting of a semiconductor integrated circuit device on which bumps using solder as an electrode material are mounted, the bumps are melted and bonded to a wiring board. For this reason, the bonding load applied to the base of the bump is overwhelmingly smaller than that of the gold bump. In particular, in the case of a semiconductor integrated circuit in which a circuit element or the like is formed in a layer immediately below the bump, the influence on the circuit element or the like. There is a merit that there is little.

  When solder is used as the bump material, tin in the molten solder penetrates very well into aluminum and gold, which are the main materials of the pad electrode. For this reason, various UBMs have conventionally been adopted, and the diffusion of tin in the solder to the pad electrode due to the heat treatment in the solder bump formation process or the mounting process has been suppressed. However, when tin in the solder forms an intermetallic compound layer or alloy layer with UBM, tin diffuses to the pad electrode even though UBM is provided, and the metal and intermetallic compound layer or alloy layer of the pad electrode material This increases the probability that the bonding strength between the bump and the pad electrode is lowered and the bonding reliability is deteriorated.

  The present invention provides means for solving such problems. In particular, the present invention provides a bump electrode structure capable of further improving the effect of suppressing diffusion of metal component elements contained in solder into a pad electrode, a semiconductor device having the structure, and a method for manufacturing the semiconductor device. For the purpose.

  A first semiconductor device according to the present invention for solving the above problems includes a pad electrode formed on a semiconductor substrate, a protective insulating film formed on the semiconductor substrate so as to cover the pad electrode, An opening provided in the protective insulating film on the pad electrode and exposing the surface of the pad electrode from the protective insulating film, and the protection around the opening from the surface of the pad electrode exposed in the opening An under barrier metal formed so as to cover a region over the insulating film, and a bump made of solder provided on the under barrier metal and having a bottom area smaller than that of the under barrier metal. .

  In an embodiment of the first semiconductor device, the under barrier metal has a film thickness larger than that of the protective insulating film, and the protection around the opening from the pad electrode exposed in the opening. The surface over the insulating film is flat.

  The first semiconductor device has various more desirable forms. First, the bottom surface of the bump is located in a region included in the opening on the under barrier metal. Alternatively, a metal layer is formed between the under barrier metal and the bump that includes an element of a metal material having wettability with respect to the solder larger than that of the under barrier metal and a component element of the solder. The metal layer is preferably located in a region included in the opening on the under barrier metal. In yet another embodiment, the metal layer has the same area as the bottom surface of the bump and contacts the entire surface.

  A suitable example of the element of the metal material having wettability with respect to the solder larger than that of the under barrier metal is at least one of Au, Ag, and Pd. In addition, the component element of the solder is Sn. Furthermore, the example of the under barrier metal is made of an alloy of Ni and P.

  In order to solve the above problems, a second semiconductor device according to the present invention includes a pad electrode formed on a semiconductor substrate, a protective insulating film formed on the semiconductor substrate so as to cover the pad electrode, An opening provided in the protective insulating film on the pad electrode and exposing the surface of the pad electrode from the protective insulating film, and the protection around the opening from the surface of the pad electrode exposed in the opening The film is formed so as to cover a region extending over the insulating film, and the film thickness thereof is larger than the film thickness of the protective insulating film. From the pad electrode exposed in the opening to the protective insulating film around the opening And an under barrier metal having a flat surface, and a bump made of solder provided on the under barrier metal.

  In the second semiconductor device, it is desirable that the thickness of the under barrier metal is 2 to 6 times the thickness of the protective insulating film.

  The first semiconductor device or the second semiconductor device described above is effective even when a flip chip mounting method or the like is used to melt a bump made of solder to join two semiconductor devices to manufacture a mounting body. Demonstrate.

  Next, a first method of manufacturing a semiconductor device according to the present invention for solving the above-described problems includes a step of forming a pad electrode on a semiconductor substrate, and a protective insulation on the semiconductor substrate so as to cover the pad electrode. Forming a film; forming an opening in the protective insulating film on the pad electrode to expose a surface of the pad electrode; and exposing the opening from the surface of the pad electrode exposed in the opening. Forming an under barrier metal so as to cover a region over the surrounding protective insulating film; forming a metal film having an area smaller than the area of the under barrier metal on the under barrier metal; and A step of supplying a solder material onto the metal film; and a step of melting the solder material to form a bump made of solder on the metal film. Wettability to solder made of an element of greater metal material than the under-barrier metal.

  Also in the first manufacturing method, as in the case of the first and second semiconductor devices, a suitable example of an element of a metal material whose wettability to the solder is larger than that of the under barrier metal is at least Au, Ag or Any one of Pd. An example of the under barrier metal is an alloy of Ni and P.

  A second method of manufacturing a semiconductor device according to the present invention for solving the above-described problems includes a step of forming a pad electrode on a semiconductor substrate, and a protective insulating film on the semiconductor substrate so as to cover the pad electrode. A step of forming an opening exposing the surface of the pad electrode in the protective insulating film on the pad electrode; and a surface of the pad electrode exposed in the opening using a plating method. Covering the region surrounding the protective insulating film around the opening, the film thickness is larger than the protective insulating film, and the protection around the opening from the pad electrode exposed in the opening. A step of forming an under barrier metal having a flat surface over the insulating film; a step of supplying a solder material onto the under barrier metal; and melting the solder material to form on the metal film And forming a bump consisting of've got.

  According to the present invention, in the semiconductor device, (1) the bump made of solder is provided on the under barrier metal so that the area of the bottom surface is smaller than the area of the under barrier metal. Or (3) the under barrier metal has a film thickness larger than that of the protective insulating film, and is provided so as to be located in a region included in the opening of the protective insulating film on the under barrier metal. The surface from the pad electrode exposed in the opening of the film to the protective insulating film around the opening is formed flat.

  Among these, according to (1) and (2), the area of the bottom surface of the bump is narrowed down to be smaller than the area of the under barrier metal, so the range in which the solder component elements such as Sn diffuse downward in the under barrier metal is limited. it can. This makes it difficult for the component elements to reach the pad electrode. In particular, according to (2), the bottom surface of the bump is not located on the opening boundary (the stepped portion of the protective insulating film due to the opening) of the protective insulating film, where the film density (or diffusion preventing ability) of the under-barrier metal tends to decrease. Great effect. According to (3), since the film density of the under barrier metal is not greatly reduced, the component elements of the solder can hardly reach the pad electrode.

  As described above, according to the present invention, the solder component element diffuses to the pad electrode, where a compound layer or an alloy layer of the solder component element and the pad electrode material is formed, and the bonding strength between the bump and the pad electrode is increased. It can suppress strongly that it falls.

Sectional drawing (a) and top view (b) which show the bump electrode part of the semiconductor device which concerns on embodiment of this invention. Process sectional drawing which shows the manufacturing method of the bump electrode part in the semiconductor device which concerns on embodiment of this invention. The process sectional view showing a part of manufacturing method of a bump electrode part in a semiconductor device concerning an embodiment of the present invention, and a mounting process following it. Process sectional drawing which shows a part of mounting process with respect to the semiconductor device manufactured by the manufacturing method which concerns on embodiment of this invention. Sectional drawing which shows an example of the mounting body of the semiconductor device manufactured by the manufacturing method which concerns on this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1A is a cross-sectional view of a bump electrode portion of a semiconductor device according to an embodiment of the present invention. The semiconductor device is assumed to be a semiconductor integrated circuit such as a memory or a system LSI in which a large number of bump electrodes are formed on one chip, and the figure shows one of the bump electrodes. FIG. 1B is a plan view of the bump electrode region shown in FIG.

  In the semiconductor device shown in FIG. 1, a circuit formation layer 2 is provided on a semiconductor substrate (silicon single crystal substrate) 1. Although the detailed structure of the circuit forming layer 2 is not shown, it is a micro-sized MOS transistor, an element such as a capacitor, a resistor, an insulating film covering them, a plurality of wiring layers and an interlayer separating the wiring layers. A multilayer wiring structure made of an insulating film is included. A pad electrode 3 made of a laminated film of a Ti / TiN barrier metal and an aluminum alloy film is formed at a predetermined position on the circuit forming layer 2. A wiring 3a is connected to the pad electrode 3 as shown in FIG. 1B, and the pad electrode 3 is electrically connected to an element included in the circuit formation layer 2 directly or indirectly through the wiring. Yes.

The peripheral portion on the pad electrode 3 is covered with a protective insulating film 4 made of a silicon nitride film (SiN _x ), a silicon oxynitride film (SiON), a silicon oxide film SiO ₂ , or an appropriate laminated film thereof, and the pad electrode 3, an opening 5 is provided in the protective insulating film 4 so that the surface of the pad electrode 3 is exposed. In the present embodiment, the openings 5 are formed in a circular pattern centered on the intersection of two diagonal lines of the rectangular pad electrode 3.

  The UBM 6 is formed so as to cover a region extending from the surface of the pad electrode 3 exposed to the opening 5 to the surface of the protective insulating film 4 around the outside of the opening 5. UMB6 is an alloy metal film of Ni-7 wt% P (phosphorus) whose main component is nickel (Ni). The pattern of the UBM 6 has a concentric shape centering on the center of the opening 5, and a part of the pattern reaches the external region of the pad electrode 3 when seen in a plan view. However, the UBM 6 is located inside the region of the pad electrode 3 plus the thickness of the protective insulating film 4 formed on the side wall of the pad electrode 5 (the thickness measured in the lateral direction). Yes.

  A thin metal layer 7 and bumps 8 thereon are formed on the surface of the UBM 6. The bumps 8 are made of, for example, Sn—Ag solder, are almost hemispherical, and have a circular bottom surface. On the other hand, the metal layer is an alloy layer containing gold (Au) and tin (Sn), which is a component element of solder, and has substantially the same shape, the same position, and the same area as the bottom surface of the bump 8. It is in contact with the entire bottom surface. However, in some cases, the metal layer 7 is located on the inner side of the bottom surface of the bump 8, and the shape is substantially the same as the bottom surface of the bump 8, but the area may be slightly smaller. As shown in FIG. 1, the bottom surface of the bump 8 and the metal layer 7 are formed so as to be smaller in size than the opening 5 of the protective insulating film 4, and in addition, provided to be located in the upper layer of the inner region of the opening 5. Is desirable.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described. 2 to 4 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, in particular, a method for manufacturing a bump electrode part and a flip chip mounting process after the bump electrode is manufactured. Each process sectional view shows the same part as the bump electrode part of the semiconductor device of FIG.

First, as shown in FIG. 2A, a circuit forming layer 2 including a semiconductor element such as a MOS transistor or a multilayer wiring structure is formed on a semiconductor substrate 1 in a wafer state using a process generally called a diffusion process. To do. Thereafter, a laminated film made of Ti / TiN film / Al alloy film is deposited on the circuit forming layer 2 to a thickness of 1 μm to 2 μm by sputtering, and the pad electrode 3 is formed by patterning. Further, a protective insulating film 4 made of, for example, at least one of SiN _x , SiON or SiO ₂ is deposited on the pad electrode 3 to a thickness of 1 μm by plasma CVD, and an opening 5 is formed by dry etching to form the pad electrode 3. To expose the surface.

  Next, as shown in FIG. 2B, a Ni-7 wt% P film is deposited to a thickness of 5 μm on the surface of the pad electrode 3 exposed in the opening 5 by using an electroless plating method to form the UBM 6. . This step can be performed by using, for example, a plating solution containing hypophosphorous acid and Ni, and the metal material on the surface of the pad electrode 3 exposed in the opening 5 serves as a catalyst to selectively perform the Ni—P alloy. A film can be deposited. After the Ni—P alloy film grows from the surface of the pad electrode 3 to the height of the upper surface of the protective insulating film 4, the Ni—P alloy film rises further upward and partly spreads in the lateral direction. Since it grows, the shape shown in FIG. 2B is obtained. Thus, the UBM 6 is deposited to be thicker than at least the thickness of the protective insulating film 4. Moreover, 5-12 wt% is suitable as P concentration of a Ni-P alloy film.

  As can be seen from this film growth mechanism, the grown UBM 6 automatically has a concentric shape with respect to the circular pattern of the openings 5 (see FIG. 1B). Therefore, this plating process does not particularly require a UBM6 pattern forming mask. In addition, what is necessary is just to adjust the hypophosphorous acid density | concentration in a plating solution, in order to obtain the desired composition ratio with respect to the phosphorus in UBM6.

  Next, as shown in FIG. 2C, a photoresist film 9 having an opening pattern that is circular and has a smaller area than the opening 5 of the protective insulating film 4 is formed on the entire surface of the UBM 6. Subsequently, a metal film, specifically, a gold film 10 is deposited on the UBM 6 exposed in the opening of the photoresist film 9 to a thickness of 0.1 μm by using an electroless plating method. Since the plating proceeds by a substitution reaction between gold and the material Ni of the UBM 6, the gold film 10 can be grown almost only on the UBM 6. Thereafter, the photoresist film 9 is removed using an organic solvent.

  Although there is a possibility that minute gold particles adhere to the surface of the photoresist film 9 by the plating of the gold film 10, the gold particles are automatically removed by a lift-off mechanism in the removal process of the photoresist film 9. By this step, the pattern of the gold film 10 is formed in a plane area that is smaller than the UBM 6 and the opening 5 and is included in the opening 5 on the UBM 6.

  Next, as shown in FIG. 2D, an organic resin film (mask pattern layer) 11 such as a photoresist in which the pattern of the opening 12 is formed on the UBM 6 is formed. The organic resin film 11 may or may not be photosensitive per se. The opening 12 has a circular shape and is smaller in size and area than the UBM 6 but larger than the pattern of the gold film 10. The opening 12 is included in the region of the UBM 6 so as to include the gold film 10. Next, a solder material, for example, a solder paste 13 is applied so as to be embedded only in the opening 12. The solder paste 13 is a material obtained by mixing flux components such as rosin, a solvent, an activator, and a thickener with, for example, Sn-Ag solder fine powder.

  Next, as shown in FIG. 3A, when the solder component in the solder paste 13 is melted by heating at a temperature of hundreds of degrees or more, bumps 8 close to a hemisphere are formed by the surface tension. At this time, the UBM 6 and the gold film 10 (shown in FIG. 2D) and the solder are in direct contact with each other. However, the Ni-P alloy constituting the UBM 6 has a property that the wettability with respect to the molten solder is small, that is, the solder material element hardly diffuses into the Ni-P alloy. On the other hand, gold has high wettability with molten solder. Due to such a difference in wettability, the molten solder does not wet and spread on the UBM 6, and conversely, the molten solder collects on the gold film 10, so that the bumps 8 become hemispherical. The molten solder collected on the gold film 10 easily diffuses into the gold film 10 and changes to a metal layer 7 of an alloy containing component elements (particularly Sn) constituting the solder and gold.

  Here, the “wetting property” of the solder represents the degree to which the molten solder wets and spreads on the base surface, and can be defined as a numerical value by various generally accepted measurement methods. The bumps 8 can also be formed by dropping a solder ball together with a flux into the opening 12 of the organic resin film 11 and performing a solder melting process instead of forming by the solder paste printing method.

  Next, the organic resin film 11 is removed, and the flux residue is washed as necessary to complete a semiconductor device in a wafer state. Thereafter, a semiconductor chip is formed through backside polishing of the semiconductor substrate 1 and singulation by dicing for each die. The semiconductor device A in FIG. 3B is a chip-like semiconductor device formed in this way.

  In the process shown in FIG. 3B, a semiconductor device B formed in the same process as the semiconductor device A is prepared. Similar to the semiconductor device A, the semiconductor device B is a semiconductor substrate 21, a circuit forming layer 22, a pad electrode 23, a protective insulating film 24 in which an opening 25 is formed, an UBM 26, for example, an alloy of tin that is a component element of gold and solder. The metal layer 27 and the bump 28 are provided. The semiconductor devices A and B are positioned and positioned so that the bumps 8 and 28 formed on the corresponding pad electrodes 3 and 23 to be electrically connected for flip chip mounting face each other.

  Next, as shown in FIG. 4, the bumps 8 and 28 are melted and bonded to each other at a temperature of several hundreds of degrees Celsius or higher to form a bonding bump 30. In this way, the semiconductor devices A and B are joined. Thereafter, a gap formed between the semiconductor devices A and B by the bump bonding is filled with an underfill 31 mainly composed of a resin, so that the bonding between the two semiconductor devices is made more reliable.

  FIG. 5 is a cross-sectional view showing an example of a mounting body in which the semiconductor device C and the semiconductor device D manufactured by the semiconductor device manufacturing method according to the present invention are flip-chip mounted. The semiconductor device C has a circuit formation layer 41 on the semiconductor substrate 40, and the semiconductor device D also has a circuit formation layer 44 on the semiconductor substrate 43. The semiconductor devices C and D are joined by a plurality of solder joining bumps 45 and an underfill 46 filled between the devices. In FIG. 5, the pad electrodes included in the bump electrodes, the UBM, the metal layer on the UBM, and the like are not directly illustrated, and are included in the circuit forming layers 41 and 44.

  The semiconductor devices C and D are semiconductor device examples in which the bump electrode according to the present invention is applied as a micro bump provided immediately above a semiconductor circuit formation region including a MOS transistor or the like. If such micro bumps are applied, the pad electrode arrangement pitch for forming the bumps can be reduced and a large number of pad electrodes can be arranged in a limited area, and the semiconductor devices are connected to each other via the large number of electrodes. Can be speeded up.

  A pad electrode 42 is formed on the periphery of the chip of the semiconductor device C and is electrically connected to either the bonding bump 45 directly or indirectly. Through this pad electrode 42, signal input / output between the semiconductor device as the mounting body and the outside can be performed. Unlike the case of FIG. 5, when two semiconductor devices to be flip-chip mounted have the same chip size and are connected to each other only by micro bumps, for example, a specific bonding bump of one semiconductor device By providing a silicon through electrode penetrating from the bottom to the back surface of the semiconductor substrate, it is possible to exchange signals with the outside.

  The semiconductor device according to the present invention described above has the UBM 6 having the shape shown in FIG. 1A or FIG. That is, the thickness of the UBM 6 is at least larger than the thickness of the protective insulating film 4, and the upper surface of the UBM 6 is substantially flat from the pad electrode 3 exposed in the inner region of the opening 5 to the protective insulating film 4 around the opening 5. Has a shape. In the film having such a shape, the density of the film does not decrease greatly even in a portion where the corner or step of the protective insulating film 4 forming the opening 5 exists, and the density tends to be maintained to some extent.

  In particular, as described in the manufacturing method according to the embodiment of the present invention, when the UBM 6 is formed by a plating method capable of selective growth, a film grows vertically upward from the surface of the pad electrode 3 exposed in the opening 5 first. Then, after growing from the opening 5, that is, after growing thicker than the protective insulating film 4, it grows so as to spread laterally. According to this film growth mechanism, it is considered that the corner portion or the stepped portion formed at the end of the opening 5 does not become a factor inhibiting the film growth. Therefore, the film density of the UBM 6 does not decrease even in this portion, and becomes more uniform.

  Due to the above property that the film density of the UBM 6 hardly decreases, the solder component Sn is contained in the UBM 6 in the heat treatment in the bump 8 formation process (see FIG. 3A) and the bump bonding process (see FIG. 4). Even if it diffuses, the probability of reaching the pad electrode 3 can be reduced. In order to further improve this effect, it is desirable that the UBM 6 is formed to a thickness of 2 to 6 times the thickness of the protective insulating film 4 by using an electroless plating method.

  On the other hand, conventionally, the UBM (or a film corresponding thereto) is formed thinner than the protective insulating film on the pad electrode (for example, Patent Documents 3 and 4), (electron beam) vapor deposition method, sputtering method (for example, patent) In most cases, it was formed using Documents 1, 2, 3, 5).

  In particular, in the latter UBM formation process using physical vapor deposition, the film grows vertically from the exposed surface of the pad electrode and from the side wall of the protective insulating film opening formed on the pad electrode in the horizontal direction. The density of the film is extremely lowered at the part where it collides with the film. In the former case, the film grows faithfully in the cross-sectional shape of the opening along the horizontal plane of the pad electrode and the side wall of the opening, and the film is bent at the corner of the opening. Therefore, even when the UBM is thin, the density of the film is lowered at the bent portion. Thus, it can be said that the conventional UBM has a small effect of preventing the abnormal diffusion of Sn.

  In the bump electrode of the semiconductor device according to the present invention, as shown in FIG. 1A and the like, the bottom surface of the bump 8 is set to an area smaller than the area of the UBM 6 and is provided so as to be included in the upper surface region of the UBM 6. Further, the bottom surface is provided so as to be included in the inner region of the opening 5 so as not to overlap the corner part (or step part) of the protective insulating film 4 formed by the opening 5 in the vertical direction. If the bottom surface of the bump 8 is arranged at such a position, Sn diffused downward from the bump 8 can hardly reach the vicinity of the corner portion of the opening 5 of the UBM 6. As a result, Sn reaches the interface between the pad electrode 3 and the UBM 6, and an alloy layer that deteriorates the bonding reliability between the pad electrode 3 and the UBM 6 or the bump 8 near the interface, for example, Al—Ni—P— in the above embodiment. The Sn alloy layer can be made more difficult to form.

  The method of manufacturing a semiconductor device according to the present invention has a smaller area than a UBM and a greater wettability than a UBM on a UBM (Ni-P alloy film) made of a conductive material having a low wettability with respect to molten solder. It includes a step of forming a metal film (gold film) (see FIGS. 2B and 2C) and a step of melting solder (see FIG. 3A). Through these steps, the area and position of the bottom surface of the bump 8 can be automatically set to the above-described conditions using the difference in wettability.

  The area of a metal film having a wettability greater than that of UBM with respect to molten solder, such as a gold film, is preferably 40% to 60% of the area of the upper surface of the UBM. When the area of the metal film exceeds 60% of the UBM, for example 90%, the probability that the molten solder spreads on the UBM is high, and the bottom surface of the bump is on the outer region of the opening in which the protective insulating film is formed. Increases the possibility of overlapping and expanding. Further, when the area of the metal film is smaller than 40% of the UBM, for example, 10%, the bottom area of the bump becomes excessively small, so that the bonding strength between the bump and the UBM tends to be insufficient.

  In the technique of forming bumps by narrowing the bottom area smaller than the area of the UBM as in the manufacturing method according to the present invention, if the solder material supplied onto the UBM is determined to be a certain amount, the bottom area of the bump is The height of the bump can be increased as compared with the conventional technique in which the area of the UBM is equal to or larger than that of the UBM. Therefore, when the semiconductor devices are joined as in the step shown in FIG. 4, the interval d between the semiconductor devices can be made wider. As a result, there is an advantage that the underfill 31 (see FIG. 4) can be filled in the gap between the semiconductor devices without generating voids.

  A semiconductor integrated circuit device that is highly integrated and highly functionalized has a large number of pins (an increase in the number of pad electrodes), a narrow pitch of the pad electrode arrangement, and a reduction in the size of the pad electrodes. As a result, the amount of bump solder material supplied to each pad electrode decreases, and the bump height and cap between semiconductor devices to be flip-chip mounted also tend to decrease. In such a case, the present invention that can increase the bump is effective.

  In the embodiment according to the present invention, Sn-Ag solder is shown as the solder material. However, other than these, Sn-Cu, Sn-Ag-Cu, Sn-Zn, and Pb-Sn solders can also be used. Moreover, although gold was shown as the material of the metal film having higher wettability than UBM against molten solder, Ag or Pt may be used in addition to gold (Au). Further, although a pad electrode mainly composed of aluminum is shown, a pad electrode in which at least the uppermost layer is a gold film (such as a gold plating layer) or a pad electrode in which a TiN film is formed on an aluminum film may be used.

  As described above, the present invention is particularly useful for mounting a semiconductor device, but is also useful for mounting not only a semiconductor device but also other electronic components. Further, the present invention can be applied to general products that are to be joined using a minute protruding member containing solder.

1, 2, 40, 43 Semiconductor substrate 2, 22, 41, 44 Circuit formation layer 3, 23, 42 Pad electrode 3a Wiring 4, 24 Protective insulating film 5, 12, 25 Opening 6, 26 UBM
7, 27 Metal layer 8, 28 Bump 9 Photoresist film 10 Gold film 11 Organic resin film 13 Solder paste 30, 45 Bond bump 31, 46 Underfill

Claims (16)

A pad electrode formed on a semiconductor substrate;
A protective insulating film formed on the semiconductor substrate so as to cover the pad electrode;
An opening provided in the protective insulating film on the pad electrode, exposing the surface of the pad electrode from the protective insulating film;
An under barrier metal formed so as to cover a region from the surface of the pad electrode exposed in the opening to the protective insulating film around the opening;
A semiconductor device comprising: a bump provided on the under barrier metal and having a bottom surface smaller than the area of the under barrier metal and made of solder.   The under barrier metal has a thickness greater than that of the protective insulating film, and the surface from the pad electrode exposed in the opening to the protective insulating film around the opening is flat. The semiconductor device according to claim 1.   3. The semiconductor device according to claim 1, wherein a bottom surface of the bump is located in a region included in the opening on the under barrier metal.   A metal layer including an element of a metal material having a wettability with respect to the solder larger than that of the under barrier metal and a component element of the solder is formed between the under barrier metal and the bump. Item 4. The semiconductor device according to any one of Items 1 to 3.   The semiconductor device according to claim 4, wherein the metal layer is located in a region included in the opening on the under barrier metal.   The semiconductor device according to claim 5, wherein the metal layer has the same area as the bottom surface of the bump and is in contact with the entire surface.   7. The semiconductor according to claim 4, wherein the element of the metal material whose wettability to the solder is larger than that of the under barrier metal is at least one of Au, Ag, and Pd. apparatus.   The semiconductor device according to claim 7, wherein a component element of the solder is Sn.   9. The semiconductor device according to claim 7, wherein the under barrier metal is made of an alloy of Ni and P. A pad electrode formed on a semiconductor substrate;
A protective insulating film formed on the semiconductor substrate so as to cover the pad electrode;
An opening provided in the protective insulating film on the pad electrode, exposing the surface of the pad electrode from the protective insulating film;
It is formed so as to cover a region from the surface of the pad electrode exposed in the opening to the protective insulating film around the opening, and the film thickness is larger than the film thickness of the protective insulating film, An under barrier metal having a flat surface from above the pad electrode exposed in the opening to the protective insulating film around the opening;
And a bump made of solder provided on the under barrier metal.   The semiconductor device according to claim 10, wherein the film thickness of the under barrier metal is 2 to 6 times the film thickness of the protective insulating film.   The first semiconductor device and the second semiconductor device having the configuration according to claim 1 or 2 are joined by bumps respectively included in the first semiconductor device and the second semiconductor device. Semiconductor device. Forming a pad electrode on a semiconductor substrate;
Forming a protective insulating film on the semiconductor substrate so as to cover the pad electrode;
Forming an opening exposing the surface of the pad electrode in the protective insulating film on the pad electrode;
Forming an under barrier metal so as to cover a region from the surface of the pad electrode exposed in the opening to the protective insulating film around the opening;
Forming a metal film having an area smaller than the area of the under barrier metal on the under barrier metal;
Supplying a solder material onto the metal film;
Melting the solder material and forming bumps made of solder on the metal film,
The method of manufacturing a semiconductor device, wherein the metal film is made of an element of a metal material having wettability with respect to the solder larger than that of the under barrier metal.   14. The method of manufacturing a semiconductor device according to claim 13, wherein the element of the metal material having wettability with respect to the solder is larger than that of the under barrier metal is at least one of Au, Ag, and Pd.   15. The method of manufacturing a semiconductor device according to claim 13, wherein the under barrier metal is made of an alloy of Ni and P. Forming a pad electrode on a semiconductor substrate;
Forming a protective insulating film on the semiconductor substrate so as to cover the pad electrode;
Forming an opening exposing the surface of the pad electrode in the protective insulating film on the pad electrode;
Using a plating method, covering the region from the surface of the pad electrode exposed in the opening to the protective insulating film around the opening, the film thickness is larger than the film thickness of the protective insulating film, Forming an under barrier metal having a flat surface from above the pad electrode exposed in the opening to the protective insulating film around the opening;
Supplying a solder material on the under barrier metal;
Melting the solder material, and forming bumps made of solder on the under-barrier metal.

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