CN117438407A - Flip-chip bonding structure convenient to weld and preparation method thereof - Google Patents

Flip-chip bonding structure convenient to weld and preparation method thereof Download PDF

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Publication number
CN117438407A
CN117438407A CN202311437849.0A CN202311437849A CN117438407A CN 117438407 A CN117438407 A CN 117438407A CN 202311437849 A CN202311437849 A CN 202311437849A CN 117438407 A CN117438407 A CN 117438407A
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China
Prior art keywords
bump
layer
substrate
diffusion barrier
metal
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Inventor
王鹏凯
位强
杨欢
马晓建
刘卫东
王家琛
苏亚兰
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Huatian Technology Xian Co Ltd
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Huatian Technology Xian Co Ltd
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Priority to CN202311437849.0A priority Critical patent/CN117438407A/en
Publication of CN117438407A publication Critical patent/CN117438407A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/16013—Structure relative to the bonding area, e.g. bond pad the bump connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16153—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/16155—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. being an insulating substrate with or without metallisation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The invention relates to the technical field of semiconductor packaging, in particular to a flip-chip bonding structure convenient to weld and a preparation method thereof. According to the invention, the metal bump structure is arranged, so that the contact area of the metal bump can be increased, the solder of the metal bump can be increased, the insufficient tin amount can be relieved, and the adhesion can be enhanced under the condition that the height of the metal bump is kept unchanged.

Description

Flip-chip bonding structure convenient to weld and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a flip bonding structure convenient for welding and a preparation method thereof.
Background
In conventional IC chips, the chip is electrically connected to a substrate, such as BGA, LGA, etc., by wire bonding. But limited by the wire bonding structure, the wire bonding distance is long, the transmission rate is slow, the loss is large, the requirement of more I/O quantity is difficult to meet, and the wire bonding structure cannot be applied to some high-end field products such as a CPU, a memory chip and the like. In the semiconductor packaging industry, flip Chip technology has therefore grown, which is different from conventional wire bonding technology in that chips are connected to a substrate by metal bumps with their front surfaces facing downward, and is commonly referred to as Flip Chip (FC) because of the different front surfaces as compared to chips in conventional wire bonding. The flip chip technology has excellent electrical property and thermal property, greatly improves the I/O number of the product, has short connection distance and remarkably improves the signal transmission rate; in addition, compared with the wire bonding technology, the flip chip technology can be completed in one working section, so that the working procedure is simplified and the production efficiency is improved.
The flip chip is composed of a wafer, a bonding pad, a passivation layer, a dielectric layer and a metal bump structure, wherein the metal bump structure is composed of a bump bottom metal layer, a bump column, a diffusion barrier layer and solder, the material commonly applied to the solder is tin or tin silver, and the solder is connected to the metal layer bonding pad of the substrate by using a reflow soldering technology to complete the preparation of the flip bonding structure. Because of the characteristics of the metal bump structure, the top solder is generally thinner, and the problem that the tin amount is insufficient, the insufficient cold joint or adhesion force and the like can be caused, so that the mechanical property and the reliability of the product are greatly influenced. In addition, in the reflow soldering process, the fluidity of the melted solder is enhanced, so that the solder climbing height is possibly too high, or the solder overflows to the area outside the window of the solder mask layer of the substrate, thereby affecting the product performance and generating the problem of solder bridging. Therefore, new techniques are needed to alleviate the problems of insufficient tin and solder bridging.
Disclosure of Invention
Aiming at the problems of insufficient tin amount and solder bridging in the bump welding process in the prior art, the invention provides a flip-chip bonding structure convenient for welding and a preparation method thereof.
The invention is realized by the following technical scheme:
the flip chip bonding structure comprises a substrate part and a chip part, wherein the substrate part comprises a substrate metal layer, a substrate bonding pad and a substrate solder mask layer, the substrate bonding pad is arranged on the substrate metal layer, the substrate bonding pad is a concave structure metal bonding pad with a concave upper surface, the substrate solder mask layer covers the substrate bonding pad, and bump matching holes are formed in the substrate solder mask layer; the substrate bonding pad is matched with the metal bump structure;
the chip part comprises a wafer, a bonding pad, a passivation layer, a dielectric layer and a metal bump structure, wherein the bonding pad is arranged on the wafer, the passivation layer is arranged on the wafer and is positioned at the outer side of the bonding pad, and the dielectric layer is arranged on the passivation layer;
the metal bump structure comprises a bump column, a diffusion barrier layer, a first solder ball, a second solder ball and a bump bottom metal layer, wherein the first solder ball and the second solder ball are connected with the top of the diffusion barrier layer, the bottom of the diffusion barrier layer is connected with the top of the bump column, the bottom of the bump column is connected with the bump bottom metal layer, the bump bottom metal layer is connected with a bonding pad, and the bump column is connected with the bonding pad of the substrate through the first solder ball and the second solder ball.
Preferably, the bump pillar is a stepped pillar structure.
Preferably, the bump column comprises a bottom bump, a middle bump and a top bump which are sequentially formed from bottom to top, the bottom bump is arranged on the metal layer at the bottom of the bump, the top bump is connected with the bottom of the diffusion barrier layer, and the top bump is of a columnar structure with stepped cross section area decreasing.
Preferably, the cross-sectional area of the middle bump is greater than the cross-sectional area of the bottom bump, and the cross-sectional area of the bottom step of the top bump is less than the cross-sectional area of the bottom bump.
Preferably, the bump bottom metal layer covers the concave opening formed by the bonding pad, the passivation layer and the dielectric layer, and the size of the bottom bump is the same as that of the concave opening.
Preferably, the bump bottom metal layer comprises an adhesion layer, a barrier layer and a wetting layer which are sequentially arranged from bottom to top, the adhesion layer is arranged on the bonding pad, and the bottom of the bottom bump is connected with the top of the wetting layer.
Preferably, the diffusion barrier layer comprises a first diffusion barrier layer and a second diffusion barrier layer, the bottom of the first diffusion barrier layer is arranged at the top of the top salient point, the lower surface of the second diffusion barrier layer is connected with the upper surface of the middle salient point, and the side surface of the second diffusion barrier layer is connected with the side surface of the top salient point.
Preferably, the melting point of the diffusion barrier layer and the melting point of the bump pillar are both higher than the melting point of the solder used for the first solder ball and the second solder ball.
Preferably, the substrate pad includes a substrate pad bump and a substrate pad under layer, the substrate solder mask layer covering a portion of an upper surface of the substrate pad bump.
A preparation method of a flip bonding structure convenient for welding comprises the following steps:
step 1, manufacturing a bump bottom metal layer on a bonding pad;
step 2, preparing bump columns on the metal layer at the bottom of the bump in a deposition mode;
step 3, preparing a diffusion barrier layer, a first solder ball and a second solder ball on the bump column;
and 4, connecting the metal bump structure with the substrate part, namely completely attaching the metal bump structure to the substrate bonding pad, completely conforming the outline of the metal bump structure and the substrate bonding pad after a reflow soldering process, and filling a gap between the metal bump structure and the substrate bonding pad by forming the solder layer after the reflow soldering process, thereby completing the preparation of the flip-chip bonding structure.
Compared with the prior art, the invention has the following beneficial effects:
the flip bonding structure convenient for welding can increase the solder of the metal bump under the condition of maintaining the height of the metal bump unchanged, relieve the insufficient tin amount and strengthen the bonding force. Meanwhile, the metal bonding pad with the concave structure on the upper surface is arranged to avoid solder overflow bridging during flip-chip bonding, and the tin climbing height is controlled, so that the mechanical property and reliability of the product are improved. Compared with the traditional metal bump structure, the structure has more solder content on the premise of keeping the height unchanged, has larger contact area between the solder and the substrate, and can provide better reflow soldering reliability and mechanical property; in addition, the metal pad concave structure can lead the melted solder to flow towards the concave part during reflow soldering, and avoid the adverse effects of solder bridging and the like caused by overflow to the area outside the window of the metal layer; meanwhile, the second bump pillar structure can control the tin climbing height, and the overlarge or undersize area of the bump pillar side surface covered by solder is avoided, so that the performance of the metal bump structure is improved.
Further, the bump bottom metal layer comprises an adhesion layer for providing good adhesion between the bump and the pad, a barrier layer for preventing inter-diffusion of bump material and pad material to form intermetallic compound, and a wetting layer for providing good wetting with the bump and serving as seed layer for preparing bump column
Further, the diffusion barrier layer comprises a first diffusion barrier layer and a second diffusion barrier layer, is used for preventing the solder and the bump column parts from being mutually diffused to generate bad intermetallic compounds, preventing the mechanical property from weakening, and simultaneously providing good wettability between the bump column and the solder, facilitating the preparation of solder balls and enhancing the reliability.
After the reflow soldering process, the metal bump structure is completely attached to the substrate bonding pad, the outline of the metal bump structure and the outline of the substrate bonding pad are completely consistent, and the gap between the metal bump structure and the substrate bonding pad are filled by a solder layer formed after the reflow soldering of a solder ball, so that the connection effect is achieved.
Drawings
FIG. 1 is a schematic diagram of a conventional bump structure;
FIG. 2 is a schematic view of the structure of a substrate portion of the present invention;
FIG. 3 is a top plan view of the structure of a substrate portion of the present invention;
FIG. 4 is a flow chart of a process for fabricating a flip-chip structure for facilitating soldering in accordance with the present invention;
FIG. 5 is a schematic illustration of a bump bottom metal layer in the fabrication of a chip portion in accordance with the present invention;
FIG. 6 is a schematic diagram of a bottom bump in the fabrication of a chip portion according to the present invention;
FIG. 7 is a schematic illustration of an intermediate bump in the fabrication of a chip portion in accordance with the present invention;
FIG. 8 is a schematic diagram of a top bump in the fabrication of a chip portion in accordance with the present invention;
FIG. 9 is a schematic illustration of a first diffusion barrier and a first solder paste layer in the fabrication of a chip portion according to the present invention;
FIG. 10 is a schematic illustration of a second diffusion barrier and a second solder paste layer in the fabrication of a chip portion in accordance with the present invention;
FIG. 11 is a schematic view of a first solder ball and a second solder ball in the fabrication of a chip portion in accordance with the present invention;
fig. 12 is a schematic diagram of the final structure.
In the figure, 1, a chip part with a conventional flip-chip bonding structure; 10. a conventional wafer; 11. a conventional bonding pad; 12. a conventional passivation layer; 13. a conventional dielectric layer; 14. a conventional bump bottom metal layer; 15. conventional bump studs; 16. a conventional diffusion barrier; 17. conventional solders; 2. a chip portion; 20. a wafer; 21. a bonding pad; 22. a passivation layer; 23. a dielectric layer; 3. a metal bump structure; 30. a bump bottom metal layer; 31. bump columns; 311. a bottom bump; 312. a middle bump; 313. top bumps; 32. a diffusion barrier layer; 321. a first diffusion barrier layer; 322. a second diffusion barrier layer; 401. a first solder ball; 402. a second solder ball; 411. a first solder paste layer; 412. a second solder paste layer; 42. a solder layer; 501. a first photoresist layer; 502. a second photoresist layer; 503. a third photoresist layer; 6. a substrate portion; 60. a substrate metal layer; 61. a substrate pad; 611. a substrate pad bottom layer; 612. a substrate pad bump; 62. and (5) a substrate solder mask layer.
Detailed Description
The invention will now be described in further detail with reference to specific examples, which are intended to illustrate, but not to limit, the invention.
The conventional flip-chip bonding structure chip part 1 in the flip-chip technology is composed of a conventional wafer 10, a conventional bonding pad 11, a conventional passivation layer 12, a conventional dielectric layer 13, a conventional bump bottom metal layer 14, a conventional bump post 15, a conventional diffusion barrier layer 16 and a conventional solder 17, wherein the material of the solder is tin or tin silver, and the solder is connected to the metal layer bonding pad of the substrate by using a reflow soldering technology to complete the preparation of the flip-chip bonding structure.
The invention discloses a flip-chip bonding structure convenient for welding, which comprises a substrate part 6 and a chip part 2, wherein the substrate part 6 comprises a substrate metal layer 60, a substrate bonding pad 61 and a substrate solder mask layer 62, referring to fig. 2 and 3, the substrate bonding pad 61 is arranged on the substrate metal layer 60, the substrate bonding pad 61 is the substrate bonding pad 61 with a concave structure on the upper surface, the substrate bonding pad 61 comprises a substrate bonding pad bottom layer 611 and a substrate bonding pad bulge 612, and the substrate solder mask layer 62 covers part of the upper surface of the substrate bonding pad bottom layer 611. The substrate pad underlayer 611 and the substrate pad bump 612 have no distinct interface.
The substrate solder mask layer 62 is provided with bump mating holes, and the substrate pads 61 are mated with the metal bump structures 3. The material of the substrate metal layer 60 is a substrate internal metal circuit layer made of copper, and the material of the substrate solder resist layer 62 is an organic material such as an acrylic oligomer.
The chip part 2 comprises a wafer 20, a bonding pad 21 and a metal bump structure 3, and further comprises a passivation layer 22 and a dielectric layer 23 for protecting the chip, wherein the bonding pad 21 is arranged on the wafer 20, the passivation layer 22 is arranged on the wafer 20 and is positioned on the outer side of the bonding pad 21, and the dielectric layer 23 is arranged on the passivation layer 22.
The metal bump structure 3 includes a bump post 31, a diffusion barrier layer 32, a first solder ball 401, a second solder ball 402, and a bump bottom metal layer 30, the first solder ball 401, the second solder ball 402 are connected to the top of the diffusion barrier layer 32, the bottom of the diffusion barrier layer 32 is connected to the top of the bump post 31, the bottom of the bump post 31 is connected to the bump bottom metal layer 30, the bump bottom metal layer 30 is connected to the pad 21, and the bump post 31 is connected to the substrate pad 61 through the first solder ball 401 and the second solder ball 402.
Wherein the bump stud 31 is a stepped stud structure with no distinct interface between the parts. The bump column 31 includes a bottom bump 311, a middle bump 312, and a top bump 313 formed sequentially from bottom to top, no distinct interface is provided between the bottom bump 311, the middle bump 312, and the top bump 313, the bottom bump 311 is disposed on the bump bottom metal layer 30, the top bump 313 is connected to the bottom of the diffusion barrier layer 32, and the top bump 313 has a columnar structure with a stepped shape and a decreasing cross-sectional area. Wherein the cross-sectional area of the middle bump 312 is greater than the cross-sectional area of the bottom bump 311 and the cross-sectional area of the bottom step of the top bump 313 is less than the cross-sectional area of the bottom bump 311.
The bump stud 31 may have a circular, oval or rectangular cross section in a direction parallel to the chip. Under the condition that the bump column 31 has a certain height, the number of the top bumps 313 can be not less than one, and the cross-sectional area is sequentially reduced from bottom to top; correspondingly, the number of solder balls is increased to match each component of the bump stud 31 according to the different numbers of the bump stud 31 components.
The bump bottom metal layer 30 comprises an adhesion layer, a barrier layer and a wetting layer, and the bottom of the bottom bump 311 is connected to the wetting layer. The bump bottom metal layer 30 covers the concave opening formed by the pad 21, the passivation layer 22 and the dielectric layer 23, and the bottom bump 311 has the same size as the concave opening.
The diffusion barrier layer 32 includes a first diffusion barrier layer 321 and a second diffusion barrier layer 322, wherein the bottom of the first diffusion barrier layer 321 is disposed at the top of the top bump 313, the lower surface of the second diffusion barrier layer 322 is connected to the upper surface of the middle bump, and the side of the second diffusion barrier layer 322 is connected to the side of the top bump 313. The melting point of the diffusion barrier layer 32 and the melting point of the bump post 31 are both higher than the melting point of the solder paste layer solder used for the first solder ball 401 and the second solder ball 402, and the heating temperature is higher than the melting point of the solder paste layer and lower than the melting point of the diffusion barrier layer 32 and the melting point of the bump post 31 when the solder balls are formed by reflow soldering.
The chip part 2 has finished processing a wafer 20, a bonding pad 21, a passivation layer 22 and a dielectric layer 23, wherein the bonding pad 21 is conductive metal on the top of the chip, the passivation layer 22 is silicon oxide, silicon nitride and other materials, and the dielectric layer 23 is Polyimide (PI), polybenzoxazole (PBO) and other organic materials. Wafer 20 is a semiconductor material such as silicon, silicon carbide, gallium nitride, gallium arsenide, or the like. The bump column 31 is a metal bump material such as copper. The diffusion barrier layer 32 is a metal material such as nickel. The solder is a metal material such as tin and tin-silver. The bump bottom metal layer 30 is a material such as titanium-copper, nickel-gold, titanium-tungsten-copper, or the like.
During preparation, the bump bottom metal layer 30 is manufactured on the bonding pad 21 by utilizing processes such as chemical plating, electroplating, sputtering and the like; manufacturing bump columns 31 above the bump bottom metal layer 30 by electroplating, electroless plating and other processes; a diffusion barrier layer 32 is manufactured above the bump columns 31 by electroplating, electroless plating and other processes; a solder paste layer is formed over the diffusion barrier 32 by printing, electroplating, electroless plating, etc., and the solder paste layer is formed into a solder ball by a reflow process.
In the substrate portion 6, there is no significant interface between the substrate pad 61 underlayer of the substrate pad 61 and the substrate pad 61 bump.
The surface of the substrate pad 61 is subjected to surface treatment to form a surface treatment coating, wherein the surface treatment method comprises the processes of electroless nickel plating and gold deposition (ENIG), electroless nickel electroless palladium plating and gold immersion (ENEPIG) and the like, and is used for protecting the substrate pad 61. When the substrate pads 61 are at a constant height, the number of bumps of the substrate pads 61 is equal to the number of components of the bump columns 31, and no distinct interface is provided between the bumps of the substrate pads 61. After the reflow soldering process, the metal bump structure 3 is completely attached to the substrate pad 61, the outline of the metal bump structure and the outline of the metal bump structure are completely consistent, and a gap between the metal bump structure and the substrate pad is filled by the solder layer 42 formed after the reflow soldering, so that the metal bump structure and the substrate pad have a connecting effect.
Taking the bump column 31 as a three-layer step and the top bump 313 as a one-layer step as an example, the bump column 31 includes a bottom bump 311, a middle bump 312 and a top bump 313, and referring to fig. 4, the method includes the following steps:
step 1, manufacturing a bump bottom metal layer 30 on a bonding pad 21; where the chip part 2 has completed the preparation of the pad 21, passivation layer 22 and dielectric layer 23, the bump bottom metal layer 30 is the part covering the passivation layer 22, dielectric layer 23 and the top of the pad 21 where the passivation layer 22, dielectric layer 23 is removed, as shown in fig. 5. The bottom bump metal layer 30 is mainly used for blocking the diffusion between subsequent metals and avoiding the formation of intermetallic compounds, and the main materials are titanium-copper, nickel-gold and titanium-tungsten-copper.
Step 2, preparing bump columns 31 on the bump bottom metal layer 30 in a deposition mode; the preparation of the bottom bump 311, the middle bump 312 and the top bump 313 of the bump column 31 is sequentially performed according to the structure of the bump column 31, and specifically comprises the following steps:
step 201, a first photoresist layer 501 is formed on the dielectric layer 23, but the first photoresist layer 501 is not formed above the bump bottom metal layer 30, and a first opening is formed on the first photoresist layer 501 after exposure, development and etching, wherein the first opening is located above the bump bottom metal layer 30; then, bottom convex points 311 are manufactured in a deposition mode, the bottoms of the bottom convex points 311 are connected with the convex point bottom metal layers 30, the side surfaces of the bottom convex points 311 are provided with first photoresist layers 501, and the upper surfaces of the bottom convex points 311 and the upper surfaces of the first photoresist layers 501 are positioned on the same horizontal plane, as shown in fig. 6;
step 202: a second photoresist layer 502 is manufactured on the first photoresist layer 501, and a second opening is formed on the second photoresist layer 502 after exposure, development and etching, wherein the second opening is positioned above the bottom bump 311, and the size of the second opening is larger than the upper surface of the bottom bump 311; then, manufacturing a middle bump 312 in a deposition mode, wherein the bottom of the middle bump 312 is connected with the bottom bump 311, the side surface of the middle bump 312 is provided with a second photoresist layer 502, and the distance from the upper surface of the bottom bump 311 to the top surface of the middle bump 312 is smaller than the distance from the upper surface of the bottom bump 311 to the upper surface of the second photoresist layer 502, as shown in fig. 7;
step 203: a third photoresist layer 503 is manufactured on the middle bump 312, a third opening is formed on the third photoresist layer 503 after exposure, development and etching, the third opening is positioned above the middle bump 312, the size of the third opening is smaller than the upper surface of the middle bump 312, and the size of the third opening is smaller than the upper surface of the bottom bump 311; and then, manufacturing a top bump 313 by a deposition mode, wherein the bottom of the top bump 313 is connected with the middle bump 312, the side surface of the top bump 313 is provided with a third photoresist layer 503, the distance from the upper surface of the middle bump 312 to the upper surface of the top bump 313 is smaller than the distance from the upper surface of the middle bump 312 to the upper surface of the third photoetching layer, and the upper surface of the third photoetching layer and the upper surface of the second photoetching layer are on the same horizontal plane.
Wherein the bottom bump 311, the middle bump 312 and the top bump 313 are made of the same material, no obvious interface exists between the bottom bump 311, the middle bump 312 and the top bump 313, and the three parts form the bump column 31, as shown in fig. 8.
When the number of steps of the top bump 313 is greater than 1, repeating step 203 on the top bump 313 to obtain a desired stepped top bump.
Step 3, preparing a diffusion barrier layer 32, a first solder ball 401 and a second solder ball 402 on the bump pillar 31; the corresponding structure is prepared according to the structure of the diffusion barrier layer 32, the first solder ball 401 and the second solder ball 402, and the diffusion barrier layer 32 comprises a first diffusion barrier layer 321 and a second diffusion barrier layer 322, specifically as follows:
step 301: a first diffusion barrier layer 321 and a first solder paste layer 411 are manufactured on the top bump 313, the first diffusion barrier layer 321 is located above the top bump 313, the first solder paste layer 411 is located above the first diffusion barrier layer 321, and the side surfaces of the first diffusion barrier layer 321 and the first solder paste layer 411 are the third photoresist layer 503; forming a first diffusion barrier layer 321 on the upper surface of the top bump 313 by deposition, and printing a first solder paste layer 411 on the upper surface of the first diffusion barrier layer 321 by solder paste printing using the third photoresist layer 503 as a mask, as shown in fig. 9;
step 302: removing the third photoresist layer 503 by ultrasonic-assisted acetone soaking; then, a second diffusion barrier layer 322 and a second solder paste layer 412 are manufactured on the middle bump 312, the lower surface of the second diffusion barrier layer 322 is connected with the upper surface of the middle bump 312, the side surface of the second diffusion barrier layer 322 is connected with the side surface of the top bump 313, and the second solder paste layer 412 is positioned above the second diffusion barrier layer 322; forming a second diffusion barrier layer 322 on the upper surface of the intermediate bump 312 by deposition, printing a second solder paste layer 412 on the upper surface of the second diffusion barrier layer 322 by solder paste printing using the second photoresist layer 502 as a mask
Wherein the first diffusion barrier layer 321 and the second diffusion barrier layer 322 are made of the same material, no obvious interface exists between the first diffusion barrier layer 321 and the second diffusion barrier layer 322, and the two parts form the diffusion barrier layer 32; the same material is used for the first solder paste layer 411 and the second solder paste layer 412, and the upper surface of the second solder paste layer 412 is lower than the upper surface of the first solder paste layer 411, as shown in fig. 10.
Step 303: the first photoresist layer 501 and the second photoresist layer 502 are removed by using an ultrasonic-assisted acetone soaking mode, and can be removed by using an ultrasonic-assisted acetone soaking mode; the first solder paste layer 411 is made into the first solder ball 401 and the second solder paste layer 412 is made into the second solder ball 402 by reflow soldering at a temperature lower than the melting points of the bump post 31 and the diffusion barrier layer 32 and higher than the melting points of the first solder paste layer 411 and the second solder paste layer 412, as shown in fig. 11.
And 4, connecting the metal bump structure 3 with the substrate metal layer 60 structure, namely completely attaching the metal bump structure 3 to the substrate bonding pad 61, completely conforming the outline of the metal bump structure 3 and the substrate bonding pad 61 after a reflow soldering process, and filling a gap between the metal bump structure 3 and the substrate bonding pad by forming the solder layer 42 after the reflow soldering process, thereby completing the preparation of the flip-chip bonding structure. The specific operation is as follows: the first solder ball 401 and the second solder ball 402 are manufactured into the solder layer 42 by a reflow soldering method, after the metal bump structure 3 is turned over, the upper surface of the solder layer 42 is connected with the upper surface of the substrate pad 61, the size of the upper surface of the bottom layer of the substrate pad 61 is larger than the size of the upper surface of the top bump 313, the size of the upper surface of the bottom layer of the substrate pad 61 is smaller than the size of the cross section of the middle bump 312 along the wafer direction, and the size of the opening of the substrate solder mask layer 62 is equal to the size of the upper surface of the cross section of the middle bump 312 along the wafer direction, as shown in fig. 12.
The foregoing description of the preferred embodiment of the present invention is not intended to limit the technical solution of the present invention in any way, and it should be understood that the technical solution can be modified and replaced in several ways without departing from the spirit and principle of the present invention, and these modifications and substitutions are also included in the protection scope of the claims.

Claims (10)

1. The flip chip bonding structure is characterized by comprising a substrate part (6) and a chip part (2), wherein the substrate part (6) comprises a substrate metal layer (60), a substrate bonding pad (61) and a substrate solder mask (62), the substrate bonding pad (61) is arranged on the substrate metal layer (60), the substrate bonding pad (61) is a concave structure metal bonding pad (21) with a concave upper surface, the substrate solder mask (62) covers the substrate bonding pad (61), and bump matching holes are formed in the substrate solder mask (62); the substrate bonding pad (61) is matched with the metal bump structure (3);
the chip part (2) comprises a wafer (20), a bonding pad (21), a passivation layer (22), a dielectric layer (23) and a metal bump structure (3), wherein the bonding pad (21) is arranged on the wafer (20), the passivation layer (22) is arranged on the wafer (20) and is positioned on the outer side of the bonding pad (21), and the dielectric layer (23) is arranged on the passivation layer (22);
the metal bump structure (3) comprises a bump column (31), a diffusion barrier layer (32), a first solder ball (401), a second solder ball (402) and a bump bottom metal layer (30), wherein the first solder ball (401), the second solder ball (402) are connected with the top of the diffusion barrier layer (32), the bottom of the diffusion barrier layer (32) is connected with the top of the bump column (31), the bottom of the bump column (31) is connected with the bump bottom metal layer (30), the bump bottom metal layer (30) is connected with a bonding pad (21), and the bump column (31) is connected with a substrate bonding pad (61) through the solder layer (42) formed by reflow soldering of the first solder ball (401) and the second solder ball (402).
2. The flip-chip bonding structure for facilitating soldering according to claim 1, wherein the bump stud (31) is a stepped pillar structure.
3. The flip-chip bonding structure for facilitating soldering according to claim 2, wherein the bump stud (31) comprises a bottom bump (311), a middle bump (312) and a top bump (313) which are formed in this order from bottom to top, the bottom bump (311) is disposed on the bump bottom metal layer (30), the top bump (313) is connected to the bottom of the diffusion barrier layer (32), and the top bump (313) is a columnar structure having a stepped shape and an upwardly decreasing cross-sectional area.
4. A flip-chip bonding structure for facilitating soldering according to claim 3, wherein the cross-sectional area of the intermediate bump (312) is larger than the cross-sectional area of the bottom bump (311), and the cross-sectional area of the bottom step of the top bump (313) is smaller than the cross-sectional area of the bottom bump (311).
5. A flip-chip bonding structure for facilitating soldering according to claim 3, wherein the bump bottom metal layer (30) covers the concave opening formed by the pad (21), the passivation layer (22) and the dielectric layer (23), and the bottom bump (311) has the same size as the concave opening.
6. A flip-chip bonding structure facilitating soldering according to claim 3, wherein the bump bottom metal layer (30) comprises an adhesion layer, a barrier layer and a wetting layer which are sequentially arranged from bottom to top, the adhesion layer is arranged on the bonding pad (21), and the bottom of the bottom bump (311) is connected with the top of the wetting layer.
7. A flip-chip bonding structure facilitating soldering according to claim 3, wherein the diffusion barrier layer (32) comprises a first diffusion barrier layer (321) and a second diffusion barrier layer (322), the bottom of the first diffusion barrier layer (321) is arranged on top of the top bump (313), the lower surface of the second diffusion barrier layer (322) is connected with the upper surface of the intermediate bump, and the side of the second diffusion barrier layer (322) is connected with the side of the top bump (313).
8. The flip-chip bonding structure for facilitating soldering according to claim 1, wherein the melting point of the diffusion barrier layer (32) and the melting point of the bump pillar (31) are higher than the melting point of the solder used for the first solder ball (401) and the second solder ball (402).
9. The flip-chip bonding structure for facilitating soldering according to claim 1, wherein the substrate pad (61) comprises a substrate pad bump (611) and a substrate pad under layer (612), and the substrate solder resist layer (62) covers a part of an upper surface of the substrate pad bump (611).
10. A method of preparing a flip-chip bonded structure for soldering according to any one of claims 1 to 9, comprising the steps of:
step 1, manufacturing a bump bottom metal layer (30) on a bonding pad (21);
step 2, preparing bump columns (31) on the bump bottom metal layer (30) in a deposition mode;
step 3, preparing a diffusion barrier layer (32), a first solder ball (401) and a second solder ball (402) on the bump column (31);
and 4, connecting the metal bump structure (3) with the substrate part (6), namely completely attaching the metal bump structure (3) to the substrate bonding pad (61), completely conforming the outline of the metal bump structure (3) and the substrate bonding pad (61) after a reflow soldering process, and filling a gap between the metal bump structure and the substrate bonding pad by forming the solder layer (42) after the reflow soldering process to finish the preparation of the flip-chip bonding structure.
CN202311437849.0A 2023-10-31 2023-10-31 Flip-chip bonding structure convenient to weld and preparation method thereof Pending CN117438407A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311437849.0A CN117438407A (en) 2023-10-31 2023-10-31 Flip-chip bonding structure convenient to weld and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311437849.0A CN117438407A (en) 2023-10-31 2023-10-31 Flip-chip bonding structure convenient to weld and preparation method thereof

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CN117438407A true CN117438407A (en) 2024-01-23

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