TWI476878B - 包含有具優選方向成長之CuSn晶粒之電性連接結構及其製備方法 - Google Patents
包含有具優選方向成長之CuSn晶粒之電性連接結構及其製備方法 Download PDFInfo
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Description
本發明係關於一種電性連接結構及其製備方法,尤指一種包含有具方向性成長之Cu6
Sn5
晶粒之電性連接結構及其製備方法。
銅金屬因具備高導電性與散熱性,同時又與銲錫的濕潤性良好,因此廣泛地使用於金屬連接裝置中(例如,金屬互連接線(metal interconnect)、凸塊下金屬(under bump metal,UBM)、銅柱凸塊(Cu pillar)、或直通矽晶穿孔(through silicon via,TSV))。
例如,應用於封裝結構之凸塊下金屬中,銅金屬經常藉由銲錫與其他電子元件電性連接。其電性連接加工過程中需要進行高溫迴焊處理,因而銅金屬與銲錫反應產生介金屬化合物(intermetallic compounds,IMCs)。
如圖1所示,例如目前三維積體電路(3D-IC)結構技術中,包含有二個晶片11,12,晶片11,12分別具有電性墊13,14(其組成為一般銅金屬),電性墊13,14以銲錫17連接。經迴焊後,電性墊13,14中之銅原子會擴散至銲錫17中並與銲錫17中之錫反應,使部分銲錫17轉換成為介金屬化合物層171,172(分別形成於銲錫17與電性墊13,14之間)。而此介金屬化合物層171,172會造成可靠度降低的問題。
而目前習知技術中,對於銲錫接點品質的改善,多以減少介金屬化合物層的厚度為手段。例如,增加擴散阻障層以防止介金屬化合物層的生長(如美國專利公告第US 6,867,503 B2號所示)。而此則增加了生產成本,且更使得電子元件有可靠性的風險存在。
因此,本領域亟需一種新的電性連接結構,使可改善銲錫接點品質,並降低生產成本,達到更符合經濟的效益。
為此,本發明提出了一種包含有具優選方向成長之Cu6
Sn5
晶粒之電性連接結構之製備方法,包括步驟:(A)提供一第一基板;(B)於該第一基板之部分表面形成一第一奈米雙晶銅層;(C)使用一銲料將該第一基板與一第二基板連接,該第二基板具有一第二電性墊,該第二電性墊包括一第二奈米雙晶銅層,且該銲料係配置於該第一奈米雙晶銅層與該第二奈米雙晶銅層之間;以及(D)以200℃至300℃的溫度進行迴焊(reflow)使該銲料至少部分轉換為一介金屬化合物(intermetallic compound,IMC)層,且該介金屬化合物層係包括具優選方向(preferred orientation)成長之複數Cu6
Sn5
晶粒;其中,該第一及第二奈米雙晶銅層之50%以上的體積係分別包括複數個雙晶銅晶粒。
本發明中,迴焊溫度需足夠使銲料可於液態下進行反應生長Cu6
Sn5
晶粒。若溫度低於此範圍,則會生長出較厚的Cu3
Sn層,且Cu3
Sn層的厚度會多於Cu6
Sn5
晶粒高度的一半。甚至存放時間越久,Cu3
Sn層的厚度會漸漸增加,而Cu6
Sn5
晶粒會漸漸消失不見。
但相反的,於本發明之迴焊溫度範圍(200℃至300℃)內進行迴焊,於正常使用時(例如溫度100℃的正常使用狀況下),時間越久,會使Cu3
Sn層的厚度增加相對緩慢,且Cu6
Sn5
晶粒尺寸係漸漸變大。因此,迴焊溫度的控制則變的相當重要。
本發明之電性連接結構之製造方法,可控制Cu6
Sn5
晶粒的生長方向,使該些微凸塊(Cu6
Sn5
晶粒)之性質互相接近(最佳係性質一致),達到各接點電性一致化之效果,使整體電性表現提升。
本發明之電性連接結構之製造方法,透過控制Cu6
Sn5
晶粒的生長方向,解決了在一般銲錫接點中,受到錫晶粒不同晶向的影響,而遭受的早期破壞。應用於三維積體電路封裝(3D-IC packaging)與矽晶片穿孔(TSV)連接之電性接點時,可以確實控制銲錫接點的品質。並且,本發明之電性連接結構之製造方法不僅可控制接點的機械性質、電性、可靠度、以及使用壽命等,更降低了生產成本(此係由於本發明不需使用額外的阻障材料、或是高溫熱處理等步驟),因此具有相當高的經濟價值。
本發明之電性連接結構之製備方法中,較佳地,該複數Cu6
Sn5
晶粒之成長方向係大致上垂直該第一奈米雙晶銅層之一表面。
本發明之電性連接結構之製備方法中,較佳地,50%以上(更佳為70%以上;最佳為90%以上)相鄰之該複數Cu6
Sn5
晶粒方向之夾角係為0至40度(亦即,50%以上任二個相鄰之晶粒其晶粒方向之夾角係為0至40度)。
此外,本發明之電性連接結構之製備方法中,較佳50%以上(更佳為70%以上;最佳為90%以上)之該複數Cu6
Sn5
晶粒之[0001]方向與奈米雙晶銅層之[111]方向之夾角係為0至40度。
本發明之電性連接結構之製備方法中,該步驟(D)中,迴焊之時間較佳為30秒至10分鐘。在此,迴焊之時間越久,Cu6
Sn5
晶粒則成長越大/越高。
本發明之電性連接結構之製備方法中,該步驟(D)中,迴焊之溫度較佳為240℃至280℃,最佳為260℃。
本發明之電性連接結構之製備方法中,該複數Cu6
Sn5
晶粒與該第一奈米雙晶銅層之間較佳可更包括一Cu3
Sn層,且該Cu3
Sn層之厚度與該複數Cu6
Sn5
晶粒中高度最高之晶粒高度比[Cu3
Sn層之厚度]/[複數Cu6
Sn5
晶粒中高度最高之晶粒高度]較佳可為0至0.5(更佳為1x10-4
至0.3)。隨著置放時間越長,Cu3
Sn層之厚度會緩慢增加,因此[Cu3
Sn層之厚度]/[複數Cu6
Sn5
晶粒中高度最高之晶粒高度]較佳大約為0至0.5之間(更佳為1x10-4
至0.3)。
此外,該複數Cu6
Sn5
晶粒所構成之層之厚度較佳為500 nm至10 μm;且該Cu3
Sn層之厚度較佳為1 nm至1000 nm。
本發明之電性連接結構之製備方法中,該複數個雙晶銅晶粒較佳可為柱狀雙晶體(columnar twinned grain)。此外,本發明之電性連接結構之製備方法中,該複數個雙晶銅晶粒較佳彼此間係互相連接,該每一雙晶銅晶粒係由複數個奈米雙晶銅沿著[111]晶軸方向堆疊而成,且相鄰之該雙晶銅晶粒間之堆疊方向(即,排列方向)之夾角係0至20度。
本發明之電性連接結構之製備方法中,該步驟(B)之該第一奈米雙晶銅層之形成方法較佳可選自由:直流電鍍、脈衝電鍍、物理氣相沉積、化學氣相沉積、以及蝕刻銅箔所組成之群組。
本發明之電性連接結構之製備方法中,當該步驟(B)使用電鍍形成該第一奈米雙晶銅層時,電鍍所使用之一電鍍液較佳可包括有:一銅的鹽化物、一酸、以及一氯離子來源。此外,本發明之電性連接結構之製備方法中,該電鍍液較佳可更包括一物質係選自由:明膠(gelatin)、介面活性劑、晶格修整劑、及其混合所組成之群組。並且,該電鍍液中的酸較佳可為硫酸、甲基磺酸、或其混合。
本發明之電性連接結構之製備方法中,該第一基板較佳可包括有一第一電性墊,該第一電性墊較佳可包括該第一奈米雙晶銅層,或是該第一奈米雙晶銅層即為該第一電性墊。
本發明之電性連接結構之製備方法中,該第二基板之第二電性墊較佳可包括有一第二奈米雙晶銅層,或是該第二奈米雙晶銅層即為該第二電性墊。
本發明之電性連接結構之製備方法中,銲料之材質較佳可選自由:共晶型錫/鉛(eutectic Sn/Pb)銲料、錫/銀/銅銲料、錫/銀銲料、以及無鉛銲料所組成之群組。
本發明之電性連接結構之製備方法中,該第一及/或第二奈米雙晶銅層之厚度較佳可為0.1μm-500μm,更佳可為0.1μm-100μm,最佳可為0.1μm-20μm。
本發明另提供一種包含有具優選方向排列之Cu6
Sn5
晶粒之電性連接結構,包括:一第一基板,係具有一第一電性墊,該第一電性墊係包括一第一奈米雙晶銅層;一第二基板,係具有一第二電性墊,該第二電性墊係包括一第二奈米雙晶銅層;以及至少一介金屬化合物(intermetallic compound,IMC)層,係位於該第一與第二奈米雙晶銅層之表面,該介金屬化合物層係配置於該第一基板與該第二基板之間,並電性連接該第一電性墊以及該第二電性墊,且該介金屬化合物層係包括複數具優選方向排列之Cu6
Sn5
晶粒;其中,該第一及第二奈米雙晶銅層之50%以上的體積係分別包括複數個雙晶銅晶粒。
本發明之電性連接結構透過控制Cu6
Sn5
晶粒的生長方向(使Cu6
Sn5
晶粒具優選方向排列),解決了一般銲錫接點中,受到錫晶粒不同晶向的影響,而遭受的早期破壞。應用於三維積體電路封裝(3D-IC packaging)與矽晶片穿孔(TSV)連接之電性接點時,可以確實控制銲錫接點的品質。詳細地說,本發明之電性連接結構中可控制Cu6
Sn5
晶粒的生長方向,使該些微凸塊(Cu6
Sn5
晶粒)之性質互相接近(最佳係性質一致),降低電性連接結構之電性與機械性質歧異度,使整體電性及可靠度表現提升。
並且,本發明之電性連接結構之製造方法不僅可控制接點的機械性質、電性、可靠度、以及使用壽命等,更降低了生產成本(此係由於本發明不需使用額外的阻障材料、或是高溫熱處理等步驟),因此具有相當高的經濟價值。
本發明之電性連接結構中,較佳地,50%以上(更佳為70%以上;最佳為90%以上)相鄰之該複數Cu6
Sn5
晶粒方向之夾角係為0至40度(亦即,50%以上任二個相鄰之晶粒其晶粒方向之夾角係為0至40度)。
此外,本發明之電性連接結構中,較佳50%以上(更佳為70%以上;最佳為90%以上)之該複數Cu6
Sn5
晶粒之[0001]方向與奈米雙晶銅層之[111]方向之夾角係為0至40度。本發明之電性連接結構中,該複數Cu6
Sn5
晶粒與該第一奈米雙晶銅層之間更包括一Cu3
Sn層,且該Cu3
Sn層之厚度與該複數Cu6
Sn5
晶粒中高度最高之晶粒高度比[Cu3
Sn層之厚度]/[複數Cu6
Sn5
晶粒中高度最高之晶粒高度]為0至0.5(更佳為1x10-4
至0.3)。
此外,該複數Cu6
Sn5
晶粒所構成之層之厚度較佳為500 nm至10 μm;且該Cu3
Sn層之厚度較佳為1 nm至1000 nm。
本發明之電性連接結構中,該複數個雙晶銅晶粒較佳係彼此間係互相連接,該每一雙晶銅晶粒係由複數個奈米雙晶銅沿著[111]晶軸方向堆疊而成,且相鄰之該雙晶銅晶粒間之堆疊方向之夾角係0至20度。
本發明之電性連接結構中,該第一基板較佳可包括有一第一電性墊,該第一電性墊係包括該第一奈米雙晶銅層。
本發明之電性連接結構中,該第二基板之第二電性墊較佳可包括有一第二奈米雙晶銅層。
本發明之電性連接結構中,該第一奈米雙晶銅層及該第二奈米雙晶銅層之厚度較佳可分別為0.1μm-500μm。
本發明之電性連接結構中,該第一基板及/或該第二基板較佳可各自獨立地選自由:一半導體晶片、一電路板、及一導電基板所組成之群組。
本發明之電性連接結構,較佳更包括一銲料層,係配置於該第一基板與第二基板之間(更詳細地,配置於該第一奈米雙晶銅層與該第二電性墊之間)。銲料層是由於迴焊時,部分銲料未轉換為介金屬化合物層而殘留下來。該銲料層之材質較佳可選自由:共晶型錫/鉛(eutectic Sn/Pb)銲料、錫/銀/銅銲料、錫/銀銲料、錫/銅銲料以及其他無鉛銲料所組成之群組。
本發明之電性連接結構較佳可更包括一晶種層(seed layer),係配置於該第一奈米雙晶銅層與該半導體晶片之一黏著層(adhesion layer)之間。
本發明之電性連接結構較佳可更包括一黏著層(adhesion layer),係配置於該晶種層(seed layer)與該半導體晶片(如,矽晶片)之間。黏著層之材質係選自由:鈦、鎢鈦(TiW)、氮化鈦(TiN)、氮化鉭(TaN)、鉭(Ta)、及其合金所組成之群組。
本發明之電性連接結構中,雙晶銅晶粒之直徑較佳可為0.1 μm-50 μm,且該晶粒之厚度較佳可為0.01 μm-1000 μm,更佳為0.01 μm-100μm,最佳為0.01 μm-200μm。
以下係藉由特定的具體實施例說明本發明之實施方式,熟習此技藝之人士可由本說明書所揭示之內容輕易地了解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實施例加以施行或應用,本說明書中的各項細節亦可基於不同觀點與應用,在不悖離本發明之精神下進行各種修飾與變更。
[實施例1]
圖2A至圖2D係本實施例之電性連接體之製備流程圖。如圖2A所示,首先提供一基板31,在此,基板31係一具有線路層32(亦可作為電性墊)之印刷電路板。接著,如圖2B所示,將該基板31置入於一電鍍裝置2中作為陰極。該電鍍裝置1包括有陽極22,係浸泡於電鍍液24中並連接至一直流電供應源26(在此係使用Keithley 2400)。陽極22使用之材料為金屬銅、磷銅或惰性陽極(如鈦鍍白金)。電鍍液24係包括有硫酸銅(銅離子濃度為20-60g/L)、氯離子(濃度為10-100ppm)、以及甲基磺酸(濃度為80-120g/L),並可添加其他界面活性劑或晶格修整劑(如BASF Lugalvan 1-100ml/L)。選擇性地,本實施例之電鍍液24更可包含有機酸(例如,甲基磺酸)、明膠(gelatin)、或以上的混合物,用以調整晶粒結構與尺寸。
接著,以2-10ASD的電流密度之直流電進行電鍍,由基板31開始朝著箭頭所指之方向(如圖2B所示)於線路層32表面成長奈米雙晶銅。成長過程中,雙晶之(111)面以及奈米雙晶銅金屬層之平面係約垂直於電場的方向,並以約1.76μm/min的速率成長雙晶銅。成長完成之第一奈米雙晶銅層33(作為電性墊)包括有複數個雙晶銅晶粒,該雙晶銅晶粒由複數個雙晶銅所組成,此奈米雙晶銅晶粒延伸到表面,因此第一奈米雙晶銅層33表面所顯露的同樣是(111)面。電鍍完成後得到的第一奈米雙晶銅層33厚度約20μm。[111]晶軸係為垂直(111)面之軸。
接著,如圖2C所示,取一半導體晶片41,該半導體晶片41係具有一同樣為奈米雙晶銅層所構成之電性墊42(亦即第二奈米雙晶銅層,其製作方法可參考第一奈米雙晶銅層33之行成方法)。接著,以一銲料51黏接該半導體晶片41之電性墊42以及該基板31上之第一奈米雙晶銅層33。
其後,進行迴焊(reflow),迴焊所使用溫度為260℃,時間可為30秒以上(例如,1分鐘、3分鐘、或5分鐘,依照所使用的銲料的多寡而不同,在此係5分鐘)。如圖2D所示,迴焊完成後,銲料51之部分會轉換為介金屬化合物層57,介金屬化合物層57包括有Cu3
Sn層54以及Cu6
Sn5
層55,Cu6
Sn5
層55包括有複數具方向性的Cu6
Sn5
晶粒551由Cu3
Sn層54表面生長出來。由於迴焊溫度需足夠使銲錫可於液態下進行反應而生長Cu6
Sn5
晶粒,因此迴焊溫度較佳為可使銲料熔融的溫度,例如大約230℃以上。但須注意,若迴焊溫度過高,仍有可能傷害到電子元件構造,因此迴焊溫度需適當的控制。
如圖3A及3B所示,其圖3A係本實施例之Cu6
Sn5
層55(複數個Cu6
Sn5
晶粒551)的橫截面電子背向散射繞射(Electron Back-Scattered Diffraction,簡稱EBSD)示意圖,而圖3B則為圖3A的圖案參考依據示意圖。由圖3B中顯示的圖案可知,當圖3A中的圖案顯示為點狀時,則表示Cu6
Sn5
晶粒551生長方向接近[0001]方向;當圖案顯示為十字狀時,則表示Cu6
Sn5
晶粒551生長方向接近[20]晶軸方向;當圖案顯示為圓圈狀時,則表示Cu6
Sn5
晶粒551生長方向接近[100]方向。如圖3A所示,本實施例之Cu6
Sn5
晶粒551的生長方向大部分係偏向[0001]方向,亦即呈現點狀圖案的Cu6
Sn5
晶粒佔大部分,因此可證實本實施例係成功地控制了Cu6
Sn5
晶粒的生長方向。
本發明透過控制Cu6
Sn5
晶粒的生長方向,解決了一般銲錫接點中,受到錫晶粒不同晶向的影響,而遭受的早期破壞。應用於三維積體電路封裝(3D-IC packaging)與矽晶片穿孔(TSV)連接之電性接點時,可以確實錫接點的品質。並且,本發明不僅可控制接點的機械性質、電性、可靠度、以及使用壽命等,更降低了生產成本(此係由於本發明不需使用額外的阻障材料、或是高溫熱處理等步驟),因此具有相當高的經濟價值。
如圖4所示,其係本實施例之電性連接結構之聚焦離子束(FIB)剖面圖。請同時參考圖2D以及圖4,本實施例之具方向性排列之Cu6
Sn5
晶粒之電性連接結構包括有:基板31,係具有線路層32,線路層32表面係具有第一奈米雙晶銅層33(以作為電性墊);半導體晶片41,係具有奈米雙晶銅層所構成之電性墊42;以及至少一介金屬化合物(intermetallic compound,IMC)層57,係位於第一奈米雙晶銅層33之表面,該介金屬化合物層57係配置於基板31與該半導體晶片41之間,且介金屬化合物層57包括Cu3
Sn層54,52以及Cu6
Sn5
層53,55,Cu6
Sn5
層53,55包含有複數具方向性排列之Cu6
Sn5
晶粒551,531;其中,該第一奈米雙晶銅層33之50%以上的體積包括複數個雙晶銅晶粒。在本實施例中,Cu6
Sn5
層55之厚度約為1 μm至5 μm,Cu3
Sn層54之厚度約為10 nm至50 nm。
此外,第一奈米雙晶銅層33之構造將在後續更詳細介紹。
[實施例2]
如圖5所示,其係本實施例之電性連接結構之示意圖。本實施例之電性連接結構大致與實施例1相似,差別在於,本實施例之迴焊時間較長(約5至6分鐘),會使Cu6
Sn5
晶粒551,531的尺寸增加(使厚度達到約10 μm至30 μm)。因此,本實施例經由銲料51厚度、以及迴焊時間的調整,使得基板31以及半導體晶片41表面之Cu6
Sn5
晶粒551,531上下互相黏合。且經過本發明之發明人實驗證實,即使Cu6
Sn5
晶粒551,531上下互相黏合,Cu6
Sn5
晶粒仍具有方向性。因此,證實了本發明之技術可控制Cu6
Sn5
晶粒的成長方向性。
而當Cu6
Sn5
晶粒551,531上下互相黏合,代表原所使用的銲料51可能全部轉換成為介金屬化合物層,或是僅留存少部分的銲料51存在於Cu6
Sn5
晶粒551,531之間。如此,Cu6
Sn5
晶粒551,531上下互相黏合的結構,可控制接點的機械性質、電性、可靠度、以及使用壽命等,因此可大幅降低銲接點變異所造成的可靠度問題,確實提升電子裝置的使用壽命。
如圖6A所示,其係上述各個實施例之奈米雙晶銅層之聚焦離子束(FIB)剖面圖,圖6B係奈米雙晶銅層之立體示意圖。如圖6A及6B所示,本發明之奈米雙晶銅層43之50%以上的體積包括有複數個柱狀晶粒66,而每一晶粒中有複數個層狀奈米雙晶銅(例如,相鄰的一組黑線與白線構成一個雙晶銅,係以堆疊方向69堆疊而構成晶粒66),因此本發明中,奈米雙晶銅層整體則包含有非常多的奈米雙金銅。此些柱狀晶粒66之直徑D之範圍係約為0.5μm至8 μm且高度L約為1μm至500μm(或1μm至100μm,更佳為1μm至20μm),奈米雙晶平面661(水平條紋)與(111)平面平行,雙晶晶粒間是晶界662,銅之(111)平面垂直於厚度T方向,且雙晶銅層之厚度T在此約為20μm(可於0.1μm-500μm之間任意調整)。相鄰之該晶粒間之堆疊方向(幾乎等同於[111]晶軸)之夾角約為0至20度。
綜上所述,本發明之電性連接結構及/或其製造方法,透過控制Cu6
Sn5
晶粒的生長方向,解決了銲錫接點中介金屬化合物層造成可靠度降低的問題,確實控制銲錫接點的品質。並且,本發明之電性連接結構及/或其製造方法不僅可控制接點的機械性質、電性、可靠度、以及使用壽命等,更降低了生產成本(此係由於本發明不需使用額外的阻障材料、或是高溫熱處理等步驟),因此具有相當高的經濟價值。
上述實施例僅係為了方便說明而舉例而已,本發明所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。
11,12...晶片
13,14...電性墊
15,18...Cu3
Sn層
16,19...Cu6
Sn5
層
17...銲錫
171,172...介金屬化合物層
2...電鍍裝置
22...陽極
24...電鍍液
26...直流電供應源
31...基板
32...線路層
33...第一奈米雙晶銅層
41...半導體晶片
42...電性墊
43...奈米雙晶銅層
51...銲料
52,54...Cu3
Sn層
53,55...Cu6
Sn5
層
531,551...Cu6
Sn5
晶粒
57...介金屬化合物層
66...晶粒
661...奈米雙晶平面
662...晶界
69...堆疊方向
D...直徑
L...高度
T...厚度
(111)...(111)平面
[111]...[111]晶軸
圖1係習知三維積體電路(3D-IC)結構。
圖2A至圖2D係本發明實施例1之電性連接結構之製備流程圖。
圖3A係本發明實施例1之Cu6
Sn5
層的俯視面電子背向散射繞射(Electron Back-Scattered Diffraction,簡稱EBSD)示意圖。
圖3B係圖3A的圖案參考依據示意圖。
圖4係本發明實施例1之電性連接結構之聚焦離子束(FIB)剖面圖。
圖5係本發明實施例2之電性連接結構之示意圖。
圖6A係本發明較佳實施例之奈米雙晶銅層之聚焦離子束(FIB)剖面圖。
及6B係本發明較佳實施例之奈米雙晶銅層之立體示意圖。
31...基板
32...線路層
33...第一奈米雙晶銅層
41...半導體晶片
42...電性墊
51...銲料
52,54...Cu3
Sn層
53,55...Cu6
Sn5
層
57...介金屬化合物層
Claims (25)
- 一種包含有具優選方向成長之Cu6 Sn5 晶粒之電性連接結構之製備方法,包括步驟:(A) 提供一第一基板;(B) 於該第一基板之部分表面形成一第一奈米雙晶銅層;(C) 使用一銲料將該第一基板與一第二基板連接,該第二基板具有一第二電性墊,該第二電性墊包括一第二奈米雙晶銅層,且該銲料係配置於該第一奈米雙晶銅層與該第二奈米雙晶銅層之間;以及(D) 以200℃至300℃的溫度進行迴焊(reflow)使該銲料至少部分轉換為一介金屬化合物(intermetallic compound,IMC)層,且該介金屬化合物層係包括具優選方向(orientational)成長之複數Cu6 Sn5 晶粒;其中,該第一奈米雙晶銅層及該第二奈米雙晶銅層之50%以上的體積係分別包括複數個雙晶銅晶粒。
- 如申請專利範圍第1項所述之電性連接結構之製備方法,其中,50%以上相鄰之該複數Cu6 Sn5 晶粒方向之夾角係為0至40度。
- 如申請專利範圍第1項所述之電性連接結構之製備方法,其中,50%以上之該複數Cu6 Sn5 晶粒之[0001]方向與該第一奈米雙晶銅層之[0001]方向之夾角係為0至40度,且50%以上之該複數Cu6 Sn5 晶粒之[0001]方向與該第二奈米雙晶銅層之[0001]方向之夾角係為0至40度。
- 如申請專利範圍第1項所述之電性連接結構之製備方法,其中,該步驟(D)中,迴焊之時間為30秒至10分鐘。
- 如申請專利範圍第1項所述之電性連接結構之製備方法,其中,該步驟(D)中,迴焊之溫度為240℃至280℃。
- 如申請專利範圍第1項所述之電性連接結構之製備方法,其中,該複數Cu6 Sn5 晶粒與該第一奈米雙晶銅層之間更包括一Cu3 Sn層,且該Cu3 Sn層之厚度與該複數Cu6 Sn5 晶粒中高度最高之晶粒高度比[Cu3 Sn層之厚度]/[複數Cu6 Sn5 晶粒中高度最高之晶粒高度]為0至0.3。
- 如申請專利範圍第1項所述之電性連接結構之製備方法,其中,該複數Cu6 Sn5 晶粒所構成之層之厚度為500nm至10μm。
- 如申請專利範圍第6項所述之電性連接結構之製備方法,其中,該Cu3 Sn層之厚度為1 nm至1000nm。
- 如申請專利範圍第1項所述之電性連接結構之製備方法,其中,該複數個雙晶銅晶粒彼此間係互相連接,該每一雙晶銅晶粒係由複數個奈米雙晶銅沿著[111]晶軸方向堆疊而成,且相鄰之該雙晶銅晶粒間之堆疊方向之夾角係0至20度。
- 如申請專利範圍第1項所述之電性連接結構之製備方法,其中,該步驟(B)之該第一奈米雙晶銅層之形成方法係選自由:直流電鍍、脈衝電鍍、物理氣相沉積、化學氣相沉積、以及蝕刻銅箔所組成之群組。
- 如申請專利範圍第10項所述之電性連接結構之製備方法,其中,當該步驟(B)使用電鍍形成該第一奈米雙晶銅層時,電鍍所使用之一電鍍液係包括有:一銅的鹽化物、一酸、以及一氯離子來源。
- 如申請專利範圍第11項所述之電性連接結構之製備方法,其中,該電鍍液更包括一物質係選自由:明膠(gelatin)、介面活性劑、晶格修整劑、及其混合所組成之群組。
- 如申請專利範圍第11項所述之電性連接結構之製備方法,其中,該電鍍液中的酸係為硫酸、甲基磺酸、或其混合。
- 如申請專利範圍第1項所述之電性連接結構之製備方法,其中,該第一基板係包括有一第一電性墊,該第一電性墊係包括該第一奈米雙晶銅層。
- 如申請專利範圍第1項所述之電性連接結構之製備方法,其中,該第一奈米雙晶銅層之厚度為0.1μm-500μm。
- 一種包含有具優選方向排列之Cu6 Sn5 晶粒之電性連接結構,包括:一第一基板,係具有一第一電性墊,該第一電性墊係包括一第一奈米雙晶銅層;一第二基板,係具有一第二電性墊,該第二電性墊係包括一第二奈米雙晶銅層;以及至少一介金屬化合物(intermetallic compound,IMC)層,係位於該第一奈米雙晶銅層及該第二奈米雙晶銅層之表面,該介金屬化合物層係配置於該第一基板與該第二基板之間,並電性連接該第一電性墊以及該第二電性墊,且該介金屬化合物層係包括複數具優選方向性排列之Cu6 Sn5 晶粒;其中,該第一奈米雙晶銅層及該第二奈米雙晶銅層之50%以上的體積係分別包括複數個雙晶銅晶粒。
- 如申請專利範圍第16項所述之電性連接結構,其中,50%以上相鄰之該複數Cu6 Sn5 晶粒方向之夾角係為0至40度。
- 如申請專利範圍第16項所述之電性連接結構,其中,50%以上之該複數Cu6 Sn5 晶粒之[0001]方向與奈米雙晶銅層之[0001]方向之夾角係為0至40度,且50%以上之該複數Cu6 Sn5 晶粒之[0001]方向與該第二奈米雙晶銅層之[0001]方向之夾角係為0至40度。
- 如申請專利範圍第16項所述之電性連接結構,其中,該複數Cu6 Sn5 晶粒與該第一奈米雙晶銅層之間更包括一Cu3 Sn層,且該Cu3 Sn層之厚度與該複數Cu6 Sn5 晶粒中高度最高之晶粒高度比[Cu3 Sn層之厚度]/[複數Cu6 Sn5 晶粒中高度最高之晶粒高度]為0至0.3。
- 如申請專利範圍第16項所述之電性連接結構,其中,該複數Cu6 Sn5 晶粒所構成之層之厚度為500nm至10μm。
- 如申請專利範圍第19項所述之電性連接結構,其中,該Cu3 Sn層之厚度為1 nm至1000 nm。
- 如申請專利範圍第16項所述之電性連接結構,其中,該複數個雙晶銅晶粒彼此間係互相連接,該每一雙晶銅晶粒係由複數個奈米雙晶銅沿著[111]晶軸方向堆疊而成,且相鄰之該雙晶銅晶粒間之堆疊方向之夾角係0至20度。
- 如申請專利範圍第16項所述之電性連接結構,其中,該第一奈米雙晶銅層及該第二奈米雙晶銅層之厚度係分別為0.1μm-500μm。
- 如申請專利範圍第16項所述之電性連接結構,其中,該第一基板係選自由:一半導體晶片、一電路板、及一導電基板所組成之群組。
- 如申請專利範圍第16項所述之電性連接結構,其中,該第二基板係選自由:一半導體晶片、一電路板、及一導電基板所組成之群組。
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CN201210154178.2A CN103390565B (zh) | 2012-05-10 | 2012-05-18 | 包括在优选方向生长的Cu6Sn5晶粒的电性连接结构及其制备方法 |
US13/829,256 US8952267B2 (en) | 2012-05-10 | 2013-03-14 | Electric connecting structure comprising preferred oriented Cu6Sn5 grains and method for fabricating the same |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11508691B2 (en) | 2021-02-22 | 2022-11-22 | United Microelectronics Corp. | Semiconductor structure with nano-twinned metal coating layer and fabrication method thereof |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8957323B2 (en) * | 2012-05-10 | 2015-02-17 | National Chiao Tung University | Electrical connecting element having nano-twinned copper, method of fabricating the same, and electrical connecting structure comprising the same |
US9355980B2 (en) * | 2013-09-03 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional chip stack and method of forming the same |
JP2015122445A (ja) * | 2013-12-24 | 2015-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US9443813B1 (en) * | 2015-03-05 | 2016-09-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and method for manufacturing the same |
RU2597835C1 (ru) * | 2015-04-23 | 2016-09-20 | Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Алтайский государственный университет" | Способ получения кристаллографически ориентированных квазимонокристаллических интерметаллических тонких пленок |
US9941230B2 (en) | 2015-12-30 | 2018-04-10 | International Business Machines Corporation | Electrical connecting structure between a substrate and a semiconductor chip |
CN107058956B (zh) * | 2017-04-13 | 2019-03-15 | 厦门大学 | 一种铜六锡五全imc微凸点的快速制造方法 |
KR102133765B1 (ko) | 2017-10-31 | 2020-07-14 | 센주긴조쿠고교 가부시키가이샤 | 납땜 이음 및 납땜 이음의 형성 방법 |
CN108565449B (zh) * | 2018-02-26 | 2020-07-31 | 厦门城市职业学院(厦门市广播电视大学) | 一种单向性Cu6Sn5纳米棒及其制备方法、应用 |
CN108857132B (zh) * | 2018-07-24 | 2021-04-20 | 哈尔滨工业大学(深圳) | 一种评估无铅焊点可靠性方法 |
US10763231B2 (en) | 2018-07-27 | 2020-09-01 | Texas Instruments Incorporated | Bump bond structure for enhanced electromigration performance |
TWI731293B (zh) * | 2019-01-18 | 2021-06-21 | 元智大學 | 奈米雙晶結構 |
TWI686518B (zh) | 2019-07-19 | 2020-03-01 | 國立交通大學 | 具有奈米雙晶銅之電連接結構及其形成方法 |
TWI709667B (zh) | 2019-12-06 | 2020-11-11 | 添鴻科技股份有限公司 | 奈米雙晶銅金屬層及其製備方法及包含其的基板 |
CN112103262B (zh) * | 2020-09-14 | 2022-09-06 | 大连理工大学 | 一种控制全金属间化合物微互连焊点晶体取向及微观组织的方法 |
CN114211075B (zh) * | 2021-12-31 | 2023-09-19 | 北京工业大学 | 一种改变Sn基钎料焊点重熔晶体取向的方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW515849B (en) * | 1999-06-22 | 2003-01-01 | Nec Corp | Copper interconnection and method of producing the same |
TW583346B (en) * | 2000-08-04 | 2004-04-11 | Mitsui Mining & Smelting Co | Manufacturing method of electrodeposited copper foil and electrodeposited copper foil |
TW200515572A (en) * | 2003-05-07 | 2005-05-01 | Texas Instruments Inc | Controlling interdiffusion rates in metal interconnection structures |
US20060267157A1 (en) * | 2005-05-31 | 2006-11-30 | Edwards Darvin R | Solder joints for copper metallization having reduced interfacial voids |
US20080182124A1 (en) * | 2007-01-30 | 2008-07-31 | International Business Machines Corporation | Modification of solder alloy compositions to suppress interfacial void formation in solder joints |
TW201133662A (en) * | 2010-03-31 | 2011-10-01 | Nat Univ Tsing Hua | Copper-Manganese compound structure for electronic packaging application |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6744142B2 (en) * | 2002-06-19 | 2004-06-01 | National Central University | Flip chip interconnection structure and process of making the same |
JP4939891B2 (ja) * | 2006-10-06 | 2012-05-30 | 株式会社日立製作所 | 電子装置 |
JP5331322B2 (ja) * | 2007-09-20 | 2013-10-30 | 株式会社日立製作所 | 半導体装置 |
CN101323059A (zh) * | 2008-07-11 | 2008-12-17 | 北京工业大学 | 内生Cu6Sn5颗粒增强无铅复合钎料合金及其制备方法 |
CN101664861B (zh) * | 2009-09-21 | 2012-02-01 | 天津大学 | 改善焊点蠕变性能的Sn-Cu基无铅钎料合金及其制备工艺 |
-
2012
- 2012-05-10 TW TW101116641A patent/TWI476878B/zh active
- 2012-05-18 CN CN201210154178.2A patent/CN103390565B/zh active Active
-
2013
- 2013-03-14 US US13/829,256 patent/US8952267B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW515849B (en) * | 1999-06-22 | 2003-01-01 | Nec Corp | Copper interconnection and method of producing the same |
TW583346B (en) * | 2000-08-04 | 2004-04-11 | Mitsui Mining & Smelting Co | Manufacturing method of electrodeposited copper foil and electrodeposited copper foil |
TW200515572A (en) * | 2003-05-07 | 2005-05-01 | Texas Instruments Inc | Controlling interdiffusion rates in metal interconnection structures |
US20060267157A1 (en) * | 2005-05-31 | 2006-11-30 | Edwards Darvin R | Solder joints for copper metallization having reduced interfacial voids |
US20080182124A1 (en) * | 2007-01-30 | 2008-07-31 | International Business Machines Corporation | Modification of solder alloy compositions to suppress interfacial void formation in solder joints |
TW201133662A (en) * | 2010-03-31 | 2011-10-01 | Nat Univ Tsing Hua | Copper-Manganese compound structure for electronic packaging application |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11508691B2 (en) | 2021-02-22 | 2022-11-22 | United Microelectronics Corp. | Semiconductor structure with nano-twinned metal coating layer and fabrication method thereof |
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US8952267B2 (en) | 2015-02-10 |
US20130302646A1 (en) | 2013-11-14 |
CN103390565A (zh) | 2013-11-13 |
TW201347111A (zh) | 2013-11-16 |
CN103390565B (zh) | 2016-03-02 |
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