TWI490962B - 電性連接結構及其製備方法 - Google Patents

電性連接結構及其製備方法 Download PDF

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Publication number
TWI490962B
TWI490962B TW102134714A TW102134714A TWI490962B TW I490962 B TWI490962 B TW I490962B TW 102134714 A TW102134714 A TW 102134714A TW 102134714 A TW102134714 A TW 102134714A TW I490962 B TWI490962 B TW I490962B
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Taiwan
Prior art keywords
copper
substrate
film
copper film
bonding
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TW102134714A
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English (en)
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TW201432828A (zh
Inventor
Chih Chen
Taochi Liu
Yi Sa Huang
Chien Min Liu
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Univ Nat Chiao Tung
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Application filed by Univ Nat Chiao Tung filed Critical Univ Nat Chiao Tung
Priority to TW102134714A priority Critical patent/TWI490962B/zh
Priority to CN201310556722.0A priority patent/CN103985667B/zh
Priority to US14/174,178 priority patent/US20140217593A1/en
Priority to DE102014101552.5A priority patent/DE102014101552A1/de
Publication of TW201432828A publication Critical patent/TW201432828A/zh
Application granted granted Critical
Publication of TWI490962B publication Critical patent/TWI490962B/zh

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    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
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Description

電性連接結構及其製備方法
本發明係關於一種電性連接結構及其製備方法，尤指一種適用於三維積體電路用之電性連接結構及其製備方法。
隨著電子產業的蓬勃發展，對於具有體積小、重量輕、多功能且高性能之電子產品需求亦日益增加。於目前積體電路的發展上，為了將多種主動元件及被動元件設於同一個裝置上，現今多採用半導體封裝技術，以達到在有限的單位面積下容納更多數量的線路及電子元件之目的。
於封裝基板或電路板之堆疊中，可使用焊料或銅膜進行堆疊。當使用一般的銅材料所做成之銅膜進行堆疊時，由於一般的銅材料晶格方向並無單一性，而形成方向性零散的小晶粒，故接合前需進行多種如精細的表面拋光且蝕刻之前處理，而後再於限制多的環境(如，氮氣、酸氣)下，進行熱壓接合，此外，熱壓接合的溫度需在300℃以上的溫度下進行，此溫度有可能會破壞電路板中的元件。另外，雖然已經有報導銅膜能在室溫下接合，但是銅表面 必須是原子級的平整，而且接合的環境必須是在10-8 torr的超高真空內，因此無法量產。
如圖1A所示，當兩基板11,13以銅膜12,14進行接合時，若銅膜12,14之接合面不具有良好平整度時，容易於接合處產生接縫或空孔(如圖1B所示)，而導致產品可靠度降低。
由於電子產業越趨精密，產品的接點也往更精細的方向發展，導致接點的接合面積也相對減少。同時，為了提升產品的可靠度，接合製程也相對更加複雜。因此，若能發展出一種可減少製程並防止接合處產生接縫之結構與製備方法，則可應用於各種半導體製程上，特別是三維積體電路上，以提升產品的可靠度，同時也可以達到無須使用銲錫之目的，而可以降低產品成本。
本發明之主要目的係在提供一種電性連接結構，其兩基板間之接點(特別是接面)具有很好的接著，只有少數的接縫或空孔，甚至沒有接縫或孔洞，而不容易產生接點斷裂的情形。
本發明之另一目的係在提供一種電性連接結構之製備方法，俾能製作出具有高度產品可靠度之電性連接結構。
為達成上述目的，本發明之用以電性連接一第一基板及一第二基板之電性連接結構之製備方法，包括下列步驟：(A)提供一第一基板及一第二基板，其中第一基 板上係設有一第一銅膜，第二基板上係設有一第一金屬膜，第一銅膜之一第一接合面係為一含(111)面之接合面，且該第一金屬膜具有一第二接合面；以及(B)將第一銅膜及第一金屬膜相互接合以形成一接點，其中第一銅膜之第一接合面係與第一金屬膜之第二接合面相互對應。
透過上述製備方法，本發明之用以電性連接一第一基板及一第二基板之電性連接結構，包括：一第一基板；一第二基板；以及一接點，係設於第一基板與第二基板間，其中該接點係由一第一銅膜及一第一金屬膜相互接合而成，且於第一銅膜與第一金屬膜間之接面係包括複數個晶粒，而該晶粒係沿著[111]晶軸方向堆疊而成。
於本發明中，所使用之第一銅膜具有高度[111]優選方向，此優選方向具有最高的自擴散速度，且其含(111)面之接合面具有最高的面堆積密度。在此，需特別強調的是，於本發明所提供之製備方法中，僅須第一銅膜具有[111]優選方向，而另一者可為無任何優選方向之銅膜或其他異質金屬材料，即可形成少數的接縫或空孔，甚至沒有接縫或孔洞之接點；即便第一銅膜為多晶銅而第一金屬膜為多晶銅或其他異質金屬材料，亦可達到此功效。其原因在於，當將至少一具有(111)接合面之銅膜形成於基板(例如，半導體晶片或電路基板等)上以作為電性連接媒介，因於(111)接合面處銅晶格方向規則排列，故僅在低溫下透過簡單的壓合製程，也不易於接合處產生接縫或空孔。
此外，透過本發明之製備方法所製得之電性連 接結構，第一銅膜與第一金屬膜間之接合處(即，接面)可形成具有[111]優選方向之晶粒結構，且完全接合而無縫隙。由於接合之第一基板與第二基板間之接點無接縫，故可減少接點斷裂的風險，提升元件可靠度與使用壽命，並同時保留了銅的高導電性與高散熱性。特別是，以本發明之製備方法所製得之電性連接結構，將銅與異質金屬材料進行接合，仍可達到接點無接縫之目的。
於本發明中，第一金屬膜之材料可與第一銅膜相同或不同，且較佳為第一金屬膜之材料係選自由金、銀、鉑、鎳、銅、鈦、鋁及鈀所組成之群組。
於本發明之一實施態樣中，第一金屬膜係為一第二銅膜。其中，第一銅膜與第二銅膜之材料並無特殊限制，只要其中一者接合面為含(111)面之接合面即可。舉例而言，本發明之第一銅膜可為接合面為含(111)面之接合面之銅層，而第二銅膜為多晶銅且無優選方向；或者本發明之第一銅膜與第二銅膜可分別為接合面為含(111)面之接合面之銅層或一奈米雙晶銅層。無論是銅層(包括多晶銅層)或奈米雙晶銅層，經接合後，接合處(接面)係形成有沿著[111]晶軸方向堆疊而成之複數個晶粒。較佳為，此些晶粒係為柱狀晶粒。於本發明中，所謂之「(111)面」係指：銅膜中複數銅晶粒之(111)面之法向量與接合面之法向量之角度在15度內。在此定義的前提下，「含(111)面之接合面」係指以該含(111)面之接合面之總面積為基準，40-100%之總面積係為(111)面；較佳為50-100%之總面積係為(111)面；更佳為60-100% 之總面積係為(111)面。若本發明之第一銅膜與第二銅膜為奈米雙晶銅層時，較佳為奈米雙晶銅層之50%以上的體積包括複數個晶粒。由於奈米雙晶銅之雙晶排列而可提升銅膜之抗電遷移能力，進而增加產品的可靠度，而特別適用於積體電路的製作上。
於本發明之一實施態樣中，第一金屬膜之材料係可為金、銀、鉑、鎳、鈦、鋁、鈀、或其合金。此時，第一銅膜之材料及其接合面係與前述相同，故在此不再贅述。
於本發明之電性連接結構之製備方法中，於步驟(A)前可更包括一步驟(A’)：清洗第一銅膜之第一接合面與第一金屬膜之第二接合面，以去除氧化物或其他雜質。特別是，使用酸液(如：鹽酸)清洗第一銅膜之第一接合面與第一金屬膜之第二接合面。此外，於本發明之電性連接結構之製備方法中，於步驟(B)中，進行接合之裝置並無特殊限制，可為本技術領域常用之技術，如以夾具進行接合。此外，更可透過加壓方式以將第一銅膜及第一金屬膜相互接合。其中，加壓之壓力並無特殊限制，較佳為低壓力，如約1.5-5kg/cm2 。
再者，於本發明之電性連接結構之製備方法中，於步驟(B)中，可於升溫下進行接合，其中接合溫度並無特殊限制，只要可在不影響兩基板結構下達到接合目的即可，例如可於100-400℃之低溫下進行接合；且較佳透過加壓並於150-300℃之溫度下，以將第一銅膜及第一金屬膜 相互接合。在此，步驟(B)之接合的溫度較佳為150-400℃；更佳為150-250℃。此外，接合時間並無特殊限制，只要可將兩基板完成接合即可，例如可約0.1-5小時，且較佳約0.1-1.5小時。
於本發明之電性連接結構之製備方法中，於步驟(B)中，可於低真空度下將第一銅膜及第一金屬膜相互接合。較佳為，低真空度為1-10-3 torr。
於本發明之電性連接結構之製備方法中，當接合時，第一銅膜之接合面為(111)面。(111)面具有較高的擴散速率且表面能較低，且為面心立方(FCC)最密堆積面，故可容易達到無接縫接合。無論是以多晶銅或奈米雙晶銅做為膜材料，只要第一接合面具有(111)優選方向，即可簡單的先將接合面表面透過拋光步驟即可進行接合，且亦可達到很少接縫接合之接點。利用銅原子在(111)表面擴散速度特別快，可以在200℃以下達到很好接合之效果。據此，而可降低接合環境的限制，而無需使用設備昂貴的機台，生產成本也因而可大幅下降。
於本發明之電性連接結構及其製備方法中，奈米雙晶銅之晶粒係為柱狀雙晶體(columnar twinned grain)。此外，複數個晶粒彼此間係互相連接，該每一晶粒係由複數個奈米雙晶銅沿著[111]晶軸方向堆疊而成，且相鄰之該晶粒間之堆疊方向之夾角係0至20度。
再者，於本發明之電性連接結構之製備方法中，做為第一銅膜及第二銅膜材料之含有(111)面之奈米雙 晶銅或多晶銅之形成方法可為直流電鍍或脈衝電鍍。較佳為，以下述方法形成含有(111)面之奈米雙晶銅或多晶銅：提供一電鍍裝置，該電鍍裝置包括一陽極、一陰極、一電鍍液、以及一電力供應源，電力供應源係分別與陽極及陰極連接，且陽極及陰極係浸泡於該電鍍液中；以及使用電力供應源提供電力進行電鍍，由陰極之一表面成長奈米雙晶銅層。在此，所使用之電鍍液可包括有：一銅的鹽化物、一酸、以及一氯離子來源。
於上述之電鍍液中，氯離子主要功能之一係可用以微調整晶粒成長方向，使銅層(特別是雙晶銅層)具有結晶優選方向。此外，其酸可為一有機或無機酸，以增加電解質濃度而提高電鍍速度，例如可使用硫酸、甲基磺酸、或其混合，此外，電鍍液中的酸之濃度較佳可為80-120g/L。再者，電鍍液須同時包含有銅離子來源(亦即，銅之鹽化物，例如，硫酸銅或甲基磺酸銅)。該電鍍液較佳的組成中，也可更包括一添加物係選自由：明膠(gelatin)、介面活性劑、晶格修整劑(lattice modification agent)、及其混合所組成之群組，用以調整此些添加物質可用以微調整晶粒成長成具有[111]優選方向。
在此，電鍍裝置之電力供應源較佳係直流電電鍍供應源、或高速脈衝電鍍供應源、或直流電鍍與高速脈衝電鍍二者交互使用為之，可使金屬層形成速率提升。當該步驟(B)中使用直流電電鍍供應源時，電流密度較佳可為1-12ASD，最佳可為2-10ASD(例如，8ASD)。當該步驟(B) 中使用高速脈衝電鍍供應源時，其操作條件較佳為：Ton /Toff (sec)為0.1/2-0.1/0.5之間(例如，0.1/2、0.1/1、或0.1/0.5)，電流密度為1-25ASD(最佳可為5ASD)。在此條件下進行電鍍，銅層之成長速率以實際通電時間計算，較佳可為0.22-2.64μm/min。例如，當電鍍之電流密度為8ASD時，金屬層之成長速率可至1.5-2μm/min(例如，1.76μm/min)。本發明中，銅層之厚度可依據電鍍時間長短進行調整，其範圍較佳為約0.1-500μm，更佳為0.8-200μm，最佳為1-20μm。
特別是，習知技術所製得具有優選方向的雙晶銅金屬層無填孔性，量產厚度僅可達到約0.1μm，因此僅可作為晶種層使用，無法直接應用於如導線之處。然而，以本發明前述方法所製得之電鍍奈米雙晶銅層的厚度可達0.1-500μm，而可直接鍍製在介電層之開口或溝槽中，而可應用於本發明之電路板之線路層製作上。
此外，當電鍍進行時，該陰極或該電鍍液係可以50-1500rpm之轉速旋轉，以幫助晶粒成長方向及速率。透過適當的電鍍條件，本發明所得之奈米雙晶銅層之晶粒之直徑較佳可為0.1-50μm，更佳可為1-10μm；晶粒厚度較佳可為0.01-500μm，更佳可為0.1-200μm。
再者，於本發明之電性連接結構及其製備方法中，第一基板及第二基板可各自獨立為一半導體晶片、一封裝基板、或一電路板；且較佳為半導體晶片。據此，本發明之技術可應用於，例如覆晶封裝(Flip chip)、晶圓接合 (wafer bonding)、晶圓級晶片封裝(wafer level chip scale packaging,WLCSP)等常見於IBM C4技術所衍生的各種封裝技術中，尤其是具高頻與高功率元件。特別是，本發明之技術更可應用於需要高機械性質且產品可靠度之三維積體電路上。舉例而言，當第一基板及第二基板為半導體晶片時，經接合後則可形成所謂的三維積體電路(3D-IC)；此外，亦可將三維積體電路做為第一基板，且封裝基板做為第二基板進行接合。在此，僅用以舉例用，而非用以限制本發明。
11,13‧‧‧基板
12,14‧‧‧銅膜
21‧‧‧第一基板
221‧‧‧第一接著層
22‧‧‧第一銅膜
221‧‧‧第一接合面
23‧‧‧第二基板
231‧‧‧第二接著層
24‧‧‧第二銅膜
241‧‧‧第二接合面
25‧‧‧接點
261,262‧‧‧夾具
27‧‧‧金膜
3‧‧‧電鍍裝置
32‧‧‧陽極
34‧‧‧電鍍液
36‧‧‧直流電供應源
41‧‧‧柱狀晶粒
411‧‧‧奈米雙晶平面
412‧‧‧晶界
D‧‧‧直徑
T‧‧‧厚度
圖1A係習知接點結構示意圖。
圖1B係習知接點結構之接合處放大示意圖。
圖2A至圖2C係為本發明實施例1之具有雙晶銅之電性連接結構之製備流程剖面示意圖。
圖3係為本發明實施例1之用以形成銅膜之電鍍裝置示意圖。
圖4係本發明實施例1之銅層之電子背向散射繞射俯視圖。
圖5A至圖5B係分別為本發明實施例1之奈米雙晶銅之聚焦離子束剖面圖及立體示意圖。
圖6係本發明實施例1之電性連接結構之接合處之聚焦離子束剖面圖。
圖7A至圖7B係為本發明實施例2之具有雙晶銅之電 性連接結構之製備流程剖面示意圖。
圖8A至圖8C係為本發明實施例3之以銅層形成之電性連接結構之製備流程剖面示意圖。
圖9係本發明實施例3之銅層之電子背向散射繞射俯視圖。
圖10係為本發明實施例3之銅層之穿透式電子顯微鏡之剖面明視野影像。
圖11係為本發明實施例3之電性連接結構之接合處之高解析穿透式電子顯微鏡影像。
圖12係為本發明實施例3之電性連接結構之接合處之穿透式電子顯微鏡之剖面明視野影像。
圖13係為本發明實施例4之電性連接結構之接合處之聚焦離子束剖面圖。
圖14係為本發明實施例5之電性連接結構之接合處之穿透式電子顯微鏡之明視野剖面影像。
圖15係為本發明實施例6之電性連接結構之接合處之穿透式電子顯微鏡之明視野影像。
圖16係為本發明實施例7之電性連接結構之接合處之穿透式電子顯微鏡之明視野剖面影像。
圖17係本發明實施例8之含有64%(111)表面之銅層之電子背向散射繞射俯視圖。
圖18係為本發明實施例8之電性連接結構之接合處之穿透式電子顯微鏡之明視野剖面影像。
圖19係為本發明實施例9之電性連接結構之接合處之 聚焦離子束剖面圖。
以下係藉由特定的具體實施例說明本發明之實施方式，熟習此技藝之人士可由本說明書所揭示之內容輕易地了解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實施例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。
實施例1
圖2A至圖2C係為本實施例之具有雙晶銅之電性連接結構之製備流程剖面示意圖。圖3係為本實施例之用以形成銅膜之電鍍裝置示意圖。圖4係本實施例之銅層之電子背向散射繞射俯視圖，(111)面之比例為100%。圖5A及5B係分別為本實施例之奈米雙晶銅層之聚焦離子束(FIB)剖面圖及立體示意圖。
如圖2A所示，首先提供一第一基板21，且第一基板21係為一晶圓。在此，為了簡潔說明，僅以示意圖表示第一基板21之結構，其線路、主動元件、被動元件或其他部分並未揭示於圖式中。
而後，使用如圖3所示之電鍍裝置，對第一基板21進行電鍍。如圖3所示，將第一基板21置於一電鍍裝置3中作為陰極；其中，該電鍍裝置3包括有陽極32，係浸泡於電鍍液34中並連接至一直流電供應源36(在此係使用Keithley 2400)。陽極32使用之材料可為金屬銅、磷銅或 惰性陽極(如鈦鍍白金)；於本實施例中，陽極32使用之材料為金屬銅。此外，電鍍液34係包括有硫酸銅(銅離子濃度為20-60g/L)、氯離子(濃度為10-100ppm)、以及甲基磺酸(濃度為80-120g/L)，並可添加其他界面活性劑或晶格修整劑(如BASF Lugalvan 1-100ml/L)。選擇性地，本實施例之電鍍液34更可包含有機酸(例如，甲基磺酸)、明膠(gelatin)、或以上的混合物，用以調整晶粒結構與尺寸。
接著，以2-10ASD的電流密度之直流電進行電鍍，由第一基板21開始朝著箭頭所指之方向(如圖3所示)於第一基板21表面成長第一銅膜22，如圖2A所示。成長過程中，雙晶之(111)面以及第一銅膜22之平面係約垂直於電場的方向，並以約1.76μm/min的速率成長雙晶銅；更具體而言，第一銅膜22(即，奈米雙晶銅層)係沿著垂直(111)方向，即平行電場方向成長。
成長完成之第一銅膜22包括有複數個雙晶銅晶粒，該雙晶銅晶粒由複數個雙晶銅所組成，此奈米雙晶銅晶粒延伸到表面，因此第一銅膜22表面所顯露的同樣是(111)面。電鍍完成後得到的第一銅膜22厚度約5~20μm，且[111]晶軸係為垂直(111)面之軸，(111)面之比例為100%。而後，將第一基板21從電鍍裝置中取出，則可得到上方形成有第一銅膜22之第一基板21，且第一銅膜22係為奈米雙晶銅層，且其第一接合面221係為(111)面，(111)面之比例為100%，如圖4之電子背向散射繞射(EBSD)俯視圖所示，其中藍色部分面積為(111)面。
在此，請參閱圖5A及圖5B，其分別為本實施例所形成之作為第一銅膜之奈米雙晶銅層之聚焦離子束(FIB)剖面圖及立體示意圖。如圖5A所示，本實施例之奈米雙晶銅層之50%以上的體積包括有複數個柱狀晶粒41，而每一晶粒中有複數個層狀奈米雙晶銅(例如，相鄰的一組黑線與白線構成一個雙晶銅，係以堆疊方向42堆疊而構成晶粒41，如圖5B所示)。因此本發明中，奈米雙晶銅層整體則包含有非常多的奈米雙晶銅。此些柱狀晶粒41之直徑D之範圍係約為0.5μm至8μm且高度L約為2μm至20μm，奈米雙晶平面411(水平條紋)與(111)平面平行，雙晶晶粒間是晶界412，銅之(111)平面垂直於厚度T方向，且雙晶銅層之厚度T約為20μm(可於0.1μm-500μm之間任意調整)。相鄰之該晶粒間之堆疊方向(幾乎等同於[111]晶軸)之夾角係0至20度以內。
接著，請參閱圖2B，提供一第二基板23，且第二基板23亦為一晶圓。同樣的，為了簡潔說明，僅以示意圖表示第二基板23之結構，其線路、主動元件、被動元件或其他部分並未揭示於圖式中。
同時，使用與形成第一銅膜22相同之電鍍方法，以於第二基板23上形成第二銅膜24，其厚度約5~20μm，且[111]晶軸係為垂直(111)面之軸。因此，第二銅膜24係為奈米雙晶銅層，且其第二接合面241亦為(111)面。在此，第二銅膜24之奈米雙晶銅層與第一銅膜22具有相同結構，故在此不再贅述。
將第一銅膜22之第一接合面221及第二銅膜24之第二接合面241以鹽酸水溶液(鹽酸與去離子水的體積比例為1：1)加以清洗後，分別將第一基板21與第二基板23置於夾具261,262上，並使第一接合面221與第二接合面241相對。而後，置於真空爐管中，以10-3 torr之低真空度，將爐管升溫至200℃接合並退火1小時，於接合期間適當調整加壓壓力，則可維持第一銅膜22與第二銅膜24及其接合處之雙晶結構。
經由上述製程，如圖2C所示，則可得到本實施例之具有雙晶銅之電性連接結構，其包括：一第一基板21；一第二基板23；以及接點25，係設於第一基板21與第二基板23間，其中接點25係由一第一銅膜22及一第二銅膜24相互接合而成，接點25之材料係為奈米雙晶銅層，該奈米雙晶銅層之50%以上的體積包括複數個晶粒。其中，第一銅膜22與第二銅膜24經接合後形成接點25，而其接合處以虛線表示。
圖6係為本實施例之具有雙晶銅之電性連接結構之接合處之聚焦離子束剖面圖；此結果顯示，以(111)面作為接合面時，第一銅膜22及第二銅膜24所形成之接點25其接合處並未見有接縫。
實施例2
圖7A至圖7B係為本實施例之具有雙晶銅之電性連接結構之製備流程剖面示意圖。
如圖7A及圖7B所示，於本實施例中，第一基 板21與第二基板23上係分別形成有複數第一銅膜22及複數第二銅膜24。在此，可搭配如黃光顯影之圖案化製程以及如實施例1所述之相同電鍍製程，以分別於第一基板21及第二基板23上形成複數第一銅膜22及複數第二銅膜24。其中，第一銅膜22及第二銅膜24分別包括複數個雙晶銅晶粒，該雙晶銅晶粒由複數個雙晶銅所組成，此奈米雙晶銅晶粒延伸到表面；且[111]晶軸係為垂直(111)面之軸。因此，第一銅膜22之第一接合面221與第二銅膜24之第二接合面241均為(111)面，(111)面之比例為100%，其電子背向散射繞射分析結果係與實施例1之圖4相同。
於本實施例中，第一基板21與第二基板23係同時為半導體晶片。同樣的，為了簡潔說明，僅以示意圖表示第一基板21與第二基板23之結構，其線路或其他部分並未揭示於圖式中。
以與實施例1相同之方法，如圖7A所示，將第一銅膜22之第一接合面221及第二銅膜24之第二接合面241以鹽酸水溶液(鹽酸與去離子水的體積比例為1：1)加以清洗後，分別將第一基板21與第二基板23置於夾具261,262上，並使第一接合面221與第二接合面241相對。而後，置於真空爐管中，以10-3 torr之低真空度，將爐管升溫至200℃接合並退火10分鐘至1小時，於接合期間適當調整加壓壓力，則可維持第一銅膜22與第二銅膜24及其接合處之雙晶結構。
經由上述製程，如圖7B所示，則可得到本實 施例之具有雙晶銅之電性連接結構，其包括：一第一基板21；一第二基板23；以及複數接點25，係設於第一基板21與第二基板23間，其中接點25之材料係為奈米雙晶銅，該奈米雙晶銅之50%以上的體積包括複數個晶粒。其中，第一銅膜22與第二銅膜24經接合後形成接點25，而其接合處以虛線表示。
實施例3
具(111)面之銅層之製作方法為在矽晶片上利用濺鍍方式先沉積厚度為100nm之鈦層(作為接著層)，之後在鈦層上利用電鍍方式沉積厚度為200nm之具(111)面之銅層，在此，可使用與先前描述相同之電鍍製程。於本實施例中，係使用艾克爾先進科技股份有限公司所提供之形成有具(111)面銅層之矽晶片。(111)之比例可藉由在矽晶片上之不同的接合層來控制，在此使用鈦做為接著(adhesion layer)層可獲得97%的(111)面。
圖8A至圖8C係為本實施例之電性連接結構之製備流程剖面示意圖；其中與實施例1不同之處主要在於使用具有前具包含97%(111)面之接合面之銅層取代奈米雙晶銅層。
如圖8A所示，首先提供一第一基板21，其係為一矽基板，且上方形成有一第一接著層221；其中，此第一接著層221係為一厚度為100nm之鈦金屬層。然而，本實施例之第一接著層僅為了用以將矽基板與後續於其上所形成之銅層有良好接合，可隨著不同基板材料不同，而選 用不同材料之接著層或不使用接著層。此外，於本實施例中，為了簡潔說明，僅以示意圖表示第一基板21之結構，其線路、主動元件、被動元件或其他部分並未揭示於圖式中。
而後，於第一基板21之第一接著層221上成長第一銅層22，此第一銅層22係為一具有為(111)面之銅層，且其厚度約200nm。
經由電子背向散射繞射(EBSD)分析後，如圖9所示，本實施例所製備之銅層表面有97%以上的面積皆為(111)面，藍色部分面積為(111)面。此外，經由穿透式電子顯微鏡(TEM)分析銅層之橫切面後，本實施例所製備之銅層呈現柱狀結構(柱狀晶體)，如圖10所示。再者，經X光繞射影像分析發現，銅層的長軸方向為[111]方向；且高解析穿透式電子顯微鏡(HRTEM)影像分析亦顯示銅層之橫切面亦顯示本實施例所製得之銅層表面為(111)平面，如圖11所示。
接著，請參閱圖8B，提供一第二基板23，其係為一矽基板，且上方形成有一第二接著層231。而後，於第二基板23之第二接著層231上成長第二銅層24，此第二銅層24係為一具有為(111)面之銅層，且其厚度約200nm。在此，第二接著層231與第二銅層24之製程、材料、厚度及功用係分別與前述之第一接著層211與第二銅層24相似，故在此不再贅述。此外，為了簡潔說明，僅以示意圖表示第二基板23之結構，其線路、主動元件、被動元件或 其他部分並未揭示於圖式中。
而後，如圖8B所示，將第一銅層22之第一接合面221及第二銅層24之第二接合面241以鹽酸水溶液(鹽酸與去離子水的體積比例為1：1)加以清洗後，分別將第一基板21與第二基板23置於夾具261,262上，並使第一接合面221與第二接合面241相對。而後，置於真空爐管中，以約10-3 torr之低真空度，將爐管升溫至200℃接合並退火一小時，於接合期間適當調整加壓壓力(約3kg/cm2 )。
經由上述製程，如圖8C所示，則可得到本實施例之具(111)但無雙晶銅之電性連接結構，其包括：一第一基板21；一第二基板23；以及接點25，係設於第一基板21與第二基板23間，其中接點25係由一第一銅層22及一第二銅層24相互接合而成，且於第一銅層22與第二銅層24間之接面係具有複數個晶粒，而晶粒係沿著[111]晶軸方向堆疊而成。其中，第一銅層22與第二銅層24經接合後形成接點25，而其接合處(即，接面)以虛線表示。
圖12係為本實施例之以銅層所形成之電性連接結構之TEM剖面結果；此結果顯示，雖未使用雙晶銅，但以具有(111)面作為接合面之銅層進行接合後，接合處(即，接面)並未見有接縫且仍保持柱狀晶粒結構。同時，經由HRTEM影像分析亦顯示銅層之橫切面亦顯示接合界面為晶界結構且無氧化層的存在，如圖11所示。
實施例4
請同時參考圖8A至圖8C，本實施例之材料、 製作流程及結構均與實施例3相同，除了本實施例之第一基板21上之第一銅層22係為一具有(111)面(第一接合面221)之多晶銅層，且其厚度約2μm；而第二基板23之第二銅層24則為不具有(111)面(第二接合面241)之銅層，且其厚度約2μm。此外，接合時之條件係為10-3 torr之低真空度，200℃之接合溫度，壓力約4kg/cm2 ，且接合時間為一小時。
圖13係為本實施例之電性連接結構之接合處之聚焦離子束(FIB)剖面圖。其結果顯示，雖未使用雙晶銅且僅一接合面221為(111)面，接合處(即，接面)仍未見有接縫。
前述結果顯示，當使用具有高度[111]優選方向之銅層，僅需其中一個接合面具有(111)面，無須兩個接合面均為(111)面，即可在低真空、低壓力及低溫下達到良好的熱壓接合結果，且接合界面無氧化層存在。同時，因接合溫度較低，故接合後的銅層(即，銅層)仍具有[111]優選方向之柱狀晶體結構。
實施例5
請同時參考圖8至圖8C，本實施例之材料、製作流程及結構均與實施例3相同，除了本實施例之第一基板21上之第一銅膜22以及第二基板23之第二銅膜24均為一奈米雙晶銅層，且其第一接合面221及第二接合面241均為含有97%之(111)面之接合面(以第一接合面221或第二接合面241之總面積為基準)。此外，接合時之條件係為10-3 torr之低真空度，250℃之接合溫度，壓力約100psi，且接合時間為10分鐘。
本實施例之銅層之電子背向散射繞射分析圖係與實施例3之圖9相同，可得知本實施例中之第一接合面221及第二接合面241均為含有97%之(111)面之接合面，藍色部分面積為(111)面。此外，如圖14之穿透式電子顯微鏡之明視野影像所示，接合處(即，接面)仍未見有接縫，且無孔洞產生。
實施例6
本實施例之材料、製作流程及結構均與實施例5相同，除了接合時之條件係為10-3 torr之低真空度，200°C之接合溫度，壓力約100psi，且接合時間為30分鐘。如圖15之穿透式電子顯微鏡之明視野影像所示，接合處(即，接面)仍未見有接縫，且無孔洞產生。
實施例7
本實施例之材料、製作流程及結構均與實施例5相同，除了接合時之條件係為10-3 torr之低真空度，150°C之接合溫度，壓力約100psi，且接合時間為60分鐘。如圖16之穿透式電子顯微鏡之明視野影像所示，接合處(即，接面)仍未見有接縫，且無孔洞產生。
實施例8
請同時參考圖8A至圖8C，本實施例之材料、製作流程及結構均與實施例3相同，除了本實施例之第一基板21上之第一銅膜22以及第二基板23之第二銅膜24 均為一奈米雙晶銅層，且其第一接合面221及第二接合面241均為含有64%之(111)面之接合面(以第一接合面221或第二接合面241之總面積為基準)。此外，接合時之條件係為10-3 torr之低真空度，200℃之接合溫度，壓力約100psi，且接合時間為30分鐘。
圖17係本實施例之銅層之電子背向散射繞射分析圖，可得知本實施例中之第一接合面221及第二接合面241均為含有64%之(111)面之接合面，藍色部分面積為(111)面。(111)之比例可藉由在矽晶片上之不同的接合層來控制，在此使用鈦鎢做為接著層可獲得64%的(111)面。此外，如圖18之穿透式電子顯微鏡之明視野影像所示，接合處(即，接面)仍未見有接縫，且無孔洞產生。
由前述結果顯示，當使用具有高度[111]優選方向之銅層，即便僅有50%之接合面為(111)面，仍可在低真空、低壓力及低溫下達到良好的熱壓接合結果，且接合界面無接縫及孔洞產生。同時，因接合溫度較低，故接合後的銅層(即，銅膜)仍具有[111]優選方向之柱狀晶體結構。
實施例9
請同時參考圖8A至圖8C，本實施例之材料、製作流程及結構均與實施例1相同，除了第二基板23之第二銅層24係以一金膜所取代，而第二基板23係為一依序層疊有二氧化矽層及鈦層之矽基板。其中，金膜係使用FCTD-0056-6 Microfab Au100電鍍液(向Electroplating Engineers of Japan Ltd.購買，室溫下以5ASD的電流密度之 直流電進行進行電鍍，形成厚度為100nm之金膜，此金膜具有(220)優選方向。此外，接合時之條件係為10-3 torr之低真空度，200℃之接合溫度，壓力約4kg/cm2 ，且接合時間為一小時。
圖19，為本實施例之電性連接結構之接合處之聚焦離子束(FIB)剖面圖。如圖19結果所示，具有(111)接合面之第一銅膜22(奈米雙晶銅膜)與金膜27的直接接合界面並無孔洞存在，此結果證實奈米雙晶銅膜與金膜的直接接合結果相當良好。
由前述結果顯示，當使用具有高度[111]優選方向之銅層，即便接合之第一金屬膜為其他異質材料之金屬層，仍可在低真空、低壓力及低溫下達到良好的熱壓接合結果，且接合界面無接縫及孔洞產生。同時，因接合溫度較低，故接合後的銅層(即，銅膜)仍具有[111]優選方向之柱狀晶體結構。
上述實施例僅係為了方便說明而舉例而已，本發明所主張之權利範圍自應以申請專利範圍所述為準，而非僅限於上述實施例。
21‧‧‧第一基板
22‧‧‧第一銅膜
23‧‧‧第二基板
24‧‧‧第二銅膜
25‧‧‧接點

Claims (20)

  1. 一種用以電性連接一第一基板及一第二基板之電性連接結構之製備方法，包括下列步驟：(A)提供一第一基板及一第二基板，其中該第一基板上係設有一第一銅膜，該第二基板上係設有一第一金屬膜，該第一銅膜之一第一接合面係為一含(111)面之接合面，且該第一金屬膜具有一第二接合面；以及(B)將該第一銅膜及該第一金屬膜相互接合以形成一接點，其中該第一銅膜之該第一接合面係與該第一金屬膜之該第二接合面相互對應。
  2. 如申請專利範圍第1項所述之製備方法，其中該第一銅膜之該第一接合面及該第一金屬膜之該第二接合面均為一含(111)面之接合面。
  3. 如申請專利範圍第1項所述之製備方法，其中該第一銅膜係包括複數具有(111)面之銅晶粒，以該銅晶粒之(111)面之法向量與接合面之法向量之角度為15度定為(111)面之基礎下，於該含(111)面之接合面中，以該含(111)面之接合面之總面積為基準，40-100%之總面積係為(111)面。
  4. 如申請專利範圍第1項所述之製備方法，其中該第一金屬膜之材料係選自由金、銀、鉑、鎳、銅、鈦、鋁及鈀所組成之群組。
  5. 如申請專利範圍第1項所述之製備方法，其中該第一金屬膜係為一第二銅膜。
  6. 如申請專利範圍第5項所述之製備方法，其中該第一銅膜及該第二銅膜之材料係分別為一接合面為(111)面之銅層、或一奈米雙晶銅層。
  7. 如申請專利範圍第1項所述之製備方法，其中於步驟(A)前更包括一步驟(A’)：以酸液清洗該第一銅膜之該第一接合面與該第一金屬膜之該第二接合面。
  8. 如申請專利範圍第6項所述之製備方法，其中該奈米雙晶銅層之50%以上的體積包括複數個晶粒。
  9. 如申請專利範圍第8項所述之製備方法，其中該晶粒係為柱狀雙晶體。
  10. 如申請專利範圍第8項所述之製備方法，其中該晶粒彼此間係互相連接，每一該晶粒係由複數個奈米雙晶銅沿著[111]晶軸方向堆疊而成，且相鄰之該晶粒間之[111]晶軸方向之夾角係0至20度。
  11. 如申請專利範圍第1項所述之製備方法，其中於步驟(B)中，係透過加壓以將該第一銅膜及該第一金屬膜相互接合。
  12. 如申請專利範圍第1項所述之製備方法，其中於步驟(B)中，係於100-400℃之溫度下，透過加壓以將該第一銅膜及該第一金屬膜相互接合。
  13. 如申請專利範圍第1項所述之製備方法，其中於步驟(B)中，係於1-10-3 torr真空度下將該第一銅膜及該第一金屬膜相互接合。
  14. 一種用以電性連接一第一基板及一第二基板之電性連接結構，包括：一第一基板；一第二基板；以及一接點，係設於該第一基板與該第二基板間，其中該接點係由一第一銅膜及一第一金屬膜相互接合而成，且於該第一銅膜與該第一金屬膜間之接面係包括複數個晶粒，而該晶粒係沿著[111]晶軸方向堆疊而成。
  15. 如申請專利範圍第14項所述之電性連接結構，其中該晶粒係為柱狀晶粒。
  16. 如申請專利範圍第14項所述之電性連接結構，其中該第一金屬膜之材料係選自由金、銀、鉑、鎳、銅、鈦、鋁及鈀所組成之群組。
  17. 如申請專利範圍第14項所述之電性連接結構，其中該第一銅膜之材料係為一接合面為(111)面之銅層、或一奈米雙晶銅層。
  18. 如申請專利範圍第17項所述之電性連接結構，其中該奈米雙晶銅層之50%以上的體積包括複數個晶粒。
  19. 如申請專利範圍第18項所述之電性連接結構，其中該晶粒係為柱狀雙晶體。
  20. 如申請專利範圍第18項所述之電性連接結構，其中該晶粒彼此間係互相連接，每一該晶粒係由複數個奈米雙晶銅沿著[111]晶軸方向堆疊而成，且相鄰之該晶粒間之[111]晶軸方向之夾角係0至20度。
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