TWI789864B - 電性連接結構及其製備方法 - Google Patents

電性連接結構及其製備方法 Download PDF

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TWI789864B
TWI789864B TW110129246A TW110129246A TWI789864B TW I789864 B TWI789864 B TW I789864B TW 110129246 A TW110129246 A TW 110129246A TW 110129246 A TW110129246 A TW 110129246A TW I789864 B TWI789864 B TW I789864B
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Taiwan
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nano
substrate
copper bump
electrical connection
twinned
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TW110129246A
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English (en)
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TW202308084A (zh
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陳智
王家俊
陳冠儒
謝昌志
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國立陽明交通大學
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Priority to TW110129246A priority Critical patent/TWI789864B/zh
Priority to US17/570,241 priority patent/US20230040128A1/en
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Publication of TWI789864B publication Critical patent/TWI789864B/zh
Publication of TW202308084A publication Critical patent/TW202308084A/zh

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Abstract

本揭露提供一種電性連接結構及其製備方法，其中電性連接結構包括：一第一基板；一第二基板；以及一接點，設置於第一基板與第二基板間，其中接點具有一寬度，且於寬度的50%以上的範圍內未存在一接合面。

Description

電性連接結構及其製備方法
本揭露關於一種電性連接結構及其製備方法，尤指一種具有高接點強度的電性連接結構及其製備方法。
隨著電子產業的蓬勃發展，對於具有體積小、重量輕、多功能且高性能之電子產品需求亦日益增加。於目前積體電路的發展上，為了將多種主動元件及被動元件設於同一個裝置上，現今多採用半導體封裝技術，以達到在有限的單位面積下容納更多數量的線路及電子元件之目的。
於封裝基板或電路板之堆疊中，可使用銅膜進行堆疊；但薄膜無凸塊結構，無法達成封裝工業接點需求。倘若以銅凸塊進行堆疊時，一般的材料晶格方向並無單一性，所形成的接點為多晶接點；但多晶接點其晶界面積比例較高，而容易產生電子散射使電阻上升，且接合處的機械強度較弱。倘若使用較貴的製程(例如：濺鍍)或較貴的材料(例如：銀)，雖然可得到具有高強度及高導電度的接點，但其成本較高而不易應用於工業製造上。
有鑑於此，目前亟需發展出一種電性連接結構及其製備方法，其可以較低的製備成本製作出去有高接點強度的電性連接結構。
本揭露提供一種具有高接點強度的電性連接結構及其製備方法。
本揭露的電性連接結構的製備方法，包括下列步驟：提供一第一基板及一第二基板，其中第一基板上設置有一第一奈米雙晶銅凸塊，第二基板上設置有一第二奈米雙晶銅凸塊，且第一奈米雙晶銅凸塊及第二奈米雙晶銅凸塊的50%以上的體積分別包括複數雙晶晶粒；以及於150°C至400°C的溫度下，接合第一奈米雙晶銅凸塊及第二奈米雙晶銅凸塊以形成一接點，其中接點具有一寬度，且於寬度的50%以上的範圍內未存在一接合面。
經由前述的製備方法，可得到本揭露的電性連接結構，其包括：一第一基板；一第二基板；以及一接點，設置於第一基板與第二基板間，其中接點具有一寬度，且於寬度的50%以上的範圍內未存在一接合面。
於本揭露中，藉由將兩基板上的奈米雙晶銅凸塊於特定的溫度範圍(150°C至400°C)下進行接合，除了可達到接合的目的外，更能使接點的至少部分接合面被削除，進而得到具有類單晶結構的接點。當接點的接合面越少，可有效提升接點的接合強度。同時，因接點具有類單晶結構而幾乎沒有晶界，更可有效降低接點的電阻，進而提升導電率。由於本揭露所提供的接點具有高接合強度及低電阻，可應用於各種電子產品上，且更能適用於高階電子的晶片封裝上。
於本揭露的電性連接結構中，於接點的寬度的50%以上的範圍內未存在一接合面。在此，可以接點的一剖面來測量接點所存在的接合面的多寡。
於本揭露的電性連接結構中，於接點的一剖面上，於接點的寬度的50%以上的範圍內未存在有接合面；特別是，於接點的寬度的50%以上的連續範圍內未存在有接合面。於本揭露的一實施例中，於接點的寬度的，例如，50%至100%、50%至99%、60%至99%、70%至99%、75%至99%、80%至99%、80%至95%、80%至90%或85%至90%的連續範圍內未存在有接合面。
於本揭露的電性連接結構中，接點的寬度可根據需求進行調整。於本揭露的一實施例中，接點的寬度可介於，例如，50 nm至50 μm、100 nm至50 μm、500 nm至50 μm、1 μm至50 μm、5 μm至50 μm、10 μm至50 μm、15 μm至50 μm、20 μm至50 μm、25 μm至50 μm、30 μm至50 μm、35 μm至50 μm或40 μm至50 μm之間。在此，所謂的接點的寬度是指，在與第一基板或第二基板的法線方向垂直的方向上，所量測而得的接點的寬度。
於本揭露的電性連接結構中，接點的厚度也可根據需求進行調整。於本揭露的一實施例中，接點的厚度可介於，例如，50 nm至50 μm、100 nm至50 μm、500 nm至50 μm、1 μm至50 μm、1 μm至40 μm、1 μm至30 μm、1 μm至25 μm、1 μm至20 μm、5 μm至20 μm或5 μm至15 μm之間。在此，所謂的接點的厚度是指，在第一基板或第二基板的法線方向上，所量測而得的接點的厚度。
於本揭露的製備方法中，於接合第一基板上的第一奈米雙晶銅凸塊及第二基板上的第二奈米雙晶銅凸塊形成接點時，第一奈米雙晶銅凸塊及第二奈米雙晶銅凸塊中的雙晶晶粒可進行再結晶。經由再結晶的過程，可使所得到的接點包括一單晶晶粒，且單晶晶粒可佔接點的50%以上的體積。因此，於本揭露的電性連接結構中，大部分的奈米雙晶晶粒已再結晶而形成單晶結構而不再具有奈米雙晶結構，故電性連接結構的接點是由設置於第一基板上的一第一銅凸塊及設置於第二基板上的一第二銅凸塊所接合而成。
於本揭露的電性連接結構中，單晶晶粒可佔接點的，例如，50%至100%、50%至99%、60%至99%、70%至99%、75%至99%、80%至99%、80%至95%、80%至90%或85%至90%的體積。
於本揭露的製備方法中，可於150°C至400°C的溫度下進行接合，例如，於150°C至350°C、150°C至300°C、175°C至300°C、175°C至275°C、200°C至275°C、200°C至250°C或 225°C至250°C的溫度下進行接合。當接合的溫度過低時，於接合的過程中無法使第一奈米雙晶銅凸塊及第二奈米雙晶銅凸塊中的雙晶晶粒進行再結晶，而無法形成包括單晶晶粒的接點。
於本揭露的製備方法中，可於200牛頓至500牛頓的壓力下進行接合。於本揭露的一實施例中，可於200牛頓至400牛頓或250牛頓至350牛頓的壓力下進行接合。
於本揭露的製備方法中，接合時間可依據第一奈米雙晶銅凸塊及第二奈米雙晶銅凸塊的大小進行調整，例如，接合時間可介於1分鐘至4小時。於本揭露的一實施例中，接合時間可為1小時至3小時。
於本揭露的製備方法中，第一及第二奈米雙晶銅凸塊可分別包括一雙晶銅層及一過度層，其中過度層位於雙晶銅層與第一/第二基板之間。其中，過度層的厚度可介於0.3 μm至1 μm之間，例如，可介於0.3 μm至0.8 μm、0.3 μm至0.7 μm、0.3 μm至0.6 μm、0.35 μm至0.6 μm、0.35 μm至0.55 μm、0.4 μm至0.55 μm或0.4 μm至0.5 μm之間。當過度層厚度過薄時，雙晶銅晶粒無法再結晶而成長跨越接合面，而無法得到接合面消除的電性連接結構。當過度層厚度過厚時，雙晶銅晶粒雖可以再結晶成長出大晶粒，但多數所成長的晶粒無法成長跨越接合面，而無法得到接合面消除的電性連接結構。在此，所謂的過度層為晶粒不具有優選方向的區域。
於本揭露的電性連接結構及其製備方法中，第一/第二基板上設置有一第一/第二絕緣層，第一/第二絕緣層包括一第一/第二凹槽，第一/第二奈米雙晶銅凸塊或第一/第二銅凸塊設於第一/第二凹槽中；其中第一/第二凹槽具有一第一/第二側壁，且第一/第二側壁與第一/第二基板的表面的夾角可介於70度至90度之間。
於本揭露的製備方法中，當第一/第二基板上的第一/第二絕緣層的第一/第二側壁與第一/第二基板的表面具有前述的夾角時，第一/第二絕緣層的第一/第二側壁可與第一/第二基板的表面垂直或接近垂直。當以電鍍法形成第一/第二奈米雙晶銅凸塊時，第一/第二奈米雙晶銅凸塊的雙晶銅層中的雙晶晶粒彼此間可互相連接，且每一雙晶晶粒可由奈米雙晶沿著[111]晶軸方向堆疊而成，而得到柱狀奈米雙晶晶粒。此外，由於第一/第二絕緣層的第一/第二側壁可與第一/第二基板的表面垂直或接近垂直，故於所得的第一/第二奈米雙晶銅凸塊中，相鄰的雙晶晶粒的[111]晶軸方向的夾角可介於0度至20度之間，使得第一/第二奈米雙晶銅凸塊的表面之50%以上的面積可顯露奈米雙晶之(111)面，而具有(111)的優選方向。
於本揭露中，第一/第二奈米雙晶銅凸塊的表面之50%以上的面積可顯露奈米雙晶之(111)面，而具有(111)的優選方向。於本揭露的一實施例中，顯露於第一/第二奈米雙晶銅凸塊的表面的奈米雙晶之(111)面可佔第一/第二奈米雙晶銅凸塊表面的總面積的，例如，50%至99%、55%至99%、60%至99%、65%至99%、70%至99%、75%至99%、75%至95%或75%至90%；但本揭露並不僅限於此。
於本揭露中，第一/第二奈米雙晶銅凸塊的雙晶銅層中相鄰的雙晶晶粒的[111]晶軸方向的夾角可介於0度至20度之間；換言之，第一/第二奈米雙晶銅凸塊的雙晶銅層中的雙晶晶粒可為與基板表面垂直或接近垂直的垂直柱狀晶粒。當第一/第二奈米雙晶銅凸塊的雙晶銅層中的雙晶晶粒為垂直或接近垂直的垂直柱狀晶粒時，於適當的溫度接合後，可形成本揭露的類單晶結構的接點。
於本揭露中，第一基板及第二基板可各自獨立為一半導體晶片、一封裝基板、或一電路板；且較佳為半導體晶片。據此，本發明之技術可應用於，例如覆晶封裝(Flip chip)、晶圓接合(wafer bonding)、晶圓級晶片封裝(wafer level chip scale packaging, WLCSP)等常見於IBM C4技術所衍生的各種封裝技術中，尤其是具高頻與高功率元件。特別是，本揭露之技術更可應用於需要高機械性質且產品可靠度之三維積體電路上。舉例而言，當第一基板及第二基板為半導體晶片時，經接合後則可形成所謂的三維積體電路(3D-IC)；此外，亦可將三維積體電路做為第一基板，且封裝基板做為第二基板進行接合。在此，僅用以舉例用，本揭露並不僅限於此。
於本揭露中，複數雙晶晶粒的直徑可分別介於0.1 μm至50 μm之間。於本揭露的一實施例中，雙晶晶粒的直徑，例如，可介於0.1 μm至45 μm、0.1 μm至40 μm、0.1 μm至35 μm、0.5 μm至35 μm、0.5 μm至30 μm、0.5 μm至25 μm、0.5 μm至20 μm、0.5 μm至15 μm、0.5 μm至10 μm、0.5 μm至5 μm、0.5 μm至3 μm或0.5 μm至2 μm之間；但本揭露並不僅限於此。於本揭露中，雙晶晶粒的直徑可為以與雙晶晶粒的雙晶方向實質上垂直的方向上所量測得到的長度；更詳細而言，雙晶晶粒的直徑可為在與雙晶晶粒的雙晶面的堆疊方向實質上垂直的方向上(也就是，雙晶面延伸方向)所量測得到的長度(例如，最大長度)。
於本揭露中，複數雙晶晶粒的厚度可分別介於0.1 μm至500 μm之間。於本揭露的一實施例中，雙晶晶粒的厚度，例如，可介於0.1 μm至500 μm、0.1 μm至400 μm、0.1 μm至300 μm、0.1 μm至200 μm、0.1 μm至100 μm、0.1 μm至80 μm、0.1 μm至50 μm、1 μm至50 μm、2 μm至50 μm、3 μm至50 μm、4 μm至50 μm、5 μm至50 μm、5 μm至40 μm、5 μm至35 μm、5 μm至30 μm或5 μm至25 μm之間。於本揭露中，雙晶晶粒的厚度可為以在雙晶晶粒的雙晶方向的方向上所量測得到的厚度；更詳細而言，雙晶晶粒的厚度可為在雙晶晶粒的雙晶面的堆疊方向上所量測得到的厚度(例如，最大厚度)。
於本揭露中，所謂的「雙晶晶粒的雙晶方向」是指雙晶晶粒中的雙晶面的堆疊方向。其中，雙晶晶粒的雙晶面可與雙晶面的堆疊方向實質上垂直。於本揭露中，雙晶晶粒是由複數雙晶沿著[111]晶軸方向堆疊而成。
於本揭露中，第一及第二奈米雙晶銅凸塊的寬度及厚度，可根據所欲形成的接點的寬度及厚度進行調整，以得到所需的接點的寬度及厚度。
於本揭露中，接點的前述特徵及奈米雙晶銅凸塊的前述特徵的量測方法並無特殊限制，可以掃描電子顯微鏡(Scanning electron microscope, SEM)、穿透式電子顯微鏡(Transmission electron microscope, TEM)、聚焦離子束系統(Focus ion beam，FIB)、背向散射電子繞射儀(Electron Backscatter Diffraction, EBSD)或其他適合手段來進行量測。
於本揭露中，第一及第二奈米雙晶銅凸塊的製備方法並無特殊限制，例如，可使用電鍍法製備而得。於本揭露的一實施例中，第一及第二奈米雙晶銅凸塊可透過下列步驟所製備：提供一電鍍裝置，該裝置包括一陽極、一陰極、一電鍍液、以及一電力供應源，電力供應源係分別與陽極及陰極連接，且陽極及陰極係浸泡於電鍍液中﹔以及使用電力供應源提供電力進行電鍍，由陰極之一表面成長奈米雙晶銅金屬層。
於本揭露中，陰極可為前述設置有第一/第二絕緣層的第一/第二基板。其中，第一/第二基板可為一表面具有金屬層之基板、或一金屬基板。其中，第一/第二基板可為一矽基板、一玻璃基板、一石英基板、一金屬基板、一塑膠基板、一印刷電路板、一三五族材料基板或其層疊基板；且第一/第二基板可具有單層或多層結構。
於本揭露中，電鍍液可包括：一銅的鹽化物、鹽酸及一鹽酸以外的酸。電鍍液中的銅的鹽類的例子可包括，但不限於，硫酸銅、甲基磺酸銅或其組合；而電鍍液中的酸的例子可包括，但不限於，硫酸、甲基磺酸或其組合。此外，電鍍液也可更包括一添加物，例如，明膠、介面活性劑、晶格修整劑或其組合。
於本揭露中，可採用直流電鍍、高速脈衝電鍍、或直流電鍍與高速脈衝電鍍二者交互使用為之，以形成奈米雙晶銅金屬層。於本揭露的一實施例中，是採用直流電鍍製備雙晶銅金屬層。其中，直流電鍍的電流密度可介於，例如0.5 ASD至30 ASD、1 ASD至30 ASD、2 ASD至30 ASD、2 ASD至25 ASD、3 ASD至25 ASD、3 ASD至20 ASD或4 ASD至20 ASD；但本揭露並不僅限於此。
下文將配合圖式並詳細說明，使本揭露的特徵更明顯。
以下提供本揭露的不同實施例。這些實施例是用於說明本揭露的技術內容，而非用於限制本揭露的權利範圍。一實施例的一特徵可透過合適的修飾、置換、組合、分離以應用於其他實施例。
應注意的是，在本文中，除了特別指明者之外，具備「一」元件不限於具備單一的該元件，而可具備一或更多的該元件。
在本文中，除了特別指明者之外，所謂的特徵甲「或」或「及/或」特徵乙，是指甲單獨存在、乙單獨存在、或甲與乙同時存在；所謂的特徵甲「及」或「與」或「且」特徵乙，是指甲與乙同時存在；所謂的「包括」、「包含」、「具有」、「含有」，是指包括但不限於此。
此外，在本文中，除了特別指明者之外，「一元件在另一元件上」或類似敘述不必然表示該元件接觸該另一元件。
此外，在本文中，除了特別指明者之外，一數值可涵蓋該數值的±10%的範圍，特別是該數值±5%的範圍。除了特別指明者之外，一數值範圍是由較小端點數、較小四分位數、中位數、較大四分位數、及較大端點數所定義的多個子範圍所組成。
圖1A及圖1B為顯示本揭露電性連接結構的製備方法的剖面示意圖。如圖1A所示，首先，提供一第一基板11及一第二基板21，其中第一基板11板上設置有一第一奈米雙晶銅凸塊13，第二基板21上設置有一第二奈米雙晶銅凸塊23，且第一奈米雙晶銅凸塊13及第二奈米雙晶銅凸塊23的50%以上的體積分別包括複數雙晶晶粒。
更詳細而言，第一基板11上設置有一第一絕緣層12，第一絕緣層12包括一第一凹槽121，第一奈米雙晶銅凸塊1設於第一凹槽121中；其中第一凹槽121具有一第一側壁122，且第一側壁122與第一基板11的一表面的夾角θ1介於70度至90度之間。此外，第二基板21上設置有一第二絕緣層22，第二絕緣層22包括一第二凹槽221，第二奈米雙晶銅凸塊23設於第二凹槽221中；其中第二凹槽221具有一第二側壁222，且第二側壁222與第二基板21的一表面的夾角θ2介於70度至90度之間。
而後，於150°C至400°C的溫度下，接合第一奈米雙晶銅凸塊13及第二奈米雙晶銅凸塊23以形成一接點3，其中該接點具有一寬度W，且於寬度W的50%以上的範圍內未存在一接合面33。
更詳細而言，於接合第一奈米雙晶銅凸塊13及第二奈米雙晶銅凸塊23形成接點3時，第一奈米雙晶銅凸塊13及第二奈米雙晶銅凸塊23中的雙晶晶粒係進行再結晶。因此，於所得到的電性連接結構中，第一奈米雙晶銅凸塊13轉換為雙晶晶界幾乎消除的第一銅凸塊31，第二奈米雙晶銅凸塊23也轉換為雙晶晶界幾乎消除的第二銅凸塊32，而所得到的接點3可視為由設置於第一基板11上的第一銅凸塊31及設置於第二基板21上的第二銅凸塊32所接合而成。
藉由前述製程，可得到本揭露的電性連接結構，包括：一第一基板11；一第二基板21；以及一接點3，設置於第一基板11與第二基板21間，其中接點3具有一寬度W，且於寬度W的50%以上的範圍內未存在一接合面33。特別是，於寬度W的一剖面上，於寬度W的50%以上的連續範圍內，未存在接合面33。此外，接點3包括一單晶晶粒，且單晶晶粒佔接點3的50%以上的體積。
實施例1
本實施例是將8吋之鍍有100 nm鈦鎢/200 nm 銅的矽晶圓作陰極進行電鍍，其中矽晶圓可視為圖1A及圖1B所示的第一基板11及第二基板21。此外，於矽晶圓上更形成有一絕緣層，且絕緣層具有一開口，此開口定義出後續形成奈米雙晶銅凸塊的區域。其中，絕緣層可視為圖1A及圖1B所示的第一絕緣層12及第二絕緣層22，而絕緣層的開口可視為第一凹槽121及第二凹槽221。在此，絕緣層的材料可為PBO、PI、SiO 2、SiCN、SiN、填充膠(underfill)、玻璃基矽 (Silicon On Glass, SOG)或其組合，於本實施例中，絕緣層的材料為SiO 2；絕緣層的厚度可為50奈米至50微米，且可透過電漿激發技術沈積(PECVD)或其他本技術領域常用的塗佈方法形成。
接著，進行奈米雙晶銅的電鍍製程。其中，電鍍液是由五水硫酸銅粉末、硫酸、鹽酸和添鴻公司所提供的108C添加劑所構成的。添加五水硫酸銅粉末196.61 g，再加入硫酸(96%)100 g、鹽酸0.1 ml及添加劑35 ml，最後再加入去離子水至總溶液為1L並且使用磁石攪拌直到溶液均勻混合。混合完成後將電鍍液倒入電鍍槽之中，設定磁石每分鐘1200轉以維持電鍍液之流動，在室溫一大氣壓下進行電鍍。以電腦操控電源供應器(Keithley 2400)，並採用直流電流電鍍為例，使用電流密度10 ASD(A/dm 2)電鍍10分鐘內，可以得到厚度(即為圖1A所示的厚度H1)約為6至8 µm且寬度(即為圖1A所示的寬度W)約為45 µm之柱狀晶粒奈米雙晶銅柱。其中，所得到的柱狀晶粒奈米雙晶銅柱可做為圖1A及圖1B所示的第一奈米雙晶銅凸塊13及第二奈米雙晶銅凸塊23。
圖2及圖3分別為本實施例的奈米雙晶銅凸塊的背向散射電子繞射儀的繞射圖及聚焦離子束影像圖。本實施例所得的柱狀晶粒奈米雙晶銅柱幾乎所有體積(97%以上的體積)均為彼此相互連接的柱狀雙晶晶粒，且柱狀雙晶晶粒的直徑約為0.87 μm，而過度層的厚度為0.3 μm。此外，雙晶晶粒是由奈米雙晶沿著[111]晶軸方向堆疊，相鄰的雙晶晶粒的[111]晶軸方向的夾角可約為0度，且奈米雙晶的雙晶面與基板表面實質上平行(即，奈米雙晶的堆疊方向與奈米雙晶銅柱的厚度方向(Y)實質上平行)，故幾乎所有的奈米雙晶銅柱的表面(97%以上的面積)均顯露奈米雙晶之(111)面，代表本實施例的奈米雙晶銅柱具有(111)的優選方向。再者，95%以上的雙晶晶粒的雙晶方向與奈米雙晶銅柱的厚度方向(Y)夾角約為0度，且95%以上的雙晶晶粒的雙晶方向與基板的表面夾角約為90度，代表雙晶晶粒的雙晶面與基板的表面實質上平行。此外，奈米雙晶銅柱中95%以上的雙晶晶粒的厚度約介於1 μm至20 μm之間。
而後，將矽晶圓進行背部拋光至剩下500 µm厚度以利熱壓接合時，紫外光顯微鏡可以穿透晶片並進行對位的動作。接者使用化學機械研磨(CMP)將銅柱表面糙度降低至2～5 nm以內。將表面研磨完成的矽晶圓分別切削成6 mm x 6 mm之上晶片與15 mm x15 mm的下晶片，使用熱檸檬酸清洗試片表面來去除氧化物，在真空壓力為10 -3torr之環境、250°C、300牛頓進行對位熱壓接合兩小時，則完成本實施例的電性連接結構。其中，電性連接結構的接點的厚度(即為圖1B所示的厚度H2)約為12至16 µm且寬度(即為圖1B所示的寬度W)約為45 µm。
使用背向散射電子繞射儀(EBSD)和聚焦離子束(FIB)來分別分析熱壓接合後所得到的接點的結構。圖4及圖5分別為本實施例的電性連接結構的背向散射電子繞射儀的繞射圖及聚焦離子束影像圖。如圖4所示，於250°C進行對位熱壓接合後，原先的奈米雙晶銅柱已經過再結晶而成長出異常大晶粒，而可得到類單晶接點，其接合面趨近80%皆被消除。同樣的，如圖5所示，接點幾乎無晶界被觀察到，且其接合面趨近80%皆被消除。
此結果顯示，經由於適當的溫度下進行熱壓接合製程後，可使奈米雙晶銅柱中的雙晶晶粒進行再結晶而成長出異常大晶粒，使得所得到的接點幾乎無晶界被觀察到；此外，異常大晶粒的成長可跨過接合面，使得銅柱間的接合面80%以上皆被消除。因此，在接點的寬度的80%以上的連續範圍內，均未存在有接合面，而得到類單晶結構的接點。
比較例1
本比較例的電性連接結構的製備方法與實施例1相似，其差異僅在於熱壓接合的溫度為150°C。圖6及圖7分別為本比較例的電性連接結構的背向散射電子繞射儀的繞射圖及聚焦離子束影像圖。
如圖6及圖7所示，於150°C進行熱壓接合時，雖然可將奈米雙晶銅柱成功接合，但奈米雙晶銅柱的雙晶晶粒仍維持很密的雙晶，且對接的奈米雙晶銅柱間的接合面也仍然存在。其原因在於，過度層的厚度較薄，但雙晶晶粒不夠小，故無法於此溫度下成長出大晶粒。
此外，更比較相同奈米雙晶銅凸塊於不同溫度、壓力及時間下接合後的拉身強度。結果如下表1所示。
表1
  接合溫度(°C) 接合壓力(MPa) 接合時間 拉伸強度(MPa)
實施例1 250 41.5 2小時 32.9
實施例2 200 41.5 2小時 19.89
實施例3 250 41.5 60秒 9.78
比較例1 150 41.5 2小時 0.82
如表1的結果所示，實施例1至3所得的電性連接結構具有最大的拉伸強度，明顯高於比較例1的電性連接結構。在此，需特別說明的是，實施例1的電性連接結構應大於32.9  MPa，這是由於試片皆未斷裂在接合介面，而是於矽基板產生脆斷。
實施例4
本實施例的奈米雙晶銅凸塊的製備方法與實施例1相似，主要差異如下。
首先，先於矽晶圓上以電漿激發技術沈積(PECVD)沉積一第一絕緣層，其中，第一絕緣的材料可為，例如SiO 2、SiCN、SiN或其組合；於本實施例中，是使用SiO 2。而後，再形成一第二絕緣層，其中第二絕緣層的材料可為正光阻或負光阻；並透過蝕刻方式圖案化第一絕緣層，以定義出可形成寬度介於50 nm 至 100 µm的區域。接著，將第二絕緣層清洗掉後，以與實施例1相同的方法進行電鍍，則可得到本實施例的奈米雙晶銅凸塊，且本實施例與實施例1的奈米雙晶銅凸塊具有類似的結構。此外，於本實施例中，除了接合面以外，奈米雙晶銅凸塊的周圍表面設有第一絕緣層。
接著，使用CMP將奈米雙晶銅凸塊表面平坦化後，透過與實施例1相同的熱壓接合製程，得到本實施例的電性連接結構。圖8為本實施例的電性連接結構的聚焦離子束影像圖，此結果顯示接合面50%以上皆被消除。
實施例5至10
本實施例的奈米雙晶銅凸塊的製備方法與實施例1相似，使用相同的電流密度但不同電鍍溫度（從0度至100度）使得得以控制晶粒尺寸以及過度層的厚薄。此外，透過與實施例1相似的熱壓接合製程，得到本實施例的電性連接結構，其中，實施例5至8的接合溫度為250°C且接合時間為2小時，實施例9的接合溫度為175°C且接合時間為90分鐘，而實施例10的接合溫度為150°C且接合時間為90分鐘。
圖9為本揭露實施例5至8的奈米雙晶銅凸塊的聚焦離子束影像圖，其中(a)至(d)分別為實施例5至8的奈米雙晶銅凸塊，其中，奈米雙晶銅凸塊包括一過度層311(即，虛線下方的區域)及一雙晶銅層312(即，虛線上方的區域)，且過度層311位於基板(圖未示)與雙晶銅層312間。如(a)所示，實施例5的奈米雙晶銅凸塊的過度層平均厚度約為0.23微米，且柱狀雙晶晶粒的直徑約為1.2至1.5微米；如(b)所示，實施例6的奈米雙晶銅凸塊的過度層平均厚度約為0.45微米 ，且柱狀雙晶晶粒的直徑約為1.2至1.5微米；如(c)所示，實施例7的奈米雙晶銅凸塊的過度層平均厚度約為1.1微米，且柱狀雙晶晶粒的直徑約為1.2至1.5微米；如(d)所示，實施例8的奈米雙晶銅凸塊的過度層平均厚度約為0.33微米 ，且柱狀雙晶晶粒的直徑約為0.71微米。
圖10為本揭露實施例5至8的電性連接結構的聚焦離子束影像圖，其中(a)至(d)分別為實施例5至8的電性連接結構。
如圖9(a)及圖10(a)所示，當過度層過薄時，大多數的晶粒無法成長跨越接合面，而無法得到接合面消除的電性連接結構。如圖9(b)及圖10(b)所示，當過度層具有適當厚度時，接合後過度層幾乎消除且大多數的晶粒可再結晶並成長跨越接合面，而得到接合面消除的電性連接結構，且可成長出異常大晶粒。然而，如圖9(c)及圖10(c)所示，當過度層過厚時，雖然有晶粒再結晶的情形，但多數所成長的晶粒無法成長跨越接合面，而無法得到接合面消除的電性連接結構。此外，如圖9(d)及圖10(d)所示，雖然過度層較薄(與圖9(a)所示的過度層厚度相近)，但因雙晶晶粒的尺寸較小，接合時因為晶粒較細且晶界較多使得內部系統能量升高，而可導致大晶粒成長並成長跨越接合面，得到接合面消除且過度層幾乎消除的電性連接結構。
圖11A及圖11B分別為本揭露實施例9及10的奈米雙晶銅凸塊的聚焦離子束影像圖。其中，實施例9的奈米雙晶銅凸塊的過度層平均厚度約為0.33微米，且柱狀雙晶晶粒的直徑約為0.74微米；實施例10的奈米雙晶銅凸塊的過度層平均厚度約為0.45微米，且柱狀雙晶晶粒的直徑約為0.52微米。
圖12A及圖12B分別為本揭露實施例9及10的電性連接結構的聚焦離子束影像圖。如圖12A及圖12B所示，當雙晶晶粒的尺寸較小，接合時因為晶粒較細且晶界較多使得內部系統能量升高，而可導致大晶粒成長並成長跨越接合面，得到接合面消除且過度層幾乎消除的電性連接結構。
由前述的結果顯示，當過度層厚度過薄時，雙晶銅晶粒無法再結晶而成長跨越接合面，而無法得到接合面消除的電性連接結構。當過度層厚度過厚時，雙晶銅晶粒雖可以再結晶成長出大晶粒，但多數所成長的晶粒無法成長跨越接合面，而無法得到接合面消除的電性連接結構。當過度層具有適當厚度時，若要在較低溫的接合溫度下得到接合面幾乎消除的電性連接結構，則需在過度層厚度較薄(但仍在適當後度範圍內)且雙晶晶粒較小的情形下進行；倘若過度層厚度較薄(但仍在適當厚度範圍內)且雙晶晶粒較大的情形下，則要在較高的接合溫度下以得到接合面幾乎消除的電性連接結構。
綜上所述，本揭露透過使用具有(111)優選表面的奈米雙晶銅凸塊，並於特定溫度(150°C至400°C)下進行熱壓接合，可使奈米雙晶銅凸塊中的雙晶再結晶而成長出異常大晶粒，且異常大晶粒的成長更可跨過接合面。此外，藉由使奈米雙晶銅中的過度層具有適當厚度或使奈米雙晶銅晶粒細化，亦可有助於使奈米雙晶銅凸塊中的雙晶再結晶而成長出異常大晶粒，且異常大晶粒的成長更可跨過接合面。因此，於本揭露所得到的電性連接結構中，幾乎未觀察到原先的奈米雙晶的晶界，且接點的接合面也大部分被消除。據此，本揭露的電性連接結構高強度、高導電率、高導熱率或高電遷移壽命，且製備成本也較低，因此很有潛力能應用於微電子三維積體電路封裝上。
11:第一基板 12:第一絕緣層 121:第一凹槽 122:第一側壁 13:第一奈米雙晶銅凸塊 21:第二基板 22:第二絕緣層 221:第二凹槽 222:第二側壁 23:第二奈米雙晶銅凸塊 3:接點 31:第一銅凸塊 311:過度層 312:雙晶銅層 32:第二銅凸塊 33:接合面 H1, H2:厚度 W:寬度 X, Y:座標軸 θ1, θ2:夾角
圖1A及圖1B為顯示本揭露電性連接結構的製備方法的剖面示意圖。 圖2為本揭露實施例1的奈米雙晶銅凸塊的背向散射電子繞射儀的繞射圖。 圖3為本揭露實施例1的奈米雙晶銅凸塊的聚焦離子束影像圖。 圖4為本揭露實施例1的電性連接結構的背向散射電子繞射儀的繞射圖。 圖5為本揭露實施例1的電性連接結構的聚焦離子束影像圖。 圖6為本揭露比較例1的電性連接結構的背向散射電子繞射儀的繞射圖。 圖7為本揭露比較例1的電性連接結構的聚焦離子束影像圖。 圖8為本揭露實施例4的電性連接結構的聚焦離子束影像圖。 圖9為本揭露實施例5至8的奈米雙晶銅凸塊的聚焦離子束影像圖；其中(a)為實施例5的奈米雙晶銅凸塊的聚焦離子束影像圖、(b)為實施例6的奈米雙晶銅凸塊的聚焦離子束影像圖、(c)為實施例7的奈米雙晶銅凸塊的聚焦離子束影像圖、(d)為實施例8的奈米雙晶銅凸塊的聚焦離子束影像圖。 圖10為本揭露實施例5至8的電性連接結構的聚焦離子束影像圖；其中(a)為實施例5的電性連接結構的聚焦離子束影像圖、(b)為實施例6的電性連接結構的聚焦離子束影像圖、(c)為實施例7的電性連接結構的聚焦離子束影像圖、(d)為實施例8的電性連接結構的聚焦離子束影像圖。 圖11A及圖11B分別為本揭露實施例9及10的奈米雙晶銅凸塊的聚焦離子束影像圖。 圖12A及圖12B分別為本揭露實施例9及10的電性連接結構的聚焦離子束影像圖。
無。
11:第一基板
12:第一絕緣層
21:第二基板
22:第二絕緣層
3:接點
31:第一銅凸塊
32:第二銅凸塊
33:接合面
H2:厚度
W:寬度
X,Y:座標軸

Claims (17)

  1. 一種電性連接結構，包括：一第一基板；一第二基板；以及一接點，設置於該第一基板與該第二基板間，其中該接點具有一寬度，且於該寬度的50%以上的範圍內未存在一接合面；其中，該接點是由設置於該第一基板上的一第一銅凸塊及設置於該第二基板上的一第二銅凸塊直接接合而成；其中，該接點包括一單晶晶粒，且該單晶晶粒佔該接點的50%以上的體積。
  2. 如請求項1所述的電性連接結構，其中，於該接點的一剖面上，於該寬度的50%以上的範圍內未存在該接合面。
  3. 如請求項2所述的電性連接結構，其中，於該寬度的50%以上的連續範圍內，未存在該接合面。
  4. 如請求項1所述的電性連接結構，其中，該接點的該寬度是介於50nm至50μm之間。
  5. 如請求項1所述的電性連接結構，其中，該接點的厚度是介於50nm至50μm之間。
  6. 如請求項1所述的電性連接結構，其中，該第一基板上設置有一第一絕緣層，該第一絕緣層包括一第一凹槽，該第一銅凸塊設於該第一凹槽中；其中該第一凹槽具有一第一側壁，且該第一側壁與該第一基板的一表面的夾角介於70度至90度之間。
  7. 如請求項1所述的電性連接結構，其中，該第二基板上設置有一第二絕緣層，該第二絕緣層包括一第二凹槽，該第二銅凸塊設於該第二凹槽中；其中該第二凹槽具有一第二側壁，且該第二側壁與該第二基板的一表面的夾角介於70度至90度之間。
  8. 一種電性連接結構的製備方法，包括下列步驟：提供一第一基板及一第二基板，其中該第一基板上設置有一第一奈米雙晶銅凸塊，該第二基板上設置有一第二奈米雙晶銅凸塊，且該第一奈米雙晶銅凸塊及該第二奈米雙晶銅凸塊的50%以上的體積分別包括複數雙晶晶粒；以及於150℃至400℃的溫度下，直接接合該第一奈米雙晶銅凸塊及該第二奈米雙晶銅凸塊以形成一接點，其中該第一奈米雙晶銅凸塊及該第二奈米雙晶銅凸塊中的該複數雙晶晶粒係進行再結晶，以使該接點包括一單晶晶粒；其中該接點具有一寬度，且於該寬度的50%以上的範圍內未存在一接合面，且該單晶晶粒佔該接點的50%以上的體積。
  9. 如請求項8所述的製備方法，其中於該接點的一剖面上，於該寬度的50%以上的範圍內未存在該接合面。
  10. 如請求項9所述的製備方法，其中於該寬度的50%以上的連續範圍內，未存在該接合面。
  11. 如請求項8所述的製備方法，其中，該接點的該寬度是介於50nm至50μm之間。
  12. 如請求項8所述的製備方法，其中，該接點的厚度是介於50nm至50μm之間。
  13. 如請求項8所述的製備方法，其中該第一基板上設置有一第一絕緣層，該第一絕緣層包括一第一凹槽，該第一奈米雙晶銅凸塊設於該第一凹槽中；其中該第一凹槽具有一第一側壁，且該第一側壁與該第一基板的一表面的夾角介於70度至90度之間。
  14. 如請求項8所述的製備方法，其中該第二基板上設置有一第二絕緣層，該第二絕緣層包括一第二凹槽，該第二奈米雙晶銅凸塊設於該第二凹槽中；其中該第二凹槽具有一第二側壁，且該第二側壁與該第二基板的一表面的夾角介於70度至90度之間。
  15. 如請求項8所述的製備方法，其中該第一奈米雙晶銅凸塊及該第二奈米雙晶銅凸塊的表面之50%以上的面積分別顯露奈米雙晶之(111)面。
  16. 如請求項8所述的製備方法，其中該複數雙晶晶粒彼此間係互相連接，且每一該複數雙晶晶粒係由複數奈米雙晶沿著[111]晶軸方向堆疊而成。
  17. 如請求項16所述的製備方法，其中相鄰的該複數雙晶晶粒的[111]晶軸方向的夾角是介於0度至20度之間。
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