TWI686518B - 具有奈米雙晶銅之電連接結構及其形成方法 - Google Patents

具有奈米雙晶銅之電連接結構及其形成方法 Download PDF

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Publication number
TWI686518B
TWI686518B TW108125724A TW108125724A TWI686518B TW I686518 B TWI686518 B TW I686518B TW 108125724 A TW108125724 A TW 108125724A TW 108125724 A TW108125724 A TW 108125724A TW I686518 B TWI686518 B TW I686518B
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Taiwan
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nano
copper layer
copper
grains
twinned
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TW108125724A
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English (en)
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TW202104689A (zh
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陳智
謝凱程
莊敬業
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國立交通大學
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Priority to TW108125724A priority Critical patent/TWI686518B/zh
Priority to CN201910941374.6A priority patent/CN112242311A/zh
Application granted granted Critical
Publication of TWI686518B publication Critical patent/TWI686518B/zh
Priority to US16/836,955 priority patent/US11145619B2/en
Publication of TW202104689A publication Critical patent/TW202104689A/zh
Priority to US17/447,294 priority patent/US11715721B2/en

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    • H01L2224/83359—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding

Abstract

一種形成具有奈米雙晶銅之電連接結構的方法，此方法包含：(i)形成第一奈米雙晶銅層，第一奈米雙晶銅層包含多個第一奈米雙晶銅晶粒；(ii)形成第二奈米雙晶銅層，第二奈米雙晶銅層包含多個第二奈米雙晶銅晶粒；以及(iii)接合第一奈米雙晶銅層之表面與第二奈米雙晶銅層之表面，使至少部分的第一奈米雙晶銅晶粒成長至第二奈米雙晶銅層中，或者至少部分的第二奈米雙晶銅晶粒成長至第一奈米雙晶銅層中。在此亦揭露一種奈米雙晶銅之電連接結構。

Description

具有奈米雙晶銅之電連接結構及 其形成方法
本發明是有關於一種電連接結構以及形成電連接結構的方法，且特別是有關於一種具有奈米雙晶銅之電連接結構以及形成該電連接結構的方法。
積體電路晶片及各種電子產品不斷往更小的尺寸發展，電子產品中不同電子元件之間的電連接也因此往更小的維度發展。微米或奈米等級的連接墊被廣泛地使用在各種電子產品的部件中，微米或奈米等級連接墊之間的接合變的非常重要，因為接合的品質直接影響最終電子產品的性能、品質和可靠度。當接合的尺度縮小，傳統的錫接點與銅所產生的介金屬化合物對於接合結構之機械性質造成不利影響的程度將增大，導致最終產品之可靠度下降，因此目前急需一種更佳的電連接結構及方法，以改善上述問題。
本發明之一態樣是提供一種形成具有奈米雙晶銅之電連接結構的方法，此方法包含：(i)形成一第一奈米雙晶銅層，第一奈米雙晶銅層包含多個第一奈米雙晶銅晶粒；(ii)形成一第二奈米雙晶銅層，第二奈米雙晶銅層包含多個第二奈米雙晶銅晶粒；以及(iii)接合第一奈米雙晶銅層之一表面與第二奈米雙晶銅層之一表面，並讓至少部分的第一奈米雙晶銅晶粒成長至第二奈米雙晶銅層中，或者至少部分的第二奈米雙晶銅晶粒成長至第一奈米雙晶銅層中。
在某些實施方式中，接合第一奈米雙晶銅層之表面與第二奈米雙晶銅層之表面形成一接合介面，其中至少部分的第一奈米雙晶銅晶粒成長超越接合介面，或者至少部分的第二奈米雙晶銅晶粒成長超越接合介面。
在某些實施方式中，第一及第二奈米雙晶銅晶粒實質上為柱狀，且第一及第二奈米雙晶銅晶粒之寬度小於5微米。
在某些實施方式中，接合第一奈米雙晶銅層之表面與第二奈米雙晶銅層之表面形成一接合介面，其中至少20%數量的第一奈米雙晶銅晶粒成長超越接合介面，或者至少20%數量的第二奈米雙 晶銅晶粒成長超越接合介面。
在某些實施方式中，成長超越接合介面的第一奈米雙晶銅晶粒越過接合介面的一高度為第二奈米雙晶銅層的一厚度的至少30%；或者成長超越接合介面的第二奈米雙晶銅晶粒越過接合介面的一高度為第一奈米雙晶銅層的一厚度的至少30%。
在某些實施方式中，接合第一奈米雙晶銅層之表面與第二奈米雙晶銅層之表面包含對第一奈米雙晶銅層及第一奈米雙晶銅層中的至少一者施加一壓力，使第一奈米雙晶銅層之表面與第二奈米雙晶銅層之表面在壓力作用下而接合，且所述壓力為約0.8Mpa至約3Mpa。
在某些實施方式中，所述壓力為約0.8Mpa至約1.5Mpa。
在某些實施方式中，接合第一奈米雙晶銅層之表面與第二奈米雙晶銅層之表面係在溫度為200℃至約350℃之環境下進行。
在某些實施方式中，接合第一奈米雙晶銅層之表面與第二奈米雙晶銅層之表面係在環境氣壓為約10-3托耳(torr)至約10-1托耳的環境下進行。
在某些實施方式中，接合第一奈米雙晶銅層之表面與第二奈米雙晶銅層之表面的接合時間係約1分鐘至約30分鐘。
在某些實施方式中，第一奈米雙晶銅晶 粒及第二奈米雙晶銅晶粒係沿著[111]晶軸方向堆疊形成。
在某些實施方式中，第一奈米雙晶銅層之表面及第二奈米雙晶銅層之表面包含(111)晶面。
本發明之另一樣態是提供一種具有奈米雙晶銅之電連接結構，此電連接結構一第一基材以及一第二基材。第一基材具有一第一奈米雙晶銅層，其中第一奈米雙晶銅層包含多個第一奈米雙晶銅晶粒。第二基材具有一第二奈米雙晶銅層，第二奈米雙晶銅層包含多個第二奈米雙晶銅晶粒。第一奈米雙晶銅層與第二奈米雙晶銅層接合。至少部分的第一奈米雙晶銅晶粒延伸至第二奈米雙晶銅層中，或者至少部分的第二奈米雙晶銅晶粒延伸至第一奈米雙晶銅層中。
在某些實施方式中，第一基材與第二基材各自包含一氧化物層和一金屬層，其中第一奈米雙晶銅層位於第一基材的金屬層上，第二奈米雙晶銅層位於第二基材的金屬層上。
在某些實施方式中，上述連接結構更包括位於第一奈米雙晶銅層與第二奈米雙晶銅層之間的一接合介面，至少20%數量的第一奈米雙晶銅晶粒延伸超越接合介面，或者至少20%數量的第二奈米雙晶銅晶粒延伸超越接合介面。
在某些實施方式中，延伸超越接合介面 的第一奈米雙晶銅晶粒越過接合介面的一高度為第二奈米雙晶銅層的一厚度的至少30%；或者延伸超越接合介面的第二奈米雙晶銅晶粒越過接合介面的一高度為第一奈米雙晶銅層的一厚度的至少30%。
在某些實施方式中，第一奈米雙晶銅晶粒越過接合介面的高度為約0.1微米至約20微米之間。
在某些實施方式中，第一及第二奈米雙晶銅晶粒實質上為柱狀。
在某些實施方式中，第一及第二奈米雙晶銅晶粒之寬度小於5微米。
在某些實施方式中，第一及第二奈米雙晶銅晶粒係沿著[111]晶軸方向堆疊而成。
10‧‧‧方法
12‧‧‧操作
14‧‧‧操作
16‧‧‧操作
100‧‧‧第一基板
102‧‧‧第一基板
104‧‧‧氧化物層
106‧‧‧第一金屬層
110‧‧‧第一奈米雙晶銅層
112‧‧‧第一奈米雙晶銅晶粒
114‧‧‧表面
200‧‧‧第二前驅基板
202‧‧‧第二基板
204‧‧‧第二氧化物層
206‧‧‧第二金屬層
210‧‧‧第二奈米雙晶銅層
212‧‧‧第二奈米雙晶銅晶粒
214‧‧‧表面
310‧‧‧接合介面
400‧‧‧電連接結構
410‧‧‧第一基材
411‧‧‧第一奈米雙晶銅層
413‧‧‧第一奈米雙晶銅晶粒
415‧‧‧基板
417‧‧‧金屬層
419‧‧‧氧化物層
420‧‧‧第二基材
422‧‧‧第二奈米雙晶銅層
423‧‧‧第二奈米雙晶銅晶粒
425‧‧‧基板
427‧‧‧金屬層
429‧‧‧氧化物層
430‧‧‧同化奈米雙晶銅晶粒
440‧‧‧接合介面
J‧‧‧接合接面
H1、H2‧‧‧高度
T1、T2‧‧‧厚度
d1、d2‧‧‧寬度
第1圖繪示根據本發明各種實施方式之形成具有奈米雙晶銅之電連接結構的方法的流程圖。
第2圖繪示根據本發明某些實施方式之方法在某一製程階段的剖面示意圖。
第3圖為本發明某一實施例所形成之第一奈米雙晶銅層的聚焦離子束(FIB)影像圖。
第4圖繪示根據本發明某些實施方式之方法在某一製程階段的剖面示意圖。
第5圖為本發明某一實施例所形成的連接結構 之聚焦離子束影像圖。
第6圖繪示本發明各種實施方式之電連接結構的剖面示意圖。
為了使本揭示內容的敘述更加詳盡與完備，下文針對了本發明的實施態樣與具體實施例提出了說明性的描述；但這並非實施或運用本發明具體實施例的唯一形式。以下所揭露的各實施例，在有益的情形下可相互組合或取代，也可在一實施例中附加其他的實施例，而無須進一步的記載或說明。
在以下描述中，將詳細敘述許多特定細節以使讀者能夠充分理解以下的實施例。然而，可在無此等特定細節之情況下實踐本發明之實施例。在其他情況下，為簡化圖式，熟知的結構與裝置僅示意性地繪示於圖中。
在本文中使用空間相對用語，例如「下方」、「之下」、「上方」、「之上」等，這是為了便於敘述一元件或特徵與另一元件或特徵之間的相對關係，如圖中所繪示。這些空間上的相對用語的真實意義包含其他的方位。例如，當圖示上下翻轉180度時，一元件與另一元件之間的關係，可能從「下方」、「之下」變成「上方」、「之上」。此外，本文中所使用的空間上的相對敘述也應作同樣的解釋。
本發明之一態樣是提供一種形成具有奈 米雙晶銅之電連接結構的方法。第1圖繪示根據本發明各種實施方式之形成具有奈米雙晶銅之電連接結構的方法10的流程圖。方法10包含操作12、操作14及操作16。第2及4圖繪示本發明某些實施方式之方法10在不同製程階段的剖面示意圖。
在操作12中，形成第一奈米雙晶銅層110，如第2圖所示。第一奈米雙晶銅層110包含多個第一奈米雙晶銅晶粒112。在各種實施方式中，第一奈米雙晶銅層110形成於第一前驅基板100之上。舉例而言，第一前驅基板100包含第一基板102及第一金屬層106。第一金屬層106是有助於形成奈米雙晶銅的底層。在一實例中，第一金屬層106包含鈦層以及形成在鈦層上的銅層，上述鈦層及銅層可使用例如物理氣相沉積(例如濺鍍製程)或化學鍍等適合的沉積方法形成，鈦層及銅層各自的厚度可例如為數十奈米至數百奈米。第一基板102可以是任何適當的基材，例如矽基板、陶瓷基板、玻璃纖維基板、印製電路板、金屬基板、塑膠基板等。當第一基板102為矽晶片或晶圓時，第一基板102上可以形成氧化物層104，例如氧化矽，而第一金屬層106形成在氧化物層104上。
在某些實施方式中，可以使用電鍍製程在第一前驅基板100的第一金屬層106上形成具有(111)晶面的第一奈米雙晶銅層110。在具體實施例 中，電鍍液包含50g/L的Cu2+、100g/L的SO4 2+、50ppm的Cl-以及4.5mL/L的添加劑(添鴻科技，型號041)。電鍍的電流密度為4-8A/dm2(ASD)，電鍍溫度為25+/-3℃，電鍍時間為約5分鐘，電鍍過程中電鍍液的攪拌速率為1200rpm。於電鍍過程中，第一奈米雙晶銅層110係沿著[111]晶軸方向堆疊生長，且第一奈米雙晶銅層110的表面114生長為(111)晶面。
詳細而言，第一奈米雙晶銅層110中形成多個第一奈米雙晶銅晶粒112。各第一奈米雙晶銅晶粒112實質上為柱狀。亦即，第一奈米雙晶銅晶粒112實質上為柱狀雙晶體(columnar twinned grain)，且彼此相鄰排列。在某些實施方式中，第一奈米雙晶銅晶粒112的寬度d1小於約5微米，較佳為約0.1微米至約2微米。例如為約0.1、0.2、0.5、0.8、1.0、1.5、2、2.5、3.0、3.5、4.0微米。此處，「寬度」是指柱狀奈米雙晶銅晶粒112的徑向寬度。根據多個實施例，當第一奈米雙晶銅晶粒112的寬度d1在上述範圍內，有益於特殊的技術效果，下文將更詳細敘述。
依據本發明某些實施方式，於電鍍形成第一奈米雙晶銅層110之後，可以選擇地執行平坦化製程，以降低第一奈米雙晶銅層110之表面114的粗糙度。在某些實施例中，平坦化製程可使用化學機械研磨技術來執行。執行平坦化製程後，第一奈米雙晶銅層110的表面114的粗糙度為約0.5nm至約10 nm(Ra)；例如為約1nm、2nm、3nm、4nm或5nm。，執行平坦化製程後，第一奈米雙晶銅層110的厚度T1為約數十奈米至約數十微米，例如約0.5μm至約10μm。
第3圖為本發明某一實施例所形成之第一奈米雙晶銅層的聚焦離子束(FIB)影像圖。由圖中清楚看出柱狀雙晶晶粒的晶界以及各柱狀雙晶晶粒中之雙晶銅層的堆疊結構。
在操作14中，形成第二奈米雙晶銅層210，如第2圖所示。在某些實施方式中，第二奈米雙晶銅層210形成於第二前驅基板200之上。第二前驅基板200的具體實施方式，可與上述第一前驅基板100相同或相似。例如，第二前驅基板200包含第二基板202、第二氧化物層204及第二金屬層206。形成的第二奈米雙晶銅晶粒212具體方法可與上述形成第一奈米雙晶銅層110的方法相同或相似。簡言之，可以使用電鍍製程在第二前驅基板200上形成第二奈米雙晶銅層210。第二奈米雙晶銅層210係沿著[111]晶軸方向堆疊生長，第二奈米雙晶銅層210的表面214生長為(111)晶面。第二奈米雙晶銅層210包含多個第二奈米雙晶銅晶粒212。各第二奈米雙晶銅晶粒212實質上為柱狀。在某些實施方式中，第二奈米雙晶銅晶粒212的寬度d2小於約5微米，較佳為約0.1微米至約2微米。例如為約0.1、0.2、0.5、0.8、1.0、 1.5、2、2.5、3.0、3.5、4.0微米。根據多個實施例，當第二奈米雙晶銅晶粒212的寬度d2在上述範圍內，有益於特殊的技術效果，下文將更詳細敘述。
在某些實施例中，第二奈米雙晶銅晶粒212的寬度d2與第一奈米雙晶銅晶粒112的寬度d1為相同數量級。在具體實例中，第二奈米雙晶銅晶粒212的寬度d2大致上相同或相當第一奈米雙晶銅晶粒112的寬度d1。此處所述「相同」或「相當」的意義是指寬度d1的平均值與寬度d2的平均值之間的差異在+/-50%內(更明確地是在+/-30%內)，或本技術領域通常知識者所認知的範圍內。但在其他實施例中，第二奈米雙晶銅晶粒212的寬度d2可以大於或小於第一奈米雙晶銅晶粒112的寬度d1。
在使用電鍍製程形成第二奈米雙晶銅層210之後，可以選擇地執行平坦化製程，以降低第二奈米雙晶銅層210之表面214的粗糙度。執行平坦化製程後，第二奈米雙晶銅層210的表面214的粗糙度為約0.5nm至約10nm(Ra)，較佳為約0.5nm至約5nm，例如為約1nm、2nm、3nm、4nm或5nm。執行平坦化製程後，第二奈米雙晶銅層210的厚度T2為約數十奈米至約數十微米，例如約0.5μm至約10μm。第二奈米雙晶銅層210的厚度T2可以相同或不同於第一奈米雙晶銅層110的厚度T1。
依據本發明的某些實施方式，在形成第 一奈米雙晶銅層110及/或形成第二奈米雙晶銅層210之後，可以對第一奈米雙晶銅層110及/或第二奈米雙晶銅層210執行清洗製程，例如，將所形成的第一奈米雙晶銅層110及/或形成第二奈米雙晶銅層210浸泡在約50~80℃的飽和檸檬酸溶液中約30-120秒。之後，再以去離子水沖洗，並以氮氣吹乾。
上述操作12及操作14的執行順序並無限制。例如，可先執行操作12，之後執行操作14。或者，先執行操作14，之後執行操作12。或者，可並行地或同時地執行操作12及操作14。
在操作16中，如第4圖所示，接合第一奈米雙晶銅層110之表面114與第二奈米雙晶銅層210之表面214，並讓至少部分數量的第一奈米雙晶銅晶粒112成長至第二奈米雙晶銅層210中；或者至少部分數量的第二奈米雙晶銅晶粒212成長至第一奈米雙晶銅層110中。
在某些實施方式中，對第一奈米雙晶銅層110及第一奈米雙晶銅層110中的至少一者施加壓力，使第一奈米雙晶銅層110之表面114與第二奈米雙晶銅層210之表面214在壓力作用下而接合。例如，可對第一前驅基板100及/或第二前驅基板200的背面施加約0.8Mpa至約3Mpa的壓力，讓第一奈米雙晶銅層110之表面114與第二奈米雙晶銅層210之表面214在約0.8Mpa至約3Mpa壓力的作用下接 合。在多個實施例中，壓力為約0.8Mpa至約1.5Mpa，例如約0.8Mpa、1.0Mpa、1.2Mpa或1.5Mpa。在某些實施方式中，接合第一奈米雙晶銅層110之表面114與第二奈米雙晶銅層210之表面214係在溫度為約200℃至約350℃之環境下進行。較佳的溫度範圍為約250℃至約320℃，例如約250℃、280℃、300℃或320℃。在某些實施方式中，上述接合第一奈米雙晶銅層110與第二奈米雙晶銅層210係在環境氣壓為約10-3托耳(torr)至約10-1托耳的真空環境下進行。在某些實施方式中，接合時間係約1分鐘至約30分鐘。上述的製程條件將提供有益的技術效果，下文將更詳細敘述。
如第4圖所示，接合後，一部分的第一奈米雙晶銅晶粒112和第二奈米雙晶銅晶粒212彼此合併，而形成一個跨越原本接合接面J的奈米雙晶銅晶粒(下文稱為「同化奈米雙晶銅晶粒」)，例如第4圖標示的112a、112b。換言之，至少部分數量的第一奈米雙晶銅晶粒112成長且合併對向的第二奈米雙晶銅晶粒212，而成長延伸至第二奈米雙晶銅層210中。或者，至少部分數量的第二奈米雙晶銅晶粒212成長且合併對向的第一奈米雙晶銅晶粒112，而成長延伸至第一奈米雙晶銅層110中，例如第4圖標示的212c、212d。因此，在某些實施方式中，接合後的第一奈米雙晶銅層110之表面114與第二奈米雙晶銅 層210之表面214形成不連續的接合介面310。請注意，接合後之「同化奈米雙晶銅晶粒」(第4圖標示的112a、112b、212c、212d)仍然保持雙晶銅的堆疊結構，而且「同化奈米雙晶銅晶粒」的寬度與第一及/或第二奈米雙晶銅晶粒112、212的寬度為相同數量級。
在某些實施方式中，至少20%數量(例如20%、30%、40%、50%、60%、80%或100%)的第一奈米雙晶銅晶粒112成長超越接合介面310(例如第4圖標示的112a、112b)，或者至少20%數量(例如20%、30%、40%、50%、60%、80%或100%)的第二奈米雙晶銅晶粒212成長超越接合介面310(例如第4圖標示的212c、212d)。根據另外某些實施方式，當大部分的第一奈米雙晶銅晶粒112和第二奈米雙晶銅晶粒212都互相合併，例如大於60%數量的第一及/或第二奈米雙晶銅晶粒112、212合併形成「同化奈米雙晶銅晶粒」，原本的接合接面將會變的不明顯，而讓原本的接合接面不易被觀察到。
在多個實施例中，在接合製程後，第二奈米雙晶銅晶粒212向第一奈米雙晶銅晶粒112方向成長所形成的「同化奈米雙晶銅晶粒」212c、212d超越接合介面310的高度H2是第一奈米雙晶銅層110的厚度T1的至少30%，例如35%、40%、45%、50%、55%、60%、65%、70%、75%、80%、85%、90 %、95%或100%。或者，第一奈米雙晶銅晶粒112向第二奈米雙晶銅晶粒212方向成長所形成的「同化奈米雙晶銅晶粒」112a、112b超越接合介面310的高度H1是第二奈米雙晶銅層210的厚度T2的至少30%，例如35%、40%、45%、50%、55%、60%、65%、70%、75%、80%、85%、90%、95%或100%。在另外某些實施方式中，部分數量的「同化奈米雙晶銅晶粒」貫穿第一及第二奈米雙晶銅層110、210，因此部分數量的「同化奈米雙晶銅晶粒」的高度為第一及第二奈米雙晶銅層的厚度T1、T2之總和。
第5圖為本發明某一實施例進行操作16後的連接結構之聚焦離子束影像圖。為了讓本領域技術人員能夠更容易理解本發明的特徵，第5圖中標示接合接面J，並以實線繪示出「同化奈米雙晶銅晶粒」290。
如上所述，上述的製程條件及特徵將提供有益的技術效果。例如，第一奈米雙晶銅晶粒112的寬度d1小於約5微米(較佳為約0.1微米至約2微米)以及第二奈米雙晶銅晶粒212的寬度d2小於約5微米(較佳為約0.1微米至約2微米)有益於讓第一及第二奈米雙晶銅晶粒合併而形成「同化奈米雙晶銅晶粒」。當第一及第二奈米雙晶銅晶粒太大時，會造成第一及第二奈米雙晶銅晶粒合併時的障礙。又例如，第一奈米雙晶銅層110與第二奈米雙晶銅層210 在約0.8Mpa至約3Mpa壓力的作用下接合(較佳為約0.8Mpa至約1.5Mpa)，也有益於讓第一及第二奈米雙晶銅晶粒合併。再例如，在溫度為約200℃至約350℃之環境下進行接合，較佳為約250℃至約320℃，有助於讓第一及第二奈米雙晶銅晶粒合併，並維持奈米雙晶銅晶體的結構及晶粒尺寸。再例如，奈米雙晶銅層表面的粗糙度較佳為約0.5nm至約5nm，也有益於讓第一及第二奈米雙晶銅晶粒成長互相合併。
由以上揭露的內容，本發明所屬技術領域的技術人員可以理解，因為一側的奈米雙晶銅晶粒成長至相對側的奈米雙晶銅晶粒，並且發生合併或同化的現象，讓所形成的連接結構能夠具有更好的機械強度、導電性、穩定性及可靠度。
本發明之另一樣態是提供一種具有奈米雙晶銅之電連接結構。第6圖繪示本發明各種實施方式之電連接結構400的剖面示意圖。電連接結構400包含第一基材410及第二基材420。
第一基材410包含第一奈米雙晶銅層411，且第一奈米雙晶銅層411中包含多個第一奈米雙晶銅晶粒413。類似地，第二基材420包含第二奈米雙晶銅層422，第二奈米雙晶銅層422包含多個第二奈米雙晶銅晶粒423。第一奈米雙晶銅層411與第二奈米雙晶銅層422接合連接。在多個實施方式中， 上述第一及第二奈米雙晶銅晶粒411、423實質上為柱狀，且第一及第二奈米雙晶銅晶粒411、423的寬度d1、d2小於約5微米，較佳為約0.1微米至約2微米。在各種實施方式中，第一及第二奈米雙晶銅晶粒411、423係沿著[111]晶軸方向堆疊而成。
請注意，部分數量的第一奈米雙晶銅晶粒413延伸至第二奈米雙晶銅層422中，例如第6圖標示的413a及413b。延伸至第二奈米雙晶銅層422的第一奈米雙晶銅晶粒413a及413b也可稱為「同化奈米雙晶銅晶粒」。類似地，部分數量的第二奈米雙晶銅晶粒423延伸至第一奈米雙晶銅層411中，例如第6圖標示的423c及423d。延伸至第一奈米雙晶銅層411的第二奈米雙晶銅晶粒423c及423d也可稱為「同化奈米雙晶銅晶粒」。
此外，在某些實施方式中，部分數量的「同化奈米雙晶銅晶粒」貫穿第一及第二奈米雙晶銅層422、411，例如第6圖標示的430，因此同化奈米雙晶銅晶粒430可以被視為第一奈米雙晶銅晶粒413的延伸，也可以被視為第二奈米雙晶銅晶粒423的延伸。同化奈米雙晶銅晶粒430的高度為第一及第二奈米雙晶銅層411、422的厚度T1、T2之總和。
在某些實施方式中，電連接結構400還包含位於第一奈米雙晶銅層411與第二奈米雙晶銅層422之間的不連續的接合介面440。上述同化奈米雙 晶銅晶粒413a、413b、423c、423d及430貫穿接合介面440，而讓接合介面440成為不連續。
在某些實施方式中，至少20%數量的第一奈米雙晶銅晶粒(例如奈米雙晶銅晶粒413a、413b)成長超越接合介面440，或者至少20%數量的第二奈米雙晶銅晶粒(例如奈米雙晶銅晶粒423c、423d)成長超越接合介面440。
請再參照第6圖，第一奈米雙晶銅晶粒413a、413b越過接合介面440的高度H1為第二奈米雙晶銅層422的厚度T2的至少30%，例如35%、40%、45%、50%、55%、60%、65%、70%、75%、80%、85%、90%、95%或100%。或者，延伸超越接合介面440的第二奈米雙晶銅晶粒423c、423d越過接合介面440的高度H2為第一奈米雙晶銅層411的厚度T1的至少30%，例如35%、40%、45%、50%、55%、60%、65%、70%、75%、80%、85%、90%、95%或100%。在具體實例中，第一奈米雙晶銅晶粒413a、413b越過接合介面440的高度H1及/或第二奈米雙晶銅晶粒423c、423d越過接合介面440的高度H2為約0.1微米至約20微米之間，例如0.1微米、0.3微米、0.5微米、0.8微米、1.0微米、1.5微米、1.8微米、2.0微米、2.5微米、3.0微米、5微米、10微米、或15微米。
在某些實施方式中，第一基材410還包含 基板415以及基板415上的金屬層417。金屬層417有助於形成奈米雙晶銅的底層，金屬層417可以包含多個子層。在一實例中，使用濺鍍方式依序形成鈦層和銅層，因此金屬層417中的銅層並不具有奈米雙晶銅晶粒。第一奈米雙晶銅層411接觸金屬層417中的銅層。在某些實例中，第一基材410還包含氧化物層419，位於基板415與金屬層417之間。
類似地，第二基材420還包含基板425以及基板425上的金屬層427。金屬層427可以包含鈦層以及形成在鈦層上的銅層。第二奈米雙晶銅層422接觸金屬層427中的銅層。在某些實例中，第二基材420還包含氧化物層429，位於基板425與金屬層427之間。
10‧‧‧方法
12‧‧‧操作
14‧‧‧操作
16‧‧‧操作

Claims (20)

  1. 一種具有奈米雙晶銅之電連接結構的形成方法，包含：形成一第一奈米雙晶銅層，該第一奈米雙晶銅層包含多個第一奈米雙晶銅晶粒；形成一第二奈米雙晶銅層，該第二奈米雙晶銅層包含多個第二奈米雙晶銅晶粒；以及接合該第一奈米雙晶銅層之一表面與該第二奈米雙晶銅層之一表面，並讓至少部分的該些第一奈米雙晶銅晶粒成長至該第二奈米雙晶銅層中，或者至少部分的該些第二奈米雙晶銅晶粒成長至該第一奈米雙晶銅層中。
  2. 如請求項1所述之方法，其中接合該第一奈米雙晶銅層之該表面與該第二奈米雙晶銅層之該表面形成一接合介面，其中至少部分的該些第一奈米雙晶銅晶粒成長超越該接合介面，或者至少部分的該些第二奈米雙晶銅晶粒成長超越該接合介面。
  3. 如請求項1所述之方法，其中該些第一及該些第二奈米雙晶銅晶粒實質上為柱狀，且該些第一及該些第二奈米雙晶銅晶粒之寬度小於5微米。
  4. 如請求項1所述之方法，其中接合該第一奈米雙晶銅層之該表面與該第二奈米雙晶銅層之該表面形成一接合介面，其中至少20%數量的該些第一奈米雙晶銅晶粒成長超越該接合介面，或者至少20%數量的該些第二奈米雙晶銅晶粒成長超越該接合介面。
  5. 如請求項4所述之方法，其中成長超越該接合介面的各該第一奈米雙晶銅晶粒越過該接合介面的一高度為該第二奈米雙晶銅層的一厚度的至少30%；或者成長超越該接合介面的各該第二奈米雙晶銅晶粒越過該接合介面的一高度為該第一奈米雙晶銅層的一厚度的至少30%。
  6. 如請求項1所述之方法，其中接合該第一奈米雙晶銅層之該表面與該第二奈米雙晶銅層之該表面包含對該第一奈米雙晶銅層及該第一奈米雙晶銅層中的至少一者施加一壓力，使該第一奈米雙晶銅層之該表面與該第二奈米雙晶銅層之該表面在該壓力作用下而接合，且該壓力為約0.8Mpa至約3Mpa。
  7. 如請求項6所述之方法，其中該壓力為約0.8Mpa至約1.5Mpa。
  8. 如請求項1所述之方法，其中接合該第一奈米雙晶銅層之該表面與該第二奈米雙晶銅層之該表面係在溫度為200℃至約350℃之環境下進行。
  9. 如請求項1所述之方法，其中接合該第一奈米雙晶銅層之該表面與該第二奈米雙晶銅層之該表面係在環境氣壓為約10-3托耳(torr)至約10-1托耳的環境下進行。
  10. 如請求項1所述之方法，其中接合該第一奈米雙晶銅層之該表面與該第二奈米雙晶銅層之該表面的接合時間係約1分鐘至約30分鐘。
  11. 如請求項1所述之方法，其中該些第一奈米雙晶銅晶粒及該些第二奈米雙晶銅晶粒係沿著[111]晶軸方向堆疊形成。
  12. 如請求項1所述之方法，其中該第一奈米雙晶銅層之該表面及該第二奈米雙晶銅層之該表面包含(111)晶面。
  13. 一種具有奈米雙晶銅之電連接結 構，包含：一第一基材，具有一第一奈米雙晶銅層，其中該第一奈米雙晶銅層包含多個第一奈米雙晶銅晶粒；以及一第二基材，具有一第二奈米雙晶銅層，該第二奈米雙晶銅層包含多個第二奈米雙晶銅晶粒，該第一奈米雙晶銅層與該第二奈米雙晶銅層接合；其中至少部分的該些第一奈米雙晶銅晶粒延伸至該第二奈米雙晶銅層中，或者至少部分的該些第二奈米雙晶銅晶粒延伸至該第一奈米雙晶銅層中。
  14. 如請求項13所述之電連接結構，其中該第一基材與該第二基材各自包含一氧化物層和一金屬層，其中該第一奈米雙晶銅層位於該第一基材的該金屬層上，該第二奈米雙晶銅層位於該第二基材的該金屬層上。
  15. 如請求項13所述之電連接結構，更包括位於該第一奈米雙晶銅層與該第二奈米雙晶銅層之間的一接合介面，至少20%數量的該些第一奈米雙晶銅晶粒延伸超越該接合介面，或者至少20%數量的該些第二奈米雙晶銅晶粒延伸超越該接合介面。
  16. 如請求項15所述之電連接結構，其中延伸超越該接合介面的各該第一奈米雙晶銅晶粒越過該接合介面的一高度為該第二奈米雙晶銅層的一厚度的至少30%；或者延伸超越該接合介面的各該第二奈米雙晶銅晶粒越過該接合介面的一高度為該第一奈米雙晶銅層的一厚度的至少30%。
  17. 如請求項16所述之電連接結構，其中各該第一奈米雙晶銅晶粒越過該接合介面的該高度為約0.1微米至約20微米之間。
  18. 如請求項13所述之電連接結構，其中該些第一及該些第二奈米雙晶銅晶粒實質上為柱狀。
  19. 如請求項13所述之電連接結構，其中該些第一及該些第二奈米雙晶銅晶粒之寬度小於5微米。
  20. 如請求項13所述之電連接結構，其中該些第一及該些第二奈米雙晶銅晶粒係沿著[111]晶軸方向堆疊而成。
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