CN104716120A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
CN104716120A
CN104716120A CN201410020221.5A CN201410020221A CN104716120A CN 104716120 A CN104716120 A CN 104716120A CN 201410020221 A CN201410020221 A CN 201410020221A CN 104716120 A CN104716120 A CN 104716120A
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China
Prior art keywords
alloy
certain embodiments
semiconductor structure
silver
crystal grain
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CN201410020221.5A
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English (en)
Inventor
郑世杰
卢东宝
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Publication of CN104716120A publication Critical patent/CN104716120A/zh
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Abstract

一种半导体结构包括：装置；在所述装置上方的导电衬垫；及安置在所述导电衬垫上的Ag1-xYx合金柱，其中所述Ag1-xYx合金的Y包含以任意重量百分比与Ag形成完全固溶体的金属，且其中所述Ag1-xYx合金的X在0.005至0.25的范围内。

Description

半导体结构及其制造方法
技术领域
本发明为关于一种半导体结构及其制造方法。
（本申请要求于2013年12月13日递交的US14/106,462的美国专利的优先权和权利，该在先申请的全部内容作为参考引入本文。）
背景技术
随着电子工业的近期进展，正开发具有高效能的电子组件，且因此存在对于小型化及高密度封装的需求。因此，必须更密集地封装用于将IC连接至主机板的中介物(interposer)。封装的高紧密化可归因于IC的I/O的数目的增大，且亦已使得用于与中介物进行连接的方法更为有效。
愈发普及的中介物技术中的一者为倒装芯片（flip chiptechnology）结合。硅集成电路(IC)装置的制造处理流程中的倒装芯片装配由若干事实驱动。第一，当与习知线结合互连技术相关的寄生电感减小时，半导体装置的电效能可得以改良。第二，较之于线结合，倒装芯片装配在晶片与封装之间提供较高互连密度。第三，较之于线结合，倒装芯片装配消耗较少硅“占据面积”，且因此有助于节省硅区域且降低装置成本。及第四，当使用并行群式结合技术而非连续个别结合步骤时，可降低制造成本。
为了减小中介物的大小及其间距，已努力用金属凸块替换先前在倒装芯片结合中的基于焊料的互连球，尤其是努力藉由经修改的线球技术来产生金属凸块。通常，在半导体晶片的接触衬垫的铝层上产生金属凸块。随后，使用焊料将晶片附接至基板。所述等金属凸块用于针对LCD、记忆体、微处理器及微波RFIC的应用的倒装晶片封装。
发明内容
在一些实施例中，一种半导体结构包括装置、在所述装置上方的导电衬垫及安置在所述导电衬垫上的Ag1-xYx合金柱，其中Ag1-xYx合金的Y包含按任意重量百分比与Ag形成完全固溶体的金属，且其中Ag1-xYx合金的X在0.005至0.25的范围内。
在一些实施例中，Y包含Au及钯中的至少一者。
在一些实施例中，Ag1-xYx合金柱具有30μm至100μm的高度。
在一些实施例中，所述半导体结构进一步包括覆盖部件，所述覆盖部件安置在所述Ag1-xYx合金柱上且包括用于与另一半导体结构电连接的焊料材料。
在一些实施例中，所述覆盖部件具有自1μm至5μm的高度。
在一些实施例中，所述覆盖部件具有与Ag1-xYx合金柱的直径实质上相同的直径。
在一些实施例中，所述导电衬垫包括晶种层，所述晶种层包括与所述Ag1-xYx合金柱介接的Ag或Ag合金。
在一些实施例中，一种半导体结构包括装置、所述装置上的导电衬垫、安置在所述装置上方且覆盖所述导电衬垫的一部分的钝化层，及包括安置在所述钝化层上方的Ag1-xYx合金的再分布层(RDL)，其中Ag1-xYx合金的Y包含按任意重量百分比与Ag形成完全固溶体的金属，且其中Ag1-xYx合金的X在0.005至0.25的范围内。
在一些实施例中，Y包含Au及Pd中的至少一者。
在一些实施例中，RDL由包含金的金属层覆盖。
在一些实施例中，所述RDL包括用于容纳导电线或导电凸块的焊盘部分。
在一些实施例中，所述RDL包括穿过所述钝化层且与所述导电衬垫电连接的通孔部分。
在一些实施例中，一种半导体结构包括：晶粒，其包括第一表面及与所述第一表面对置的第二表面；及通孔，其自所述第一表面至所述第二表面穿过所述晶粒，Ag1-xYx合金填充所述通孔，且其中Ag1-xYx合金的Y包含按任意重量百分比与Ag形成完全固溶体的金属，且其中Ag1-xYx合金的X在0.005至0.25的范围内。
在一些实施例中，Y包含Au及Pd中的至少一者。
在一些实施例中，通孔为穿硅通孔(TSV)，且具有自3至20的纵横比。
在一些实施例中，所述通孔具有自5μm至500μm的高度。
在一些实施例中，所述半导体结构进一步包括导电衬垫，其在所述通孔的末端安置在所述第一表面或所述第二表面上。
在一些实施例中，所述导电衬垫经组态用于容纳导电凸块、导电柱或另一导电衬垫且用于与另一半导体结构结合。
在一些实施例中，所述导电衬垫包括银或金。
在一些实施例中，所述半导体结构进一步包括安置在Ag1-xYx合金与通孔的侧壁之间的晶种层。
在一些实施例中，晶粒包括面向下的有效侧，Ag1-xYx合金柱安置在所述晶粒的有效侧上方，且接点经组态用于与Ag1-xYx合金柱结合且电连接，其中Ag1-xYx合金的Y包含按任意重量百分比与Ag形成完全固溶体的金属，且其中Ag1-xYx合金的X在0.005至0.25的范围内。
在一些实施例中，Y包含Au及Pd中的至少一者。
在一些实施例中，所述接点为扁平无引线，其包括用于容纳Ag1-xYx合金柱的顶表面及用于安装在另一半导体结构上的暴露的底表面。
在一些实施例中，所述扁平无引线与Ag1-xYx合金柱结合以成为倒装芯片双边扁平无引线(FCDFN)封装。
在一些实施例中，所述半导体结构进一步包括基板，所述基板包括用于安置所述接点的第一表面及与所述第一表面对置用于安置配置成球状栅格阵列(BGA)的复数个导电凸块的第二表面。在一些实施例中，Ag1-xYx合金柱与安置在所述基板上的所述接点结合且电连接以成为倒装芯片球状栅格阵列封装(FCBGA)。
在一些实施例中，一种用于制造一半导体结构的方法包括：制备基于氰化物的镀敷溶液，其包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4中的至少一者；将所述半导体结构浸没于所述镀敷溶液中；将0.1ASD至1.0ASD的电镀电流密度施加至所述半导体结构以自所述镀敷溶液还原银离子、金离子或钯离子；及在所述半导体结构上形成Ag1-xYx合金结构，其中Ag1-xYx合金的Y包含按任意重量百分比与Ag形成完全固溶体的金属，且其中Ag1-xYx合金的X在0.005至0.25的范围内。
在一些实施例中，在所述半导体结构上形成所述Ag1-xYx合金结构包含在安置在所述半导体结构的装置上的导电衬垫上电镀Ag1-xYx合金柱。
在一些实施例中，在所述半导体结构上形成theAg1-xYx合金结构包含在安置在所述半导体结构的装置上方的钝化层上电镀Ag1-xYx合金RDL。
在一些实施例中，所述方法进一步包括藉由电镀操作或无电极镀敷操作在所述Ag1-xYx合金RDL上形成金属层。
在一些实施例中，形成Ag1-xYx合金结构包括：形成自晶粒的第一表面朝向所述晶粒的与所述第一表面对置的第二表面延伸的穿硅通孔(TSV)；及用所述Ag1-xYx合金填充所述TSV。
在一些实施例中，形成所述TSV包括按预定图案在所述晶粒的第一表面上安置遮罩层；及藉由蚀刻操作自所述第一表面移除所述晶粒的一部分。
在一些实施例中，形成所述TSV包括雷射钻孔操作。
在一些实施例中，形成所述Ag1-xYx合金结构包括自所述第二表面研磨所述晶粒以暴露所述Ag1-xYx合金。
附图说明
当结合附图阅读时，可自以下详细描述最佳地理解本发明的态样。应强调，根据工业中的标准实务，各种特征不按比例绘制。实际上，为了论述的清楚起见，可任意增大或减小各种特征的尺寸。
图1为根据本发明的一些实施例的银合金凸块结构的横截面图；
图2为根据本发明的一些实施例的粒径分散曲线；
图3为根据本发明的一些实施例的银合金凸块结构的横截面图；
图4为根据本发明的一些实施例的多层凸块结构的横截面图；
图5为根据本发明的一些实施例的具有覆盖部件的银柱结构的横截面图；
图6为根据本发明的一些实施例的具有银合金凸块结构的膜上晶片(COF)半导体结构的横截面图；
图7为根据本发明的一些实施例的展示于图6中的接头部分的放大视图；
图8为根据本发明的一些实施例的具有多层凸块结构的膜上晶片(COF)半导体结构的横截面图；
图9为根据本发明的一些实施例的展示于图8中的接头部分的放大视图；
图10为根据本发明的一些实施例的具有银合金柱及覆盖部件的膜上晶片(COF)半导体结构的横截面图；
图11为根据本发明的一些实施例的具有银合金凸块结构的玻璃上晶片(COG)半导体结构的横截面图；
图12为根据本发明的一些实施例的具有多层凸块结构的玻璃上晶片(COG)半导体结构的横截面图；
图13为根据本发明的一些实施例的具有多层凸块结构的玻璃上晶片(COG)半导体结构的横截面图；
图14至图20展示根据本发明的一些实施例的制造银合金柱结构的操作。
图21为根据本发明的一些实施例的具有重分布层(RDL)的半导体结构的俯视图；
图22为根据本发明的一些实施例的具有沿图21的AA'的重分布层(RDL)的半导体结构的横截面图；
图23为根据本发明的一些实施例的具有包括金属层的重分布层(RDL)的半导体结构的横截面图；
图24至图31展示根据本发明的一些实施例的制造重分布层(RDL)的操作；
图32为根据本发明的一些实施例的具有若干穿硅通孔(TSV)的晶粒的横截面图；
图33为根据本发明的一些实施例的经堆叠且藉由穿硅通孔(TSV)彼此连接的若干晶粒的横截面图；
图34为根据本发明的一些实施例的安装于基板上的若干经堆叠晶粒的横截面图；
图35至图41展示根据本发明的一些实施例的制造镀敷有银合金的穿硅通孔(TSV)的操作；
图42为根据本发明的一些实施例的双边扁平无引线(DFN)封装的俯视图；
图43为根据本发明的一些实施例的沿图42的BB'的双边扁平无引线(DFN)封装的横截面图；及
图44为根据本发明的一些实施例的具有银合金柱的倒装芯片球状栅格阵列(FCBGA)封装的横截面图。
附图标识：
10  银合金凸块结构
20  银合金凸块结构
30  多层凸块结构
40  银柱结构
50  膜上晶片(COF)半导体封装
60  膜上晶片(COF)半导体封装
70  膜上晶片(COF)半导体封装
80  玻璃上晶片(COG)半导体封装
90  玻璃上晶片(COG)半导体封装
110 玻璃上晶片(COG)半导体封装
100 装置
100'容器
100A入口
100B出口
101 银合金凸块
101A晶粒
101B顶表面
101C底表面
101D侧壁
102 导电衬垫
102A顶表面
103 钝化层
104 凸块下金属化(UBM)层
105 晶种层
107 金属层
109 第一遮罩层
109A开口
111 阳极
112 阴极
113 电镀浴
114 覆盖部件
115 Ag1-xYx合金柱
115A顶表面
301 可挠性膜
301A第一表面
301B第二表面
302 导电层
303 点框
304 底部填充材料
305 阻焊剂图案
306 焊料层
307 点框
308 焊料层
401 透明基板
401A第一表面
402 导电迹线
406 ACF
406A塑胶球体
501 晶粒
501-1  晶粒
501-2  晶粒
501-3  晶粒
501A第一表面
501A'  新第一表面
501A-1  第一表面
501A-2  第一表面
501A-3  第一表面
501B 第二表面
501B'  新第二表面
501B-1  第二表面
501B-2  第二表面
501B-3  第二表面
502  金属结构
502-1  金属结构
502-2  金属结构
502-3  金属结构
502A 第一衬垫
502A-1  第一衬垫
502A-2  第一衬垫
502A-3  第一衬垫
502B 第二衬垫
502B-1  第二表面
502B-2  第二衬垫
502B-3  第二表面
502C 细长部分
503  TSV/通孔
503-1  TSV
503-2  TSV
503-3  TSV
503B 底表面
504  基板
505  接合衬垫
506  导电凸块
507  遮罩层
508  晶种层
600  半导体封装
601  晶粒
602  扁平无引线
602A 顶表面
602B 底表面
603  模制化合物
700  倒装芯片球状栅格阵列(FCBGA)封装
701  晶粒
702  基板
702A 第一表面
702B 第二表面
703  凸块衬垫
704  导电凸块
705  球式衬垫
800  半导体结构
801  装置
802  衬垫
802A 顶表面
803  钝化层
803A 开口
803B 顶表面
804  聚合材料层
804A 顶表面
804B 开口
805  遮罩层
806 RDL
806A 焊盘部分
806B 通孔部分
806D 流道部分
807  额外金属层
具体实施方式
在以下详细描述中，列出了若干特定细节以便提供对本发明的全面了解。然而，熟习此项技术者应了解，本发明可在无该等特定细节的情况下实施。在其他情形中，未对熟知方法、程序、组件及电路进行详细描述，以免混淆本发明。应理解，以下揭示内容提供用于建构各种实施例的不同特征的许多不同实施例或实例。下文描述组件及配置的特定实例以简化本发明。当然，此等仅为实例，而并不意欲为限制性的。
下文详细论述实施例的制作及使用。然而，应了解，本发明提供可在广泛多种特定内容脉络中体现的许多适用的发明性概念。所论述的特定实施例仅为说明制作及使用本发明的特定方式，而并不限制本发明的范畴。
在半导体封装的金属凸块技术当中，金凸块由于与此项技术中的材料特性及处理技术的类似性而最为风行。然而，高材料成本、较差结合可靠性及诸如低电导率及低热导率的不令人满意的材料特性仍为待解决的问题。制造金属凸块的替代成本节省方法为藉由产生多层凸块，例如，Cu(底部层)、Ni(中间层)及Au(顶部层)凸块。此方法节省金属凸块的金材料消耗，但铜底部层易受氧化及腐蚀，且因此产生可靠性忧虑。
当藉由回焊已沉积在衬垫上的焊料而将金凸块接合至基板衬垫时，形成数个金/锡金属间物(intermetallics)。因为金在熔融焊料中的高溶解率，具有金凸块的焊料接头在一次回焊之后具有大体积分率的金属间化合物(其中AuSn4为主要相)，其使接头大大变脆。在两次或两次以上回焊(对于装配迭层封装产品通常为需要的)之后，金凸块可能完全耗尽且转化成金/锡金属间化合物。由于此等化合物及金属间物与晶片侧上的铝衬垫的直接接触的脆性，接头经常由于在凸块/晶片界面处开裂而通不过诸如机械坠落测试的可靠性测试。
银凸块的成本为金凸块的二十分之一，且银凸块在本文中论述的三种金属(Au、Cu、Ag)中具有最高电导率及最高热导率。此外，银凸块的退火温度低于金凸块的退火温度，因此大大减少钝化裂痕的风险。就将银凸块接合至基板的焊料而言，在高于共晶温度的温度下，银/锡界面表现出优于金/锡界面的结合特性的结合特性。在本发明的一些实施例中，银合金用于银凸块以避免银针、银迁移、纯银所固有的氧化及硫化问题。
本发明的一些实施例提供一种具有银合金凸块的半导体结构。银合金凸块可为具有0.005至0.25原子%(atomic percent)的非银元件的二元合金或三元合金。在一些实施例中，因为银合金凸块为藉由电镀而形成，因此观测到均一的粒径分布，且可藉由量测粒径分布的标准差而量化该粒径分布。
本发明的一些实施例提供一种具有含有银的多层合金凸块的半导体结构。该多层合金凸块包括具有0.005至0.25原子%的非银元件的二元合金或三元合金。在一些实施例中，包括金(Au)的额外金属层定位在该二元合金或三元合金上。在一些实施例中，该额外金属层覆盖该二元合金或三元合金的侧壁。在一些实施例中，因为该多层合金凸块为藉由电镀而形成，因此观测到均一粒径分布，且可藉由量测粒径分布的标准差而量化该粒径分布。
本发明的一些实施例提供一种包括经电镀银合金凸块的胶带自动结合(TAB)半导体结构。在一些实施例中，膜上晶片(COF)结构包括在薄膜上的银合金凸块与导电铜线之间的银/锡界面。在一些实施例中，额外金属层定位在该COF结构中的经电镀银合金凸块上。在一些实施例中，该额外金属层覆盖该COF结构中的该经电镀银合金凸块的侧壁。
本发明的一些实施例提供一种包括经电镀Ag1-xYx合金凸块的玻璃上晶片(COG)结构，该经电镀Ag1-xYx合金凸块将半导体晶片电耦接至导电层。在一些实施例中，该经电镀Ag1-xYx合金凸块的Y包括Pd及Au中的至少一者。在一些实施例中，额外金属层定位在该COG结构中的经电镀银合金凸块上。在一些实施例中，该额外金属层覆盖该COG结构中的该经电镀银合金凸块的侧壁。
本发明的一些实施例提供一种在一半导体结构中的经电镀银合金凸块。在一些实施例中，由本文中所描述的经电镀银合金凸块制成的银合金薄膜具有自250W/(mK)至450W/(mK)的热导率。在其他实施例中，该经电镀银合金凸块具有自35(Ωm)-1至65(Ωm)-1的电导率。
本发明的一些实施例提供一种半导体结构，其具有安置在具有该半导体结构的装置上的银合金柱。该银合金柱可为包含0.005至0.25原子%的非银元素的二元合金或三元合金。
在一些实施例中，该银合金柱包括经电镀Ag1-xYx合金，其中Y包括钯(Pd)及金(Au)中的至少一者，且X为0.005至0.25。在一些实施例中，因为该银合金柱为藉由电镀而形成，因此观测到均一粒径分布，且可藉由量测粒径分布的标准差而量化该粒径分布。
本发明的一些实施例提供一种半导体结构，其具有安置在钝化层或具有该半导体结构的装置上的重分布层(RDL)。该RDL包括可为具有0.005至0.25原子%的非银元素的二元合金或三元合金的银合金。
在一些实施例中，该RDL包括经电镀Ag1-xYx合金，其中Y包括钯(Pd)及金(Au)中的至少一者，且X为0.005至0.25。在一些实施例中，包括金(Au)的额外金属层安置在该银合金上。
本发明的一些实施例提供一种半导体结构，其具有镀敷有银合金且穿过晶粒或中介物而作为“穿硅通孔(TSV)”的若干通孔，使得该晶粒的一侧经配置用于电连接另一晶粒。在一些实施例中，该银合金可为包含0.005至0.25原子%的非银元素的二元合金或三元合金。在一些实施例中，该银合金包括经电镀Ag1-xYx合金，其中Y包括钯(Pd)及金(Au)中的至少一者，且X为0.005至0.25。
本发明的一些实施例提供一种半导体结构，其具有堆叠在彼此的上且藉由镀敷有银合金的若干TSV电互连的若干晶粒。在一些实施例中，该银合金可为包含0.005至0.25原子%的非银元素的二元合金或三元合金。在一些实施例中，该银合金包括经电镀Ag1-xYx合金，其中Y包括钯(Pd)及金(Au)中的至少一者，且X为0.005至0.25。
本发明的一些实施例提供一种在一半导体封装中的半导体结构。在一些实施例中，该半导体封装为倒装芯片双边扁平无引线(FCDFN)封装，其包括藉由若干银合金柱与若干扁平无引线电连接的倒装芯片晶粒。在一些实施例中，该银合金可为包含0.005至0.25原子%的非银元素的二元合金或三元合金。在一些实施例中，该银合金包括经电镀Ag1-xYx合金，其中Y包括钯(Pd)及金(Au)中的至少一者，且X为0.005至0.25。
本发明的一些实施例提供一种在一半导体封装中的半导体结构。在一些实施例中，该半导体封装为倒装芯片球状栅格阵列(FCBGA)封装，其包括藉由若干银合金柱与安置在基板上的若干导电衬垫电连接的倒装芯片晶粒。在一些实施例中，该银合金可为包含0.005至0.25原子%的非银元素的二元合金或三元合金。在一些实施例中，该银合金包括经电镀Ag1-xYx合金，其中Y包括钯(Pd)及金(Au)中的至少一者，且X为0.005至0.25。
定义
在描述及主张本发明时，将根据下文所阐述的定义使用以下术语。
如本文所使用，“平均粒径”为藉由诸如X射线绕射(XRD)、电子束散射型式(EBSP)、穿透电子显微术(TEM)或扫描电子显微术(SEM)的任何习知粒径量测技术而量测。样本的经预处理横截面平面经准备用于本发明中所论述的粒径量测。经受本文中所论述的量测中的任一者的横截面平面为穿过银合金凸块结构10的银合金凸块101、具有垂直于纵向方向、平行于如图1中所示的Y方向的平面法线的任何平面。
如本文所使用，用于平均粒径量测的“电子束散射型式(EBSP)”由电脑分析程式(例如，TSLOIM分析)加以辅助。电脑分析程式的设定包括但不限于15度的晶界错向、等于或大于0.1的CI值，及至少为5测试点的极小粒径。在一些实施例中，EBSP量测的平均粒径为藉由对至少在横截面平面的三个不同测试位置上的粒径求平均而获得。在每一测试位置量测一预定区域。预定区域根据不同实施例的特征而变化。每一测试位置距邻近测试位置至少1mm远。在一些实施例中，一个测试位置中的每一量测点之间的间隔为至少5μm。在一些实施例中，在20kV的加速电压及100倍至500倍的放大率下观测经受EBSP量测的所制备样本。在一些实施例中，所制备样本定位在70度的倾斜角处。
如本文所使用，用于平均粒径量测的“穿透电子显微术(TEM)或扫描电子显微术(SEM)”为由影像分析程式(例如，CLEMEX VisionPE)加以辅助。在一些实施例中，TEM或SEM量测的平均粒径为藉由对横截面平面的至少三个不同测试位置上的粒径求平均而获得。在每一测试位置中量测一预定区域。该预定区域根据不同实施例的特征而变化。每一测试位置距邻近测试位置至少1mm远。在一些实施例中，一个测试位置中的每一量测点之间的间隔为至少5μm。在一些实施例中，在5kV至20kV的加速电压及100倍至500倍的放大率下观测经受TEM或SEM量测的所制备样本。
如本文所使用，银合金凸块的“粒径分布的标准差”为指使用本文中所论述的影像分析程式获得的统计结果。在获得粒径分布的分散曲线之后，一个标准差被定义为自均值粒径(期望值)偏离的粒径，其中粒径在所偏离粒径与均值粒径之间的晶粒的数目占到晶粒的总数目的34%。
图1为具有连接至导电衬垫102的银合金凸块101的银合金凸块结构10的横截面。银合金凸块101及导电衬垫102定位在装置100上。在一些实施例中，装置100包括但不限于诸如记忆体、电晶体、二极管(PN或PIN接面)、集成电路或可变电抗器的主动装置。在其他实施例中，装置100包括诸如电阻器、电容器或电感器的被动装置。
银合金凸块101的微观结构展示于图1中。银合金凸块101的横截面为藉由沿纵向方向(Y方向)切割银合金凸块结构10而制备，且因此获得XY表面。使用电子显微镜，在XY平面上识别银合金凸块101的晶粒结构，且在本文中所论述的影像分析软件的帮助下，可获得粒径分布的统计资讯。
参看图1，晶粒101A的一区域用直线划出阴影。银合金凸块101中所示的SEM图像为取自本文中所描述的银合金凸块101的真实横截面平面。在一些实施例中，因为银合金凸块101为藉由电镀操作而形成，因此粒径分布相当均一，且未观测到如螺柱凸块(未图示)中的受热影响区(HAZ)的受热影响区。HAZ由于以下事实而产生粒径的突变：晶粒生长程序经受局部高温。通常，粒径在HAZ中明显地增大。在本发明的一些实施例中，可在银合金凸块101的晶粒中识别出子晶粒结构。举例而言，在晶粒101A中，可以如下方式看到子晶粒域：可识别出藉由域边界分离的晶粒101A内的若干区。
在一些实施例中，银合金凸块101包括Ag1-xYx合金。Ag1-xYx合金中的物质Y包括以任何重量百分比与银形成完成固溶体的金属。在一些实施例中，可自二元相图识别出物质Y。二元相图中形成透镜形状的液相线及固相线指示在两种金属组分的任何组成下的固溶体的完全混合。举例而言，在本发明的一些实施例中，物质Y为金(Au)、钯(Pd)，或其组合。在一些实施例中，Ag1-xYx合金为诸如Ag1-xAux或Ag1-xPdx的二元金属合金。在一些实施例中，Ag1-xYx合金为诸如Ag1-x(AuPd)x的三元金属合金。在一些实施例中，物质Y在Ag1-xYx合金中的含量介于0.005至0.25原子%之间。
在一些实施例中，图1中的银合金凸块101的粒径形成如图2中所示的分散曲线。图2中的分散曲线为经由诸如但不限于CLEMEXVision PE的影像分析软件程式而获得。在图2中，该分散曲线的X轴指示以微米(μm)计的粒径，而该分散曲线的Y轴展示经正规化的晶粒数目。本发明中的粒径计算为藉由电脑分析程式(例如，TSLOIM分析)加以辅助。在一些实施例中，电脑分析程式将晶粒的面积转换为具有相同面积的假设圆，且此假设圆的直径被界定为按一长度单位(通常为微米)的粒径。然而，粒径计算不限于上述操作。在其他实施例中，平均粒径为藉由在本文中所描述的银合金凸块结构的横截面平面的TEM图像或SEM图像上绘制对角线，并将该对角线的长度除以该对角线所遇到的晶粒的数目而获得。任何粒径量测操作为适当的，只要其藉由电脑软件加以辅助或其为以一致且系统化的方式进行即可。
在绘出如图2中所示的分散曲线之后，可将标准差量测为银合金凸块101的微观结构的形态特征。在一些实施例中，该分散曲线具有近钟形状(skewed bell shape)，其最大值较接近于该分散曲线的右端。在一些实施例中，粒径的均值或期望值由分散曲线的最大值表示。如图2中所示，均值M对应于粒径A，其在一些实施例中在0.7μm至0.8μm的范围内。离开均值M至正方向一个标准差(+1σ)对应于粒径C，其在一些实施例中在l.0μm至1.1μm的范围内。离开平均值M至负方向一个标准差(-1σ)对应于粒径B，其在一些实施例中在0.4μm至0.5μm的范围内。在一些实施例中，一个标准差被定义为自均值M偏离的粒径，且其中粒径在所偏离粒径B或C与均值M之间的晶粒的数目占到晶粒的总数目的34%。注意，获自实际粒径量测的分散曲线并不必须关于均值M对称，且因此，在一些实施例中，离开均值M至粒径C处的正方向一个标准差(+1σ)与均值M之间的差异未必与在粒径B处在负方向上离开均值M一个标准差(-1σ)与均值M之间的差异相同。
在本发明的一些实施例中，粒径C与粒径A之间的差异自0.2μm至0.4μm。在其他实施例中，粒径B与粒径A之间的差异自0.2μm至0.4μm。藉由利用本发明中所论述的电镀操作，银合金凸块101的粒径表现出均一分布，且离开均值M(至正或负方向)一个标准差之间的差异可量化为在0.2μm至0.4μm的范围内。
参看图3，展示银合金凸块结构20的横截面。与图1中的银合金凸块结构10相比，银合金凸块结构20进一步包括凸块下金属化(UBM)层104及晶种层105。在一些实施例中，晶种层105含有银或银合金。在一些实施例中，晶种层105为藉由诸如化学气相沉积(CVD)、溅镀、电镀等适当操作而制备。在一些实施例中，UBM层104具有单层结构或包括由不同材料形成的若干子层的复合结构，且包括选自以下各者的一(或多)层：镍(Ni)层、钛(Ti)层、钛钨(W)层、钯(Pd)层、金(Au)层、银(Ag)层，及其组合。
如图3中所示，银合金凸块101的高度H1为自银合金凸块101的顶表面101B至导电衬垫102的顶表面102A而量测。在一些实施例中，银合金凸块101或Ag1-xYx合金的高度H1在9μm至15μm的范围内。与银合金凸块101的高度H1成比例，UBM层104的厚度T2与晶种层105的厚度T1相当。在一些实施例中，UBM层104的厚度T2在1000A至3000A的范围内，且晶种层105的厚度T1在1000A至3000A的范围内。
参看图4，展示多层凸块结构30的横截面。与图3中的银合金凸块结构20相比，多层凸块结构30进一步包括在银合金凸块101的顶表面101B上的金属层107。在一些实施例中，多层凸块结构30包括银合金凸块101，银合金凸块101具有安置在晶种层105、UBM层104及导电衬垫102上的底表面101C。因此，金属层107、银合金凸块101、晶种层105、UBM层104与导电衬垫102与彼此电连接。在一些实施例中，金属层107及银合金凸块101经由晶种层105、UBM层104及导电衬垫102电连接至装置100。
在一些实施例中，金属层107包括不同于银的金属材料。在其他实施例中，金属层107包括金。金属层107的厚度H2足够厚以在银合金凸块101与外部装置的电路(诸如晶粒、基板、封装、印刷电路板(PCB)等)之间形成接头界面。在一些实施例中，金属层107的厚度H2自1μm至3μm，且金属层107为藉由电镀操作而形成。
在图4中，多层凸块结构30包括凸块下金属化(UBM)层104及晶种层105。在一些实施例中，晶种层105含有银或银合金，且为藉由诸如化学气相沉积(CVD)、溅镀、电镀等适当操作而制备。在一些实施例中，UBM层104具有单层结构或包括由不同材料形成的若干子层的复合结构，且包括选自以下各者的一层或多层：镍(Ni)层、钛(Ti)层、钛钨(W)层、钯(Pd)层、金(Au)层、银(Ag)层，及其组合。
图4中所示的银合金凸块101包括Ag1-xYx合金，其中物质Y为金、钯，或其组合。举例而言，Ag1-xYx合金可为诸如Ag1-xAux或Ag1-xPdx的二元金属合金，此外，Ag1-xYx合金可为诸如Ag1-x(AuPd)x的三元金属合金。在一些实施例中，物质Y在Ag1-xYx合金中的含量介于0.005至0.25原子%之间。在一些实施例中，Ag1-xYx合金中的物质Y包括以任何重量百分比与银形成完全固溶体的金属。如图4中所示，银合金凸块101的高度H1在9μm至15μm的范围内。
参看图5，展示银柱结构40的横截面。与图4中的多层凸块结构30相比，图4中的多层凸块结构30的银合金凸块101及金属层107不同于图5中的银柱结构40的柱115及覆盖部件114。此外，图5中的柱115与图4中的银合金凸块101在大小上具有实质差异。在一些实施例中，图5中的柱115的大小大于图4中的银合金凸块101。柱115的高度大于银合金凸块101。在一些实施例中，柱115的高度自30μm至100μm，而银合金凸块101的高度自9μm至15μm。与图4及图5中所示的数字标记具有相同数字标记的元件为指相同元件或其等效物，且为简单起见不在此处加以重复。在一些实施例中，柱115安置在包括晶种层105及UBM层104的导电衬垫102上。在一些实施例中，柱115、晶种层105、UBM层104与装置100电连接。在一些实施例中，晶种层105包括与柱115介接的银或银合金。
在一些实施例中，柱115包括Ag1-xYx合金作为Ag1-xYx合金柱，其中，其中物质Y为金、钯，或其组合。举例而言，Ag1-xYx合金可为诸如Ag1-xAux或Ag1-xPdx的二元金属合金，此外，Ag1-xYx合金可为诸如Ag1-x(AuPd)x的三元金属合金。在一些实施例中，物质Y在Ag1-xYx合金中的含量介于0.005至0.25原子%之间。在一些实施例中，Ag1-xYx合金中的物质Y包括以任何重量百分比与银形成完成固溶体的金属。
在一些实施例中，Ag1-xYx合金柱115为藉由诸如电镀、溅镀或其类似者的任何适当操作而形成。如图5中所示，Ag1-xYx合金柱115的高度H1在30μm至100μm的范围内。
在一些实施例中，额外覆盖部件114安置在Ag1-xYx合金柱115的顶表面115A上，且因此覆盖部件114、Ag1-xYx合金柱115、晶种层105、UBM层104与装置100与彼此电连接。在一些实施例中，覆盖部件114包括诸如锡或银的用于与另一半导体结构电连接的焊料材料。在一些实施例中，覆盖部件114呈半球形形状。在一些实施例中，覆盖部件114为藉由诸如胶合或电镀的任何适当操作而形成于Ag1-xYx合金柱115上。
在一些实施例中，覆盖部件114为Ag1-xYx合金柱115与外部装置的电路(诸如晶粒、基板、封装、印刷电路板(PCB)等)之间的接头界面。在一些实施例中，覆盖部件114的高度H3自1μm至5μm。在一些实施例中，覆盖部件114具有与Ag1-xYx合金柱115的直径Dpillar实质上相同的直径Dcover。
参看图6，展示膜上晶片(COF)半导体封装50的横截面。在一些实施例中，COF半导体封装50包括可挠性膜301，该可挠性膜301具有第一表面301A及第二表面301B。可挠性膜301包括但不限于可挠性印刷电路板(FPCB)或聚酰亚胺(PI)。导电层302包括电路，或导电迹线经图案化于可挠性膜301的第一表面301A上。
在图6中，与图1及图3中所示的数字标记具有相同数字标记的元件为指相同元件或其等效物，且为简单起见不在此处加以重复。在图6中，两个银合金凸块101将装置100电耦接至可挠性膜301的导电层302以成为COF半导体封装50。在一些实施例中，例如无溶剂环氧树脂的具有适当粘度的底部填充材料304注入至可挠性膜301与装置100之间的空间中以包围银合金凸块101。
图6中所示的银合金凸块101包括Ag1-xYx合金，其中物质Y为金、钯，或其组合。举例而言，Ag1-xYx合金可为诸如Ag1-xAux或Ag1-xPdx的二元金属合金，此外，Ag1-xYx合金可为诸如Ag1-x(AuPd)x的三元金属合金。在一些实施例中，物质Y在Ag1-xYx合金中的含量介于0.005至0.25原子%之间。在一些实施例中，Ag1-xYx合金中的物质Y包括以任何重量百分比与银形成完成固溶体的金属。
如图6中所示，银合金凸块101的高度H1在9μm至15μm的范围内，且邻近的银合金凸块101之间的间距P低于10μm。在一些实施例中，导电衬垫102的宽度W在10μm至20μm的范围内。
在图6中，阻焊剂图案305定位在导电层302上。焊料层306根据阻焊剂图案305而施加于导电层302上。焊料层306经组态用于使银合金凸块101与导电层302结合。在本发明的一些实施例中，焊料层306包括习知焊料材料、无铅焊料材料等。
图6中的接头部分由点框303包围，且经放大，如图7中所示。参看图7，焊料层306不仅包括焊料材料自身且亦包括Ag1-aSna合金。在一些实施例中，Ag1-aSna合金至少包括Ag0.5Sn0.5合金。在某些实施例中，当用于COF的在银合金凸块侧设定的内部引线结合(ILB)温度为摄氏400度时，AgSn合金系统的液相实质上大于AuSn合金系统的液相(给定在合金凸块的自由端设定的相同结合温度)。AgSn合金的过量液相促进银合金凸块101与导电层302之间的粘附，且因此藉由使用基于Ag的合金凸块在AgSn合金系统中获得较好接面可靠性。另一方面，用于COF的较低ILB温度可用于AgSn合金系统中。例如低于摄氏400度的较低ILB温度可防止可挠性膜301变形或收缩。在其他实施例中，各向异性导电膜(ACF)可用以连接银合金凸块101与导电层302。
参看图7，展示银合金凸块101的微观结构。银合金凸块101的平均粒径在0.5μm至1.5μm的范围内。因为银的熔化温度为摄氏962度，因此施加至银合金凸块101的退火温度可低于摄氏250度以避免图1、图3、图4、图5及图6中所示的钝化层103的开裂。与金的较高熔化温度(摄氏1064度)相比，较低熔化温度导致较低退火温度，且因此诸如钝化层的先前生长的结构经受较低热应力。在一些实施例中，在于低于摄氏250度的温度下对银合金凸块101进行退火之后，藉由本文中所描述的方法量测的Ag1-xYx合金的平均粒径为1μm。
参看图8，展示膜上晶片(COF)半导体封装60的横截面。COF半导体封装60包括可挠性膜301，该可挠性膜301具有第一表面301A及第二表面301B。可挠性膜301包括但不限于可挠性印刷电路板(FPCB)或聚酰亚胺(PI)。诸如导电铜迹线的导电层302经图案化于可挠性膜301的第一表面301A上，且阻焊剂图案305定位在导电层302上。在图8中，与图1、图3、图4、图5及图6中所示的数字标记具有相同数字标记的元件为指相同元件或其等效物，且为简单起见不在此处加以重复。在图8中，包括银合金凸块101及金属层107的两个多层凸块结构将装置100电耦接至可挠性膜301的导电层302。在一些实施例中，例如无溶剂环氧树脂的具有适当粘度的底部填充材料304注入至可挠性膜301与装置100之间的空间中。在金属层107为由经电镀金膜制成的情况下，可挠性膜301与银合金凸块101的后续结合可利用此项技术中对于金凸块所习知的结合操作。
图8中所示的银合金凸块101包括Ag1-xYx合金，其中物质Y为金、钯，或其组合。举例而言，Ag1-xYx合金可为诸如Ag1-xAux或Ag1-xPdx的二元金属合金，此外，Ag1-xYx合金可为诸如Ag1-x(AuPd)x的三元金属合金。在一些实施例中，物质Y在Ag1-xYx合金中的含量介于0.005至0.25原子%之间。在一些实施例中，Ag1-xYx合金中的物质Y包括以任何重量百分比与银形成完全固溶体的金属。图8中所示的金属层107包括不同于银的金属材料，例如金。
如图8中所示，银合金凸块101的高度H1在9μm至15μm的范围内，且邻近的银合金凸块101之间的间距P低于10μm。金属层107的高度H2在1μm至3μm的范围内。在一些实施例中，导电衬垫102的宽度W在10μm至20μm的范围内。
在图8中，阻焊剂图案305定位在导电层302上。焊料层308施加至金属层107与导电层302的接头。在本发明的一些实施例中，焊料层308为习知焊料材料或无铅焊料。由点框307包围的图8中的接头部分经放大且于图9中展示。参看图9，焊料层308不仅包括焊料材料自身，且亦包括Ag1-aSna合金(若金属层107为由金(Au)制成)。在一些实施例中，Au1-aSna合金至少包括Au0.5Sn0.5合金。在其他实施例中，各向异性导电膜(ACF)可用以连接金属层107与导电层302。
参看图10，展示膜上晶片(COF)半导体封装70的横截面。在图10中，与图6中所示的数字标记具有相同数字标记的元件为指相同元件或其等效物，且为简单起见不在此处加以重复。在图10中，包括Ag1-xYx合金柱115及覆盖部件114的两个柱结构将装置100电耦接至可挠性膜301的导电层302。在一些实施例中，例如无溶剂环氧树脂的具有适当粘度的底部填充材料304注入至可挠性膜301与装置100之间的空间中。
图10中所示的Ag1-xYx合金柱115包括Ag1-xYx合金，其中物质Y为金、钯，或其组合。举例而言，Ag1-xYx合金可为诸如Ag1-xAux或Ag1-xPdx的二元金属合金，此外，Ag1-xYx合金可为诸如Ag1-x(AuPd)x的三元金属合金。在一些实施例中，物质Y在Ag1-xYx合金中的含量介于0.005至0.25原子%之间。在一些实施例中，Ag1-xYx合金中的物质Y包括以任意重量百分比与银形成完成固溶体的金属。
在图10中，覆盖部件114与导电层302结合，使得装置100藉由诸如回焊的热处理而与可挠性膜301电连接。在一些实施例中，覆盖部件114包括诸如锡或银的焊料材料。
在本发明的一些实施例中，如图11中所示，本文中论述的银合金凸块101亦可用于玻璃上晶片(COG)半导体封装80中。透明基板401的第一表面401A上的导电迹线402藉由各向异性导电膜(ACF)406而与装置100的银合金凸块101电连接。在一些实施例中，透明基板401为玻璃基板。在一些实施例中，ACF406包括涂有Au的塑胶球体406A，其直径自3μm至5μm，分散在热固性环氧树脂基质中。在一些实施例中，用于在COG半导体封装80中使用ACF406的结合温度为摄氏200度。
在本发明的一些实施例中，如图12中所示，本文中论述的多层凸块结构亦可用于玻璃上晶片(COG)半导体封装90中。玻璃基板401的第一表面401A上的导电迹线402藉由各向异性导电薄(ACF)406与装置100的银合金凸块101电连接。在一些实施例中，导电迹线402为由诸如氧化铟锡(ITO)的透明且导电材料制成。在一些实施例中，ACF406包括涂有Au的塑胶球体406A，其直径自3μm至5μm，分散在热固性环氧树脂基质中。在一些实施例中，用于在COG半导体封装90中使用ACF406的结合温度为摄氏200度。在一些实施例中，安置在银合金凸块101上的金属层107为经电镀金膜，其厚度自lμm至3μm。在此情况下，对于金凸块技术习知的结合操作可用于连接银合金凸块101与导电迹线402。
在本发明的一些实施例中，如图13中所示，本文中论述的多层凸块结构亦可用于玻璃上晶片(COG)半导体封装110中。玻璃基板401的第一表面401A上的导电迹线402与银合金凸块101之间的电连接为各向异性导电膜(ACF)406。举例而言，ACF406包括涂有Au的塑胶球体406A，其直径自3μm至5μm，分散在热固性环氧树脂基质中。在一些实施例中，用于在COG半导体封装110中使用ACF406的结合温度为摄氏200度。在一些实施例中，安置在银合金凸块101上的金属层107为经电镀金膜，其厚度自1μm至3μm，覆盖银合金凸块101的顶表面101B及侧壁101D。在此情况下，对于金凸块技术习知的结合操作可用于经由ACF406及金属层107连接银合金凸块101与导电迹线402。在一些实施例中，顶表面101B上的金属层107的厚度不同于覆盖银合金凸块101的侧壁101D的金属层107的厚度。
可易于藉由选择适当电镀浴来调整本文中论述的银合金凸块及银帽盖的硬度。举例而言，可将用于如图11、图12及图13中的COG应用的银合金凸块的硬度调整至100HV。对于另一实例，可将用于如图6及图8中的COF应用的银合金凸块的硬度调整至55HV。因为纯银的硬度(85HV)介于55HV与100HV之间，因此可藉由使用不同电镀浴来电镀银合金凸块而定制具有所要硬度的银合金。在一些实施例中，COG应用需要银合金凸块具有较大硬度以促进ACF结合操作。在其他实施例中，COF应用需要银合金凸块具有较低硬度以防止损伤可挠性膜上的导电迹线。
图14至图19展示本发明中描述的图5的银合金柱115的制造操作。在图14中，在钝化层103及导电衬垫102的一部分上形成UBM层104。在一些实施例中，UBM层104为藉由对材料进行CVD、溅镀、电镀或无电极镀敷而形成，该等材料为选自镍、钛、钛钨、钯、金、银，及其组合。在一些实施例中，将UBM层104的厚度T2控制在自1000A至3000A的范围内。
在图15中，将晶种层105沉积在UBM层104上。在一些实施例中，晶种层105为藉由对含有银的材料进行CVD、溅镀、电镀或无电极镀敷而形成。在一些实施例中，将晶种层105的厚度T1控制为与UBM层104的厚度T2相当。举例而言，在自1000A至3000A的范围内。
参看图16，在晶种层105上方形成可为硬式遮罩或光阻剂的第一遮罩层109。在晶种层105及导电衬垫102上方形成第一遮罩层109的开口109A。开口109A用于接收导电柱材料。在一些实施例中，第一遮罩层109为由厚度T3大于待镀敷的导电柱的厚度的正光阻剂制成。在其他实施例中，第一遮罩层109为由负光阻剂制成。
图17展示电镀操作，且图18展示其后的结果。图17展示一电镀系统，其包括容纳电镀浴113、阳极111及阴极112的容器100'。在一些实施例中，阳极111不可溶且可由涂有铂的钛制成，沉积有晶种层105的装置100定位在阴极112处，且电镀浴113含有基于氰化物的镀敷溶液，包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4及其盐中的至少一者。
在一些实施例中，直流电(DC)施加至连接至阴极的装置100用于还原装置100的晶种层105上的银离子、金离子或钯离子。在一些实施例中，直流电(DC)具有范围介于0.1ASD至1.0ASD的电镀电流密度。在一些实施例中，将电镀浴113的pH值控制为中性，例如自6至8。将电镀浴113的温度控制为摄氏40度至摄氏50度。在一些实施例中，可藉由定位在容器100'下的热板(未图示)来维持电镀浴113的温度。在其他实施例中，可藉由一电镀溶液循环系统来维持电镀浴113的温度，在该电镀溶液循环系统中，出口100B排放电镀溶液，且入口100A吸入温度受控的电镀溶液。可将浓度自2ml/L至5ml/L的包括草酸盐的适当调平剂添加至电镀浴113。
参看图17，阴极112包括沉积有含有银或银合金的晶种层105的装置100，且在阴极处发生的反应可为以下反应中的一者：
KAg(CN)2→K++Ag++2CN-
KAu(CN)2→K++Au++2CN-
K2Pd(CN)4→2K++Pd2++4CN-
图17中所示的阳极111包括铂电极，且其上发生的反应可为：
2H2O→4H++O2(g)+4e-
外部DC电流的正端连接至阳极111，且外部DC电流的负端连接至阴极112。如图17中可见，经还原的银离子及经还原的金离子沉积至装置100的晶种层105上，填充由第一遮罩层109界定的开口109A且在开口109A内形成AgAu二元合金。
在一些实施例中，若电镀浴113包括银离子源(例如，KAg(CN)2)及钯离子源(例如，K2Pd(CN)4)，则经由上文描述的相同电镀操作设定，经还原的银离子及经还原的金离子沉积至装置100的晶种层105上，填充由第一遮罩层109界定的开口109A且在开口109A内形成AgPd二元合金。
在一些实施例中，若电镀浴113包括银离子源(例如，KAg(CN)2及其盐)、金离子源(例如，(CN)2及其盐)及钯离子源(例如，K2Pd(CN)4及其盐)，则经由上文描述的相同电镀操作设定，经还原的银离子、经还原的金离子及经还原的钯离子沉积至装置100的晶种层105上，填充由第一遮罩层109界定的开口109A，且在开口109A内形成AgAuPd三元合金。
在如图17中所示的电镀操作之后，自电镀浴113移除装置100，且包括Ag1-xYx合金的银合金柱115形成于如图18中所示的晶种层105上。Ag1-xYx合金柱115形成于导电衬垫102及装置100上方。
在于开口109A内形成Ag1-xYx合金柱115之后，覆盖部件114形成于如图19中所示的Ag1-xYx合金柱115的顶表面115A上。在一些实施例中，覆盖部件114包括诸如锡或银的焊料材料。在一些实施例中，覆盖部件114为藉由模板印刷、胶合、电镀、无电极镀敷或其类似者而形成于Ag1-xYx合金柱115上。
在图20中，藉由剥除操作移除第一遮罩层109。另外，亦藉由蚀刻操作移除由第一遮罩层109覆盖的UBM层104及晶种层105以隔离Ag1-xYx合金柱115。在一些实施例中，覆盖部件114如在图20中般在回焊操作之后呈半球形形状。在一些实施例中，覆盖部件114经组态用于与外部装置上的衬垫或外部装置内的电路结合，使得装置100经由Ag1-xYx合金柱115及覆盖部件114而与外部装置电连接。
在本发明的一些实施例中，本文中论述的包括Ag1-xYx合金的银合金亦可用于在半导体结构800内形成再分布层(RDL)806，如图21及图22中所示。RDL806将半导体结构800内的电路的路径自衬垫802重新导引至焊盘部分806A。焊盘部分806A经组态用于容纳诸如金线的导电线或诸如焊球的导电凸块，使得半导体结构800藉由使外部装置上的结合衬垫与导电凸块结合而与另一外部装置电连接。
图21展示半导体结构800的RDL806的俯视图。RDL806包括焊盘部分806A、通孔部分806B及连接焊盘部分806A与通孔部分806B的流道部分806D。在一些实施例中，包括Ag1-xYx合金的RDL806为藉由电镀、溅镀等而形成于钝化层803或聚合材料层804上方。在一些实施例中，通孔部分806B穿过钝化层803及聚合材料层804。在一些实施例中，通孔部分806B与衬垫802电连接。
在一些实施例中，RDL806包括Ag1-xYx合金，其可为具有0.005至0.25原子%的非银元素的二元合金或三元合金。在一些实施例中，RDL806包括经电镀Ag1-xYx合金，其中Y包括钯(Pd)及金(Au)中的至少一者，且X为0.005至0.25。在一些实施例中，Ag1-xYx合金为诸如Ag1-xAux或Ag1-xPdx的二元金属合金。在一些实施例中，Ag1-xYx合金为诸如Ag1-x(AuPd)x的三元金属合金。在一些实施例中，物质Y在Ag1-xYx合金中的含量介于0.005至0.25原子%之间。
图22展示半导体结构800的沿图21的AA'的横截面图。在一些实施例中，如在图22中，半导体结构800包括诸如晶粒或基板的装置801。在一些实施例中，衬垫802安置在装置801上。衬垫802为用于连接装置801内的电路与外部电路或装置的接触端子。在一些实施例中，诸如氮氧化硅或氮化硅的钝化层803安置在装置801上方且覆盖衬垫802的顶表面802A的一部分。在一些实施例中，诸如聚酰亚胺或聚苯并恶唑(PBO)的聚合材料层804安置在衬垫802及钝化层803上方。
在一些实施例中，RDL806安置在钝化层803及装置801上方。在一些实施例中，RDL806安置在聚合材料层804的顶表面804A上。在一些实施例中，焊盘部分806A经组态用于容纳导电线或导电凸块，使得装置801可经由导电线或导电凸块与另一半导体结构电连接。在一些实施例中，焊盘部分806A经组态用于后续线接合操作。焊盘部分806A容纳金属线的一端，使得焊盘部分806A电连接于与金属线的另一端结合的外部电路。在一些实施例中，焊盘部分806A容纳导电凸块，该导电凸块经组态用于结合在另一半导体结构的结合衬垫上。
图23展示半导体结构800的沿图21的AA'的横截面图。在一些实施例中，RDL806为多层结构，其包括Ag1-xYx合金及安置在电镀有Ag1-xYx合金的RDL806上的额外金属层807。在一些实施例中，额外金属层807包括金(Au)。在一些实施例中，金属层807为藉由电镀操作而形成。在一些实施例中，在焊盘部分806A上方的金属层807经组态用于容纳诸如金线的导电线或诸如焊球的导电凸块，使得半导体结构800藉由使外部装置上的结合衬垫与导电凸块或金线结合而与另一外部装置电连接。
图24至图31展示如在图21至图23中具有RDL806(包括Ag1-xYx合金)的半导体结构800的制造操作。在图24中，提供装置801及衬垫802。衬垫802安置在装置801上。在一些实施例中，装置801为包括组件及连接该组件的电路的晶粒或基板。在一些实施例中，衬垫802包括铝。
在图25中，钝化层803安置在装置801及衬垫802上方。在一些实施例中，钝化层803为藉由诸如氧化硅、氮氧化硅、氮化硅等介电材料形成。在图26中，藉由蚀刻操作在衬垫802的顶表面802A上形成开口803A。在图27中，聚合材料层804安置在衬垫802及钝化层803上方。聚合材料层804填充开口803A，且沿钝化层803的顶表面803B延伸。
在图28中，开口804B形成于衬垫802的顶表面802A上及钝化层803的开口803A内。在一些实施例中，开口804B为藉由蚀刻操作而形成。在图29中，遮罩层805按预定图案安置在聚合材料层804的顶表面804A上。在一些实施例中，遮罩层805可为硬式遮罩或光阻剂。遮罩层805为由正或负光阻剂制成。在一些实施例中，遮罩层805的预定图案为藉由微影操作而形成，使得聚合材料层804的顶表面804A的一部分由遮罩层805覆盖。
在图30中，RDL806形成于聚合材料层804上。RDL806为藉由电镀Ag1-xYx合金而形成。在一些实施例中，半导体结构800浸没在含有基于氰化物的镀敷溶液的电镀浴中，该镀敷溶液包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4及其盐中的至少一者。半导体结构800连接至阴极，使得银离子、金离子及钯离子自镀敷溶液被还原，且沉积至聚合材料层804上，且因此形成包括AgAu二元合金(Ag1-xAux)、AgPd二元合金(Ag1-xPdx)或AgAuPd三元合金(Ag1-x(AuPd)x)的RDL806。在一些实施例中，X范围介于0.005至0.25原子%之间。在一些实施例中，直流电(DC)施加至连接至阴极的半导体结构800用于还原半导体结构800的聚合材料层804上的银离子、金离子或钯离子。该直流电具有范围介于0.1ASD至1.0ASD的电镀电流密度。在图31中，藉由剥除操作移除遮罩层805，且因此形成具有经电镀Ag1-xYx合金的RDL806。
在一些实施例中，RDL806为如图23中的多层结构，且因此额外金属层807安置在电镀有Ag1-xYx合金的RDL806上。在一些实施例中，金属层807在剥除遮罩层805的前藉由电镀操作形成于RDL806上。在一些实施例中，金属层807为藉由无电极镀敷操作而形成于RDL806上。
在本发明的一些实施例中，本文中论述的包括Ag1-xYx合金的银合金亦可用于填充穿过晶粒、晶圆、中介物或基板的穿硅通孔(TSV)，如图32至图34中所示。图32展示晶粒501，其包括第一表面501A及与第一表面501A对置的第二表面501B。在一些实施例中，晶粒501具有镀敷有Ag1-xYx合金的若干TSV503。TSV503自第一表面501A至第二表面501B穿过晶粒501。在一些实施例中，TSV503由Ag1-xYx合金填充，该Ag1-xYx合金可为具有0.005至0.25原子%的非银元素的二元合金或三元合金。在一些实施例中，Ag1-xYx合金的Y包括钯(Pd)及金(Au)中的至少一者，且X自0.005至0.25。在一些实施例中，TSV503具有高纵横比。在一些实施例中，TSV503的纵横比自3至20。在一些实施例中，TSV503具有自1μm至100μm的直径Dtsv，且具有自5μm至500μm的高度Htsv。
在一些实施例中，TSV503藉由电镀操作由Ag1-xYx合金填充以形成金属结构502。在一些实施例中，金属结构502包括在第一表面501A上的第一衬垫502A、在第二表面501B上的第二衬垫502B，及自第一表面501A延伸至第二表面501B的细长部分502C。在一些实施例中，第一衬垫502A及第二衬垫502B经组态用于容纳外部晶粒上的另一衬垫。在一些实施例中，第一衬垫502A及第二衬垫502B经组态用于容纳导电凸块或导电柱以便与外部晶粒结合。在一些实施例中，第一衬垫501A在TSV503的一端安置在第一表面501A上，且第二衬垫502B在TSV503的另一端安置在第二表面501B上。在一些实施例中，第一衬垫502A及第二衬垫502B分别包含银或金。
图33展示藉由结合TSV(503-1、503-2、503-3)的金属结构(502-1、502-2、502-3)而向上堆叠且彼此互连的若干晶粒(501-1、501-2、501-3)。在一些实施例中，晶粒(501-1、501-2、501-3)向上堆叠，使得TSV(503-1、503-2、503-3)与彼此垂直地对准。在一些实施例中，晶粒(501-1、501-2、501-3)中的每一者为用于资料储存应用的动态随机存取记忆体(DRAM)晶粒。如图33中所示，三个DRAM晶粒堆叠在彼此上以成为堆叠式记忆体晶片。
在一些实施例中，金属结构(502-1、502-2、502-3)中的每一者为藉由电镀操作而由Ag1-xYx合金制成。在一些实施例中，Ag1-xYx合金的Y包括钯(Pd)及金(Au)中的至少一者，且X自0.005至0.25。
在一些实施例中，晶粒501-1的TSV503-1与晶粒501-2的TSV503-2对准，且晶粒501-1的第二表面501B-1上的第二衬垫502B与晶粒501-2的第一表面501A-2上的第一衬垫502A-2结合。由此，晶粒501-1与晶粒501-2经由TSV503-1及TSV503-2自第一表面501A-1上的第一衬垫502A-1电连接至第二表面501B-2上的第二衬垫502B-2。类似地，晶粒501-2的TSV503-2与晶粒501-3的TSV503-3对准，且晶粒501-2的第二表面501B-2上的第二衬垫502B-2与晶粒501-3的第一表面501A-3上的第一衬垫502A-3结合。由此，晶粒501-2与晶粒501-3经由TSV503-2及TSV503-3自第一表面501A-2上的第一衬垫502A-2电连接至第二表面501B-3上的第二衬垫502B-3，且最终晶粒(501-1、501-2、501-3)经由TSV(503-1、503-2、503-3)自第一表面501A-1上的第一衬垫502A-1电连接至第二表面501B-3上的第二衬垫502B-3。
图34展示安装在中介物或基板504上的图33的堆叠的晶粒(501-1、501-2、501-3)。在一些实施例中，基板504由硅、陶瓷等制成，用于携载电路且支撑诸如电晶体的组件。在一些实施例中，基板504包括用于容纳晶粒501-3的第二衬垫502B-3或分别安置在第二衬垫502B-3上的导电凸块的若干接合衬垫505。在一些实施例中，接合衬垫505包括预焊材料以促进后续结合操作。在一些实施例中，接合衬垫505分别安装有导电凸块，使得导电凸块可与晶粒501-3上的第二衬垫502B-3结合。
在一些实施例中，接合衬垫505藉由诸如熔融结合、热压缩结合、藉由ACF的粘附等任何适当结合操作而与第二衬垫502B-3电连接。在结合第二衬垫502B-3与结合衬垫505之后，晶粒(501-1、501-2、501-3)与基板504内的电路电连接。在一些实施例中，晶粒501-1的第一衬垫502A-1经由TSV(503-1、503-2、503-3)及接合衬垫505与安置在基板504的底部的导电凸块506电连通。
在一些实施例中，基板504的导电凸块506可进一步安装在另一基板或装置上以便进一步将晶粒(501-1、501-2、501-3)及基板504与另一基板或装置连接以成为半导体封装。
图35至图41展示如在图32中具有藉由Ag1-xYx合金填充的TSV的半导体结构的制造操作。在图35中，提供晶粒501及具有预定图案的遮罩层507。在一些实施例中，遮罩层507由光阻剂制成，且按预定图案安置在晶粒501的第一表面501A上。在一些实施例中，遮罩层507的预定图案为藉由微影操作而形成，使得晶粒501的第一表面501A的一部分由遮罩层507覆盖。
在图36中，形成高纵横比的若干通孔503。在一些实施例中，通孔503为藉由蚀刻操作或藉由雷射钻孔操作而形成。移除晶粒501不由遮罩层507覆盖的一些部分以形成通孔503。在一些实施例中，通孔503为藉由深反应性离子蚀刻(DRIE)而形成。在图37中，藉由剥除操作移除遮罩层507，且晶种层508安置在晶粒501的第一表面501A、通孔503的侧壁503A及通孔503的底表面503B上。在一些实施例中，晶种层508为藉由诸如化学气相沉积(CVD)、溅镀、电镀等适当操作而制备。在一些实施例中，晶种层508包括银或银合金。
在图38中，银合金502安置在晶种层508上且填充通孔503。在一些实施例中，银合金502包括Ag1-xYx合金，其中物质Y为金、钯，或其组合。举例而言，Ag1-xYx合金可为诸如Ag1-xAux或Ag1-xPdx的二元金属合金，此外，Ag1-xYx合金可为诸如Ag1-x(AuPd)x的三元金属合金。在一些实施例中，物质Y在Ag1-xYx合金中的含量介于0.005至0.25原子%之间。
在一些实施例中，晶粒501浸没在含有基于氰化物的镀敷溶液的电镀浴中，该镀敷溶液包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4及其盐中的至少一者。晶粒501连接至阴极，使得银离子、金离子及钯离子自镀敷溶液被还原，且沉积至晶种层508上，且因此包括AgAu二元合金(Ag1-xAux)、AgPd二元合金(Ag1-xPdx)或AgAuPd三元合金(Ag1-x(AuPd)x)的银合金502形成在晶种层508上且填充通孔503。用银合金502镀敷通孔503。在一些实施例中，直流电(DC)施加至连接至阴极的晶粒501用于还原晶粒501的晶种层508上的银离子、金离子或钯离子。该直流电具有范围介于0.1ASD至1.0ASD的电镀电流密度。
在图39中，晶粒501藉由诸如电平坦化、化学机械抛光(CMP)或其类似者的薄化操作而自第一表面501A薄化。移除晶粒501的邻近于第一表面501A的一些及银合金502及晶种层508的自通孔503溢出的一些，使得第一表面501A成为晶粒501的新第一表面501A'，且该新第一表面501A'与晶种层508的暴露部分及银合金502的暴露部分处于实质上相同层级。
在图40中，晶粒501藉由诸如电平坦化、化学机械抛光(CMP)等的薄化操作而自与第一表面501A对置的第二表面501B薄化，使得银合金502的底表面503B自晶粒501暴露。在一些实施例中，自第二表面501B移除晶粒501的一些，使得第二表面501B成为新第二表面501B'，且银合金502的底表面503B与晶粒501的新第二表面501B'处于实质上相同层级。
在图41中，藉由诸如电镀的任何适当操作分别在银合金502的末端处形成若干衬垫(502A、502B)。在一些实施例中，衬垫(502A、502B)由与银合金502相同的材料制成。在一些实施例中，衬垫(502A、502B)包含金或银。衬垫502A经由镀敷有银合金502的通孔503与衬垫502B电连接。在一些实施例中，衬垫(502A、502B)分别经组态用于容纳安置在外部晶粒或基板上的导电凸块或结合衬垫，使得晶粒501可藉由使衬垫502A或衬垫502B与安置在外部晶粒或基板上的导电凸块或结合衬垫结合而与外部晶粒或基板电连接。
在本发明的一些实施例中，本文中论述的包括Ag1-xYx合金的图5的银合金柱结构40亦可用于将晶粒安装在诸如引线框、基板或PCB的外部装置上以成为诸如四边扁平封装(QFP)、四边扁平无引线(QFN)封装、球状栅格阵列(BGA)封装、晶片级封装(CSP)、层迭封装(PoP)、多晶片模组(MCM)等的半导体封装。
图42展示包括若干银合金柱115的晶粒601的俯视图，该等银合金柱115与若干接点602连接以成为如图42及图43中所示的半导体封装600。在一些实施例中，晶粒601为倒装芯片晶粒，其具有安置有银合金柱115的有效侧。晶粒601的有效侧面向下。在一些实施例中，接点602为扁平无引线。安置在晶粒601上方的银合金柱115与扁平无引线602结合以成为倒装芯片双边扁平无引线(FCDFN)封装。
图43展示沿图42的BB'的作为FCDFN封装的半导体封装600的横截面图。在一些实施例中，银合金柱115与扁平无引线602结合。在一些实施例中，银合金柱115包括经电镀Ag1-xYx合金，其中Y包括钯(Pd)及金(Au)中的至少一者，且X自0.005至0.25。在一些实施例中，Ag1-xYx合金为诸如Ag1-xAux或Ag1-xPdx的二元金属合金。在一些实施例中，Ag1-xYx合金为诸如Ag1-x(AuPd)x的三元金属合金。在一些实施例中，物质Y在Ag1-xYx合金中的含量介于0.005至0.25原子%之间。
在一些实施例中，银合金柱115为藉由电镀操作而形成，如图17中所示。具有晶种层105及UBM层104的晶粒601与阴极连接。晶粒601接着浸没在含有基于氰化物的镀敷溶液的电镀浴中，该镀敷溶液包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4及其盐中的至少一者，使得诸如银离子、金离子或钯离子自镀敷溶液被还原，且安置在晶种层105上以形成包括AgAu二元合金(Ag1-xAux)、AgPd二元合金(Ag1-xPdx)或AgAuPd三元合金(Ag1-x(AuPd)x)的银合金柱115。
在一些实施例中，银合金柱115安置在含有银或银合金的晶种层105上。在一些实施例中，晶种层105为藉由诸如溅镀的任何适当操作而安置在UBM层104上。在一些实施例中，UBM层104安置在晶粒601的有效侧上。在一些实施例中，UBM层104为单层结构或包括由不同材料形成的若干子层的复合结构。UBM层104包括选自以下各者的一(或多)层：镍(Ni)层、钛(Ti)层、钛钨(W)层、钯(Pd)层、金(Au)层、银(Ag)层，及其组合。
在一些实施例中，安置在晶粒601的有效侧上方的银合金柱115藉由在银合金柱115与扁平无引线602之间施加焊料材料、无铅焊料材料或ACF而与扁平无引线602结合且电连接。在一些实施例中，覆盖部件114安置在银合金柱115的顶表面115A上。在一些实施例中，覆盖部件114经组态用于使银合金柱115与扁平无引线602的顶表面602A结合。在一些实施例中，覆盖部件114包括诸如锡或银的焊料材料。
在一些实施例中，银合金柱115藉由诸如熔融结合、热压缩结合等任何适当操作而与扁平无引线602结合，使得银合金柱115的顶表面115A与扁平无引线602的顶表面602A介接。晶粒601经由银合金柱115与扁平无引线602电连接。
在一些实施例中，扁平无引线602具有暴露的底表面602B，其经暴露而用于容纳另一结合衬垫或外部装置的导电凸块。在一些实施例中，模制化合物603覆盖晶粒601及扁平无引线602以成为FCDFN封装600。在一些实施例中，暴露的底表面602B自模制化合物603暴露。在一些实施例中，模制化合物603亦填充晶粒601、银合金柱115与扁平无引线602之间的间隙。在一些实施例中，模制化合物603包括环氧树脂、聚酰亚胺、聚苯并恶唑(PBO)等。
在本发明的一些实施例中，本文中论述的包括Ag1-xYx合金的图5的银合金柱结构40亦可用于将晶粒701安装在基板702上以成为如图44中所示的BGA封装。在图44中，晶粒701为经翻转且安装在基板702上以成为倒装芯片球状栅格阵列(FCBGA)封装700的倒装芯片晶粒。在一些实施例中，银合金柱115藉由回焊操作而与基板702的第一表面702A上的凸块衬垫703结合。
在一些实施例中，基板702包括在与第一表面702A对置的第二表面702B上的若干导电凸块704。导电凸块704安置在基板702的球式衬垫705上。在一些实施例中，导电凸块704为呈球面形状的包括焊料材料的焊球。导电凸块704经组态以安装在另一基板或PCB上的结合衬垫上，使得晶粒701经由银合金柱115及导电凸块704与另一基板或PCB电连接。
在一些实施例中，一种半导体结构包括装置、在该装置上方的导电衬垫及安置在该导电衬垫上的Ag1-xYx合金柱，其中Ag1-xYx合金的Y包含按任意重量百分比与Ag形成完全固溶体的金属，且其中Ag1-xYx合金的X在0.005至0.25的范围内。
在一些实施例中，Y包含Au及钯中的至少一者。在一些实施例中，Ag1-xYx合金柱具有30μm至100μm的高度。在一些实施例中，该半导体结构进一步包括覆盖部件，该覆盖部件安置在该Ag1-xYx合金柱上且包括用于与另一半导体结构电连接的焊料材料。在一些实施例中，该覆盖部件具有自1μm至5μm的高度。在一些实施例中，该覆盖部件具有与Ag1-xYx合金柱的直径实质上相同的直径。在一些实施例中，该导电衬垫包括晶种层，该晶种层包括与该Ag1-xYx合金柱介接的Ag或Ag合金。
在一些实施例中，一种半导体结构包括一装置、该装置上的导电衬垫、安置在该装置上方且覆盖该导电衬垫的一部分的钝化层，及包括安置在该钝化层上方的Ag1-xYx合金的再分布层(RDL)，其中Ag1-xYx合金的Y包含按任意重量百分比与Ag形成完全固溶体的金属，且其中Ag1-xYx合金的X在0.005至0.25的范围内。
在一些实施例中，Y包含Au及Pd中的至少一者。在一些实施例中，RDL由包含金的金属层覆盖。在一些实施例中，该RDL包括用于容纳导电线或导电凸块的焊盘部分。在一些实施例中，该RDL包括穿过该钝化层且与该导电衬垫电连接的通孔部分。
在一些实施例中，一种半导体结构包括：晶粒，其包括第一表面及与该第一表面对置的第二表面；及通孔，其自该第一表面至该第二表面穿过该晶粒，Ag1-xYx合金填充该通孔，且其中Ag1-xYx合金的Y包含按任意重量百分比与Ag形成完全固溶体的金属，且其中Ag1-xYx合金的X在0.005至0.25的范围内。
在一些实施例中，Y包含Au及Pd中的至少一者。在一些实施例中，通孔为穿硅通孔(TSV)，且具有自3至20的纵横比。在一些实施例中，该通孔具有自5μm至500μm的高度。在一些实施例中，该半导体结构进一步包括导电衬垫，其在该通孔的末端安置在该第一表面或该第二表面上。在一些实施例中，该导电衬垫经组态用于容纳导电凸块、导电柱或另一导电衬垫且用于与另一半导体结构结合。在一些实施例中，该导电衬垫包括银或金。在一些实施例中，该半导体结构进一步包括安置在Ag1-xYx合金与通孔的侧壁之间的晶种层。
在一些实施例中，一晶粒包括面向下的有效侧和接点，Ag1-xYx合金柱安置在该晶粒的有效侧上方，接点经组态用于与Ag1-xYx合金柱结合且电连接，其中Ag1-xYx合金的Y包含按任意重量百分比与Ag形成完全固溶体的金属，且其中Ag1-xYx合金的X在0.005至0.25的范围内。
在一些实施例中，Y包含Au及Pd中的至少一者。在一些实施例中，该接点为扁平无引线，其包括用于容纳Ag1-xYx合金柱的顶表面及用于安装在另一半导体结构上的暴露的底表面。在一些实施例中，该扁平无引线与Ag1-xYx合金柱结合以成为倒装芯片双边扁平无引线(FCDFN)封装。在一些实施例中，该半导体结构进一步包括一基板，该基板包括用于安置该接点的第一表面及与该第一表面对置用于安置配置成球状栅格阵列(BGA)的复数个导电凸块的第二表面。在一些实施例中，Ag1-xYx合金柱与安置在该基板上的该接点结合且电连接以成为倒装芯片球状栅格阵列封装(FCBGA)。
在一些实施例中，一种用于制造半导体结构的方法包括：制备基于氰化物的镀敷溶液，其包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4中的至少一者；将该半导体结构浸没于该镀敷溶液中；将0.1ASD至1.0ASD的电镀电流密度施加至该半导体结构以自该镀敷溶液还原银离子、金离子或钯离子；及在该半导体结构上形成Ag1-xYx合金结构，其中Ag1-xYx合金的Y包含按任意重量百分比与Ag形成完全固溶体的金属，且其中Ag1-xYx合金的X在0.005至0.25的范围内。
在一些实施例中，在该半导体结构上形成该Ag1-xYx合金结构包含在安置在该半导体结构的装置上的导电衬垫上电镀Ag1-xYx合金柱。在一些实施例中，在该半导体结构上形成Ag1-xYx合金结构包含在安置在该半导体结构的装置上方的钝化层上电镀Ag1-xYx合金RDL。在一些实施例中，该方法进一步包括藉由电镀操作或无电极镀敷操作在该Ag1-xYx合金RDL上形成金属层。在一些实施例中，形成Ag1-xYx合金结构包括：形成自晶粒的第一表面朝向该晶粒的与该第一表面对置的第二表面延伸的穿硅通孔(TSV)；及用该Ag1-xYx合金填充该TSV。在一些实施例中，形成该TSV包括按预定图案在该晶粒的第一表面上安置一遮罩层；及藉由蚀刻操作自该第一表面移除该晶粒的一部分。在一些实施例中，形成该TSV包括雷射钻孔操作。在一些实施例中，形成该Ag1-xYx合金结构包括自该第二表面研磨该晶粒以暴露该Ag1-xYx合金。
此外，本申请案的范畴不意欲限于说明书中描述的制程、机器、制造，及物质组成、构件、方法及步骤的特定实施例。如熟习此项技术者将易于自本发明的揭示内容而了解，可根据本发明利用执行与本文中所描述的对应实施例执行实质上相同的功能或达成与该等对应实施例实质上相同的结果的当前现有或稍后待开发的程序、机器、制造、物质组成、构件、方法或步骤。
因此，所附申请专利范围意欲在其范畴中包括程序、机器、制造，及物质组成、构件、方法或步骤。此外，每一权利要求构成一单独实施例，且各种权利要求及实施例的组合在本发明的范畴内。

Claims (30)

1.一种半导体结构，其特征在于其包含：
装置；
在所述装置上方的导电衬垫；及
安置在所述导电衬垫上的Ag1-xYx合金柱，
其中所述Ag1-xYx合金的Y包含以任意重量百分比与Ag形成完全固溶体的金属，且
其中所述Ag1-xYx合金的X在0.005至0.25的范围内。
2.如权利要求1所述的半导体结构，其特征在于，所述Y包含Au及Pd中的至少一者。
3.如权利要求1所述的半导体结构，其特征在于，所述Ag1-xYx合金柱具有自30μm至100μm的高度。
4.如权利要求1所述的半导体结构，其特征在于，其进一步包含覆盖部件，所述覆盖部件安置在所述Ag1-xYx合金柱上且包括用于与另一半导体结构电连接的焊料材料。
5.如权利要求4所述的半导体结构，其特征在于，其中所述覆盖部件具有自1μm至5μm的高度。
6.如权利要求1所述的半导体结构，其特征在于，所述导电衬垫包括晶种层，所述晶种层包括与所述Ag1-xYx合金柱介接的Ag或Ag合金。
7.如权利要求1所述的半导体结构，其特征在于，其进一步包含接点，所述接点包括用于容纳所述Ag1-xYx合金柱的顶表面及用于安装在另一半导体结构上的暴露的底表面。
8.如权利要求7所述的半导体结构，其特征在于，所述接点为扁平无引线，所述扁平无引线与所述Ag1-xYx合金柱结合以成为倒装芯片双边扁平无引线(FCDFN)封装。
9.如权利要求1所述的半导体结构，其特征在于，其进一步包含基板，所述基板包括用于安置接点的第一表面及与所述第一表面对置用于安置以球状栅格阵列(BGA)配置的复数个导电凸块的一第二表面，且所述基板的所述接点与所述Ag1-xYx合金柱结合以成为倒装芯片球状栅格阵列封装(FCBGA)。
10.一种半导体结构，其特征在于，其包含：
装置；
在所述装置上的导电衬垫；
钝化层，其安置在所述装置上方且覆盖所述导电衬垫的一部分；及
再分布层(RDL)，其包括安置在所述钝化层上方的Ag1-xYx合金，
其中所述Ag1-xYx合金的Y包含以任意重量百分比与Ag形成完全固溶体的金属，且
其中所述Ag1-xYx合金的X在0.005至0.25的范围内。
11.如权利要求10所述的半导体结构，其特征在于，所述Y包含Au及Pd中的至少一者。
12.如权利要求10所述的半导体结构，其特征在于，所述RDL由包含金的金属层覆盖。
13.如权利要求10所述的半导体结构，其特征在于，所述RDL包括用于接收导电线或导电凸块的焊盘部分。
14.如权利要求10所述的半导体结构，其特征在于，所述RDL包括穿过所述钝化层且与所述导电衬垫电连接的通孔部分。
15.一种半导体结构，其特征在于，其包含：
晶粒，其包括第一表面及与所述第一表面对置的第二表面；及
通孔，其自所述第一表面至所述第二表面穿过所述晶粒，
填充所述通孔的Ag1-xYx合金，且
其中所述Ag1-xYx合金的Y包含以任意重量百分比与Ag形成完全固溶体的金属，且
其中所述Ag1-xYx合金的X在0.005至0.25的范围内。
16.如权利要求15所述的半导体结构，其特征在于，所述Y包含Au及Pd中的至少一者。
17.如权利要求15所述的半导体结构，其特征在于，所述通孔为一穿硅通孔(TSV)，且具有自3至20的纵横比。
18.如权利要求15所述的半导体结构，其特征在于，其中所述通孔具有自5μm至500μm的高度。
19.如权利要求15所述的半导体结构，其特征在于，其进一步包含导电衬垫，所述导电衬垫在所述通孔的一端安置在所述第一表面或所述第二表面上。
20.如权利要求19所述的半导体结构，其特征在于，所述导电衬垫经组态用于接收导电凸块、导电柱或另一导电衬垫且用于与另一半导体结构结合。
21.如权利要求19所述的半导体结构，其特征在于，所述导电衬垫包括银或金。
22.如权利要求15所述的半导体结构，其特征在于，其进一步包含晶种层，所述晶种层安置在所述Ag1-xYx合金与所述通孔的侧壁之间。
23.一种用于制造半导体结构的方法，其特征在于，其包含：
制备基于氰化物的镀敷溶液，其包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4中的至少一者；
将所述半导体结构浸没至所述镀敷溶液中；
将0.1ASD至1.0ASD的电镀电流密度施加至所述半导体结构以自所述镀敷溶液还原银离子、金离子或钯离子；及
在所述半导体结构上形成Ag1-xYx合金结构，
其中所述Ag1-xYx合金的Y包含按任意重量百分比与Ag形成完全固溶体的金属，且其中所述Ag1-xYx合金的X在0.005至0.25的范围内。
24.如权利要求23所述的方法，其特征在于，所述在所述半导体结构上形成所述Ag1-xYx合金结构包含在安置在所述半导体结构的装置上的导电衬垫上电镀Ag1-xYx合金柱。
25.如权利要求23所述的方法，其特征在于，所述在所述半导体结构上形成所述Ag1-xYx合金结构包含在安置在所述半导体结构的装置上方的钝化层上电镀Ag1-xYx合金RDL。
26.如权利要求25所述的方法，其特征在于，其进一步包含藉由电镀操作或无电极镀敷操作而在所述Ag1-xYx合金RDL上形成金属层。
27.如权利要求23所述的方法，其特征在于，所述形成所述Ag1-xYx合金结构包括：形成自晶粒的第一表面朝向所述晶粒的与所述第一表面对置的第二表面延伸的穿硅通孔(TSV)；及用所述Ag1-xYx合金填充所述TSV。
28.如权利要求27所述的方法，其特征在于，所述形成所述TSV包括：按预定图案在所述晶粒的所述第一表面上安置遮罩层；及藉由蚀刻操作自所述第一表面移除所述晶粒的一部分。
29.如权利要求27所述的方法，其特征在于，所述形成所述TSV包括雷射钻孔操作。
30.如权利要求27所述的方法，其特征在于，所述形成所述Ag1-xYx合金结构包括自所述第二表面研磨所述晶粒以暴露所述Ag1-xYx合金。
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Application publication date: 20150617