TW201523819A - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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Publication number
TW201523819A
TW201523819A TW102148605A TW102148605A TW201523819A TW 201523819 A TW201523819 A TW 201523819A TW 102148605 A TW102148605 A TW 102148605A TW 102148605 A TW102148605 A TW 102148605A TW 201523819 A TW201523819 A TW 201523819A
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Taiwan
Prior art keywords
alloy
semiconductor structure
layer
silver
conductive
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TW102148605A
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English (en)
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TWI532131B (zh
Inventor
Shih-Jye Cheng
Tung-Bao Lu
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Chipmos Technologies Inc
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Abstract

一種半導體結構包括：一裝置；在該裝置上方之一導電襯墊；及安置在該導電襯墊上之一Ag1-xYx合金柱，其中該Ag1-xYx合金之Y包含以任意重量百分比與Ag形成完全固溶體之金屬，且其中該Ag1-xYx合金之X在約0.005至約0.25之範圍內。

Description

半導體結構及其製造方法
本發明係關於一種半導體結構及其製造方法。
隨著電子工業之近期進展，正開發具有高效能之電子組件，且因此存在對於小型化及高密度封裝之需求。因此，必須更密集地封裝用於將IC連接至主機板之中介物(interposer)。封裝之高緊密化可歸因於IC之I/O的數目之增大，且亦已使得用於與中介物進行連接的方法更為有效。
愈發普及的中介物技術中的一者為覆晶結合。矽積體電路(IC)裝置之製造處理流程中的覆晶裝配由若干事實驅動。第一，當與習知線結合互連技術相關的寄生電感減小時，半導體裝置之電效能可得以改良。第二，較之於線結合，覆晶裝配在晶片與封裝之間提供較高互連密度。第三，較之於線結合，覆晶裝配消耗較少矽「佔據面積」，且因此有助於節省矽區域且降低裝置成本。及第四，當使用並行群式結合技術而非連續個別結合步驟時，可降低製造成本。
為了減小中介物的大小及其間距，已努力用金屬凸塊替換先前在覆晶結合中之基於焊料的互連球，尤其是努力藉由經修改的線球技術來產生金屬凸塊。通常，在半導體晶片之接觸襯墊之鋁層上產生金屬凸塊。隨後，使用焊料將晶片附接至基板。該等金屬凸塊用於針對 LCD、記憶體、微處理器及微波RFIC之應用的倒裝晶片封裝。
10‧‧‧銀合金凸塊結構
20‧‧‧銀合金凸塊結構
30‧‧‧多層凸塊結構
40‧‧‧銀柱結構
50‧‧‧膜上晶片(COF)半導體封裝
60‧‧‧膜上晶片(COF)半導體封裝
70‧‧‧膜上晶片(COF)半導體封裝
80‧‧‧玻璃上晶片(COG)半導體封裝
90‧‧‧玻璃上晶片(COG)半導體封裝
100‧‧‧裝置
100'‧‧‧容器
100A‧‧‧入口
100B‧‧‧出口
101‧‧‧銀合金凸塊
101A‧‧‧晶粒
101B‧‧‧頂表面
101C‧‧‧底表面
101D‧‧‧側壁
102‧‧‧導電襯墊
102A‧‧‧頂表面
103‧‧‧鈍化層
104‧‧‧凸塊下金屬化(UBM)層
105‧‧‧晶種層
107‧‧‧金屬層
109‧‧‧第一遮罩層
109A‧‧‧開口
111‧‧‧陽極
112‧‧‧陰極
113‧‧‧電鍍浴
114‧‧‧覆蓋部件
115‧‧‧Ag1-xYx合金柱
115A‧‧‧頂表面
301‧‧‧可撓性膜
301A‧‧‧第一表面
301B‧‧‧第二表面
302‧‧‧導電層
303‧‧‧點框
304‧‧‧底部填充材料
305‧‧‧阻焊劑圖案
306‧‧‧焊料層
307‧‧‧點框
308‧‧‧焊料層
401‧‧‧透明基板
401A‧‧‧第一表面
402‧‧‧導電跡線
406‧‧‧ACF
406A‧‧‧塑膠球體
501‧‧‧晶粒
501-1‧‧‧晶粒
501-2‧‧‧晶粒
501-3‧‧‧晶粒
501A‧‧‧第一表面
501A'‧‧‧新第一表面
501A-1‧‧‧第一表面
501A-2‧‧‧第一表面
501A-3‧‧‧第一表面
501B‧‧‧第二表面
501B'‧‧‧新第二表面
501B-1‧‧‧第二表面
501B-2‧‧‧第二表面
501B-3‧‧‧第二表面
502‧‧‧金屬結構
502-1‧‧‧金屬結構
502-2‧‧‧金屬結構
502-3‧‧‧金屬結構
502A‧‧‧第一襯墊
502A-1‧‧‧第一襯墊
502A-2‧‧‧第一襯墊
502A-3‧‧‧第一襯墊
502B‧‧‧第二襯墊
502B-1‧‧‧第二表面
502B-2‧‧‧第二襯墊
502B-3‧‧‧第二表面
502C‧‧‧細長部分
503‧‧‧TSV/通孔
503-1‧‧‧TSV
503-2‧‧‧TSV
503-3‧‧‧TSV
503B‧‧‧底表面
504‧‧‧基板
505‧‧‧接合襯墊
506‧‧‧導電凸塊
507‧‧‧遮罩層
508‧‧‧晶種層
600‧‧‧半導體封裝
601‧‧‧晶粒
602‧‧‧扁平無引線
602A‧‧‧頂表面
602B‧‧‧底表面
603‧‧‧模製化合物
700‧‧‧覆晶球狀柵格陣列(FCBGA)封裝
701‧‧‧晶粒
702‧‧‧基板
702A‧‧‧第一表面
702B‧‧‧第二表面
703‧‧‧凸塊襯墊
704‧‧‧導電凸塊
705‧‧‧球式襯墊
800‧‧‧半導體結構
801‧‧‧裝置
802‧‧‧襯墊
802A‧‧‧頂表面
803‧‧‧鈍化層
803A‧‧‧開口
803B‧‧‧頂表面
804‧‧‧聚合層
804A‧‧‧頂表面
804B‧‧‧開口
805‧‧‧遮罩層
806‧‧‧RDL
806A‧‧‧焊盤部分
806B‧‧‧通孔部分
806D‧‧‧流道部分
807‧‧‧額外金屬層
當結合附圖閱讀時，可自以下詳細描述最佳地理解本發明之態樣。應強調，根據工業中之標準實務，各種特徵不按比例繪製。實際上，為了論述之清楚起見，可任意增大或減小各種特徵之尺寸。
圖1為根據本發明之一些實施例的銀合金凸塊結構之橫截面圖；圖2為根據本發明之一些實施例的粒徑分散曲線；圖3為根據本發明之一些實施例的銀合金凸塊結構之橫截面圖；圖4為根據本發明之一些實施例的多層凸塊結構之橫截面圖；圖5為根據本發明之一些實施例的具有覆蓋部件的銀柱結構之橫截面圖；圖6為根據本發明之一些實施例的具有銀合金凸塊結構之膜上晶片(COF)半導體結構之橫截面圖；圖7為根據本發明之一些實施例的展示於圖6中之接頭部分之放大視圖；圖8為根據本發明之一些實施例的具有多層凸塊結構之膜上晶片(COF)半導體結構之橫截面圖；圖9為根據本發明之一些實施例的展示於圖8中之接頭部分之放大視圖；圖10為根據本發明之一些實施例的具有銀合金柱及覆蓋部件之膜上晶片(COF)半導體結構之橫截面圖；圖11為根據本發明之一些實施例的具有銀合金凸塊結構之玻璃上晶片(COG)半導體結構之橫截面圖；圖12為根據本發明之一些實施例的具有多層凸塊結構之玻璃上晶片(COG)半導體結構之橫截面圖；圖13為根據本發明之一些實施例的具有多層凸塊結構之玻璃上 晶片(COG)半導體結構之橫截面圖；圖14至圖20展示根據本發明之一些實施例的製造銀合金柱結構之操作。
圖21為根據本發明之一些實施例的具有重分佈層(RDL)之半導體結構之俯視圖；圖22為根據本發明之一些實施例的具有沿圖21之AA'的重分佈層(RDL)之半導體結構之橫截面圖；圖23為根據本發明之一些實施例的具有包括金屬層的重分佈層(RDL)之半導體結構之橫截面圖；圖24至圖31展示根據本發明之一些實施例的製造重分佈層(RDL)之操作；圖32為根據本發明之一些實施例的具有若干穿矽通孔(TSV)的晶粒之橫截面圖；圖33為根據本發明之一些實施例的經堆疊且藉由穿矽通孔(TSV)彼此連接的若干晶粒之橫截面圖；圖34為根據本發明之一些實施例的安裝於基板上的若干經堆疊晶粒之橫截面圖；圖35至圖41展示根據本發明之一些實施例的製造鍍敷有銀合金的穿矽通孔(TSV)之操作；圖42為根據本發明之一些實施例的雙邊扁平無引線(DFN)封裝之俯視圖；圖43為根據本發明之一些實施例的沿圖42的BB'的雙邊扁平無引線(DFN)封裝之橫截面圖；及圖44為根據本發明之一些實施例的具有銀合金柱之覆晶球狀柵格陣列(FCBGA)封裝之橫截面圖。
在以下詳細描述中，列出了若干特定細節以便提供對本發明之全面瞭解。然而，熟習此項技術者應瞭解，本發明可在無該等特定細節的情況下實施。在其他情形中，未對熟知方法、程序、組件及電路進行詳細描述，以免混淆本發明。應理解，以下揭示內容提供用於建構各種實施例之不同特徵的許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本發明。當然，此等僅為實例，而並不意欲為限制性的。
下文詳細論述實施例之製作及使用。然而，應瞭解，本發明提供可在廣泛多種特定內容脈絡中體現的許多適用的發明性概念。所論述之特定實施例僅為說明製作及使用本發明之特定方式，而並不限制本發明之範疇。
在半導體封裝之金屬凸塊技術當中，金凸塊由於與此項技術中之材料特性及處理技術之類似性而最為風行。然而，高材料成本、較差結合可靠性及諸如低電導率及低熱導率之不令人滿意的材料特性仍為待解決之問題。製造金屬凸塊之替代成本節省方法係藉由產生多層凸塊，例如，Cu(底部層)、Ni(中間層)及Au(頂部層)凸塊。此方法節省金屬凸塊之金材料消耗，但銅底部層易受氧化及腐蝕，且因此產生可靠性憂慮。
當藉由回焊已沈積在襯墊上之焊料而將金凸塊接合至基板襯墊時，形成數個金/錫金屬間物(intermetallics)。因為金在熔融焊料中之高溶解率，具有金凸塊之焊料接頭在一次回焊之後具有大體積分率之金屬間化合物(其中AuSn4為主要相)，其使接頭大大變脆。在兩次或兩次以上回焊(對於裝配疊層封裝產品通常為需要的)之後，金凸塊可能完全耗盡且轉化成金/錫金屬間化合物。由於此等化合物及金屬間物與晶片側上之鋁襯墊之直接接觸的脆性，接頭經常由於在凸塊/晶片界面處開裂而通不過諸如機械墜落測試之可靠性測試。
銀凸塊的成本為金凸塊之二十分之一，且銀凸塊在本文中論述之三種金屬(Au、Cu、Ag)中具有最高電導率及最高熱導率。此外，銀凸塊之退火溫度低於金凸塊之退火溫度，因此大大減少鈍化裂痕之風險。就將銀凸塊接合至基板之焊料而言，在高於共晶溫度之溫度下，銀/錫界面表現出優於金/錫界面之結合特性的結合特性。在本發明之一些實施例中，銀合金用於銀凸塊以避免銀針、銀遷移、純銀所固有的氧化及硫化問題。
本發明之一些實施例提供一種具有銀合金凸塊之半導體結構。銀合金凸塊可為具有約0.005至約0.25原子%之非銀元件之二元合金或三元合金。在一些實施例中，因為銀合金凸塊係藉由電鍍而形成，因此觀測到均一的粒徑分佈，且可藉由量測粒徑分佈之標準差而量化該粒徑分佈。
本發明之一些實施例提供一種具有含有銀之多層合金凸塊之半導體結構。該多層合金凸塊包括具有約0.005至約0.25原子%之非銀元件的二元合金或三元合金。在一些實施例中，包括金(Au)之額外金屬層定位在該二元合金或三元合金上。在一些實施例中，該額外金屬層覆蓋該二元合金或三元合金之側壁。在一些實施例中，因為該多層合金凸塊係藉由電鍍而形成，因此觀測到均一粒徑分佈，且可藉由量測粒徑分佈之標準差而量化該粒徑分佈。
本發明之一些實施例提供一種包括經電鍍銀合金凸塊之膠帶自動結合(TAB)半導體結構。在一些實施例中，膜上晶片(COF)結構包括在薄膜上之銀合金凸塊與導電銅線之間的銀/錫界面。在一些實施例中，額外金屬層定位在該COF結構中之經電鍍銀合金凸塊上。在一些實施例中，該額外金屬層覆蓋該COF結構中之該經電鍍銀合金凸塊之側壁。
本發明之一些實施例提供一種包括經電鍍Ag1-xYx合金凸塊之玻 璃上晶片(COG)結構，該經電鍍Ag1-xYx合金凸塊將半導體晶片電耦接至導電層。在一些實施例中，該經電鍍Ag1-xYx合金凸塊之Y包括Pd及Au中之至少一者。在一些實施例中，額外金屬層定位在該COG結構中之經電鍍銀合金凸塊上。在一些實施例中，該額外金屬層覆蓋該COG結構中之該經電鍍銀合金凸塊之側壁。
本發明之一些實施例提供一種在一半導體結構中之經電鍍銀合金凸塊。在一些實施例中，由本文中所描述的經電鍍銀合金凸塊製成之銀合金薄膜具有自約250W/(mK)至約450W/(mK)之熱導率。在其他實施例中，該經電鍍銀合金凸塊具有自約35(Ωm)-1至約(Ωm)-1之電導率。
本發明之一些實施例提供一種半導體結構，其具有安置在具有該半導體結構之裝置上的銀合金柱。該銀合金柱可為包含約0.005至約0.25原子%之非銀元素之二元合金或三元合金。
在一些實施例中，該銀合金柱包括經電鍍Ag1-xYx合金，其中Y包括鈀(Pd)及金(Au)中之至少一者，且X為約0.005至約0.25。在一些實施例中，因為該銀合金柱係藉由電鍍而形成，因此觀測到均一粒徑分佈，且可藉由量測粒徑分佈之標準差而量化該粒徑分佈。
本發明之一些實施例提供一種半導體結構，其具有安置在鈍化層或具有該半導體結構之裝置上的重分佈層(RDL)。該RDL包括可為具有約0.005至約0.25原子%之非銀元素之二元合金或三元合金的銀合金。
在一些實施例中，該RDL包括經電鍍Ag1-xYx合金，其中Y包括鈀(Pd)及金(Au)中之至少一者，且X為約0.005至約0.25。在一些實施例中，包括金(Au)之額外金屬層安置在該銀合金上。
本發明之一些實施例提供一種半導體結構，其具有鍍敷有銀合金且穿過晶粒或中介物而作為「穿矽通孔(TSV)」的若干通孔，使得 該晶粒之一側經配置用於電連接另一晶粒。在一些實施例中，該銀合金可為包含約0.005至約0.25原子%之非銀元素之二元合金或三元合金。在一些實施例中，該銀合金包括經電鍍Ag1-xYx合金，其中Y包括鈀(Pd)及金(Au)中之至少一者，且X為約0.005至約0.25。
本發明之一些實施例提供一種半導體結構，其具有堆疊在彼此之上且藉由鍍敷有銀合金之若干TSV電互連之若干晶粒。在一些實施例中，該銀合金可為包含約0.005至約0.25原子%之非銀元素之二元合金或三元合金。在一些實施例中，該銀合金包括經電鍍Ag1-xYx合金，其中Y包括鈀(Pd)及金(Au)中之至少一者，且X為約0.005至約0.25。
本發明之一些實施例提供一種在一半導體封裝中之半導體結構。在一些實施例中，該半導體封裝為覆晶雙邊扁平無引線(FCDFN)封裝，其包括藉由若干銀合金柱與若干扁平無引線電連接的覆晶晶粒。在一些實施例中，該銀合金可為包含約0.005至約0.25原子%之非銀元素之二元合金或三元合金。在一些實施例中，該銀合金包括經電鍍Ag1-xYx合金，其中Y包括鈀(Pd)及金(Au)中之至少一者，且X為約0.005至約0.25。
本發明之一些實施例提供一種在一半導體封裝中之半導體結構。在一些實施例中，該半導體封裝為覆晶球狀柵格陣列(FCBGA)封裝，其包括藉由若干銀合金柱與安置在基板上之若干導電襯墊電連接的覆晶晶粒。在一些實施例中，該銀合金可為包含約0.005至約0.25原子%之非銀元素之二元合金或三元合金。在一些實施例中，該銀合金包括經電鍍Ag1-xYx合金，其中Y包括鈀(Pd)及金(Au)中之至少一者，且X為約0.005至約0.25。
定義
在描述及主張本發明時，將根據下文所闡述的定義使用以下術 語。
如本文所使用，「平均粒徑」係藉由諸如X射線繞射(XRD)、電子束散射型式(EBSP)、穿透電子顯微術(TEM)或掃描電子顯微術(SEM)之任何習知粒徑量測技術而量測。樣本之經預處理橫截面平面經準備用於本發明中所論述之粒徑量測。經受本文中所論述之量測中之任一者的橫截面平面為穿過銀合金凸塊結構10的銀合金凸塊101、具有垂直於縱向方向、平行於如圖1中所示之Y方向之平面法線的任何平面。
如本文所使用，用於平均粒徑量測之「電子束散射型式(EBSP)」由電腦分析程式(例如，TSL OIM分析)加以輔助。電腦分析程式之設定包括但不限於15度之晶界錯向、等於或大於0.1之CI值，及至少為5測試點之極小粒徑。在一些實施例中，EBSP量測之平均粒徑係藉由對至少在橫截面平面之三個不同測試位置上的粒徑求平均而獲得。在每一測試位置量測一預定區域。預定區域根據不同實施例之特徵而變化。每一測試位置距鄰近測試位置至少1mm遠。在一些實施例中，一個測試位置中之每一量測點之間的間隔為至少5μm。在一些實施例中，在20kV之加速電壓及100倍至500倍之放大率下觀測經受EBSP量測之所製備樣本。在一些實施例中，所製備樣本定位在70度之傾斜角處。
如本文所使用，用於平均粒徑量測之「穿透電子顯微術(TEM)或掃描電子顯微術(SEM)」係由影像分析程式(例如，CLEMEX Vision PE)加以輔助。在一些實施例中，TEM或SEM量測之平均粒徑係藉由對橫截面平面之至少三個不同測試位置上的粒徑求平均而獲得。在每一測試位置中量測一預定區域。該預定區域根據不同實施例之特徵而變化。每一測試位置距鄰近測試位置至少1mm遠。在一些實施例中，一個測試位置中之每一量測點之間的間隔為至少5μm。在一些實 施例中，在約5kV至約20kV之加速電壓及100倍至500倍之放大率下觀測經受TEM或SEM量測之所製備樣本。
如本文所使用，銀合金凸塊之「粒徑分佈之標準差」係指使用本文中所論述之影像分析程式獲得之統計結果。在獲得粒徑分佈之分散曲線之後，一個標準差被定義為自均值粒徑(期望值)偏離之粒徑，其中粒徑在所偏離粒徑與均值粒徑之間的晶粒之數目占到晶粒之總數目的34%。
圖1為具有連接至導電襯墊102的銀合金凸塊101之銀合金凸塊結構10的橫截面。銀合金凸塊101及導電襯墊102定位在裝置100上。在一些實施例中，裝置100包括但不限於諸如記憶體、電晶體、二極體(PN或PIN接面)、積體電路或可變電抗器之主動裝置。在其他實施例中，裝置100包括諸如電阻器、電容器或電感器之被動裝置。
銀合金凸塊101之微觀結構展示於圖1中。銀合金凸塊101之橫截面係藉由沿縱向方向(Y方向)切割銀合金凸塊結構10而製備，且因此獲得XY表面。使用電子顯微鏡，在XY平面上識別銀合金凸塊101之晶粒結構，且在本文中所論述之影像分析軟體之幫助下，可獲得粒徑分佈之統計資訊。
參看圖1，晶粒101A之一區域用直線劃出陰影。銀合金凸塊101中所示的SEM圖像係取自本文中所描述的銀合金凸塊101之真實橫截面平面。在一些實施例中，因為銀合金凸塊101係藉由電鍍操作而形成，因此粒徑分佈相當均一，且未觀測到如螺柱凸塊(未圖示)中之受熱影響區(HAZ)的受熱影響區。HAZ由於以下事實而產生粒徑之突變：晶粒生長程序經受局部高溫。通常，粒徑在HAZ中明顯地增大。在本發明之一些實施例中，可在銀合金凸塊101之晶粒中識別出子晶粒結構。舉例而言，在晶粒101A中，可以如下方式看到子晶粒域：可識別出藉由域邊界分離的晶粒101A內之若干區。
在一些實施例中，銀合金凸塊101包括Ag1-xYx合金。Ag1-xYx合金中之物質Y包括以任何重量百分比與銀形成完成固溶體之金屬。在一些實施例中，可自二元相圖識別出物質Y。二元相圖中形成透鏡形狀之液相線及固相線指示在兩種金屬組分之任何組成下的固溶體之完全混合。舉例而言，在本發明之一些實施例中，物質Y為金(Au)、鈀(Pd)，或其組合。在一些實施例中，Ag1-xYx合金為諸如Ag1-xAux或Ag1-xPdx之二元金屬合金。在一些實施例中，Ag1-xYx合金為諸如Ag1-x(AuPd)x之三元金屬合金。在一些實施例中，物質Y在Ag1-xYx合金中之含量介於約0.005至約0.25原子%之間。
在一些實施例中，圖1中的銀合金凸塊101之粒徑形成如圖2中所示之分散曲線。圖2中之分散曲線係經由諸如但不限於CLEMEX Vision PE之影像分析軟體程式而獲得。在圖2中，該分散曲線之X軸指示以微米(μm)計的粒徑，而該分散曲線之Y軸展示經正規化之晶粒數目。本發明中之粒徑計算係藉由電腦分析程式(例如，TSL OIM分析)加以輔助。在一些實施例中，電腦分析程式將晶粒之面積轉換為具有相同面積之假設圓，且此假設圓之直徑被界定為按一長度單位(通常為微米)之粒徑。然而，粒徑計算不限於上述操作。在其他實施例中，平均粒徑係藉由在本文中所描述的銀合金凸塊結構之橫截面平面之TEM圖像或SEM圖像上繪製對角線，並將該對角線之長度除以該對角線所遇到之晶粒的數目而獲得。任何粒徑量測操作為適當的，只要其藉由電腦軟體加以輔助或其係以一致且系統化之方式進行即可。
在繪出如圖2中所示的分散曲線之後，可將標準差量測為銀合金凸塊101之微觀結構之形態特徵。在一些實施例中，該分散曲線具有近鐘形狀(eschewed bell shape)，其最大值較接近於該分散曲線之右端。在一些實施例中，粒徑之均值或期望值由分散曲線之最大值表示。如圖2中所示，均值M對應於粒徑A，其在一些實施例中在約0.7 μm至約0.8μm之範圍內。離開均值M至正方向一個標準差(+1σ)對應於粒徑C，其在一些實施例中在約1.0μm至約1.1μm之範圍內。離開平均值M至負方向一個標準差(-1σ)對應於粒徑B，其在一些實施例中在約0.4μm至約0.5μm之範圍內。在一些實施例中，一個標準差被定義為自均值M偏離之粒徑，且其中粒徑在所偏離粒徑B或C與均值M之間的晶粒之數目占到晶粒之總數目的34%。注意，獲自實際粒徑量測之分散曲線並不必須關於均值M對稱，且因此，在一些實施例中，離開均值M至粒徑C處之正方向一個標準差(+1σ)與均值M之間的差異未必與在粒徑B處在負方向上離開均值M一個標準差(-1σ)與均值M之間的差異相同。
在本發明之一些實施例中，粒徑C與粒徑A之間的差異約自0.2μm至約0.4μm。在其他實施例中，粒徑B與粒徑A之間的差異約自0.2μm至約0.4μm。藉由利用本發明中所論述之電鍍操作，銀合金凸塊101之粒徑表現出均一分佈，且離開均值M(至正或負方向)一個標準差之間的差異可量化為在約0.2μm至約0.4μm之範圍內。
參看圖3，展示銀合金凸塊結構20之橫截面。與圖1中之銀合金凸塊結構10相比，銀合金凸塊結構20進一步包括凸塊下金屬化(UBM)層104及晶種層105。在一些實施例中，晶種層105含有銀或銀合金。在一些實施例中，晶種層105係藉由諸如化學氣相沈積(CVD)、濺鍍、電鍍等適當操作而製備。在一些實施例中，UBM層104具有單層結構或包括由不同材料形成之若干子層的複合結構，且包括選自以下各者之一(或多)層：鎳(Ni)層、鈦(Ti)層、鈦鎢(W)層、鈀(Pd)層、金(Au)層、銀(Ag)層，及其組合。
如圖3中所示，銀合金凸塊101之高度H1係自銀合金凸塊101之頂表面101B至導電襯墊102之頂表面102A而量測。在一些實施例中，銀合金凸塊101或Ag1-xYx合金之高度H1在約9μm至約15μm之範圍內。 與銀合金凸塊101之高度H1成比例，UBM層104之厚度T2與晶種層105之厚度T1相當。在一些實施例中，UBM層104之厚度T2在約1000A至約3000A之範圍內，且晶種層105之厚度T1在約1000A至約3000A之範圍內。
參看圖4，展示多層凸塊結構30之橫截面。與圖3中之銀合金凸塊結構20相比，多層凸塊結構30進一步包括在銀合金凸塊101之頂表面101B上之金屬層107。在一些實施例中，多層凸塊結構30包括銀合金凸塊101，銀合金凸塊101具有安置在晶種層105、UBM層104及導電襯墊102上之底表面101C。因此，金屬層107、銀合金凸塊101、晶種層105、UBM層104與導電襯墊102與彼此電連接。在一些實施例中，金屬層107及銀合金凸塊101經由晶種層105、UBM層104及導電襯墊102電連接至裝置100。
在一些實施例中，金屬層107包括不同於銀之金屬材料。在其他實施例中，金屬層107包括金。金屬層107之厚度H2足夠厚以在銀合金凸塊101與外部裝置之電路(諸如晶粒、基板、封裝、印刷電路板(PCB)等)之間形成接頭界面。在一些實施例中，金屬層107之厚度H2自約1μm至約3μm，且金屬層107係藉由電鍍操作而形成。
在圖4中，多層凸塊結構30包括凸塊下金屬化(UBM)層104及晶種層105。在一些實施例中，晶種層105含有銀或銀合金，且係藉由諸如化學氣相沈積(CVD)、濺鍍、電鍍等適當操作而製備。在一些實施例中，UBM層104具有單層結構或包括由不同材料形成之若干子層的複合結構，且包括選自以下各者之一(或多)層：鎳(Ni)層、鈦(Ti)層、鈦鎢(W)層、鈀(Pd)層、金(Au)層、銀(Ag)層，及其組合。
圖4中所示的銀合金凸塊101包括Ag1-xYx合金，其中物質Y為金、鈀，或其組合。舉例而言，Ag1-xYx合金可為諸如Ag1-xAux或Ag1-xPdx之二元金屬合金，此外，Ag1-xYx合金可為諸如Ag1-x(AuPd)x之三元金 屬合金。在一些實施例中，物質Y在Ag1-xYx合金中之含量介於約0.005至約0.25原子%之間。在一些實施例中，Ag1-xYx合金中之物質Y包括以任何重量百分比與銀形成完全固溶體之金屬。如圖4中所示，銀合金凸塊101之高度H1在約9μm至約15μm之範圍內。
參看圖5，展示銀柱結構40之橫截面。與圖4中的多層凸塊結構30相比，圖4中的多層凸塊結構30之銀合金凸塊101及金屬層107不同於圖5中的銀柱結構40之柱115及覆蓋部件114。此外，圖5中的柱115與圖4中的銀合金凸塊101在大小上具有實質差異。在一些實施例中，圖5中的柱115的大小大於圖4中的銀合金凸塊101。柱115的高度大於銀合金凸塊101。在一些實施例中，柱115的高度自約30μm至約100μm，而銀合金凸塊101的高度自約9μm至約15μm。與圖4及圖5中所示的數字標記具有相同數字標記之元件係指相同元件或其等效物，且為簡單起見不在此處加以重複。在一些實施例中，柱115安置在包括晶種層105及UBM層104之導電襯墊102上。在一些實施例中，柱115、晶種層105、UBM層104與裝置100電連接。在一些實施例中，晶種層105包括與柱115介接之銀或銀合金。
在一些實施例中，柱115包括Ag1-xYx合金作為Ag1-xYx合金柱，其中，其中物質Y為金、鈀，或其組合。舉例而言，Ag1-xYx合金可為諸如Ag1-xAux或Ag1-xPdx之二元金屬合金，此外，Ag1-xYx合金可為諸如Ag1-x(AuPd)x之三元金屬合金。在一些實施例中，物質Y在Ag1-xYx合金中之含量介於約0.005至約0.25原子%之間。在一些實施例中，Ag1-xYx合金中的物質Y包括以任何重量百分比與銀形成完成固溶體之金屬。
在一些實施例中，Ag1-xYx合金柱115係藉由諸如電鍍、濺鍍或其類似者之任何適當操作而形成。如圖5中所示，Ag1-xYx合金柱115之高度H1在約30μm至約100μm之範圍內。
在一些實施例中，額外覆蓋部件114安置在Ag1-xYx合金柱115之頂表面115A上，且因此覆蓋部件114、Ag1-xYx合金柱115、晶種層105、UBM層104與裝置100與彼此電連接。在一些實施例中，覆蓋部件114包括諸如錫或銀之用於與另一半導體結構電連接之焊料材料。在一些實施例中，覆蓋部件114呈半球形形狀。在一些實施例中，覆蓋部件114係藉由諸如膠合或電鍍之任何適當操作而形成於Ag1-xYx合金柱115上。
在一些實施例中，覆蓋部件114為Ag1-xYx合金柱115與外部裝置之電路(諸如晶粒、基板、封裝、印刷電路板(PCB)等)之間的接頭界面。在一些實施例中，覆蓋部件114之高度H3自約1μm至約5μm。在一些實施例中，覆蓋部件114具有與Ag1-xYx合金柱115之直徑Dpillar實質上相同的直徑Dcover。
參看圖6，展示膜上晶片(COF)半導體封裝50之橫截面。在一些實施例中，COF半導體封裝50包括可撓性膜301，該可撓性膜301具有第一表面301A及第二表面301B。可撓性膜301包括但不限於可撓性印刷電路板(FPCB)或聚醯亞胺(PI)。導電層302包括電路，或導電跡線經圖案化於可撓性膜301之第一表面301A上。
在圖6中，與圖1及圖3中所示的數字標記具有相同數字標記之元件係指相同元件或其等效物，且為簡單起見不在此處加以重複。在圖5中，兩個銀合金凸塊101將裝置100電耦接至可撓性膜301之導電層302以成為COF半導體封裝50。在一些實施例中，例如無溶劑環氧樹脂之具有適當黏度之底部填充材料304注入至可撓性膜301與裝置100之間的空間中以包圍銀合金凸塊101。
圖6中所示的銀合金凸塊101包括Ag1-xYx合金，其中物質Y為金、鈀，或其組合。舉例而言，Ag1-xYx合金可為諸如Ag1-xAux或Ag1-xPdx之二元金屬合金，此外，Ag1-xYx合金可為諸如Ag1-x(AuPd)x之三元金 屬合金。在一些實施例中，物質Y在Ag1-xYx合金中之含量介於約0.005至約0.25原子%之間。在一些實施例中，Ag1-xYx合金中的物質Y包括以任何重量百分比與銀形成完成固溶體之金屬。
如圖6中所示，銀合金凸塊101之高度H1在約9μm至約15μm之範圍內，且鄰近的銀合金凸塊101之間的間距P低於10μm。在一些實施例中，導電襯墊102之寬度W在約20μm至約30μm之範圍內。
在圖6中，阻焊劑圖案305定位在導電層302上。焊料層306根據阻焊劑圖案305而施加於導電層302上。焊料層306經組態用於使銀合金凸塊101與導電層302結合。在本發明之一些實施例中，焊料層306包括習知焊料材料、無鉛焊料材料等。
圖6中的接頭部分由點框303包圍，且經放大，如圖7中所示。參看圖7，焊料層306不僅包括焊料材料自身且亦包括Ag1-aSna合金。在一些實施例中，Ag1-aSna合金至少包括Ag0.5Sn0.5合金。在某些實施例中，當用於COF的在銀合金凸塊側設定的內部引線結合(ILB)溫度為約攝氏400度時，AgSn合金系統之液相實質上大於AuSn合金系統之液相(給定在合金凸塊之自由端設定的相同結合溫度)。AgSn合金之過量液相促進銀合金凸塊101與導電層302之間的黏附，且因此藉由使用基於Ag之合金凸塊在AgSn合金系統中獲得較好接面可靠性。另一方面，用於COF之較低ILB溫度可用於AgSn合金系統中。例如低於攝氏400度之較低ILB溫度可防止可撓性膜301變形或收縮。在其他實施例中，各向異性導電膜(ACF)可用以連接銀合金凸塊101與導電層302。
參看圖7，展示銀合金凸塊101之微觀結構。銀合金凸塊101之平均粒徑在約0.5μm至約1.5μm之範圍內。因為銀之熔化溫度為約攝氏962度，因此施加至銀合金凸塊101之退火溫度可低於攝氏250度以避免圖1、圖3、圖4、圖5及圖6中所示的鈍化層103之開裂。與金之較高熔化溫度(攝氏1064度)相比，較低熔化溫度導致較低退火溫度，且因 此諸如鈍化層之先前生長的結構經受較低熱應力。在一些實施例中，在於低於攝氏250度之溫度下對銀合金凸塊101進行退火之後，藉由本文中所描述的方法量測的Ag1-xYx合金之平均粒徑為約1μm。
參看圖8，展示膜上晶片(COF)半導體封裝60之橫截面。COF半導體封裝60包括可撓性膜301，該可撓性膜301具有第一表面301A及第二表面301B。可撓性膜301包括但不限於可撓性印刷電路板(FPCB)或聚醯亞胺(PI)。諸如導電銅跡線之導電層302經圖案化於可撓性膜301之第一表面301A上，且阻焊劑圖案305定位在導電層302上。在圖8中，與圖1、圖3、圖4、圖5及圖6中所示的數字標記具有相同數字標記的元件係指相同元件或其等效物，且為簡單起見不在此處加以重複。在圖8中，包括銀合金凸塊101及金屬層107之兩個多層凸塊結構將裝置100電耦接至可撓性膜301之導電層302。在一些實施例中，例如無溶劑環氧樹脂之具有適當黏度的底部填充材料304注入至可撓性膜301與裝置100之間的空間中。在金屬層107係由經電鍍金膜製成之情況下，可撓性膜301與銀合金凸塊101之後續結合可利用此項技術中對於金凸塊所習知之結合操作。
圖8中所示的銀合金凸塊101包括Ag1-xYx合金，其中物質Y為金、鈀，或其組合。舉例而言，Ag1-xYx合金可為諸如Ag1-xAux或Ag1-xPdx之二元金屬合金，此外，Ag1-xYx合金可為諸如Ag1-x(AuPd)x之三元金屬合金。在一些實施例中，物質Y在Ag1-xYx合金中之含量介於約0.005至約0.25原子%之間。在一些實施例中，Ag1-xYx合金中的物質Y包括以任何重量百分比與銀形成完全固溶體之金屬。圖8中所示的金屬層107包括不同於銀之金屬材料，例如金。
如圖8中所示，銀合金凸塊101之高度H1在約9μm至約15μm之範圍內，且鄰近的銀合金凸塊101之間的間距P低於10μm。金屬層107之高度H2在約1μm至約3μm之範圍內。在一些實施例中，導電襯墊102 之寬度W在約20μm至約30μm之範圍內。
在圖8中，阻焊劑圖案305定位在導電層302上。焊料層308施加至金屬層107與導電層302之接頭。在本發明之一些實施例中，焊料層308為習知焊料材料或無鉛焊料。由點框307包圍的圖8中的接頭部分經放大且於圖9中展示。參看圖9，焊料層308不僅包括焊料材料自身，且亦包括Ag1-aSna合金(若金屬層107係由金(Au)製成)。在一些實施例中，Au1-aSna合金至少包括Au0.5Sn0.5合金。在其他實施例中，各向異性導電膜(ACF)可用以連接金屬層107與導電層302。
參看圖10，展示膜上晶片(COF)半導體封裝70之橫截面。在圖10中，與圖6中所示的數字標記具有相同數字標記之元件係指相同元件或其等效物，且為簡單起見不在此處加以重複。在圖10中，包括Ag1-xYx合金柱115及覆蓋部件114之兩個柱結構將裝置100電耦接至可撓性膜301之導電層302。在一些實施例中，例如無溶劑環氧樹脂之具有適當黏度之底部填充材料304注入至可撓性膜301與裝置100之間的空間中。
圖10中所示的Ag1-xYx合金柱115包括Ag1-xYx合金，其中物質Y為金、鈀，或其組合。舉例而言，Ag1-xYx合金可為諸如Ag1-xAux或Ag1-xPdx之二元金屬合金，此外，Ag1-xYx合金可為諸如Ag1-x(AuPd)x之三元金屬合金。在一些實施例中，物質Y在Ag1-xYx合金中之含量介於約0.005至約0.25原子%之間。在一些實施例中，Ag1-xYx合金中的物質Y包括以任意重量百分比與銀形成完成固溶體之金屬。
在圖10中，覆蓋部件114與導電層302結合，使得裝置100藉由諸如回焊之熱處理而與可撓性膜301電連接。在一些實施例中，覆蓋部件114包括諸如錫或銀之焊料材料。
在本發明之一些實施例中，如圖11中所示，本文中論述之銀合金凸塊101亦可用於玻璃上晶片(COG)半導體封裝80中。透明基板401之 第一表面401A上的導電跡線402藉由各向異性導電膜(ACF)406而與裝置100之銀合金凸塊101電連接。在一些實施例中，透明基板401為玻璃基板。在一些實施例中，ACF 406包括塗有Au之塑膠球體406A，其直徑自約3μm至約5μm，分散在熱固性環氧樹脂基質中。在一些實施例中，用於在COG半導體封裝80中使用ACF 406之結合溫度為約攝氏200度。
在本發明之一些實施例中，如圖12中所示，本文中論述之多層凸塊結構亦可用於玻璃上晶片(COG)半導體封裝90中。玻璃基板401之第一表面401A上的導電跡線402藉由各向異性導電薄(ACF)406與裝置100之銀合金凸塊101電連接。在一些實施例中，導電跡線402係由諸如氧化銦錫(ITO)之透明且導電材料製成。在一些實施例中，ACF 406包括塗有Au之塑膠球體406A，其直徑自約3μm至約5μm，分散在熱固性環氧樹脂基質中。在一些實施例中，用於在COG半導體封裝90中使用ACF 406之結合溫度為約攝氏200度。在一些實施例中，安置在銀合金凸塊101上之金屬層107為經電鍍金膜，其厚度自約1μm至約3μm。在此情況下，對於金凸塊技術習知之結合操作可用於連接銀合金凸塊101與導電跡線402。
在本發明之一些實施例中，如圖13中所示，本文中論述之多層凸塊結構亦可用於玻璃上晶片(COG)半導體封裝101中。玻璃基板401之第一表面401A上的導電跡線402與銀合金凸塊101之間的電連接為各向異性導電膜(ACF)406。舉例而言，ACF 406包括塗有Au之塑膠球體406A，其直徑自約3μm至約5μm，分散在熱固性環氧樹脂基質中。在一些實施例中，用於在COG半導體封裝101中使用ACF 406之結合溫度為約攝氏200度。在一些實施例中，安置在銀合金凸塊101上之金屬層107為經電鍍金膜，其厚度自約1μm至約3μm，覆蓋銀合金凸塊101之頂表面101B及側壁101D。在此情況下，對於金凸塊技術習 知之結合操作可用於經由ACF 406及金屬層107連接銀合金凸塊101與導電跡線402。在一些實施例中，頂表面101B上之金屬層107的厚度不同於覆蓋銀合金凸塊101之側壁101D之金屬層107的厚度。
可易於藉由選擇適當電鍍浴來調整本文中論述的銀合金凸塊及銀帽蓋之硬度。舉例而言，可將用於如圖11、圖12及圖13中的COG應用之銀合金凸塊之硬度調整至約100HV。對於另一實例，可將用於如圖6及圖8中的COF應用之銀合金凸塊之硬度調整至約55HV。因為純銀之硬度(約85HV)介於55HV與100HV之間，因此可藉由使用不同電鍍浴來電鍍銀合金凸塊而定製具有所要硬度之銀合金。在一些實施例中，COG應用需要銀合金凸塊具有較大硬度以促進ACF結合操作。在其他實施例中，COF應用需要銀合金凸塊具有較低硬度以防止損傷可撓性膜上之導電跡線。
圖14至圖19展示本發明中描述的圖5之銀合金柱115之製造操作。在圖14中，在鈍化層103及導電襯墊102之一部分上形成UBM層104。在一些實施例中，UBM層104係藉由對材料進行CVD、濺鍍、電鍍或無電極鍍敷而形成，該等材料係選自鎳、鈦、鈦鎢、鈀、金、銀，及其組合。在一些實施例中，將UBM層104之厚度T2控制在自約1000A至約3000A之範圍內。
在圖15中，將晶種層105沈積在UBM層104上。在一些實施例中，晶種層105係藉由對含有銀之材料進行CVD、濺鍍、電鍍或無電極鍍敷而形成。在一些實施例中，將晶種層105之厚度T1控制為與UBM層104之厚度T2相當。舉例而言，在自約1000A至約3000A之範圍內。
參看圖16，在晶種層105上方形成可為硬式遮罩或光阻劑之第一遮罩層109。在晶種層105及導電襯墊102上方形成第一遮罩層109之開口109A。開口109A用於接收導電柱材料。在一些實施例中，第一遮 罩層109係由厚度T3大於待鍍敷之導電柱之厚度的正光阻劑製成。在其他實施例中，第一遮罩層109係由負光阻劑製成。
圖17展示電鍍操作，且圖18展示其後之結果。圖17展示一電鍍系統，其包括容納電鍍浴113、陽極111及陰極112之容器100'。在一些實施例中，陽極111不可溶且可由塗有鉑之鈦製成，沈積有晶種層105之裝置100定位在陰極112處，且電鍍浴113含有基於氰化物之鍍敷溶液，包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4及其鹽中之至少一者。
在一些實施例中，直流電(DC)施加至連接至陰極之裝置100用於還原裝置100之晶種層105上的銀離子、金離子或鈀離子。在一些實施例中，直流電(DC)具有範圍介於約0.1ASD至約1.0ASD之電鍍電流密度。在一些實施例中，將電鍍浴113之pH值控制為約中性，例如自約6至約8。將電鍍浴113之溫度控制為約攝氏40度至攝氏50度。在一些實施例中，可藉由定位在容器100'下之熱板(未圖示)來維持電鍍浴113之溫度。在其他實施例中，可藉由一電鍍溶液循環系統來維持電鍍浴113之溫度，在該電鍍溶液循環系統中，出口100B排放電鍍溶液，且入口100A吸入溫度受控之電鍍溶液。可將濃度自約2ml/L至約5ml/L之包括草酸鹽之適當調平劑添加至電鍍浴113。
參看圖17，陰極112包括沈積有含有銀或銀合金之晶種層105的裝置100，且在陰極處發生的反應可為以下反應中的一者：KAg(CN)2 → K ++Ag ++2CN -
KAu(CN)2 → K ++Au ++2CN -
K 2 Pd(CN)4 → 2K ++Pd 2++4CN -
圖17中所示的陽極111包括鉑電極，且其上發生的反應可為：2H 2 O → 4 H ++O 2(g)+4e -
外部DC電流之正端連接至陽極111，且外部DC電流之負端連接至陰極112。如圖17中可見，經還原之銀離子及經還原之金離子沈積 至裝置100之晶種層105上，填充由第一遮罩層109界定之開口109A且在開口109A內形成AgAu二元合金。
在一些實施例中，若電鍍浴113包括銀離子源(例如，KAg(CN)2)及鈀離子源(例如，K2Pd(CN)4)，則經由上文描述之相同電鍍操作設定，經還原之銀離子及經還原之金離子沈積至裝置100之晶種層105上，填充由第一遮罩層109界定之開口109A且在開口109A內形成AgPd二元合金。
在一些實施例中，若電鍍浴113包括銀離子源(例如，KAg(CN)2及其鹽)、金離子源(例如，(CN)2及其鹽)及鈀離子源(例如，K2Pd(CN)4及其鹽)，則經由上文描述之相同電鍍操作設定，經還原之銀離子、經還原之金離子及經還原之鈀離子沈積至裝置100之晶種層105上，填充由第一遮罩層109界定之開口109A，且在開口109A內形成AgAuPd三元合金。
在如圖17中所示的電鍍操作之後，自電鍍浴113移除裝置100，且包括Ag1-xYx合金之銀合金柱115形成於如圖18中所示的晶種層105上。Ag1-xYx合金柱115形成於導電襯墊102及裝置100上方。
在於開口109A內形成Ag1-xYx合金柱115之後，覆蓋部件114形成於如圖19中所示的Ag1-xYx合金柱115之頂表面115A上。在一些實施例中，覆蓋部件114包括諸如錫或銀之焊料材料。在一些實施例中，覆蓋部件114係藉由模板印刷、膠合、電鍍、無電極鍍敷或其類似者而形成於Ag1-xYx合金柱115上。
在圖20中，藉由剝除操作移除第一遮罩層109。另外，亦藉由蝕刻操作移除由第一遮罩層109覆蓋之UBM層104及晶種層105以隔離Ag1-xYx合金柱115。在一些實施例中，覆蓋部件114如在圖20中般在回焊操作之後呈半球形形狀。在一些實施例中，覆蓋部件114經組態用於與外部裝置上之襯墊或外部裝置內之電路結合，使得裝置100經由 Ag1-xYx合金柱115及覆蓋部件114而與外部裝置電連接。
在本發明之一些實施例中，本文中論述之包括Ag1-xYx合金之銀合金亦可用於在半導體結構800內形成再分佈層(RDL)806，如圖21及圖22中所示。RDL 806將半導體結構800內之電路的路徑自襯墊802重新導引至焊盤部分806A。焊盤部分806A經組態用於容納諸如金線之導電線或諸如焊球之導電凸塊，使得半導體結構800藉由使外部裝置上之結合襯墊與導電凸塊結合而與另一外部裝置電連接。
圖21展示半導體結構800之RDL 806之俯視圖。RDL 806包括焊盤部分806A、通孔部分806B及連接焊盤部分806A與通孔部分806B之流道部分806D。在一些實施例中，包括Ag1-xYx合金之RDL 806係藉由電鍍、濺鍍等而形成於鈍化層803或聚合層804上方。在一些實施例中，通孔部分806B穿過鈍化層803及聚合層804。在一些實施例中，通孔部分806B與襯墊802電連接。
在一些實施例中，RDL 806包括Ag1-xYx合金，其可為具有約0.005至約0.25原子%之非銀元素的二元合金或三元合金。在一些實施例中，RDL 806包括經電鍍Ag1-xYx合金，其中Y包括鈀(Pd)及金(Au)中之至少一者，且X為約0.005至約0.25。在一些實施例中，Ag1-xYx合金為諸如Ag1-xAux或Ag1-xPdx之二元金屬合金。在一些實施例中，Ag1-xYx合金為諸如Ag1-x(AuPd)x之三元金屬合金。在一些實施例中，物質Y在Ag1-xYx合金中之含量介於約0.005至約0.25原子%之間。
圖22展示半導體結構800之沿圖21之AA'的橫截面圖。在一些實施例中，如在圖22中，半導體結構800包括諸如晶粒或基板之裝置801。在一些實施例中，襯墊802安置在裝置801上。襯墊802為用於連接裝置801內的電路與外部電路或裝置的接觸端子。在一些實施例中，諸如氮氧化矽或氮化矽之鈍化層803安置在裝置801上方且覆蓋襯墊802之頂表面802A的一部分。在一些實施例中，諸如聚醯亞胺或聚 苯并噁唑(PBO)之聚合材料804安置在襯墊802及鈍化層803上方。
在一些實施例中，RDL 806安置在鈍化層803及裝置801上方。在一些實施例中，RDL 806安置在聚合材料804之頂表面804A上。在一些實施例中，焊盤部分806A經組態用於容納導電線或導電凸塊，使得裝置801可經由導電線或導電凸塊與另一半導體結構電連接。在一些實施例中，焊盤部分806A經組態用於後續線接合操作。焊盤部分806A容納金屬線之一端，使得焊盤部分806A電連接於與金屬線之另一端結合的外部電路。在一些實施例中，焊盤部分806A容納導電凸塊，該導電凸塊經組態用於結合在另一半導體結構之結合襯墊上。
圖23展示半導體結構800之沿圖21之AA'的橫截面圖。在一些實施例中，RDL 806為多層結構，其包括Ag1-xYx合金及安置在電鍍有Ag1-xYx合金之RDL 806上之額外金屬層807。在一些實施例中，額外金屬層807包括金(Au)。在一些實施例中，金屬層807係藉由電鍍操作而形成。在一些實施例中，在焊盤部分806A上方的金屬層807經組態用於容納諸如金線之導電線或諸如焊球之導電凸塊，使得半導體結構800藉由使外部裝置上之結合襯墊與導電凸塊或金線結合而與另一外部裝置電連接。
圖24至圖31展示如在圖21至圖23中具有RDL 806(包括Ag1-xYx合金)的半導體結構800之製造操作。在圖24中，提供裝置801及襯墊802。襯墊802安置在裝置801上。在一些實施例中，裝置801為包括組件及連接該組件之電路的晶粒或基板。在一些實施例中，襯墊802包括鋁。
在圖25中，鈍化層803安置在裝置801及襯墊802上方。在一些實施例中，鈍化層803係藉由諸如氧化矽、氮氧化矽、氮化矽等介電材料形成。在圖26中，藉由蝕刻操作在襯墊802之頂表面802A上形成開口803A。在圖27中，聚合材料804安置在襯墊802及鈍化層803上方。 聚合材料804填充開口803A，且沿鈍化層803之頂表面803B延伸。
在圖28中，開口804B形成於襯墊802之頂表面802A上及鈍化層803之開口803A內。在一些實施例中，開口804B係藉由蝕刻操作而形成。在圖29中，遮罩層805按預定圖案安置在聚合材料804之頂表面804A上。在一些實施例中，遮罩層805可為硬式遮罩或光阻劑。遮罩層805係由正或負光阻劑製成。在一些實施例中，遮罩層805之預定圖案係藉由微影操作而形成，使得聚合材料804之頂表面804A的一部分由遮罩層805覆蓋。
在圖30中，RDL 806形成於聚合層804上。RDL 806係藉由電鍍Ag1-xYx合金而形成。在一些實施例中，半導體裝置800浸沒在含有基於氰化物的鍍敷溶液之電鍍浴中，該鍍敷溶液包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4及其鹽中之至少一者。半導體裝置800連接至陰極，使得銀離子、金離子及鈀離子自鍍敷溶液被還原，且沈積至聚合層804上，且因此形成包括AgAu二元合金(Ag1-xAux)、AgPd(Ag1-xPdx)二元合金或AgAuPd三元合金(Ag1-x(AuPd)x)之RDL 806。在一些實施例中，X範圍介於約0.005至約0.25原子%之間。在一些實施例中，直流電(DC)施加至連接至陰極之半導體裝置800用於還原半導體裝置800之聚合層804上的銀離子、金離子或鈀離子。該直流電具有範圍介於約0.1ASD至約1.0ASD之電鍍電流密度。在圖31中，藉由剝除操作移除遮罩層805，且因此形成具有經電鍍Ag1-xYx合金之RDL 806。
在一些實施例中，RDL 806為如圖23中之多層結構，且因此額外金屬層807安置在電鍍有Ag1-xYx合金之RDL 806上。在一些實施例中，金屬層807在剝除遮罩層805之前藉由電鍍操作形成於RDL 806上。在一些實施例中，金屬層807係藉由無電極鍍敷操作而形成於RDL 806上。
在本發明之一些實施例中，本文中論述之包括Ag1-xYx合金之銀 合金亦可用於填充穿過晶粒、晶圓、中介物或基板之穿矽通孔(TSV)，如圖32至圖34中所示。圖32展示晶粒501，其包括第一表面501A及與第一表面501A對置之第二表面501B。在一些實施例中，晶粒501具有鍍敷有Ag1-xYx合金之若干TSV 503。TSV 503自第一表面501A至第二表面501B穿過晶粒501。在一些實施例中，TSV 503由Ag1-xYx合金填充，該Ag1-xYx合金可為具有約0.005至約0.25原子%之非銀元素的二元合金或三元合金。在一些實施例中，Ag1-xYx合金之Y包括鈀(Pd)及金(Au)中之至少一者，且X自約0.005至約0.25。在一些實施例中，TSV 503具有高縱橫比。在一些實施例中，TSV 503之縱橫比自約3至約20。在一些實施例中，TSV 503具有自約1μm至約100μm之直徑Dtsv，且具有自約5μm至約500μm之高度Htsv。
在一些實施例中，TSV 503藉由電鍍操作由Ag1-xYx合金填充以形成金屬結構502。在一些實施例中，金屬結構502包括在第一表面501A上的第一襯墊502A、在第二表面501B上的第二襯墊502B，及自第一表面501A延伸至第二表面501B之細長部分502C。在一些實施例中，第一襯墊502A及第二襯墊502B經組態用於容納外部晶粒上之另一襯墊。在一些實施例中，第一襯墊502A及第二襯墊502B經組態用於容納導電凸塊或導電柱以便與外部晶粒結合。在一些實施例中，第一襯墊501A在TSV 503之一端安置在第一表面501A上，且第二襯墊502B在TSV 503之另一端安置在第二表面501B上。在一些實施例中，第一襯墊502A及第二襯墊502B分別包含銀或金。
圖33展示藉由結合TSV(503-1、503-2、503-3)之金屬結構(502-1、502-2、502-3)而向上堆疊且彼此互連之若干晶粒(501-1、501-2、501-3)。在一些實施例中，晶粒(501-1、501-2、501-3)向上堆疊，使得TSV(503-1、503-2、503-3)與彼此垂直地對準。在一些實施例中，晶粒(501-1、501-2、501-3)中的每一者為用於資料儲存應用之動態隨 機存取記憶體(DRAM)晶粒。如圖33中所示，三個DRAM晶粒堆疊在彼此上以成為堆疊式記憶體晶片。
在一些實施例中，金屬結構(502-1、502-2、502-3)中的每一者係藉由電鍍操作而由Ag1-xYx合金製成。在一些實施例中，Ag1-xYx合金之Y包括鈀(Pd)及金(Au)中之至少一者，且X自約0.005至約0.25。
在一些實施例中，晶粒501-1之TSV 503-1與晶粒501-2之TSV 503-2對準，且晶粒501-1之第二表面501B-1上的第二襯墊502B與晶粒501-2之第一表面501A-2上的第一襯墊502A-2結合。由此，晶粒501-1與晶粒501-2經由TSV 503-1及TSV 503-2自第一表面501A-1上之第一襯墊502A-1電連接至第二表面501B-2上之第二襯墊502B-2。類似地，晶粒501-2之TSV 503-2與晶粒501-3之TSV 503-3對準，且晶粒501-2之第二表面501B-2上的第二襯墊502B-2與晶粒501-3之第一表面501A-3上的第一襯墊502A-3結合。由此，晶粒501-2與晶粒501-3經由TSV 503-2及TSV 503-3自第一表面501A-2上之第一襯墊502A-2電連接至第二表面501B-3上之第二襯墊502B-3，且最終晶粒(501-1、501-2、501-3)經由TSV(503-1、503-2、503-3)自第一表面501A-1上之第一襯墊502A-1電連接至第二表面501B-3上之第二襯墊502B-3。
圖34展示安裝在中介物或基板504上之圖33之堆疊的晶粒(501-1、501-2、501-3)。在一些實施例中，基板504由矽、陶瓷等製成，用於攜載電路且支撐諸如電晶體之組件。在一些實施例中，基板504包括用於容納晶粒501-3之第二襯墊502B-3或分別安置在第二襯墊502B-3上之導電凸塊的若干接合襯墊505。在一些實施例中，接合襯墊505包括預焊材料以促進後續結合操作。在一些實施例中，接合襯墊505分別安裝有導電凸塊，使得導電凸塊可與晶粒501-3上之第二襯墊502B-3結合。
在一些實施例中，接合襯墊505藉由諸如熔融結合、熱壓縮結 合、藉由ACF之黏附等任何適當結合操作而與第二襯墊502B-3電連接。在結合第二襯墊502B-3與結合襯墊505之後，晶粒(501-1、501-2、501-3)與基板504內的電路電連接。在一些實施例中，晶粒501-1之第一襯墊502A-1經由TSV(503-1、503-2、503-3)及接合襯墊505與安置在基板504之底部的導電凸塊506電連通。
在一些實施例中，基板504之導電凸塊506可進一步安裝在另一基板或裝置上以便進一步將晶粒(501-1、501-2、501-3)及基板504與另一基板或裝置連接以成為半導體封裝。
圖35至圖41展示如在圖32中具有藉由Ag1-xYx合金填充的TSV之半導體結構的製造操作。在圖35中，提供晶粒501及具有預定圖案的遮罩層507。在一些實施例中，遮罩層507由光阻劑製成，且按預定圖案安置在晶粒501之第一表面501A上。在一些實施例中，遮罩層507之預定圖案係藉由微影操作而形成，使得晶粒501之第一表面501A的一部分由遮罩層507覆蓋。
在圖36中，形成高縱橫比之若干通孔503。在一些實施例中，通孔503係藉由蝕刻操作或藉由雷射鑽孔操作而形成。移除晶粒501不由遮罩層507覆蓋之一些部分以形成通孔503。在一些實施例中，通孔503係藉由深反應性離子蝕刻(DRIE)而形成。在圖37中，藉由剝除操作移除遮罩層507，且晶種層508安置在晶粒501之第一表面501A、通孔503之側壁503A及通孔503之底表面503B上。在一些實施例中，晶種層508係藉由諸如化學氣相沈積(CVD)、濺鍍、電鍍等適當操作而製備。在一些實施例中，晶種層508包括銀或銀合金。
在圖38中，銀合金502安置在晶種層508上且填充通孔503。在一些實施例中，銀合金502包括Ag1-xYx合金，其中物質Y為金、鈀，或其組合。舉例而言，Ag1-xYx合金可為諸如Ag1-xAux或Ag1-xPdx之二元金屬合金，此外，Ag1-xYx合金可為諸如Ag1-x(AuPd)x之三元金屬合 金。在一些實施例中，物質Y在Ag1-xYx合金中之含量介於約0.005至約0.25原子%之間。
在一些實施例中，晶粒501浸沒在含有基於氰化物的鍍敷溶液之電鍍浴中，該鍍敷溶液包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4及其鹽中之至少一者。晶粒501連接至陰極，使得銀離子、金離子及鈀離子自鍍敷溶液被還原，且沈積至晶種層508上，且因此包括AgAu二元合金(Ag1-xAux)、AgPd(Ag1-xPdx)二元合金或AgAuPd三元合金(Ag1-x(AuPd)x)之銀合金502形成在晶種層508上且填充通孔503。用銀合金502鍍敷通孔503。在一些實施例中，直流電(DC)施加至連接至陰極之晶粒501用於還原晶粒501之晶種層105上的銀離子、金離子或鈀離子。該直流電具有範圍介於約0.1ASD至約1.0ASD之電鍍電流密度。
在圖39中，晶粒501藉由諸如電平坦化、化學機械拋光(CMP)或其類似者之薄化操作而自第一表面501A薄化。移除晶粒501之鄰近於第一表面501A之一些及銀合金502及晶種層508之自通孔508溢出之一些，使得第一表面501A成為晶粒501之新第一表面501A'，且該新第一表面501A'與晶種層508之暴露部分及銀合金502之暴露部分處於實質上相同層級。
在圖40中，晶粒501藉由諸如電平坦化、化學機械拋光(CMP)等之薄化操作而自與第一表面501A對置之第二表面501B薄化，使得銀合金502之底表面503B自晶粒501暴露。在一些實施例中，自第二表面501B移除晶粒501之一些，使得第二表面501B成為新第二表面501B'，且銀合金502之底表面503B與晶粒501之新第二表面501B'處於實質上相同層級。
在圖41中，藉由諸如電鍍之任何適當操作分別在銀合金502之末端處形成若干襯墊(502A、502B)。在一些實施例中，襯墊(502A、502B)由與銀合金502相同之材料製成。在一些實施例中，襯墊 (502A、502B)包含金或銀。襯墊502A經由鍍敷有銀合金502之通孔503與襯墊502B電連接。在一些實施例中，襯墊(502A、502B)分別經組態用於容納安置在外部晶粒或基板上的導電凸塊或結合襯墊，使得晶粒501可藉由使襯墊502A或襯墊502B與安置在外部晶粒或基板上的導電凸塊或結合襯墊結合而與外部晶粒或基板電連接。
在本發明之一些實施例中，本文中論述之包括Ag1-xYx合金之圖5之銀合金柱結構40亦可用於將晶粒安裝在諸如引線框、基板或PCB之外部裝置上以成為諸如四邊扁平封裝(QFP)、四邊扁平無引線(QFN)封裝、球狀柵格陣列(BGA)封裝、晶片級封裝(CSP)、層疊封裝(PoP)、多晶片模組(MCM)等之半導體封裝。
圖42展示包括若干銀合金柱115之晶粒601之俯視圖，該等銀合金柱115與若干接點602連接以成為如圖42及圖43中所示的半導體封裝600。在一些實施例中，晶粒601為覆晶晶粒，其具有安置有銀合金柱115之有效側。晶粒601之有效側面向下。在一些實施例中，接點602為扁平無引線。安置在晶粒601上方之銀合金柱115與扁平無引線602結合以成為覆晶雙邊扁平無引線(FCDFN)封裝。
圖43展示沿圖42之BB'的作為FCDFN封裝之半導體結構600之橫截面圖。在一些實施例中，銀合金柱115與扁平無引線602結合。在一些實施例中，銀合金柱115包括經電鍍Ag1-xYx合金，其中Y包括鈀(Pd)及金(Au)中之至少一者，且X自約0.005至約0.25。在一些實施例中，Ag1-xYx合金為諸如Ag1-xAux或Ag1-xPdx之二元金屬合金。在一些實施例中，Ag1-xYx合金為諸如Ag1-x(AuPd)x之三元金屬合金。在一些實施例中，物質Y在Ag1-xYx合金中之含量介於約0.005至約0.25原子%之間。
在一些實施例中，銀合金柱115係藉由電鍍操作而形成，如圖17中所示。具有晶種層105及UBM層104之晶粒601與陰極連接。晶粒 601接著浸沒在含有基於氰化物的鍍敷溶液之電鍍浴中，該鍍敷溶液包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4及其鹽中之至少一者，使得銀離子自鍍敷溶液被還原，且安置在晶種層105上以形成包括AgAu二元合金(Ag1-xAux)、AgPd(Ag1-xPdx)二元合金或AgAuPd三元合金(Ag1-x(AuPd)x)之銀合金柱115。
在一些實施例中，銀合金柱115安置在含有銀或銀合金之晶種層105上。在一些實施例中，晶種層105係藉由諸如濺鍍之任何適當操作而安置在UBM層104上。在一些實施例中，UBM層104安置在晶粒601之有效側上。在一些實施例中，UBM層104為單層結構或包括由不同材料形成的若干子層之複合結構。UBM層104包括選自以下各者之一(或多)層：鎳(Ni)層、鈦(Ti)層、鈦鎢(W)層、鈀(Pd)層、金(Au)層、銀(Ag)層，及其組合。
在一些實施例中，安置在晶粒601之有效側上方的銀合金柱115藉由在銀合金柱115與扁平無引線602之間施加焊料材料、無鉛焊料材料或ACF而與扁平無引線602結合且電連接。在一些實施例中，覆蓋部件114安置在銀合金柱115之頂表面115A上。在一些實施例中，覆蓋部件114經組態用於使銀合金柱115與扁平無引線602之頂表面602A結合。在一些實施例中，覆蓋部件114包括諸如錫或銀之焊料材料。
在一些實施例中，銀合金柱115藉由諸如熔融結合、熱壓縮結合等任何適當操作而與扁平無引線602結合，使得銀合金柱115之頂表面115A與扁平無引線602之頂表面602A介接。晶粒601經由銀合金柱115與扁平無引線602電連接。
在一些實施例中，扁平無引線602具有暴露之底表面602B，其經暴露而用於容納另一結合襯墊或外部裝置之導電凸塊。在一些實施例中，模製化合物603覆蓋晶粒601及扁平無引線602以成為FCDFN封裝600。在一些實施例中，暴露之底表面602B自模製化合物603暴露。 在一些實施例中，模製化合物603亦填充晶粒601、銀合金柱115與扁平無引線602之間的間隙。在一些實施例中，模製化合物603包括環氧樹脂、聚醯亞胺、聚苯并噁唑(PBO)等。
在本發明之一些實施例中，本文中論述之包括Ag1-xYx合金之圖5之銀合金柱結構40亦可用於將晶粒701安裝在基板702上以成為如圖44中所示的BGA封裝。在圖44中，晶粒701為經翻轉且安裝在基板702上以成為覆晶球狀柵格陣列(FCBGA)封裝700之覆晶晶粒。在一些實施例中，銀合金柱115藉由回焊操作而與基板702之第一表面702A上的凸塊襯墊703結合。
在一些實施例中，基板702包括在與第一表面702A對置之第二表面702B上的若干導電凸塊704。導電凸塊704安置在基板702之球式襯墊705上。在一些實施例中，導電凸塊704為呈球面形狀的包括焊料材料的焊球。導電凸塊704經組態以安裝在另一基板或PCB上的結合襯墊上，使得晶粒701經由銀合金柱115及導電凸塊704與另一基板或PCB電連接。
在一些實施例中，一種半導體結構包括裝置、在該裝置上方之導電襯墊及安置在該導電襯墊上之Ag1-xYx合金柱，其中Ag1-xYx合金之Y包含按任意重量百分比與Ag形成完全固溶體之金屬，且其中Ag1-xYx合金之X在約0.005至約0.25之範圍內。
在一些實施例中，Y包含Au及鈀中之至少一者。在一些實施例中，Ag1-xYx合金柱具有約30μm至約100μm之高度。在一些實施例中，該半導體結構進一步包括覆蓋部件，該覆蓋部件安置在該Ag1-xYx合金柱上且包括用於與另一半導體結構電連接的焊料材料。在一些實施例中，該覆蓋部件具有自約1μm至約5pm之高度。在一些實施例中，該覆蓋部件具有與Ag1-xYx合金柱之直徑實質上相同的直徑。在一些實施例中，該導電襯墊包括晶種層，該晶種層包括與該Ag1-xYx合金 柱介接之Ag或Ag合金。
在一些實施例中，一種半導體結構包括一裝置、該裝置上之導電襯墊、安置在該裝置上方且覆蓋該導電襯墊的一部分之鈍化層，及包括安置在該鈍化層上方之Ag1-xYx合金的再分佈層(RDL)，其中Ag1-xYx合金之Y包含按任意重量百分比與Ag形成完全固溶體之金屬，且其中Ag1-xYx合金之X在約0.005至約0.25之範圍內。
在一些實施例中，Y包含Au及Pd中之至少一者。在一些實施例中，RDL由包含金之金屬層覆蓋。在一些實施例中，該RDL包括用於容納導電線或導電凸塊之焊盤部分。在一些實施例中，該RDL包括穿過該鈍化層且與該導電襯墊電連接之通孔部分。
在一些實施例中，一種半導體結構包括：晶粒，其包括第一表面及與該第一表面對置之第二表面；及通孔，其自該第一表面至該第二表面穿過該晶粒，Ag1-xYx合金填充該通孔，且其中Ag1-xYx合金之Y包含按任意重量百分比與Ag形成完全固溶體之金屬，且其中Ag1-xYx合金之X在約0.005至約0.25之範圍內。
在一些實施例中，Y包含Au及Pd中之至少一者。在一些實施例中，通孔為穿矽通孔(TSV)，且具有自約3至約20之縱橫比。在一些實施例中，該通孔具有自約5μm至約500μm之高度。在一些實施例中，該半導體結構進一步包括導電襯墊，其在該通孔之末端安置在該第一表面或該第二表面上。在一些實施例中，該導電襯墊經組態用於容納導電凸塊、導電柱或另一導電襯墊且用於與另一半導體結構結合。在一些實施例中，該導電襯墊包括銀或金。在一些實施例中，該半導體結構進一步包括安置在Ag1-xYx合金與通孔之側壁之間的晶種層。
在一些實施例中，一晶粒包括面向下的有效側，Ag1-xYx合金柱安置在該晶粒之有效側上方，且一接點經組態用於與Ag1-xYx合金柱結合且電連接，其中Ag1-xYx合金之Y包含按任意重量百分比與Ag形成 完全固溶體之金屬，且其中Ag1-xYx合金之X在約0.005至約0.25之範圍內。
在一些實施例中，Y包含Au及Pd中之至少一者。在一些實施例中，該接點為扁平無引線，其包括用於容納Ag1-xYx合金柱之頂表面及用於安裝在另一半導體結構上之暴露之底表面。在一些實施例中，該扁平無引線與Ag1-xYx合金柱結合以成為覆晶雙邊扁平無引線(FCDFN)封裝。在一些實施例中，該半導體結構進一步包括一基板，該基板包括用於安置該接點之第一表面及與該第一表面對置用於安置配置成球狀柵格陣列(BGA)之複數個導電凸塊的第二表面。在一些實施例中，Ag1-xYx合金柱與安置在該基板上之該接點結合且電連接以成為覆晶球狀柵格陣列封裝(FCBGA)。
在一些實施例中，一種用於製造一半導體結構之方法包括：製備基於氰化物之鍍敷溶液，其包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4中之至少一者；將該半導體結構浸沒於該鍍敷溶液中；將約0.1ASD至約1.0ASD之電鍍電流密度施加至該半導體結構以自該鍍敷溶液還原銀離子、金離子或鈀離子；及在該半導體結構上形成Ag1-xYx合金結構，其中Ag1-xYx合金之Y包含按任意重量百分比與Ag形成完全固溶體之金屬，且其中Ag1-xYx合金之X在約0.005至約0.25之範圍內。
在一些實施例中，在該半導體結構上形成該Ag1-xYx合金結構包含在安置在該半導體結構之裝置上的導電襯墊上電鍍Ag1-xYx合金柱。在一些實施例中，在該半導體結構上形成the Ag1-xYx合金結構包含在安置在該半導體結構之裝置上方的鈍化層上電鍍Ag1-xYx合金RDL。在一些實施例中，該方法進一步包括藉由電鍍操作或無電極鍍敷操作在該Ag1-xYx合金RDL上形成金屬層。在一些實施例中，形成Ag1-xYx合金結構包括：形成自晶粒之第一表面朝向該晶粒之與該第一表面對置的第二表面延伸的穿矽通孔(TSV)；及用該Ag1-xYx合金填 充該TSV。在一些實施例中，形成該TSV包括按預定圖案在該晶粒之第一表面上安置一遮罩層；及藉由蝕刻操作自該第一表面移除該晶粒之一部分。在一些實施例中，形成該TSV包括雷射鑽孔操作。在一些實施例中，形成該Ag1-xYx合金結構包括自該第二表面研磨該晶粒以暴露該Ag1-xYx合金。
此外，本申請案之範疇不意欲限於說明書中描述之製程、機器、製造，及物質組成、構件、方法及步驟之特定實施例。如熟習此項技術者將易於自本發明之揭示內容而瞭解，可根據本發明利用執行與本文中所描述的對應實施例執行實質上相同的功能或達成與該等對應實施例實質上相同的結果的當前現有或稍後待開發的程序、機器、製造、物質組成、構件、方法或步驟。
因此，所附申請專利範圍意欲在其範疇中包括程序、機器、製造，及物質組成、構件、方法或步驟。此外，每一請求項構成一單獨實施例，且各種請求項及實施例之組合在本發明之範疇內。
40‧‧‧銀柱結構
100‧‧‧裝置
102‧‧‧導電襯墊
103‧‧‧鈍化層
114‧‧‧覆蓋部件
115‧‧‧Ag1-xYx合金柱
115A‧‧‧頂表面

Claims (30)

  1. 一種半導體結構，其包含：一裝置；在該裝置上方之一導電襯墊；及安置在該導電襯墊上之一Ag1-xYx合金柱，其中該Ag1-xYx合金之Y包含以任意重量百分比與Ag形成完全固溶體之金屬，且其中該Ag1-xYx合金之X在約0.005至約0.25之範圍內。
  2. 如請求項1之半導體結構，其中該Y包含Au及Pd中之至少一者。
  3. 如請求項1之半導體結構，其中該Ag1-xYx合金柱具有自約30μm至約100μm之一高度。
  4. 如請求項1之半導體結構，其進一步包含一覆蓋部件，該覆蓋部件安置在該Ag1-xYx合金柱上且包括用於與另一半導體結構電連接的一焊料材料。
  5. 如請求項4之半導體結構，其中該覆蓋部件具有自約1μm至約5μm之一高度。
  6. 如請求項1之半導體結構，其中該導電襯墊包括一晶種層，該晶種層包括與該Ag1-xYx合金柱介接之Ag或Ag合金。
  7. 如請求項1之半導體結構，其進一步包含一接點，該接點包括用於容納該Ag1-xYx合金柱之一頂表面及用於安裝在另一半導體結構上之一暴露之底表面。
  8. 如請求項7之半導體結構，其中該接點為一扁平無引線，其與該Ag1-xYx合金柱結合以成為一覆晶雙邊扁平無引線(FCDFN)封裝。
  9. 如請求項1之半導體結構，其進一步包含一基板，該基板包括用 於安置一接點之一第一表面及與該第一表面對置用於安置配置成一球狀柵格陣列(BGA)之複數個導電凸塊的一第二表面，且該基板之該接點與該Ag1-xYx合金柱結合以成為一覆晶球狀柵格陣列封裝(FCBGA)。
  10. 一種半導體結構，其包含：一裝置；在該裝置上之一導電襯墊；一鈍化層，其安置在該裝置上方且覆蓋該導電襯墊的一部分；及一再分佈層(RDL)，其包括安置在該鈍化層上方之Ag1-xYx合金，其中該Ag1-xYx合金之Y包含以任意重量百分比與Ag形成完全固溶體之金屬，且其中該Ag1-xYx合金之X在約0.005至約0.25之範圍內。
  11. 如請求項10之半導體結構，其中該Y包含Au及Pd中之至少一者。
  12. 如請求項10之半導體結構，其中該RDL由包含金之一金屬層覆蓋。
  13. 如請求項10之半導體結構，其中該RDL包括用於接收一導電線或一導電凸塊之一焊盤部分。
  14. 如請求項10之半導體結構，其中該RDL包括穿過該鈍化層且與該導電襯墊電連接之一通孔部分。
  15. 一種半導體結構，其包含：一晶粒，其包括一第一表面及與該第一表面對置之一第二表面；及一通孔，其自該第一表面至該第二表面穿過該晶粒，填充該通孔之一Ag1-xYx合金，且 其中該Ag1-xYx合金之Y包含以任意重量百分比與Ag形成完全固溶體之金屬，且其中該Ag1-xYx合金之X在約0.005至約0.25之範圍內。
  16. 如請求項15之半導體結構，其中該Y包含Au及Pd中之至少一者。
  17. 如請求項15之半導體結構，其中該通孔為一穿矽通孔(TSV)，且具有自約3至約20之一縱橫比。
  18. 如請求項15之半導體結構，其中該通孔具有自約5μm至約500μm之一高度。
  19. 如請求項15之半導體結構，其進一步包含一導電襯墊，該導電襯墊在該通孔之一端安置在該第一表面或該第二表面上。
  20. 如請求項19之半導體結構，其中該導電襯墊經組態用於接收一導電凸塊、一導電柱或另一導電襯墊且用於與另一半導體結構結合。
  21. 如請求項19之半導體結構，其中該導電襯墊包括銀或金。
  22. 如請求項15之半導體結構，其進一步包含一晶種層，該晶種層安置在該Ag1-xYx合金與該通孔之一側壁之間。
  23. 一種用於製造一半導體結構之方法，其包含：製備一基於氰化物之鍍敷溶液，其包括KAg(CN)2、KAu(CN)2、K2Pd(CN)4中之至少一者；將該半導體結構浸沒至該鍍敷溶液中；將約0.1ASD至約1.0ASD之一電鍍電流密度施加至該半導體結構以自該鍍敷溶液還原銀離子、金離子或鈀離子；及在該半導體結構上形成一Ag1-xYx合金結構，其中該Ag1-xYx合金之Y包含按任意重量百分比與Ag形成完全固溶體之金屬，且其中該Ag1-xYx合金之X在約0.005至約0.25之範圍內。
  24. 如請求項23之方法，其中該在該半導體結構上形成該Ag1-xYx合金結構包含在安置在該半導體結構之一裝置上的一導電襯墊上電鍍一Ag1-xYx合金柱。
  25. 如請求項23之方法，其中該在該半導體結構上形成該Ag1-xYx合金結構包含在安置在該半導體結構之一裝置上方的一鈍化層上電鍍一Ag1-xYx合金RDL。
  26. 如請求項23之方法，其進一步包含藉由電鍍操作或無電極鍍敷操作而在該Ag1-xYx合金RDL上形成一金屬層。
  27. 如請求項23之方法，其中該形成該Ag1-xYx合金結構包括：形成自一晶粒之一第一表面朝向該晶粒之與該第一表面對置的一第二表面延伸的一穿矽通孔(TSV)；及用該Ag1-xYx合金填充該TSV。
  28. 如請求項23之方法，其中該形成該TSV包括：按一預定圖案在該晶粒之該第一表面上安置一遮罩層；及藉由一蝕刻操作自該第一表面移除該晶粒之一部分。
  29. 如請求項23之方法，其中該形成該TSV包括一雷射鑽孔操作。
  30. 如請求項23之方法，其中該形成該Ag1-xYx合金結構包括自該第二表面研磨該晶粒以暴露該Ag1-xYx合金。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI815549B (zh) * 2021-08-18 2023-09-11 美商美光科技公司 包括整合區段之設備及製造其之方法

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9305131B2 (en) * 2013-12-03 2016-04-05 Mediatek Inc. Method for flip chip packaging co-design
JP6188025B2 (ja) * 2014-05-16 2017-08-30 国立研究開発法人物質・材料研究機構 銀拡散障壁材料、銀拡散障壁、銀拡散障壁被覆
US9564409B2 (en) 2015-01-27 2017-02-07 Semiconductor Components Industries, Llc Methods of forming semiconductor packages with an intermetallic layer comprising tin and at least one of silver, copper or nickel
US20160308100A1 (en) * 2015-04-17 2016-10-20 Chipmos Technologies Inc Semiconductor package and method of manufacturing thereof
US9754906B2 (en) * 2015-06-25 2017-09-05 Advanced Semiconductor Engineering, Inc. Double plated conductive pillar package substrate
KR101717423B1 (ko) * 2015-10-01 2017-03-17 에이치엔티 일렉트로닉스(주) 카메라 모듈 패키지 및 카메라 모듈 패키지 제조방법
US10115692B2 (en) * 2016-09-14 2018-10-30 International Business Machines Corporation Method of forming solder bumps
US10658318B2 (en) * 2016-11-29 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Film scheme for bumping
WO2019066977A1 (en) 2017-09-29 2019-04-04 Intel Corporation FIRST-LEVEL THIN-LEVEL INTERCONNECTIONS DEFINED BY AUTOCATALYTIC METAL FOR LITHOGRAPHIC INTERCONNECTION HOLES
KR102099750B1 (ko) * 2017-11-01 2020-04-10 삼성전자주식회사 반도체 패키지
TWI697078B (zh) * 2018-08-03 2020-06-21 欣興電子股份有限公司 封裝基板結構與其接合方法
KR20200025159A (ko) * 2018-08-29 2020-03-10 삼성전자주식회사 범프 구조체를 갖는 반도체 소자 및 이를 포함하는 반도체 패키지
KR20210068891A (ko) 2019-12-02 2021-06-10 삼성전자주식회사 인터포저, 및 이를 가지는 반도체 패키지
JP7484663B2 (ja) * 2020-10-29 2024-05-16 株式会社デンソー 接合構造体、電子装置、接合構造体の製造方法
US11456267B2 (en) 2020-12-16 2022-09-27 Texas Instruments Incorporated Fet construction with copper pillars or bump directly over the fet

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4121982A (en) * 1978-02-03 1978-10-24 American Chemical & Refining Company Incorporated Gold alloy plating bath and method
US4922322A (en) * 1989-02-09 1990-05-01 National Semiconductor Corporation Bump structure for reflow bonding of IC devices
JPH06184789A (ja) * 1992-12-22 1994-07-05 Asahi Glass Co Ltd 耐酸化性金属部材、メッキ液、及び回路装置
JP3329696B2 (ja) * 1997-07-08 2002-09-30 株式会社東芝 半導体装置の製造方法
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US20040007779A1 (en) * 2002-07-15 2004-01-15 Diane Arbuthnot Wafer-level method for fine-pitch, high aspect ratio chip interconnect
JP2004353004A (ja) * 2003-05-27 2004-12-16 Ebara Corp めっき装置
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
JP2007142271A (ja) * 2005-11-21 2007-06-07 Tanaka Electronics Ind Co Ltd バンプ材料および接合構造
WO2007062165A2 (en) * 2005-11-23 2007-05-31 Williams Advanced Materials, Inc. Alloys for flip chip interconnects and bumps
KR100744149B1 (ko) * 2006-08-30 2007-08-01 삼성전자주식회사 은 범프를 이용한 반도체 패키지 구조 및 형성 방법
JP2010147051A (ja) * 2008-12-16 2010-07-01 Renesas Technology Corp 半導体集積回路装置および半導体集積回路装置の製造方法
JP4995883B2 (ja) * 2009-10-19 2012-08-08 力成科技股▲分▼有限公司 半導体フリップチップ構造体
JP2010084235A (ja) * 2010-01-18 2010-04-15 Ebara Corp めっき装置
US10096540B2 (en) * 2011-05-13 2018-10-09 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance
JP2013098514A (ja) * 2011-11-07 2013-05-20 Seiko Epson Corp 半導体装置の製造方法及び半導体装置、電子機器
JP5165810B1 (ja) * 2012-09-12 2013-03-21 田中電子工業株式会社 銀金パラジウム系合金バンプワイヤ
TWI395313B (zh) * 2012-11-07 2013-05-01 Wire technology co ltd 銲球凸塊結構及其形成方法
US8779604B1 (en) * 2013-11-06 2014-07-15 Chipmos Technologies Inc. Semiconductor structure and manufacturing method thereof
US8877630B1 (en) * 2013-11-12 2014-11-04 Chipmos Technologies Inc. Semiconductor structure having a silver alloy bump body and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI815549B (zh) * 2021-08-18 2023-09-11 美商美光科技公司 包括整合區段之設備及製造其之方法
US11894327B2 (en) 2021-08-18 2024-02-06 Micron Technology, Inc. Apparatus including integrated segments and methods of manufacturing the same

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KR20150069492A (ko) 2015-06-23
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US20150171039A1 (en) 2015-06-18
TWI532131B (zh) 2016-05-01
JP2015115596A (ja) 2015-06-22

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