TW201133662A - Copper-Manganese compound structure for electronic packaging application - Google Patents

Copper-Manganese compound structure for electronic packaging application Download PDF

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Publication number
TW201133662A
TW201133662A TW099109755A TW99109755A TW201133662A TW 201133662 A TW201133662 A TW 201133662A TW 099109755 A TW099109755 A TW 099109755A TW 99109755 A TW99109755 A TW 99109755A TW 201133662 A TW201133662 A TW 201133662A
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TW
Taiwan
Prior art keywords
copper
manganese
solder
conductive portion
electronic
Prior art date
Application number
TW099109755A
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Chinese (zh)
Inventor
zheng-gong Du
Jian-Fu Ceng
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Nat Univ Tsing Hua
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Application filed by Nat Univ Tsing Hua filed Critical Nat Univ Tsing Hua
Priority to TW099109755A priority Critical patent/TW201133662A/en
Publication of TW201133662A publication Critical patent/TW201133662A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)

Abstract

Disclosed is a copper-manganese compound structure for electronic packaging application, which is mainly applied to the under bump metallurgy (UBM) at the solder joint in the packaging technique. The compound structure comprises an electronic component, at least a solder material and at least a manganese binding material. At least a copper conducting part is disposed on the electronic component; the solder material corresponds to the copper conducting part; the manganese binding material is disposed between the copper conducting part and the solder material; and the solder material adheres to the copper conducting part through the manganese binding material. Through using the manganese binding material, the present invention can reduce the formation of quasi metal compound Cu3Sn which is hard and brittle and easily to be produced previously, restrain the production of holes, prevent the copper conducting part from being consumed due to the production of the quasi metal compound, and therefore can protect and improve the whole structure.

Description

201133662 六、發明說明： ' 【發明所屬之技術領域】 [0001] 本發明係有關一種電子封裝技術，尤指一種應用於電 子封裝之銅锰結合結構。 【先前技術】 於今’半導體業界不斷的在製程技術上有所突破，使 得摩爾定律持續適用，亦使得封裝技術受到極大的挑戰 ’製程技術再好’仍必須配合封裝技術才能應用於電路 板上’若封装技術沒有辦法跟進，製程技術之突破便顯 付毫無用武之地。於是，覆晶技術（Flip Chip，F/c) 的發展’著實連接上製程技術的進·步，覆晶技術著眼於 需要使用1¾腳數（I/G)特性、散齡較佳及較為輕薄短小 的封裝技術’除此之外’覆晶技術有助於提升電子訊號 的傳遞速度，因此逐漸形成高密度封裝主流。 [〇〇〇3] 胃參閱「圖^所示，其係為習知覆晶技術之結構示 意圖，一晶片1配董有複數個銲墊2，而一基板3上設置有 複數個接點4，並以複數個錫基銲球5設置於該銲墊2與該 接點4，對該晶片1與該基板3間形成連結，而該銲墊2與 接點4的材料為銅，且由該晶片}依序銲墊2、錫基銲球5 及接點4產生電性連結到該基板3，另外，為避免濕氣與 機械應力的破壞，所以一膠體6填補於該晶片丨與該基板3 之間的空隙，包覆該銲墊2、錫基銲球5及接點4。 請在參閱圖2-1及圖2-2，其係為上述習知技術的界面 反應熱處理前及熱處理後的電子顯微鏡圖，在將該銲墊2 與該錫基銲球5連接後，該銲墊2與該錫基銲球5之間會產 099109755 表單編號A010〗 第3頁/共15頁 0992017252-0 201133662 生一第一介金屬層7,以本實施例說明，該銲墊2通常為 銅所製成，該第一介金屬層7為CuRSnR，在封裝完成後， 其照片如圖2-1所示，因為該晶片1使用產生之熱能影響 在經過長時間使用之後，會促使該銲墊2上之銅會與該錫 基銲球5之錫結合生長，如圖2-2所示，在經過熱處理後 ，該銲塾2進而生成一第二介金屬層8，該第二介金屬層8 之材質為CuqSn，並造成該第二介金屬層8内之孔洞 9(voids)的生成。更進一步的說明，該孔洞9的生成， 與銅原子和錫原子在該第二介金屬層8中的擴散速度有很 大的關係，由於銅原子的擴散速度大於錫原子，因此會 在銅與該第二介金屬層8的接觸面造成金屬原子來不及回 補，因而有原子空缺累積過多生成該孔洞9，該孔洞9的 生成，會造成該銲墊2與該接點4對該錫基銲球5的連結性 降低，大大的降低該晶片1與該基板3之間可承受的剪力 及應力，因而造成銲點的可靠度下降，增加該晶片1因為 震動或摔落時造成連接不良的可能。 【發明内容】 [0005] [0006] 本發明之主要目的，在於解決習知技術中因為熱能影 響，造成孔洞生成，進而降低銲點可靠度的問題。 為達上述目的，本發明提供一種應用於電子封裝之銅 錳結合結構，其係主要應用於封裝技術中的銲料接合處 之金屬墊層，該結合結構包括有一電子元件、至少一銲 錫材料及至少一錳結合材，該電子元件上設置有至少一 銅導電部；該銲錫材料係對應該銅導電部；而該錳結合 材係設置在該銅導電部與該銲錫材料之間；該銲錫材料 099109755 表單編號A0101 第4頁/共15頁 0992017252-0 201133662 係藉由该錳結合材與該銅導電部黏結。 [0007] 由上述說明可知’與習知技術相比，藉由該錳結合材 之設置’可以減少原本容易生成硬脆的介金屬化合物 C U S 、 3 n並抑制孔洞的產生《另一方面，由於本發明能使 • 5導電不會因.為介金屬化合物的生成而被消耗，所 以月b夠保護且改善該電子元件、該銅導電部、該錳結合 材與該辉錫材料的機械強度與電性傳導的完整性。 【實施方式】 Ο [0008] 有關本發明之詳細說明及技街内容，現就配合圖式說 明如下： [0009]201133662 VI. Description of the invention: 'Technical field to which the invention pertains. [0001] The present invention relates to an electronic packaging technology, and more particularly to a copper-manganese bonding structure applied to an electronic package. [Prior Art] Yujin's semiconductor industry has made breakthroughs in process technology, making Moore's Law continue to be applied, and packaging technology is also greatly challenged. 'Processing technology is good' still has to be combined with packaging technology to be applied to the board.' If there is no way to follow up the packaging technology, the breakthrough in process technology will be useless. Therefore, the development of flip chip technology (Flip Chip, F/c) is a step in the process of connecting the process technology. The flip chip technology focuses on the need to use the 13⁄4 pin number (I/G) characteristics, better age and lighter weight. The short package technology 'except this' flip-chip technology helps to increase the speed of electronic signal transmission, so it gradually forms the mainstream of high-density packaging. [〇〇〇3] The stomach is shown in Fig. 2, which is a schematic diagram of the conventional flip chip technology. A wafer 1 has a plurality of pads 2, and a substrate 3 is provided with a plurality of contacts 4 And a plurality of tin-based solder balls 5 are disposed on the solder pad 2 and the contact 4, and a connection is formed between the wafer 1 and the substrate 3. The material of the solder pad 2 and the contact 4 is copper, and The wafers are sequentially electrically connected to the substrate 3, and the solder balls 6 and the contacts 4 are electrically connected to the substrate 3. Further, in order to avoid damage of moisture and mechanical stress, a colloid 6 is filled in the wafer and the wafer The gap between the substrates 3 covers the bonding pad 2, the tin-based solder balls 5, and the contacts 4. Referring to Figures 2-1 and 2-2, the interface reaction heat treatment of the above-mentioned prior art is After the heat treatment, after the solder pad 2 is connected to the tin-based solder ball 5, the solder pad 2 and the tin-based solder ball 5 will produce 099109755. Form No. A010〗 Page 3 of 15 0992017252-0 201133662 A first metal layer 7 is formed. According to the embodiment, the solder pad 2 is usually made of copper, and the first dielectric layer 7 is CuRSnR. After the package is completed, The photo is shown in Figure 2-1. Because the thermal energy generated by the wafer 1 is used after a long period of use, the copper on the pad 2 will be combined with the tin of the tin-based solder ball 5, as shown in the figure. 2-2, after the heat treatment, the solder bump 2 further generates a second metal layer 8, the material of which is CuqSn, and causes the hole 9 in the second metal layer 8. The formation of (voids). Further, the formation of the pores 9 has a great relationship with the diffusion rate of copper atoms and tin atoms in the second intermetallic layer 8, since the diffusion rate of copper atoms is greater than that of tin atoms. Therefore, the metal atoms are not able to be replenished at the contact surface of the copper and the second intermetallic layer 8. Therefore, an atomic vacancy accumulates excessively to form the hole 9, and the formation of the hole 9 causes the pad 2 and the contact. 4 The connection of the tin-based solder ball 5 is reduced, the shear force and stress that can be withstood between the wafer 1 and the substrate 3 are greatly reduced, thereby causing the reliability of the solder joint to decrease, and the wafer 1 is increased due to vibration or falling. Poor connection caused by falling time. [0006] The main object of the present invention is to solve the problem that the hole is generated and the reliability of the solder joint is reduced due to the influence of thermal energy in the prior art. To achieve the above object, the present invention provides a copper applied to an electronic package. a manganese bonding structure, which is mainly applied to a metal pad layer of a solder joint in a packaging technology, the bonding structure comprising an electronic component, at least one solder material and at least one manganese bonding material, wherein the electronic component is provided with at least one copper conductive The solder material is corresponding to the copper conductive portion; and the manganese bonding material is disposed between the copper conductive portion and the solder material; the solder material 099109755 Form No. A0101 Page 4 / Total 15 Page 0992017252-0 201133662 The manganese bonding material is bonded to the copper conductive portion. [0007] From the above description, it can be seen that "the arrangement of the manganese bonding material can reduce the formation of the hard and brittle intermetallic compound CUS, 3 n and suppress the generation of voids" compared with the prior art. The invention can prevent the conduction of the conductive material from being caused by the formation of the intermetallic compound, so that the monthly b is sufficient to protect and improve the mechanical strength of the electronic component, the copper conductive portion, the manganese bonding material and the tin-tin material. The integrity of electrical conduction. [Embodiment] 0008 [0008] A detailed description of the present invention and the contents of the technical street will now be described as follows: [0009]

GG

[0010] 099109755 凊參閱圖3所示，係本發明-較佳實施例之結構示意 圖，如圖所示：本發明係為一種應用於電子封裝之銅錳 ° α…構，包括有一電子元件10、至少一銲錫材料2〇及 至少—錳結合材30，該電子元件10上設置有至少一銅導 :部乂 ；該銲錫材料20係對應該鋼導電部"；而該錳結 。材3U係設置在_導電部η與該銲騎獅之間其 α材3〇係為一銅锰混合之合金，且該錳結合 〇:應用型態係選自於由膜狀、片狀、粉末、柱狀與 址人好如成之群組或其組合；該銲錫材料20储由該猛 …材3G與該鱗電部u黏結。 更進步說明的是，本發明係以覆晶封裝技術為一較 佳實施例’因此，該電子元件㈣指—晶片12及 …主^料晶化利用覆晶«方式與該基板13藉 由該銅¥電部u、贿結合材3G及該銲錫材料2〇電性連 接表二:合材3?製—作方式選自於電錢、無電錄、化 第5頁/共15頁 099201' 201133662 學反應合成、濺鍍、碾壓、融合與粉末合成所組成之群 組；而該銅導電部11係選自於由銅與黃銅所組成之群組 *在本貫施例中’該銅導電部11係為銅導電線，該鲜錫 材料20係為一錫基銲球。藉由圖3之說明，由上層至底層 之材料分別為該晶片12、該銅導電部11、該錳結合材30 、該銲錫材料20、該錳結合材30、該銅導電部11及該基 板13，藉此將該晶片12上之輸入及輸出端口與該基板13 連接。此外，該銅導電部11與該錳結合材30可同為銅錳 合金之材質所構成，因此，該銅導電部11與該錳結合材 30在實際狀況應用時，不會有明顯分界。再者，為避免 濕氣與機械應力的破壞，所以一膠體14填補於該晶片12 與該基板13之間。 [0011] [0012] 請參閱圖4所示，其係本發明另一較佳實施例之結構 示意圖，如圖所示：其中該錳結合材30與該銲錫材料20 之間設置有一濕潤層40，該濕潤層40與該銲錫材料20之 潤濕程度較高，在迴焊（Reflow)時銲錫可完全滯留附立 其上而成球狀。 請再參閱圖5-1及圖5-2所示，其係為本發明一較佳實 施例之界面反應熱處理前及熱處理後的電子顯微鏡照片 ，兩圖之差別在於圖5-2係經過20天，以及150°C熱處 理過後，該電子元件10與該銲錫材料20之間所呈現的界 面反應，藉此模擬在經過高溫、長久使用後之實際狀況 。需先說明的是，該銅導電部11與該錳結合材30所使用 之材料皆為銅锰合金，因此在圖中並無明顯分界，在此 僅標示該錳結合材30做為代表。如圖5-1所示，該錳結合 099109755 表單編號A0101 第6頁/共15頁 0992017252-0 201133662 材30與該銲錫材料2〇形成一介金屬層5〇 (a Sn )，該 介金屬層50為針狀結構，而針狀結構有效^強5了與該 輝錫材料2G的機械性質，強化了與該銲錫材料2〇的連接 效果。而在反錢，如圖5_2所示，魅結合材3q有效的 抑制了-含猛相層6〇 (Cu3Sn+Mn)的生長，藉此有效抑 制了孔洞的生成，避免連接結構可靠度的降低。 [0013] Ο 〇 [0014] 綜上所述，由於本發明藉由該猛結合材3〇之設置，可 以減少原本容易生成硬脆的該含錳相層6〇之生成，並抑 制孔洞的產生。此外，該介金屬層5〇所形成之針狀結構 有效強化了與該銲錫材料2〇的連接效果。另_方面由 於本發明能使該銅導電部u不會因為介金屬化合物的生 成而被消耗，所以能夠保護且改善該電子元件1〇、該銅 導電部11、該錳結合材30與該銲錫材料2〇的機械強度與 電性傳導的完整性》因此本發明極具進步性及符合申請 發明專利之要件，爰依法提出申請，祈鈎局早日賜准專 利，實感德便。 以上已將本發明做一詳細說明，惟以上所述係應用於 覆晶技術，其僅爲本發明之一較佳實施例而已，本發明 亦可應用於表面黏著技術（Surface Mount Technology, SMT)、 打 線技術（Wire bonding)、 貼帶 自動接 合技術（tape automatic bonding, TAB)以及 3_d 多 層明片結合封裝技術等，因此當不能限定本發明實施之 範圍。即凡依本發明申請範圍所作之均等變化與修飾等 ’皆應仍屬本發明之專利涵蓋範圍内。 【圖式簡單說明】 099109755 表單編號A0101 第7頁/共15頁 0992017252-0 201133662 [0015] 圖1，係習知覆晶技術之結構示意圖。 [0016] 圖2-1，習知技術的界面反應熱處理前電子顯微鏡圖。 [0017] 圖2-2，習知技術的界面反應熱處理後電子顯微鏡圖。 [0018] 圖3，係本發明一較佳實施例之結構示意圖。 [0019] 圖4，係本發明另一較佳實施例之結構示意圖。 [0020] 圖5-1，係本發明一較佳實施例之界面反應熱處理前電子 顯微鏡圖。 [0021] 圖5-2，係本發明一較佳實施例之界面反應熱處理後電子 顯微鏡圖。 【主要元件符號說明】 [0022] 習知技術 [0023] 1 :晶片 [0024] 2 :銲墊 [0025] 3 :基板 [0026] 4 :接點 [0027] 5 :錫基銲球 [0028] 6 :膠體 [0029] 7 :第一介金屬層 [0030] 8 :第二介金屬層 [0031] 9 :孔洞 099109755 表單編號A0101 第8頁/共15頁 0992017252-0 201133662 [0032] [0033] [0034] [0035] [0036] [0037] [0038] Ο [0039] [0040] [0041] [0042] 本發明 10 :電子元件 11 :銅導電部 12 ·晶片 13 :基板 14 :膠體 20 :銲錫材料 3 0 :猛結合材 40 :濕潤層 50 :介金屬層 60 :含錳相層 099109755 表單編號 Α0101 第9頁/共15頁 0992017252-0[0010] 099109755 Referring to FIG. 3, it is a schematic structural view of a preferred embodiment of the present invention, as shown in the drawing: the present invention is a copper-manganese structure for electronic packaging, comprising an electronic component 10. At least one solder material 2 〇 and at least a manganese bonding material 30, the electronic component 10 is provided with at least one copper conductor: a portion; the solder material 20 corresponds to the steel conductive portion " and the manganese junction. The material 3U is disposed between the conductive portion η and the soldering lion, and the α material 3〇 is a copper-manganese mixed alloy, and the manganese bonded germanium: application form is selected from a film shape, a sheet shape, A group of powders, columns, and a group of people, or a combination thereof; the solder material 20 is deposited by the sturdy material 3G and the scale portion u. More advanced, the present invention is based on a flip chip packaging technology as a preferred embodiment. Thus, the electronic component (4) refers to the wafer 12 and the crystallization of the main material by means of flip chip « and the substrate 13 by the Copper ¥Electricity Department u, bribe bond material 3G and the solder material 2〇Electrical connection Table 2: Composite material 3? system - the method is selected from the electricity money, no electricity record, the fifth page / a total of 15 pages 099201' 201133662 a group consisting of reaction synthesis, sputtering, rolling, fusion, and powder synthesis; and the copper conductive portion 11 is selected from the group consisting of copper and brass * in the present embodiment, the copper The conductive portion 11 is a copper conductive wire, and the fresh tin material 20 is a tin-based solder ball. As illustrated in FIG. 3, the material from the upper layer to the bottom layer is the wafer 12, the copper conductive portion 11, the manganese bonding material 30, the solder material 20, the manganese bonding material 30, the copper conductive portion 11, and the substrate. 13. The input and output ports on the wafer 12 are connected to the substrate 13. Further, since the copper conductive portion 11 and the manganese bonding material 30 can be made of a material of a copper-manganese alloy, the copper conductive portion 11 and the manganese bonding material 30 do not have a significant boundary when applied in actual conditions. Further, in order to avoid damage of moisture and mechanical stress, a colloid 14 is filled between the wafer 12 and the substrate 13. [0012] Please refer to FIG. 4, which is a schematic structural view of another preferred embodiment of the present invention, as shown in FIG. 4, wherein a wet layer 40 is disposed between the manganese bonding material 30 and the solder material 20. The wet layer 40 has a high degree of wetting with the solder material 20, and the solder can be completely retained and adhered to a spherical shape during reflow. Please refer to FIG. 5-1 and FIG. 5-2, which are electron micrographs of the interface reaction heat treatment before and after the heat treatment according to a preferred embodiment of the present invention. The difference between the two figures is that FIG. 5-2 is after 20 After the heat treatment at 150 ° C, the interface between the electronic component 10 and the solder material 20 reacts, thereby simulating the actual condition after high temperature and long-term use. It should be noted that the materials used for the copper conductive portion 11 and the manganese bonding material 30 are both copper-manganese alloys, so there is no obvious boundary in the figure, and only the manganese bonding material 30 is shown as a representative. As shown in FIG. 5-1, the manganese alloy 099109755 Form No. A0101 Page 6 / 15 pages 0992017252-0 201133662 The material 30 and the solder material 2〇 form a dielectric layer 5〇(a Sn ), the metal layer 50 It is a needle-like structure, and the needle-like structure is effective and strong with the mechanical properties of the tin-tin material 2G, and the connection effect with the solder material 2〇 is enhanced. In the anti-money, as shown in Fig. 5_2, the charm bonding material 3q effectively suppresses the growth of the turbid phase layer 6〇(Cu3Sn+Mn), thereby effectively suppressing the formation of voids and avoiding the reduction of the reliability of the joint structure. . [0013] In summary, since the present invention can reduce the formation of the manganese-containing phase layer 6 容易 which is easy to generate hard and brittle, and suppress the generation of voids, by the arrangement of the splicing material 3 〇 . Further, the acicular structure formed by the intermetallic layer 5 有效 effectively enhances the connection effect with the solder material 2 。. According to the present invention, since the copper conductive portion u is not consumed by the formation of the intermetallic compound, the electronic component 1 , the copper conductive portion 11 , the manganese bonding material 30 and the solder can be protected and improved. The mechanical strength of the material 2〇 and the integrity of the electrical conduction” Therefore, the invention is highly progressive and conforms to the requirements of the invention patent application, and the application is filed according to law, and the office of the hook is granted an instant patent. The present invention has been described in detail above, but the above is applied to the flip chip technology, which is only a preferred embodiment of the present invention, and the present invention can also be applied to Surface Mount Technology (SMT). Wire bonding, tape automatic bonding (TAB), and 3_d multi-layer chip bonding technology, etc., and thus do not limit the scope of the present invention. That is, the equivalent changes and modifications made by the scope of the present application should remain within the scope of the patent of the present invention. [Simple description of the drawing] 099109755 Form No. A0101 Page 7 of 15 0992017252-0 201133662 [0015] FIG. 1 is a schematic structural view of a conventional flip chip technique. 2-1, an electron micrograph of a prior art interface reaction prior to heat treatment. 2-2, an electron micrograph of a conventional reaction of the interface reaction heat treatment. 3 is a schematic structural view of a preferred embodiment of the present invention. 4 is a schematic structural view of another preferred embodiment of the present invention. 5-1 is an electron microscope image of an interface reaction heat treatment according to a preferred embodiment of the present invention. 5-2 is an electron micrograph of an interface reaction heat treatment according to a preferred embodiment of the present invention. [Main Element Symbol Description] [0022] Conventional Technology [0023] 1 : Wafer [0024] 2 : Solder Pad [0025] 3 : Substrate [0026] 4 : Contact [0027] 5 : Tin-based solder ball [0028] 6: colloid [0029] 7 : first intermetallic layer [0030] 8 : second intermetallic layer [0031] 9 : hole 099109755 Form No. A0101 Page 8 / Total 15 Page 0992017252-0 201133662 [0033] [0038] [0038] [0042] The present invention 10: electronic component 11: copper conductive portion 12 · wafer 13 : substrate 14 : colloid 20 : Solder material 30: Meng bonding material 40: Wetting layer 50: Metal intermetallic layer 60: Manganese-containing phase layer 099109755 Form No. Α0101 Page 9/Total 15 Page 0992017252-0

Claims (1)

201133662 七、申請專利範圍： 1 . 一種應用於電子封裝之銅錳結合結構，包括有： 一電子元件，該電子元件上設置有至少一銅導電部； 至少一對應該銅導電部之銲錫材料；及 至少一錳結合材，該錳結合材係設置在該銅導電部與該銲 錫材料之間，該銲錫材料係藉由該錳結合材與該銅導電部 黏結。 2 .如申請專利範圍第1項所述之應用於電子封裝之銅錳結合 結構，其中該锰結合材之材料為銅锰合金。 3 .如申請專利範圍第1項所述之應用於電子封裝之銅錳結合 結構，其中該銅導電部之材質與該錳結合材相同。 4 .如申請專利範圍第1項所述之應用於電子封裝之銅錳結合 結構，其中該錳結合材的應用型態係選自於由膜狀、片狀 、粉末、柱狀與合金所組成之群組。 5 .如申請專利範圍第1項所述之應用於電子封裝之銅錳結合 結構，其中該錳結合材的製作方式選自於電鍍、無電鍍、 化學反應合成、濺鍍、碾壓、融合與粉末合成所組成之群 組。 6 .如申請專利範圍第1項所述之應用於電子封裝之銅錳結合 結構，其中該錳結合材與該銲錫材料之間設置有一濕潤層 0 7 .如申請專利範圍第1項所述之應用於電子封裝之銅錳結合 結構，其中該銅導電部係選自於由銅與黃銅所組成之群組 〇 8 .如申請專利範圍第1項所述之應用於電子封裝之銅錳結合 099109755 表單編號A0101 第10頁/共15頁 0992017252-0 201133662 結構，其中該銅導電部係為一銅導線。 如申請專利範圍第1項所述之應用於電子封裝之銅錳結合 結構，其中該銲錫材料係為錫基銲球。 099109755 表單編號A0101 第11頁/共15頁 0992017252-0201133662 VII. Patent application scope: 1. A copper-manganese bonding structure applied to an electronic package, comprising: an electronic component, wherein the electronic component is provided with at least one copper conductive portion; at least one pair of solder materials corresponding to the copper conductive portion; And at least one manganese bonding material disposed between the copper conductive portion and the solder material, the solder material being bonded to the copper conductive portion by the manganese bonding material. 2. The copper-manganese bonding structure applied to an electronic package according to claim 1, wherein the material of the manganese bonding material is a copper-manganese alloy. 3. The copper-manganese bonding structure applied to an electronic package according to claim 1, wherein the copper conductive portion is made of the same material as the manganese bonding material. 4. The copper-manganese bonding structure for electronic packaging according to claim 1, wherein the application form of the manganese bonding material is selected from the group consisting of a film, a sheet, a powder, a column and an alloy. Group of. 5. The copper-manganese bonding structure for electronic packaging according to claim 1, wherein the manganese bonding material is selected from the group consisting of electroplating, electroless plating, chemical reaction synthesis, sputtering, rolling, fusion, and A group consisting of powder synthesis. 6. The copper-manganese bonding structure for electronic packaging according to claim 1, wherein the manganese bonding material and the solder material are provided with a wetting layer 0 7 as described in claim 1 The copper-manganese bonding structure applied to the electronic package, wherein the copper conductive portion is selected from the group consisting of copper and brass. The copper-manganese combination applied to the electronic package according to claim 1 of the patent application. 099109755 Form No. A0101 Page 10 of 15 0992017252-0 201133662 Structure in which the copper conductor is a copper wire. The copper-manganese bonding structure for electronic packaging according to claim 1, wherein the solder material is a tin-based solder ball. 099109755 Form No. A0101 Page 11 of 15 0992017252-0
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US8952267B2 (en) 2012-05-10 2015-02-10 National Chiao Tung University Electric connecting structure comprising preferred oriented Cu6Sn5 grains and method for fabricating the same
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US9142533B2 (en) 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
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US9773755B2 (en) 2010-05-20 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US11315896B2 (en) 2012-04-17 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9991224B2 (en) 2012-04-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect having varying widths and methods of forming same
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US9508668B2 (en) 2012-09-18 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive contacts having varying widths and method of manufacturing same
US9953939B2 (en) 2012-09-18 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive contacts having varying widths and method of manufacturing same
US10008459B2 (en) 2012-09-18 2018-06-26 Taiwan Semiconductor Manufacturing Company Structures having a tapering curved profile and methods of making same
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