KR100392498B1 - Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating - Google Patents

Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating Download PDF

Info

Publication number
KR100392498B1
KR100392498B1 KR10-1999-0036363A KR19990036363A KR100392498B1 KR 100392498 B1 KR100392498 B1 KR 100392498B1 KR 19990036363 A KR19990036363 A KR 19990036363A KR 100392498 B1 KR100392498 B1 KR 100392498B1
Authority
KR
South Korea
Prior art keywords
plating
electroless
copper
nickel
flip chip
Prior art date
Application number
KR10-1999-0036363A
Other languages
Korean (ko)
Other versions
KR20010019775A (en
Inventor
전영두
나재웅
임명진
백경욱
Original Assignee
한국과학기술원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 한국과학기술원 filed Critical 한국과학기술원
Priority to KR10-1999-0036363A priority Critical patent/KR100392498B1/en
Publication of KR20010019775A publication Critical patent/KR20010019775A/en
Application granted granted Critical
Publication of KR100392498B1 publication Critical patent/KR100392498B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11464Electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent

Abstract

본 발명은 전도성 폴리머 플립칩 접속용 무전해 니켈/구리 범프 형성방법에 관한 것으로서 보다 상세하게는 알루미늄(Al) 패드(pad)위에 무전해 니켈(Ni) 도금, 무전해 구리(Cu) 도금, 금(Au) 치환도금 공정으로 이루어진 니켈/구리 범프를 형성하여 이방성 전도성 폴리머를 이용하여 플립칩 접속한 후 고속 고주파 칩에 이용하는 방법에 관한 것이다.The present invention relates to a method for forming electroless nickel / copper bumps for conductive polymer flip chip connection, and more particularly, to electroless nickel (Ni) plating, electroless copper (Cu) plating, and gold on aluminum (Al) pads. (Au) The present invention relates to a method of forming a nickel / copper bump formed by a substitution plating process, connecting a flip chip using an anisotropic conductive polymer, and then using the same in a high speed high frequency chip.

본 발명의 무전해 니켈/구리 범프를 형성방법은 알루미늄 패드를 세척하는 공정과, 아연산염(zincate)으로 전처리를 거치는 공정과, 무전해 도금방법으로 니켈을 도금하는 공정과, 도금된 니켈에 다시 무전해 도금 방법으로 구리를 도금하는 공정 및, 무전해 구리도금의 일부를 금으로 치환하는 도금의 공정으로 이루어짐을 특징으로 한다.The electroless nickel / copper bump forming method of the present invention comprises the steps of washing the aluminum pads, pretreatment with zincate (zincate), plating the nickel by electroless plating, and back to the plated nickel. A process of plating copper by an electroless plating method, and a plating process of replacing a part of the electroless copper plating with gold.

본 발명은 무전해 니켈/구리 범프를 형성하고 이를 전자 패키지 기술에 이용하여 고속 고주파 칩(Chip)에의 응용 뿐만 아니라 공정이 간단하고 저가형의 전도성 폴리머 플립칩 접속용 범프를 개발하는 것을 목적으로 한다.An object of the present invention is to form electroless nickel / copper bumps and use them in electronic package technology to develop bumps for conductive polymer flip chip connection with a simple process and low cost as well as application to high speed high frequency chips.

Description

무전해도금법을 이용한 전도성 폴리머 플립칩 접속용 범프 형성방법{Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating}Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating}

본 발명은 전도성 폴리머 플립칩 접속용 무전해 니켈/구리 범프 형성방법에 관한 것으로서 보다 상세하게는 알루미늄(Al) 패드(pad)위에 무전해 니켈(Ni) 도금, 무전해 구리(Cu) 도금, 금(Au) 치환도금 공정으로 이루어진 니켈/구리 범프 형성방법 및 상기의 범프와 이방성 전도성 폴리머를 플립칩 접속하여 고속 고주파 칩에 이용하는 것에 관한 것이다.The present invention relates to a method of forming electroless nickel / copper bumps for conductive polymer flip chip connection. (Au) The present invention relates to a nickel / copper bump forming method comprising a substitution plating process, and the bump and the anisotropic conductive polymer are flip-chip connected to each other for use in a high speed high frequency chip.

최근 급속히 발전하는 반도체기술은 이미 백만 개 이상의 셀(cell) 집적, 비메모리 소자의 경우 많은 I/O 핀 개수, 큰 다이 크기, 많은 열 방출, 고전기적 성능 등의 경향으로 발전하고 있다. 그러나 상대적으로 이런 소자를 패키지하기 위한 전자 패키징 기술은 급속한 반도체 발전을 따라주지 못하였던 것이 사실이다.In recent years, the rapidly developing semiconductor technology has been developed with the trend of more than one million cell integration, large I / O pin count, large die size, large heat dissipation, and high performance of non-memory devices. Relatively, however, electronic packaging techniques for packaging such devices have not kept up with rapid semiconductor development.

전자 패키지기술은 반도체 소자에서부터 최종 제품까지의 모든 단계를 포함하는 매우 광범위하고 다양한 시스템 제조 기술로서 최종전자 제품의 성능, 크기,가격, 신뢰성 등을 결정하는데 매우 중요하다. 특히 고전기적 성능, 극소형/고밀도, 저 전력, 다기능, 초고속 신호 처리, 영구적 신뢰성을 추구하는 최근의 전자제품에 있어 극소형 패키지 부품은 컴퓨터, 정보통신, 이동통신, 고급 가전제품 등의 필수 부품으로서 플립 칩(Flip Chip) 기술은 현재 스마트카드(Smart cards), LCD, PDP 등의 디스플레이(Display) 패키징, 컴퓨터, 휴대용 전화기, 통신시스템 (Communication system) 등에 그 활용 범위를 넓혀 가고 있다.Electronic packaging technology is a very wide variety of system fabrication techniques, covering all stages from semiconductor devices to final products, and is very important in determining the performance, size, price, and reliability of final electronic products. Particularly for the latest electronic products that pursue high performance, ultra small / high density, low power, multifunctional, ultra high speed signal processing, and permanent reliability, ultra small packaged parts are essential parts for computers, telecommunications, mobile communication, and high-end consumer electronics. Flip chip technology is currently expanding its use in display packaging such as smart cards, LCDs, and PDPs, computers, mobile phones, and communication systems.

이러한 플립 칩 기술은 기존의 솔더(Solder)를 이용한 접속 공정에서 저가, 극미세 전극 피치 가능, 무용제(fluxless)의 환경 친화적인 공정, 저온 공정 등의 장점을 가지는 전도성 접착제를 이용한 접속으로 대체해 가고 있다.This flip chip technology is being replaced by a connection using a conductive adhesive that has advantages such as low cost, extremely fine electrode pitch, a solventless environment friendly process, and a low temperature process in a conventional solder process. have.

전도성 접착제를 이용한 플립 칩 기술은 패드에 균일한 높이의 범프(Bump)를 형성하는 공정, 전도성 입자가 포함된 접착제를 도포하는 공정, 칩(Chip)과 기판과의 접합 공정으로 이루어진다.Flip chip technology using a conductive adhesive consists of forming a bump having a uniform height on a pad, applying an adhesive containing conductive particles, and bonding a chip to a substrate.

이러한 플립 칩 기술을 구성하는 여러 공정 중, 범프 형성 기술은 미세한 패드마다 선택적으로 원하는 높이의 범프를 형성시켜야 하는 어려움이 있다.Among the various processes constituting the flip chip technology, bump forming technology has a difficulty in forming a bump of a desired height selectively for each fine pad.

범프 형성 방법으로서 현재는 증발법(Evaporation), 스퍼터링법 (Sputtering), 전해도금법(Electroplating) 등의 방법과 포토리소그래피 (Photolithography)를 혼합한 범프 형성 방법과 골드 스터드(Gold stud) 범프를 기계적으로 형성시키는 방법들이 주로 사용되고 있으나 이런 방법은 고비용이며 복잡하기 때문에 무전해 도금법을 이용해 범프를 형성하는 공정을 도입하고 있다.As a bump forming method, a bump forming method and a gold stud bump are mechanically formed by mixing evaporation, sputtering, electroplating, photolithography, and the like. However, these methods are mainly used, but since these methods are expensive and complicated, a process of forming bumps using an electroless plating method is introduced.

무전해 도금을 이용한 범프 형성 기술은 도금액 속에 담금만으로 알루미늄(Al) 패드 위에 선택적인 범프 형성이 가능하기 때문에 저비용이며 공정이 간단하다. 또한, 웨이퍼 단위의 공정이 가능하며 균일한 높이, 우수한 전기적·기계적 성질 등의 장점으로 미세 전자 패키징에 큰 가능성을 갖고 있다.Bump forming technology using electroless plating is low cost and simple process because selective bump formation is possible on aluminum (Al) pad only by immersion in plating solution. In addition, wafer-based processes are possible and have great potential for microelectronic packaging due to advantages such as uniform height and excellent electrical and mechanical properties.

현재는 무전해 Ni 도금을 이용한 범프 형성 기술이 솔더 플립 칩(Solder Flip Chip) 분야에서 UBM(Under Bump Metallurgy) 형성 기술로서 쓰이고 있으며 독일을 중심으로 하여 미국, 일본 등에서 응용 분야를 넓히기 위해 활발히 연구중이다.Currently, bump forming technology using electroless Ni plating is used as an under bump metallurgy (UBM) forming technology in solder flip chips, and is actively researching to expand the application field in the US and Japan, mainly in Germany. .

한편 종래기술로서 미국특허 제 5,583,073호는 무전해 Ni 도금을 이용해 솔더범프의 플립칩용 UBM층을 형성하고자 한 것으로 확산장애물(Diffusion Barrier)로서의 역할이 주된 내용으로 Ni-Cu 범프에 관한 내용은 언급이 되어있지 않는 반면 본 발명은 ACA 플립칩용 범프 형성에 무전해 도금을 이용하였으므로 응용분야가 다르며 고속 고주파칩에의 응용, 무전해 Cu 도금의 적용에서 차이가 있다.Meanwhile, US Pat. No. 5,583,073, which is a prior art, intends to form UBM layer for flip chip of solder bump using electroless Ni plating, and its role as a diffusion barrier is mainly mentioned. On the other hand, since the present invention uses electroless plating to form bumps for ACA flip chips, the application fields are different, and there are differences in applications to high-speed high frequency chips and application of electroless Cu plating.

또한 롤프 아센브레너 등이 발표(Rolf Ascenbrenner, Andreas Ostmann, Ute Buetler abd H. Reichl, "Electroless Ni/Cu plating as a New Bump Metallization" IEES CPMT-B, 18, 2, 1995)한 논문은 무전해 Ni-Cu 범프를 사용했다는 점에서 본 발명과 흡사하지만, 이 논문에서 Ni-Cu 범프는 단단한 무전해 Ni의 단점을 보완하기 위해 부드러운 무전해 Cu를 도입함으로써 TAB 본딩(전자패키지의 종류로서 플립칩 패키지는 아님)과 와이어 본딩(wire bonding)에 응용하기 위한 것으로서 본 발명에서의 ACA 플립칩을 위한 무전해 범프 및 고속 고주파용 칩의 플립칩을 위해 Cu의 성능(전기전도도, low inductance)을 이용하고자 한 점에 차이가있다.Also published by Rolf Ascenbrenner, Andreas Ostmann, Ute Buetler abd H. Reichl, "Electroless Ni / Cu plating as a New Bump Metallization" IEES CPMT-B, 18, 2, 1995 Similar to the present invention in that -Cu bumps are used, in this paper, Ni-Cu bumps are TAB bonding (flip chip package as a kind of electronic package) by introducing soft electroless Cu to compensate for the shortcomings of hard electroless Ni. To use the performance of Cu (low inductance) for the electroless bump for ACA flip chip and the flip chip of high speed high frequency chip in the present invention. There is a difference in one point.

본 발명은 알루미늄(Al) 패드(pad)위에 무전해 니켈(Ni) 도금, 무전해 구리 (Cu) 도금, 금(Au) 치환도금 공정으로 이루어진 니켈/구리 범프를 형성하고 이를 전자 패키지 기술에 이용하여 고속 고주파 칩(Chip)에의 응용 뿐만 아니라 공정이 간단하고 저가형의 전도성 폴리머 플립칩 접속용 범프를 개발하는 것을 목적으로 한다.The present invention forms nickel / copper bumps on electroless nickel (Ni), electroless copper (Cu), and gold (Au) substitution plating on aluminum (Al) pads and uses them in electronic packaging technology. Therefore, the present invention aims to develop bumps for conductive polymer flip chip connection with low cost and simple process as well as application to high speed high frequency chip.

도 1은 무전해 니켈 도금-무전해 구리 도금-치환 금 도금 형성의 공정도로서,1 is a process diagram of electroless nickel plating-electroless copper plating-substitution gold plating formation,

도 1a는 전처리 공정을 나타낸다.1A shows a pretreatment process.

도 1b는 아연산염 처리공정을 나타낸다.Figure 1b shows a zincate treatment process.

도 1c는 무전해 니켈 도금공정을 나타낸다.1C shows an electroless nickel plating process.

도 1d는 무전해 구리 도금과 금 치환도금 공정을 나타낸다.1D shows an electroless copper plating and gold substitution plating process.

도 2a는 고속 고주파 칩의 알루미늄 패드를 나타낸 사진이다.Figure 2a is a photograph showing the aluminum pad of the high speed high frequency chip.

도 2b는 무전해 니켈 도금을 나타낸 사진이다.2b is a photograph showing electroless nickel plating.

도 2c는 무전해 구리 도금을 나타낸 사진이다.2C is a photograph showing electroless copper plating.

도 2d는 금 치환 도금을 나타낸 사진이다.Figure 2d is a photograph showing the gold substitution plating.

도 3a는 무전해 니켈-구리-금 범프의 단면을 나타낸 사진으로 범프의 아래쪽은 니켈을 나타내고, 위쪽은 구리를 나타낸다.Figure 3a is a photograph showing the cross-section of the electroless nickel-copper-gold bump, the bottom of the bump represents nickel, the top represents copper.

도 3b는 무전해 니켈-구리-금 범프의 계면을 나타낸 사진으로 왼쪽의 두꺼운부분은 니켈을 나타내고, 오른쪽의 얇은 부분은 구리를 나타낸다.Figure 3b is a photograph showing the interface of the electroless nickel-copper-gold bumps, the thick portion on the left represents nickel, the thin portion on the right represents copper.

도 4a는 전도성 폴리머를 이용한 무전해 니켈-구리-금 범프의 플립칩 접속 단면을 나타낸 사진이다.4A is a photograph showing a flip chip connection section of an electroless nickel-copper-gold bump using a conductive polymer.

도 4b는 전도성 폴리머를 이용한 무전해 니켈-구리-금 범프의 플립칩 접속을 나타낸 사진이다.4B is a photograph showing flip chip connection of an electroless nickel-copper-gold bump using a conductive polymer.

본 발명의 무전해 니켈(Ni), 구리(Cu), 금(Au) 도금법을 이용한 니켈/구리 범프 형성방법을 첨부한 도면에 의하여 설명하면 다음과 같다.The nickel / copper bump forming method using the electroless nickel (Ni), copper (Cu), and gold (Au) plating methods of the present invention will be described with reference to the accompanying drawings.

본 발명의 니켈/구리 범프를 형성하는 방법은 알루미늄(Al) 패드를 세척하는 (도 1a) 공정과, 아연산염(zincate)으로 알루미늄 패드의 전처리(도 1b)를 하는 공정과, 무전해 도금방법으로 니켈을 도금(도 1c)하는 공정과, 도금된 니켈 부분에 무전해 도금 방법으로 구리를 도금하는 공정 및 무전해 구리도금의 일부를 금으로 치환하는 도금의 공정(도 1d)으로 이루어진다.The method of forming the nickel / copper bumps of the present invention comprises the steps of washing the aluminum (Al) pad (FIG. 1A), pretreating the aluminum pad with zinc acid (zincate), and electroless plating method. The process of plating nickel (FIG. 1C), the process of plating copper on the plated nickel part by the electroless plating method, and the process of plating which replaces a part of electroless copper plating with gold (FIG. 1D).

상기의 공정에서 아연산염(zincate)은 수산화나트륨(NaOH) 120g/ℓ과 산화아연(ZnO) 3∼4g/ℓ를 증류수에 녹인 용액을 사용하며 무전해 니켈 도금과의 접착력을 좋게 하기 위하여 아연산염 용액 20초, 50% 질산 용액 10초 및 아연산염 용액20초의 전처리 단계를 거친다.In the above process, zincate (zincate) is a solution of 120 g / l of sodium hydroxide (NaOH) and 3 to 4 g / l of zinc oxide (ZnO) in distilled water and is used to improve adhesion to electroless nickel plating. A pretreatment step of 20 seconds of solution, 10 seconds of 50% nitric acid solution and 20 seconds of zincate solution.

무전해 니켈 도금액은 황산니켈(Nickel Sulfate)이 10∼30g/ℓ, 차아인산나트륨(H2PO2 -)이 25∼40g/ℓ의 범위내에서 보다 바람직하게는 황산 니켈이 13g/ℓ, 차아인산나트륨이 30g/ℓ가 포함된 용액을 사용하는 것이 좋다. 차아인산나트륨을 이용한 무전해 니켈 도금시의 반응은 다음의 주반응과 2차 반응으로 나눌 수 있다Electroless nickel plating solution of nickel sulfate (Nickel Sulfate) is 10~30g / ℓ, and sodium hypophosphite (H 2 PO 2 -) is preferably the nickel sulfate 13g / ℓ, the car than in the range of 25~40g / ℓ It is recommended to use a solution containing 30 g / l of sodium phosphite. The reaction of electroless nickel plating with sodium hypophosphite can be divided into the following main reactions and secondary reactions.

주반응 Ni+2+ H2PO2 -+ H2O → Ni + H2PO3 -+ 2H+(1)Note reaction Ni +2 + H 2 PO 2 - + H 2 O → Ni + H 2 PO 3 - + 2H + (1)

H2PO2 -+ H2O → H2PO3 -+ H2(2) H 2 PO 2 - + H 2 O → H 2 PO 3 - + H 2 (2)

2차 반응 2H++ 2e-→ H2(3)The second reaction 2H + + 2e - → H 2 (3)

H2PO2 -+ H+→ P + OH-+ H2O (4) H 2 PO 2 - + H + → P + OH - + H 2 O (4)

상기 반응식 중 (1)식에 의해 니켈의 환원이 이루어지며 (2)식은 차아인산나트륨의 소모, (3)식은 수소의 발생, (4)식은 인(P)의 생성을 나타낸다. 니켈의 환원은 아연산염 처리에서 치환된 아연(Zn)입자가 핵으로 작용해 일어나기 때문에 아연산염 전처리를 한 알루미늄 표면에만 니켈이 성장하게 된다. 따라서 무전해 니켈도금으로써 알루미늄 패드만을 선택적으로 도금이 가능하고 균일한 높이(15μm)를 얻을 수 있다.Reduction of nickel is performed by the formula (1) in the above reaction formula, where (2) represents the consumption of sodium hypophosphite, (3) represents the generation of hydrogen, and (4) represents the production of phosphorus (P). The reduction of nickel is caused by the zinc (Zn) particles that are substituted in the zincate treatment, so that the nickel grows only on the aluminum surface subjected to the zincate pretreatment. Therefore, only aluminum pads can be selectively plated by electroless nickel plating, and a uniform height (15 μm) can be obtained.

무전해 구리 도금은 포름알데히드(HCHO)를 환원제로 하여 다음의 반응을 통해 구리가 환원된다.In electroless copper plating, formaldehyde (HCHO) is used as a reducing agent to reduce copper through the following reaction.

Cu2++ 2HCHO + 4OH-→ Cu + 2H2O + 2HCO2 - Cu 2+ + 2HCHO + 4OH - → Cu + 2H 2 O + 2HCO 2 -

무전해 구리 도금은 니켈을 핵으로 일어날 수 있어 전처리 없이 니켈/구리의 범프를 형성할 수 있으며 균일한 높이(5μm)를 얻을 수 있다. 금 치환 도금은 구리를 금(Au)으로 치환시켜주는 단계로 다음의 반응식에 의하여 구리의 표면을 금으로 치환시키며 구리의 표면이 금으로 치환되면 더 이상 금의 도금은 일어나지 않는다.Electroless copper plating can cause nickel to nucleate, forming bumps of nickel / copper without pretreatment and achieving a uniform height (5 μm). Gold substitution plating is a step of replacing copper with gold (Au), and the surface of the copper is replaced with gold by the following reaction formula. If the surface of copper is replaced with gold, the plating of gold no longer occurs.

Cu + Au2+→ Cu2++ AuCu + Au 2+ → Cu 2+ + Au

본 발명에서는 1,000∼5,000Å의 두께로 금을 치환도금 하여 구리의 산화를 방지한다.In the present invention, gold is substituted with a thickness of 1,000 to 5,000 kPa to prevent oxidation of copper.

여러 가지 무전해 도금법 중에서 무전해 니켈 도금은 알루미늄 패드 위에 범프형성이 가능하며 도금속도가 빠르고 선택성이 뛰어난 장점이 있다. 하지만 도금중 인(P)의 첨가로 인해 비저항이 크고, 열팽창계수의 차이로 인한 크랙 발생 등의 단점을 갖는다. 무전해 구리 도금은 비저항이 매우 낮은 반면에 알루미늄 패드 위에 직접 형성이 불가능하고 도금속도가 느린 단점이 있다. 하지만, 니켈에는 직접 무전해 구리 도금이 가능하므로 이 두 가지 무전해 도금법을 이용하여 범프를 형성하였다. 마지막으로 구리의 산화를 방지하기 위해 금(Au)을 치환 도금한다.Among various electroless plating methods, electroless nickel plating enables bump formation on aluminum pads and has advantages of high plating speed and excellent selectivity. However, due to the addition of phosphorus (P) during plating has a high specific resistance, such as cracks due to the difference in the coefficient of thermal expansion. While electroless copper plating has a very low resistivity, it cannot be formed directly on an aluminum pad and has a disadvantage of slow plating speed. However, nickel can be directly electroless copper plated to form bumps using these two electroless plating methods. Finally, the plating of gold (Au) is substituted to prevent the oxidation of copper.

기존의 무전해 니켈 만을 이용한 범프 시스템을 고속 고주파 칩에 응용할 때, 비저항이 크며 니켈의 강자성으로 인해 인덕턴스(inductance)가 증가하여 임피던스(impedance)가 증가하기 때문에 지연시간이 커지는 요인이 된다. 하지만, 본발명의 무전해 니켈-구리-금 범프를 적용하면, 구리층이 니켈을 대체함에 따라 비저항이 줄어들고 구리의 반자성으로 인해 인덕턱스(inductance)를 줄일 수 있다. 또한, 니켈, 구리 금 도금시 모두 무전해 도금법을 이용하기 때문에 공정의 일관성을 갖는다.When the conventional bumper system using only electroless nickel is applied to a high-speed high frequency chip, the resistivity is large and the delay time is increased because the inductance is increased due to the inductance due to the ferromagnetic property of nickel. However, by applying the electroless nickel-copper-gold bump of the present invention, the resistivity decreases as the copper layer replaces nickel and the inductance can be reduced due to the diamagnetic of copper. In addition, both nickel and copper gold plating use the electroless plating method so that the process is consistent.

도 2(a)(b)(c)(d)는 고속 고주파 칩에 형성된 무전해 니켈-구리-금 범프 사진을 나타낸 것으로서 150μm 피치의 알루미늄 패드로 이루어진 고속 고주파 칩(도 2a)에 무전해 니켈 도금(도 2b), 무전해 구리 도금(도 2c), 금 치환 도금(도2d)을 차례로 진행할 때의 사진이다. 알루니늄 패드위에만 선택적으로 범프가 형성됨을 확인할 수 있고 범프의 모양도 윗 부분이 평평하여 전도성 폴리머 플립 칩 접속시 유리하게 작용한다.2 (a) (b) (c) (d) show electroless nickel-copper-gold bumps formed on high-speed high-frequency chips, and show electroless nickel on high-speed high-frequency chips (Fig. 2a) made of aluminum pads with a 150 μm pitch. It is a photograph at the time of performing plating (FIG. 2B), electroless copper plating (FIG. 2C), and gold substitution plating (FIG. 2D) in order. It can be seen that the bumps are selectively formed only on the aluminum pad, and the shape of the bumps is also flat, which is advantageous when connecting the conductive polymer flip chip.

도 3a는 니켈/구리 범프의 단면구조를 나타낸 사진으로서 범프의 아래쪽은 니켈을 나타내고, 위쪽은 구리를 나타내고 있으며 평평한 면을 갖는 니켈/구리 범프를 확인할 수 있다. 도3b는 니켈/구리 범프 계면 사진으로서 왼쪽의 두꺼운 부분은 니켈을 나타내고, 오른쪽의 얇은 부분은 구리를 나타내고 있으며 약 15μm의 니켈과 과 약 5 μm의 구리가 균일한 높이를 이루고 있음을 알 수 있다.Figure 3a is a photograph showing the cross-sectional structure of the nickel / copper bumps, the bottom of the bumps represent nickel, the upper represents copper, it can be seen that the nickel / copper bumps having a flat surface. 3b is a nickel / copper bump interface photograph showing that the thick portion on the left side represents nickel, the thin portion on the right side represents copper, and that about 15 μm of nickel and about 5 μm of copper have a uniform height. .

도 4a는 이방성 전도성 접착제(Anisotropic Conductive Adhesive, ACA)를 이용하여 IC 칩(chip) 위의 무전해 니켈/구리 범프와 기질(substrate)의 플립 칩 접속을 나타낸 단면도이다. 범프가 형성된 칩을 뒤집어 ACA를 통해 기판의 패드와 연결시킨다. ACA는 전도성 입자를 포함하고 있어 무전해 니켈/구리 범프와 기판 패드 사이를 전도입자를 통해 연결해 준다. 한편 도 4b는 ACA 플립 칩 접속의 전체를 나타낸 사진이다.FIG. 4A is a cross-sectional view illustrating flip chip connection of an electroless nickel / copper bump and a substrate on an IC chip using an anisotropic conductive adhesive (ACA). The bumped chip is flipped over and connected to the pad of the substrate through the ACA. The ACA contains conductive particles that connect through the conductive particles between the electroless nickel / copper bumps and the substrate pad. 4B is a photograph showing the entire ACA flip chip connection.

본 발명의 전도성 폴리머 플립칩용 무전해 니켈/구리 범프는 무전해 니켈 도금과 무전해 구리 도금을 함께 도입함으로써 무전해 니켈 도금의 장점인 빠른 도금 속도와 무전해 구리 도금의 장점인 낮은 비저항의 성질을 모두 갖도록 한다.The electroless nickel / copper bumps for the conductive polymer flip chip of the present invention adopt electroless nickel plating and electroless copper plating together to achieve high plating speed, which is an advantage of electroless nickel plating, and low resistivity, which is an advantage of electroless copper plating. Have them all.

또한 무전해 니켈/구리 범프를 전도성 폴리머 플립칩 접속시, 구리의 낮은 비저항 성질로 인한 저항의 감소와 니켈의 강자성(ferromagnetic)을 구리의 반자성 (diamagnetic)으로 전환시켜 인덕턴스(inductance)를 낮출 수 있어 지연시간(delay time)이 감소하는 효과를 얻을 수 있다. 따라서 상기의 범프를 이용한 플립칩 패키지를 고속 고주파용 칩의 전자패키지에 응용하여 향상된 전기적 성능을 얻을 수 있다.In addition, when connecting electroless nickel / copper bumps to conductive polymer flip chips, the inductance can be lowered by reducing the resistance due to the low resistivity of copper and converting the ferromagnetic of nickel to the diamagnetic of copper. It is possible to obtain an effect of reducing the delay time. Therefore, improved electrical performance can be obtained by applying the flip chip package using the bump to the electronic package of the high-speed high-frequency chip.

Claims (3)

전도성 폴리머 플립칩 접속용 범프 형성방법에 있어서,In the bump forming method for conductive polymer flip chip connection, 아연산염으로 알루미늄 패드를 전처리하는 단계와, 전처리를 거친 알루미늄 패드 상에 무전해 도금방법으로 니켈 도금층을 형성하는 단계와, 니켈 도금층위에 무전해 도금방법으로 구리 도금층을 형성하는 단계 및, 무전해 구리도금의 일부를 금으로 치환하는 단계를 포함함을 특징으로 하는 전도성 폴리머 플립칩 접속용 범프 형성방법Pretreatment of the aluminum pad with zincate, forming a nickel plating layer on the pretreated aluminum pad by an electroless plating method, forming a copper plating layer on the nickel plating layer by an electroless plating method, and electroless copper Method for forming a bump for connecting a conductive polymer flip chip comprising the step of replacing a portion of the plating with gold. 제 1항에 있어서, 무전해 니켈 도금과의 접착력을 향상시키기 위하여 아연산염 전처리 공정은 수산화나트륨(NaOH) 120g/ℓ과 산화아연(ZnO) 3∼4g/ℓ를 증류수에 녹인 용액을 아연산염 용액 20초-질산 50% 용액 10초-아연산염 용액 20초 동안 처리함을 특징으로 하는 무전해도금법을 이용한 전도성 폴리머 플립칩 접속용 범프 형성방법.The zincate pretreatment process according to claim 1, wherein the zincate pretreatment step is a zincate solution containing 120 g / l sodium hydroxide (NaOH) and 3-4 g / l zinc oxide (ZnO) in distilled water to improve adhesion to the electroless nickel plating. 20 seconds-50% nitric acid solution 10 seconds-nitrate solution Process for forming a bump for conductive polymer flip chip connection using an electroless plating method characterized in that for 20 seconds. 삭제delete
KR10-1999-0036363A 1999-08-30 1999-08-30 Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating KR100392498B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR10-1999-0036363A KR100392498B1 (en) 1999-08-30 1999-08-30 Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-1999-0036363A KR100392498B1 (en) 1999-08-30 1999-08-30 Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating

Publications (2)

Publication Number Publication Date
KR20010019775A KR20010019775A (en) 2001-03-15
KR100392498B1 true KR100392498B1 (en) 2003-07-22

Family

ID=19609275

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-1999-0036363A KR100392498B1 (en) 1999-08-30 1999-08-30 Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating

Country Status (1)

Country Link
KR (1) KR100392498B1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3679001B2 (en) * 2000-12-22 2005-08-03 シャープ株式会社 Semiconductor device and manufacturing method thereof
JP3999945B2 (en) * 2001-05-18 2007-10-31 株式会社東芝 Manufacturing method of semiconductor device
KR20030094692A (en) * 2002-06-07 2003-12-18 삼성테크윈 주식회사 Method of forming electroless solder bumps
KR100873040B1 (en) * 2002-06-11 2008-12-09 삼성테크윈 주식회사 Semiconductor Package and Manufacturing Method For Bump of Semiconductor Package
KR100464537B1 (en) * 2002-06-29 2005-01-03 주식회사 하이닉스반도체 Manufacturing of Method of Semiconductor Device
KR100886701B1 (en) * 2002-07-09 2009-03-04 주식회사 하이닉스반도체 Method for packaging a semiconductor chip in fbga type
KR100476301B1 (en) * 2002-07-27 2005-03-15 한국과학기술원 Fabrication Method of multilayer UBM by Electroplating for Flip chip Interconnections
KR100936782B1 (en) * 2003-04-04 2010-01-14 삼성테크윈 주식회사 Semiconductor device having metal bumps formed by 2-step electroless Ni plating and method of fabricating the bumps
KR100659527B1 (en) 2003-10-22 2006-12-20 삼성전자주식회사 Semiconductor chip having three dimension type ubm for flip chip bonding and mounting structure thereof
KR102624624B1 (en) 2016-06-15 2024-01-12 삼성디스플레이 주식회사 Integrated circuit and method for manufacturing thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63122248A (en) * 1986-11-12 1988-05-26 Nec Corp Manufacture of semiconductor device
JPH022132A (en) * 1988-06-14 1990-01-08 Nec Corp Manufacture of bump electrode
JPH04292803A (en) * 1991-03-20 1992-10-16 Hitachi Ltd Anisotropic conductive film
JPH04318935A (en) * 1991-04-17 1992-11-10 Seiko Epson Corp Electrode and manufacture thereof and connecting method thereof
KR100264479B1 (en) * 1996-10-16 2000-09-01 가시오 가즈오 Structure of bump electrode and method of forming the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63122248A (en) * 1986-11-12 1988-05-26 Nec Corp Manufacture of semiconductor device
JPH022132A (en) * 1988-06-14 1990-01-08 Nec Corp Manufacture of bump electrode
JPH04292803A (en) * 1991-03-20 1992-10-16 Hitachi Ltd Anisotropic conductive film
JPH04318935A (en) * 1991-04-17 1992-11-10 Seiko Epson Corp Electrode and manufacture thereof and connecting method thereof
KR100264479B1 (en) * 1996-10-16 2000-09-01 가시오 가즈오 Structure of bump electrode and method of forming the same

Also Published As

Publication number Publication date
KR20010019775A (en) 2001-03-15

Similar Documents

Publication Publication Date Title
US6362090B1 (en) Method for forming flip chip bump and UBM for high speed copper interconnect chip using electroless plating method
US6028011A (en) Method of forming electric pad of semiconductor device and method of forming solder bump
US6608374B1 (en) Semiconductor chip assembly with bumped conductive trace
TW201121376A (en) Circuit wiring board incorporating heat resistant substrate
TW444236B (en) Bumpless flip chip assembly with strips and via-fill
US20080001271A1 (en) Flipped, stacked-chip IC packaging for high bandwidth data transfer buses
TW200303588A (en) Semiconductor device and its manufacturing method
CN101295692B (en) Semiconductor device
TW200849428A (en) Under bump metallurgy structure and die structure using the same and method of manufacturing die structure
KR100392498B1 (en) Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating
US20120186852A1 (en) Structure of electrolessly palladium and gold plated films and process for making the same, assembled structure of palladium and gold plated films bonded with copper or copper-palladium wire and assembling process therefore
JP2007266131A (en) Semiconductor device and its manufacturing method
US6506672B1 (en) Re-metallized aluminum bond pad, and method for making the same
US6396156B1 (en) Flip-chip bonding structure with stress-buffering property and method for making the same
JPH11214421A (en) Method for forming electrode of semiconductor element
US20060019481A1 (en) Gold bump structure and fabricating method thereof
JP3156417B2 (en) Method for forming electrodes of semiconductor device
CN218769525U (en) Adapter plate and packaging structure based on silver nanoparticles
US6537851B1 (en) Method of connecting a bumped compliant conductive trace to a semiconductor chip
CN104066267A (en) Chemical plating structure of copper base material and technique thereof
JPH07193068A (en) Flip chip bump and its manufacture
KR101083099B1 (en) Electronic device and use thereof
CN218498063U (en) Circuit interconnection structure and electronic device
JP5282380B2 (en) Semiconductor device and manufacturing method thereof
KR100422271B1 (en) beam lead of micro BGA type semiconductor package

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090629

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee