JPH022132A - Manufacture of bump electrode - Google Patents
Manufacture of bump electrodeInfo
- Publication number
- JPH022132A JPH022132A JP14720988A JP14720988A JPH022132A JP H022132 A JPH022132 A JP H022132A JP 14720988 A JP14720988 A JP 14720988A JP 14720988 A JP14720988 A JP 14720988A JP H022132 A JPH022132 A JP H022132A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- solder
- semiconductor substrate
- plating
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000007747 plating Methods 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052802 copper Inorganic materials 0.000 claims abstract description 8
- 239000010949 copper Substances 0.000 claims abstract description 8
- 238000007772 electroless plating Methods 0.000 claims abstract description 7
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052725 zinc Inorganic materials 0.000 claims abstract description 3
- 239000011701 zinc Substances 0.000 claims abstract description 3
- 238000006073 displacement reaction Methods 0.000 claims description 5
- 150000002739 metals Chemical class 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 32
- 238000000206 photolithography Methods 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 230000004907 flux Effects 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 238000007689 inspection Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000005476 soldering Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- KWSLGOVYXMQPPX-UHFFFAOYSA-N 5-[3-(trifluoromethyl)phenyl]-2h-tetrazole Chemical compound FC(F)(F)C1=CC=CC(C2=NNN=N2)=C1 KWSLGOVYXMQPPX-UHFFFAOYSA-N 0.000 description 1
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910001379 sodium hypophosphite Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の表面電極にバンプ電極を形成する
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming bump electrodes on surface electrodes of semiconductor devices.
従来、半導体装置の回路基板に実装する方法としてフリ
ップチップ方式があるが、このときに、半導体装置の基
板の表面に形成されているのがバンプ電極である。特に
、ゲートアレイのような多数の電極を有する半導体装置
は、この実装方式が有利なため、多く利用されている。Conventionally, there is a flip-chip method as a method of mounting a semiconductor device on a circuit board, and in this case, bump electrodes are formed on the surface of the substrate of the semiconductor device. In particular, this mounting method is advantageous for semiconductor devices having a large number of electrodes, such as gate arrays, and is therefore widely used.
通常、このバンプ電極を製作する方法は、まず、半導体
基板の表面に熱酸化法により酸化膜を形成する。次に、
ホトリソグラフィ法により、電極パッドを形成する領域
の酸化膜を選択的に除去し、除去した部分にアルミニウ
ムを金属蒸着することにより電極パッドを形成する。次
に、電極パッドを含む半導体基板上に、金属蒸着法によ
り、例えば、チタン、クロム及び金等の複層の金属層を
形成する。この複層の金属層をホトリソグラフィ法によ
り、電極パッド以外の蒸着金属層を除去して電極パッド
の上の複層の金属層を残し中間層とする。次に、再び、
ホトリソグラフィ法により、まず、ポリイミド層を半導
体基板全面に塗布し、電極パッド上のポリイミド層を窓
状に除去する。次に、電解めっき法により中間層の上に
銅もしくはニッケルめっき層を形成し、更に、前記めっ
き層の上に、例えば、鉗９５％、錫５％のはんだを供給
し、はんだめっき層を形成し、引続きはんだめっき層を
加熱して半球状のバンプ電極を形成していた。Usually, in the method of manufacturing this bump electrode, an oxide film is first formed on the surface of a semiconductor substrate by thermal oxidation. next,
The oxide film in the region where the electrode pad is to be formed is selectively removed using a photolithography method, and aluminum is deposited on the removed portion to form the electrode pad. Next, a multilayer metal layer of, for example, titanium, chromium, and gold is formed on the semiconductor substrate including the electrode pad by a metal vapor deposition method. From this multilayer metal layer, the vapor deposited metal layers other than the electrode pads are removed by photolithography, leaving the multilayer metal layer above the electrode pads as an intermediate layer. Then again,
First, a polyimide layer is applied to the entire surface of the semiconductor substrate by photolithography, and the polyimide layer on the electrode pads is removed in a window shape. Next, a copper or nickel plating layer is formed on the intermediate layer by electrolytic plating, and a solder containing, for example, 95% tin and 5% tin is supplied on the plating layer to form a solder plating layer. However, the solder plating layer was subsequently heated to form a hemispherical bump electrode.
上述した従来のバンプ電極の製造方法は、中間層を形成
するために真空蒸着法を使用するとか、また、各めっき
層を形成する毎に、数度のホトリソグラフィ法によるパ
ターンを形成するという工程を必要とする。このため歩
留り低下や、多大な工数を費やし、更に、これらの工程
に用いる設備費も高く、製品原価に跳返るという問題が
ある。The above-mentioned conventional method for manufacturing bump electrodes involves steps such as using a vacuum evaporation method to form an intermediate layer, or forming a pattern using photolithography several times each time each plating layer is formed. Requires. For this reason, there are problems in that the yield decreases, a large number of man-hours are required, and the cost of equipment used in these steps is also high, which increases the product cost.
本発明の目的は、かかる複雑な工程を必要とせず簡易的
な工程でバンプ電極を形成するバンプ電極の製造方法を
提供することにある。An object of the present invention is to provide a method for manufacturing bump electrodes that does not require such complicated steps and forms bump electrodes through simple steps.
本発明のバンプ電極の製造方法は、半導体基板上の電極
上にパラジウムあるいは亜鉛のいずれか、もしくは両金
属による金属層を置換めっき法で形成する工程と、前記
金属層上にニッケルあるいは銅のいずれかの金属、もし
くは両金属による無電解めっき層を形成する工程と、前
記半導体基板を溶融金属に浸すことにより前記無電解め
っき層上に前記溶融金属のバンプ状の金属層を形成する
工程とを含んで構成される。The method for manufacturing a bump electrode of the present invention includes the steps of forming a metal layer of either palladium or zinc, or both metals, on an electrode on a semiconductor substrate by displacement plating, and forming a metal layer of either nickel or copper on the metal layer. a step of forming an electroless plating layer of the above metal or both metals; and a step of forming a bump-shaped metal layer of the molten metal on the electroless plating layer by immersing the semiconductor substrate in the molten metal. It consists of:
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明によるバンプ電極を含めた半導体基板の
断面図、第２図は本発明の第１の実施例を説明するため
の多数の電極が形成された半導体基板の側面図、第３図
は本発明の第１の実施例を説明するための半導体基板と
溶融はんだ付は装置の断面図である。まず、第１図を示
すように、従来例と同様に、半導体基板１上の酸化膜２
の上にアルミニウム製の電極パッド３を形成する。次に
、半導体基板１を、例えば、アルカリ水溶液中に浸して
電極パッド３の酸化膜を除去して清浄化を行い。次に、
例えば、パラジウム、亜鈴を置換めっき法により中間層
４を形成する。次に、次亜りん酸ソーダを還元剤とする
無電解ニッケルめっき液に半導体基板ｌを浸して無電解
ニッケルめっき層５を形成する。例えば、この無電解ニ
ッケルめっき層５は１μｍ以上の厚さを確保する必要が
ある。FIG. 1 is a cross-sectional view of a semiconductor substrate including bump electrodes according to the present invention, FIG. 2 is a side view of a semiconductor substrate on which a large number of electrodes are formed for explaining the first embodiment of the present invention, and FIG. The figure is a sectional view of a semiconductor substrate and a molten soldering device for explaining a first embodiment of the present invention. First, as shown in FIG. 1, as in the conventional example, an oxide film 2 on a semiconductor substrate 1 is
An electrode pad 3 made of aluminum is formed thereon. Next, the semiconductor substrate 1 is cleaned by immersing it in, for example, an alkaline aqueous solution to remove the oxide film on the electrode pads 3. next,
For example, the intermediate layer 4 is formed using a displacement plating method using palladium or dumbbell. Next, the semiconductor substrate 1 is immersed in an electroless nickel plating solution using sodium hypophosphite as a reducing agent to form an electroless nickel plating layer 5. For example, the electroless nickel plating layer 5 needs to have a thickness of 1 μm or more.
次に、無電解ニッケルめっき層５の酸化防止やバング形
成後の外観検査を容易にするために、無電解鋼めっき層
６を形成する。この無電解銅めっきｒｒＪＪ６の厚さは
、せいぜい０．１μｍ程度あればよい、またこのめっき
方法は置換めっき法で行ってもよい。次に、第２図に示
すように、前述の方法で多数の電極パッド３のめっき層
の上に、例えば、活性剤の含まないロジン系のペースト
であるはんだフラックス１２を塗布する。次に、第３図
に示すように、噴流式溶融はんだ槽８の溶融はんだ９を
矢印１０の方向に対流させはんだ噴流部分１６を生じさ
せ、このはんだ噴流部分１６に矢印１１の方向に半導体
基板１をいずれかの一端から走行させ、無電解めっき層
６の上にはんだ層を形成し、はんだ層が冷却するととも
に半球状のバンプ状はんだ層７が得られる。この実施例
では、鉛と錫系のはんだの例についって述べたが、金と
錫系のロー材の場合も適用出来る。Next, an electroless steel plating layer 6 is formed to prevent oxidation of the electroless nickel plating layer 5 and to facilitate appearance inspection after forming the bang. The thickness of this electroless copper plating rrJJ6 may be about 0.1 μm at most, and this plating method may be performed by displacement plating. Next, as shown in FIG. 2, solder flux 12, which is, for example, a rosin-based paste containing no activator, is applied onto the plating layer of a large number of electrode pads 3 using the method described above. Next, as shown in FIG. 3, the molten solder 9 in the jet-type molten solder bath 8 is caused to convect in the direction of the arrow 10 to generate a solder jet portion 16, and the solder jet portion 16 is applied to the semiconductor substrate in the direction of the arrow 11. 1 is run from either end, a solder layer is formed on the electroless plating layer 6, and as the solder layer cools, a hemispherical bump-shaped solder layer 7 is obtained. In this embodiment, an example of lead and tin based solder has been described, but the present invention can also be applied to the case of gold and tin based brazing material.
第４図は本発明による第２の実施例を説明するための半
導体基板と溶融はんだ付は装置の断面図である。この実
施例は半導体基板１の電極パッド３上に中間層４、無電
解ニッケルめっき層５及び無電解銅めっき層６を形成す
るまでは、第１の実施例と同じである。第１の実施例の
はんだフラックスの代りに、第４図に示すように、噴流
式溶融はんだ槽８のはんだ噴流部分１６の近傍に非酸化
性ガス１４を収容箱１５の外から配管１３ａ及び１３ｂ
を通し吹付けながら半導体基板１を矢印１１の方向に走
行させ、電極パッドの無電解銅めっき層６にはんだ層を
形成する。このはんだ層は冷却するとともに半球状にな
り、バンプ状のはんだ層７が形成される。配管１３ａ及
び１３ｂはいずれもその幅が半導体基板ｌより大きく、
通常の配管を横方向に押しつぶしてノズル状に製作され
、互いに対向するように取付けられている。また、ガス
の送風圧は大気に対して０．０５〜０．２５ａ ｔ ｒ
ｎ程度の圧力差ではんだ噴流部分１６の周囲を非酸１ヒ
性ガス１４で包むように吹付ける。ここで、非酸化性ガ
ス１４には、例えば、窒素、アルゴン、または窒素と水
素の混合ガスを用いればよい。この実施例によるはんだ
バンプ電極は第１の実施例よるはんだバンプ電極に比ベ
バンプ状のはんだ層７の表面の仕上がりが良い。FIG. 4 is a sectional view of a semiconductor substrate and a molten soldering device for explaining a second embodiment of the present invention. This embodiment is the same as the first embodiment until an intermediate layer 4, an electroless nickel plating layer 5, and an electroless copper plating layer 6 are formed on the electrode pad 3 of the semiconductor substrate 1. Instead of the solder flux in the first embodiment, as shown in FIG.
The semiconductor substrate 1 is moved in the direction of the arrow 11 while being sprayed through the solder layer to form a solder layer on the electroless copper plating layer 6 of the electrode pad. This solder layer becomes hemispherical as it cools, and a bump-shaped solder layer 7 is formed. Both of the pipes 13a and 13b have a width larger than the semiconductor substrate l;
They are made into nozzle shapes by crushing normal piping horizontally, and are installed so that they face each other. In addition, the gas blowing pressure is 0.05 to 0.25 atr relative to the atmosphere.
The non-acidic arsenic gas 14 is sprayed so as to surround the solder jet portion 16 with a pressure difference of about n. Here, the non-oxidizing gas 14 may be, for example, nitrogen, argon, or a mixed gas of nitrogen and hydrogen. The solder bump electrode according to this embodiment has a better surface finish of the bump-shaped solder layer 7 than the solder bump electrode according to the first embodiment.
以上説明したように、本発明はアルミニウム製の電極に
置換めっき法により中間層を形成し、中間層の上に無電
解めっきを施し、更に、その上に溶融金属めっきをする
こによって、ホトリソグラフィ法により金属層を除去す
る工程がなく、より工数がかからない、より設備コスト
の安いバンプ電極の製造方法が得られるという効果があ
る。As explained above, the present invention forms an intermediate layer on an aluminum electrode by a displacement plating method, performs electroless plating on the intermediate layer, and further performs molten metal plating on top of the intermediate layer, thereby forming a photolithography method. This method does not require the step of removing the metal layer, and has the advantage of providing a method for manufacturing bump electrodes that requires less man-hours and has lower equipment costs.
第１図は本発明によるバンプ電極を含めた半導体基板の
断面図、第２図は本発明の詳細な説明するための多数の
電極が形成された半導体基板の側面図、第３図は本発明
の第１の実施例を説明するための半導体基板と溶融はん
だ付は装置の断面図、第４図は本発明による第２の実施
例をを説明するための半導体基板と溶融はんだ付は装置
の断面図である。FIG. 1 is a cross-sectional view of a semiconductor substrate including bump electrodes according to the present invention, FIG. 2 is a side view of a semiconductor substrate on which a large number of electrodes are formed for explaining the present invention in detail, and FIG. 3 is a cross-sectional view of a semiconductor substrate including bump electrodes according to the present invention. FIG. 4 is a cross-sectional view of a semiconductor substrate and molten soldering apparatus for explaining the first embodiment of the present invention, and FIG. FIG.
１・・・半導体基板、２・・・酸化膜、３・・・電極パ
ッド、４・・・中間層、５・・・無電解ニッケルめっき
層、６・・・無電解銅めっき層、７・・・バンプ状はん
だ層、８・・・噴流式溶融はんだ槽、９・・・溶融はん
だ、１０．１１・・・矢印、１２・・・はんだフラック
ス、１３ａ、１３ｂ・・・配管、１４・・・非酸化性ガ
ス、１５・・・収容箱、１６・・・はんだ噴流部分。DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Oxide film, 3... Electrode pad, 4... Intermediate layer, 5... Electroless nickel plating layer, 6... Electroless copper plating layer, 7... ... Bump-shaped solder layer, 8 ... Jet type molten solder tank, 9 ... Molten solder, 10.11 ... Arrow, 12 ... Solder flux, 13a, 13b ... Piping, 14 ... - Non-oxidizing gas, 15... Storage box, 16... Solder jet part.
Claims (1)
れか、もしくは両金属による金属層を置換めっき法で形
成する工程と、前記金属層上にニッケルあるいは銅のい
ずれかの金属、もしくは両金属による無電解めっき層を
形成する工程と、前記半導体基板を溶融金属に浸すこと
により前記無電解めっき層上に前記溶融金属のバンプ状
の金属層を形成する工程とを含んでいることを特徴とす
るバンプ電極の製造方法。A process of forming a metal layer of either palladium or zinc, or both metals, on an electrode on a semiconductor substrate by displacement plating, and an electroless process of forming a metal layer of nickel or copper, or both metals, on the metal layer. A bump electrode comprising the steps of forming a plating layer and forming a bump-shaped metal layer of the molten metal on the electroless plating layer by immersing the semiconductor substrate in molten metal. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14720988A JPH022132A (en) | 1988-06-14 | 1988-06-14 | Manufacture of bump electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14720988A JPH022132A (en) | 1988-06-14 | 1988-06-14 | Manufacture of bump electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH022132A true JPH022132A (en) | 1990-01-08 |
Family
ID=15425033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14720988A Pending JPH022132A (en) | 1988-06-14 | 1988-06-14 | Manufacture of bump electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH022132A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19616373A1 (en) * | 1996-04-24 | 1997-08-14 | Fraunhofer Ges Forschung | Forming galvanically deposited contact bumps for integrated circuits |
| US5989993A (en) * | 1996-02-09 | 1999-11-23 | Elke Zakel | Method for galvanic forming of bonding pads |
| WO2000060649A1 (en) * | 1999-03-30 | 2000-10-12 | Pac Tech - Packaging Technologies Gmbh | Contact bump with support metallization and method of producing said support metallization |
| EP1100123A1 (en) * | 1999-11-09 | 2001-05-16 | Corning Incorporated | Dip formation of flip-chip solder bumps |
| KR100392498B1 (en) * | 1999-08-30 | 2003-07-22 | 한국과학기술원 | Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating |
-
1988
- 1988-06-14 JP JP14720988A patent/JPH022132A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5989993A (en) * | 1996-02-09 | 1999-11-23 | Elke Zakel | Method for galvanic forming of bonding pads |
| DE19616373A1 (en) * | 1996-04-24 | 1997-08-14 | Fraunhofer Ges Forschung | Forming galvanically deposited contact bumps for integrated circuits |
| WO2000060649A1 (en) * | 1999-03-30 | 2000-10-12 | Pac Tech - Packaging Technologies Gmbh | Contact bump with support metallization and method of producing said support metallization |
| US6720257B1 (en) * | 1999-03-30 | 2004-04-13 | Pac Tech-Packaging Technologies Gmbh | Bump with basic metallization and method for manufacturing the basic metallization |
| KR100392498B1 (en) * | 1999-08-30 | 2003-07-22 | 한국과학기술원 | Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating |
| EP1100123A1 (en) * | 1999-11-09 | 2001-05-16 | Corning Incorporated | Dip formation of flip-chip solder bumps |
| US6551650B1 (en) | 1999-11-09 | 2003-04-22 | Corning Incorporated | Dip formation of flip-chip solder bumps |
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