CN218769525U - Adapter plate and packaging structure based on silver nanoparticles - Google Patents
Adapter plate and packaging structure based on silver nanoparticles Download PDFInfo
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- CN218769525U CN218769525U CN202223375073.8U CN202223375073U CN218769525U CN 218769525 U CN218769525 U CN 218769525U CN 202223375073 U CN202223375073 U CN 202223375073U CN 218769525 U CN218769525 U CN 218769525U
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Abstract
The utility model discloses a keysets based on silver nanoparticle, its first wafer and the second wafer that includes the bonding. The first wafer comprises a first medium layer and a first silver nano layer, a first pad hole penetrating through the first medium layer is formed in the first medium layer, the first silver nano layer comprises silver nano particles filled in the first pad hole, and the first surface of the first wafer is flush with the first surface of the first medium layer. The second wafer comprises a second medium layer and a second silver nano layer, a penetrating second pad hole is formed in the position, corresponding to the first pad hole, of the second medium layer, the second silver nano layer comprises silver nano particles filled in the second pad hole, and the first surface of the second silver nano layer is flush with the first surface of the second medium layer. The pad holes are filled with the silver nanoparticles and are used as interconnection metal, the metal bonding interconnection of the upper wafer and the lower wafer can be realized at a temperature far lower than the melting point of bulk silver by utilizing the high surface energy of the silver nanoparticles, and the bonding metal has excellent heat conduction and electric conduction performance.
Description
Technical Field
The utility model relates to a semiconductor package technical field, in particular to keysets and packaging structure based on silver nanoparticle.
Background
As stated in moore's law, the microelectronics industry has developed rapidly over the past few decades, with photolithographic line dimensions continually being optimized and process nodes increasingly shrinking. However, as the feature size of the transistor gradually approaches the physical limit, the quantum effect and the short channel effect are gradually shown, and it is difficult to make the semiconductor chip always meet the increasing data processing requirement of the modern society in this way. To solve this problem, a chip stacking technique for extending the interconnect dimension to three dimensions has been developed. The chip stacking technology can effectively shorten the interconnection length and improve the functional density of the chip, and is recognized as an ideal solution for meeting the performance requirements of the middle-high-end applications such as artificial intelligence and data centers.
The bonding of the chip is a key link for realizing the three-dimensional integrated application of the chip. The traditional flip chip mounting mode of micro-bumps and underfill meets the risks of nonuniform underfill distribution, solder melting and bridging during reflow when meeting the requirement of ultrahigh-density interconnection. The copper/medium mixed bonding technology can be compatible with the mixed interconnection of copper-copper and medium-medium, does not need micro bumps and underfill, and is a key technology for realizing high-density chip integration. Wherein the high density chip integration generally means that the interconnection pitch is less than or equal to 10 μm and/or the interconnection density is more than or equal to 10000/mm 2 The chip integration of (2).
However, in the copper/dielectric hybrid bonding technology, the process temperature for realizing copper-copper bonding is high, usually exceeding 400 ℃, which is very easy to cause device damage, so the development of the metal/dielectric hybrid bonding technology under the low temperature condition is urgently needed.
SUMMERY OF THE UTILITY MODEL
To some or all problems among the prior art, the utility model discloses the first aspect provides a keysets based on silver nanoparticle, and it includes:
a first wafer, comprising:
a first dielectric layer having a first pad hole penetrating therethrough
The first dielectric layer; and
the first silver nano layer comprises silver nano particles, the silver nano particles are filled in the first bonding pad holes, and the first surface of the first silver nano layer is flush with the first surface of the first dielectric layer; and
a second wafer having a first surface bonded to the first surface of the first wafer and comprising:
a second dielectric layer having a second solder disposed at a position corresponding to the first pad hole
The second pad hole penetrates through the second dielectric layer; and
and the second silver nano layer comprises silver nano particles, the silver nano particles are filled in the second bonding pad hole, and the first surface of the second silver nano layer is flush with the first surface of the second dielectric layer.
Further, the first wafer further comprises a first metal layer which comprises a first metal, the first metal is filled in the first pad hole, the first surface of the first metal layer is connected with the second surface of the first silver nano layer, and the second surface of the first metal layer is flush with the second surface of the first dielectric layer.
Further, the first metal is copper, or aluminum, or an alloy thereof.
Further, the second wafer further comprises a second metal layer which comprises a second metal, the second metal fills the second pad hole, a first surface of the second metal layer is connected with a second surface of the second silver nano layer, and the second surface is flush with a second surface of the second dielectric layer.
Further, the second metal is copper, or aluminum, or an alloy thereof.
Further, the second surface of the first silver nanolayer is flush with the second surface of the first dielectric layer.
Further, the second surface of the second silver nano layer is flush with the second surface of the second dielectric layer.
Based on the foregoing patch panel based on silver nanoparticles, a second aspect of the present invention provides a package structure, which employs the foregoing patch panel to realize electrical interconnection and/or signal interconnection between chips.
The utility model provides a pair of keysets and packaging structure based on silver nanoparticle adopts silver nanoparticle to fill in the pad hole as the unique structure of interconnection metal, and then usable silver nanoparticle interconnection metal structure's high surface energy reduces bonding temperature, realizes the metal-medium hybrid bonding of low temperature (< 300 ℃), and this temperature is far below the silver melting point of block, consequently can effectively avoid causing destruction to active chip. In addition, the silver nanoparticle interconnection metal structure also has good heat conduction and electric conduction performance.
Drawings
To further clarify the above and other advantages and features of various embodiments of the present invention, a more particular description of various embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 shows a schematic structural diagram of an adapter plate based on silver nanoparticles according to an embodiment of the present invention;
fig. 2 shows a schematic structural diagram of an adapter plate based on silver nanoparticles according to another embodiment of the present invention;
fig. 3a-3d show schematic cross-sectional views of a process of forming a silver nanoparticle-based interposer according to an embodiment of the present invention; and
fig. 4a-4d show schematic cross-sectional views of a process of forming a silver nanoparticle-based interposer according to yet another embodiment of the present invention.
Detailed Description
The invention will be further elucidated with reference to the drawings in conjunction with the detailed description. It should be noted that the components in the figures may be shown exaggerated for illustrative purposes and are not necessarily to scale. In the figures, identical or functionally identical components are provided with the same reference symbols.
In the present invention, unless otherwise specified, "disposed on …", "disposed above …" and "disposed above …" do not exclude the presence of an intermediate therebetween. Further, "disposed on or above …" merely indicates the relative positional relationship between two members, and may also be converted to "disposed under or below …" or vice versa in certain cases, such as after reversing the product direction.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present application, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise indicated.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those skilled in the art will appreciate that the components or assemblies may be added as needed for specific scenarios, given the teachings of the present invention.
It is also to be noted that, within the scope of the present invention, the expressions "identical", "equal", etc., do not mean that the two values are absolutely equal, but allow a certain reasonable error, that is, the expressions also cover "substantially identical", "substantially equal". By analogy, in the present disclosure, the terms "perpendicular to", "parallel to", and the like in the table direction also cover the meaning of "substantially perpendicular to", "substantially parallel to".
To the realization copper-copper interconnected temperature higher, cause this problem of destruction to active chip easily, the utility model provides a keysets and packaging structure based on silver nanoparticle adopts silver nanoparticle to fill the pad hole and as interconnection metal, utilizes silver nanoparticle's high surface energy to reduce bonding temperature, realizes the metal-medium mixed bonding of low temperature (< 300 ℃). The invention will be further elucidated with reference to the drawings in conjunction with the detailed description.
Fig. 1 shows a schematic structural diagram of an interposer based on silver nanoparticles according to an embodiment of the present invention. As shown, a silver nanoparticle-based interposer includes a first wafer and a second wafer. Wherein the first surface of the first wafer is bonded to the first surface of the second wafer.
As shown in fig. 1, the first wafer includes a first dielectric layer 111, a first silver nano-layer 112 and a first metal layer 113. A first pad hole 114 is formed in the first dielectric layer 111, and the first pad hole 114 penetrates through the first dielectric layer 111. The first silver nanolayer 112 includes silver nanoparticles, and the silver nanoparticles are filled in the first pad hole 114 such that the first surface of the first silver nanolayer 112 is flush with the first surface of the first dielectric layer 111. The first metal layer 113 includes a first metal, and the first metal fills the first pad hole 114, such that a first surface of the first metal layer 113 is connected to a second surface of the first silver nano-layer 112, and the second surface is flush with the second surface of the first dielectric layer 111. It should be understood that in other embodiments of the present invention, the first wafer may not include the first metal layer 113, that is, as shown in fig. 2, the first pad holes 114 are completely filled with silver nanoparticles, so that the second surface of the first silver nano-layer 112 is flush with the second surface of the first dielectric layer 111. In an embodiment of the present invention, the first metal layer 113 is made of metal such as copper, aluminum or alloy thereof. In yet another embodiment of the present invention, the thickness of the first metal layer 113 is greater than the thickness of the first silver nanolayer 112. Preferably, the first silver nanolayer 112 has a thickness of 1 micron.
As shown in fig. 1, the second wafer includes a second dielectric layer 121, a second silver nanolayer 122, and a second metal layer 123. A second pad hole 124 is disposed on the second dielectric layer 121 at a position corresponding to the first pad hole 114, and the second pad hole 124 penetrates the second dielectric layer 121. The second silver nano-layer 122 includes silver nano-particles, and the silver nano-particles are filled in the second pad holes 124, so that the first surface of the second silver nano-layer 122 is flush with the first surface of the second dielectric layer 121. The second metal layer 133 includes a second metal, and the second metal fills the second pad hole 124, such that the first surface of the second metal layer 123 is connected to the second surface of the second silver nano-layer 122, and the second surface is flush with the second surface of the second dielectric layer 121. It should be understood that in other embodiments of the present invention, the second wafer may not include the second metal layer 123, i.e., as shown in fig. 2, the second pad holes 124 are completely filled with silver nanoparticles, such that the second surface of the second silver nanolayer 122 is flush with the second surface of the second dielectric layer 121. In an embodiment of the present invention, the second metal layer 123 is made of metal such as copper, aluminum or alloy thereof. In yet another embodiment of the present invention, the thickness of the second metal layer 123 is greater than the thickness of the second silver nanolayer 122. Preferably, the thickness of the second silver nanolayer 122 is 1 micron.
It should be understood that, in other embodiments of the present invention, the first pad hole may be completely filled with the silver nanoparticles, and the upper portion and the lower portion of the second pad hole are respectively filled with the second metal and the silver nanoparticles. Or the second bonding pad hole is completely filled with silver nanoparticles, and the upper part and the lower part in the first bonding pad hole are respectively filled with the first metal and the silver nanoparticles, so long as the silver nanoparticles are filled at the bonded side of the first wafer and the second wafer, namely the silver nanoparticles are bonded with the silver nanoparticles when the first wafer and the second wafer are bonded, so as to achieve the purpose of reducing the bonding temperature.
Fig. 3a-3d show cross-sectional schematic views of a process of forming an interposer as shown in fig. 1 according to an embodiment of the present invention. As shown, the formation of the interposer as shown in fig. 1 includes:
firstly, as shown in fig. 3a, a damascene process is used to prepare a copper interconnection line and a first pad hole to be bonded in a first dielectric layer, a first metal is used to fill the first pad hole, and a certain thickness margin, for example, about 1 μm, is left on the top of the first metal filling from a first surface of the first dielectric layer, wherein the filled metal may be copper, aluminum, or an alloy thereof;
then, as shown in fig. 3b, filling silver nanoparticles, wherein the filling method may be magnetron sputtering or drying after slurry blade coating, and at this time, the first pad hole and the first surface of the first dielectric layer are both covered with silver nanoparticles, and the first pad hole is already filled with silver nanoparticles;
next, as shown in fig. 3c, using a chemical mechanical polishing technique to polish the excess silver nanoparticles on the surfaces of the first dielectric layer and the first pad hole, so as to obtain a first dielectric layer bonding surface with low roughness and a metal height closer to the height of the first dielectric layer, thereby forming a first wafer; and
finally, as shown in fig. 3d, a second wafer is formed by the same process, and the first and second wafers are bonded by using a hybrid bonding technique. The bonding process may include plasma activation, water washing or moisture treatment to introduce hydrophilic groups, alignment, bonding work, annealing treatment, and the like. During annealing, a suitable pressure may be applied.
Fig. 4a-4d illustrate schematic cross-sectional views of a process of forming an interposer as shown in fig. 2 according to an embodiment of the present invention. As shown, the formation of the interposer as shown in fig. 2 includes:
firstly, as shown in fig. 4a, an interconnect and a first pad hole to be bonded are prepared on a first dielectric layer by using a damascene process, wherein the interconnect can be made of copper, aluminum, or an alloy thereof;
next, as shown in fig. 4b, filling silver nanoparticles, where the filling method may be magnetron sputtering or drying after slurry blade coating, and at this time, the first pad hole and the first and second surfaces of the first dielectric layer are both covered with silver nanoparticles, and the first pad hole is already filled with silver nanoparticles;
next, as shown in fig. 4c, using a chemical mechanical polishing technique to polish the excess silver nanoparticles on the surfaces of the first dielectric layer and the first pad hole, so as to obtain a first dielectric layer bonding surface with low roughness and a metal height closer to the height of the first dielectric layer, thereby forming a first wafer; and
finally, as shown in fig. 4d, a second wafer is formed through the same process, and the first and second wafers are bonded by using a hybrid bonding technique. The bonding process may include plasma activation, water washing or moisture treatment to introduce hydrophilic groups, alignment, bonding operation, annealing treatment, and the like. During annealing, a suitable pressure may be applied.
Based on as before the keysets based on silver nanoparticle, the utility model discloses still provide an encapsulated structure, its adoption is as before the keysets realizes the electric interconnection and/or the signal interconnection between the chip.
The bonding pad holes are filled with the silver nanoparticles and used as interconnection metal, the high surface energy of the silver nanoparticles is utilized, so that metal bonding interconnection of upper and lower wafers can be realized at a temperature far lower than the melting point of bulk silver, and the bonding metal has excellent heat conduction and electric conduction performance.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (8)
1. An interposer based on silver nanoparticles, comprising:
a first wafer, comprising:
the first medium layer is provided with a first pad hole, and the first pad hole penetrates through the first medium layer; and
the first silver nano layer comprises silver nano particles, the silver nano particles are filled in the first bonding pad hole, and the first surface of the first silver nano layer is flush with the first surface of the first dielectric layer; and
a second wafer having a first surface bonded to the first surface of the first wafer and comprising:
a second bonding pad hole is formed in the second dielectric layer corresponding to the first bonding pad hole, and penetrates through the second dielectric layer; and
and the second silver nano layer comprises silver nano particles, the silver nano particles are filled in the second bonding pad hole, and the first surface of the second silver nano layer is flush with the first surface of the second dielectric layer.
2. The interposer as recited in claim 1, wherein the first wafer further comprises a first metal layer comprising a first metal, the first metal filling the first pad hole, a first surface of the first metal layer being contiguous with a second surface of the first silver nanolayer, the second surface being flush with the second surface of the first dielectric layer.
3. The interposer as recited in claim 2 wherein said first metal is copper or aluminum or alloys thereof.
4. The interposer as recited in claim 1, wherein the second wafer further comprises a second metal layer comprising a second metal, the second metal filling the second pad hole, a first surface of the second metal layer being connected to a second surface of the second silver nanolayer, the second surface being flush with a second surface of the second dielectric layer.
5. The interposer as recited in claim 4 wherein said second metal is copper or aluminum or alloys thereof.
6. The interposer as recited in claim 1 wherein said first silver nanolayer has a second surface that is flush with a second surface of said first dielectric layer.
7. The interposer as recited in claim 1 wherein said second surface of said second silver nanolayer is flush with said second surface of said second dielectric layer.
8. A package structure comprising the interposer of any of claims 1-7, wherein the interposer is configured to enable electrical and/or signal interconnection between chips.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202223375073.8U CN218769525U (en) | 2022-12-15 | 2022-12-15 | Adapter plate and packaging structure based on silver nanoparticles |
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| CN202223375073.8U CN218769525U (en) | 2022-12-15 | 2022-12-15 | Adapter plate and packaging structure based on silver nanoparticles |
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| CN218769525U true CN218769525U (en) | 2023-03-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116960058A (en) * | 2023-09-20 | 2023-10-27 | 湖北江城芯片中试服务有限公司 | Preparation method of adapter plate and adapter plate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116960058A (en) * | 2023-09-20 | 2023-10-27 | 湖北江城芯片中试服务有限公司 | Preparation method of adapter plate and adapter plate |
| CN116960058B (en) * | 2023-09-20 | 2024-01-26 | 湖北江城芯片中试服务有限公司 | Preparation method of adapter plate and adapter plate |
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