KR100886701B1 - Method for packaging a semiconductor chip in fbga type - Google Patents

Method for packaging a semiconductor chip in fbga type Download PDF

Info

Publication number
KR100886701B1
KR100886701B1 KR1020020039670A KR20020039670A KR100886701B1 KR 100886701 B1 KR100886701 B1 KR 100886701B1 KR 1020020039670 A KR1020020039670 A KR 1020020039670A KR 20020039670 A KR20020039670 A KR 20020039670A KR 100886701 B1 KR100886701 B1 KR 100886701B1
Authority
KR
South Korea
Prior art keywords
printed circuit
circuit board
semiconductor chip
tape
package
Prior art date
Application number
KR1020020039670A
Other languages
Korean (ko)
Other versions
KR20040006134A (en
Inventor
송호욱
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020020039670A priority Critical patent/KR100886701B1/en
Publication of KR20040006134A publication Critical patent/KR20040006134A/en
Application granted granted Critical
Publication of KR100886701B1 publication Critical patent/KR100886701B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Abstract

더욱 얇은 패키지 두께와 우수한 열 방출 특성을 제공할 수 있는 반도체 칩패키징 방법이 개시된다. 본 발명은 반도체 칩을 수용할 수 있는 크기의 윈도우를 갖는 인쇄 회로 기판의 제1 면에 테이프를 붙이는 단계와, 상기 인쇄 회로 기판의 제2 면에서 상기 윈도우를 통해 상기 반도체 칩을 상기 테이프에 붙이는 단계와, 상기 제2 면에서 상기 반도체 칩과 상기 인쇄 회로 기판에 대해 와이어 본딩(wire bonding)과 몰딩(molding)을 행하는 단계와, 상기 인쇄 회로 기판의 제1 면에서 상기 테이프를 제거하는 단계와, 상기 테이프가 제거된 인쇄 회로 기판의 제1 면에 솔더볼을 부착하는 단계와, 상기 솔더볼이 부착된 인쇄 회로 기판을 최종 패키지 형태로 절단하는 단계를 포함한다. Disclosed are a semiconductor chip packaging method that can provide thinner package thicknesses and better heat dissipation characteristics. The present invention provides a method of attaching a tape to a tape on a first side of a printed circuit board having a window sized to accommodate a semiconductor chip, and attaching the semiconductor chip to the tape through the window on a second side of the printed circuit board. Performing wire bonding and molding of the semiconductor chip and the printed circuit board on the second surface, and removing the tape from the first surface of the printed circuit board; And attaching solder balls to the first surface of the printed circuit board from which the tape is removed, and cutting the printed circuit board to which the solder balls are attached in a final package form.

에프비지에이, 반도체, 패키지, 몰딩, 인쇄 회로 기판FB AV, Semiconductor, Package, Molding, Printed Circuit Board

Description

에프비지에이 타입으로 반도체 칩을 패키징하는 방법{METHOD FOR PACKAGING A SEMICONDUCTOR CHIP IN FBGA TYPE}METHOD FOR PACKAGING A SEMICONDUCTOR CHIP IN FBGA TYPE

도 1은 본 발명의 일 실시예에 의한 테이프 부착 공정을 설명하는 도면.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a tape attaching process according to an embodiment of the present invention.

도 2는 본 발명의 일 실시예에 의한 칩 부착 공정을 설명하는 도면.2 is a view for explaining a chip attaching process according to an embodiment of the present invention.

도 3은 본 발명의 일 실시예에 의한 와이어링 공정을 설명하는 도면.3 is a diagram illustrating a wiring process according to an embodiment of the present invention.

도 4는 본 발명의 일 실시예에 의한 몰딩 공정을 설명하는 도면.4 is a view for explaining a molding process according to an embodiment of the present invention.

도 5는 본 발명의 일 실시예에 의한 테이프 제거 공정을 설명하는 도면.5 is a diagram illustrating a tape removal process according to an embodiment of the present invention.

도 6은 본 발명의 일 실시예에 의한 솔더볼 부착 공정을 설명하는 도면.6 is a view for explaining a solder ball attaching process according to an embodiment of the present invention.

본 발명은 반도체 칩 패키징 방법에 관한 것으로서, 특히 에프비지에이(FBGA) 타입으로 반도체 칩을 패키징하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for packaging a semiconductor chip, and more particularly, to a method for packaging a semiconductor chip in an FBGA type.

오늘날 전자제품은 더욱 소형화, 경량화, 고속화, 다기능화되고 있으며, 이를 가능하게 위해 개발된 새로운 반도체 칩 패키지 기술 중의 하나가 볼 그리드 어레이(Ball Grid Array : 이하, "BGA"라고 함) 방식이다. BGA 패키지는 통상적인 플라스틱 패키지와는 달리 리드프레임(leadframe) 대신에 인쇄 회로 기판을 사용한 다. 인쇄 회로 기판은 반도체 칩이 접착되는 면의 반대쪽 전면(全面)을 솔더볼(solder ball)들을 배치할 수 있는 영역으로 제공할 수 있기 때문에 모 기판에 대한 실장 밀도 면에서 유리하다.Today's electronic products are becoming smaller, lighter, faster and more versatile, and one of the new semiconductor chip package technologies developed to make this possible is the ball grid array (BGA) method. Unlike conventional plastic packages, BGA packages use printed circuit boards instead of leadframes. The printed circuit board is advantageous in terms of mounting density for the parent substrate because the entire surface opposite to the surface where the semiconductor chip is bonded can be provided as a region in which solder balls can be placed.

그러나, 인쇄 회로 기판의 크기를 축소하는 데는 근본적으로 한계가 있다. 반도체 칩을 실장하기 위하여 회로 배선이 형성되지 않은 영역을 필요로 하기 때문에 인쇄 회로 기판의 크기는 여전히 반도체 칩의 크기보다 클 수밖에 없는 것이다. 이러한 한계를 극복하기 위해 제안된 패키지 형태가 소위 칩 스케일 패키지(Chip Scale Package : 이하, "CSP"라고 함)이다.However, there is a fundamental limit to reducing the size of a printed circuit board. The size of the printed circuit board is still larger than the size of the semiconductor chip because the area where the circuit wiring is not formed is required to mount the semiconductor chip. To overcome this limitation, the proposed package type is a so-called chip scale package (hereinafter referred to as "CSP").

칩 스케일 패키지는 최근 몇 년 사이에 미국, 일본, 한국 등의 수십 개의 회사로부터 여러 유형들이 소개되어 왔으며, 현재도 개발이 진행되고 있다. 칩 스케일 패키지는 구조로 분류했을 때 테이프를 사용하는 형태, 세라믹 기판 또는 두꺼운 폴리이미드 기판을 사용하는 형태, 및 리드프레임과 금속 배선 패턴을 사용하는 형태로 크게 분류될 수 있다. 그 중에서 테이프를 사용하는 형태의 칩 스케일 패키지로는 미세 피치 볼 그리드 어레이(Fine Pitch Ball Grid Array : 이하, "FBGA"라고 함) 패키지가 잘 알려져 있다. Chip scale packages have been introduced in recent years by dozens of companies from the United States, Japan, and Korea, and are still in development. Chip scale packages can be broadly classified into types using tape, types using ceramic substrates or thick polyimide substrates, and types using lead frames and metal wiring patterns. Among them, a fine pitch ball grid array (FBGA) package is known as a chip scale package using a tape.

FBGA형 패키지에는 반도체 칩의 소자 비형성면이 인쇄 회로 기판을 향하는 타입과, 소자 형성면이 인쇄 회로 기판을 향하는 타입이 있다. 이중 전자는 접착제를 통해 인쇄 회로 기판의 일면에 소자 비형성면이 부착된다. 이로 인해 패키지 전체 두께에 인쇄 회로 기판의 두께가 포함되므로 패키지 전체 두께를 줄이는데 한계가 있다. 또한 반도체 칩 전체가 인쇄 회로 기판 또는 몰딩 재료로 둘러 쌓여 있기 때문에 반도체 칩의 어느 부분도 패키지 외부로 노출되지 않게 되어 열 방출 특성이 불량하다는 문제점이 있다. In the FBGA type package, there are a type in which an element non-forming surface of a semiconductor chip faces a printed circuit board, and a type in which an element forming surface faces a printed circuit board. The double electrons are attached to the non-element forming surface on one surface of the printed circuit board through the adhesive. As a result, the thickness of the printed circuit board is included in the overall thickness of the package, thereby limiting the overall thickness of the package. In addition, since the entire semiconductor chip is enclosed by a printed circuit board or a molding material, no part of the semiconductor chip is exposed to the outside of the package, so that a heat dissipation characteristic is poor.

본 발명은 이와 같은 문제점을 해결하기 위하여 제안된 것으로서, 기존의 FBGA 타입 패키지에 비해 더욱 얇게 반도체 칩을 패키징하는 방법을 제공하는 것을 일 목적으로 한다. The present invention has been proposed to solve such a problem, and an object of the present invention is to provide a method of packaging a semiconductor chip thinner than a conventional FBGA type package.

또한 본 발명은 열 방출 특성이 우수한 FBGA 타입의 반도체 칩 패키징 방법을 제공하는 것을 다른 목적으로 한다. Another object of the present invention is to provide a FBGA type semiconductor chip packaging method having excellent heat dissipation characteristics.

이러한 목적을 이루기 위한 본 발명은 FBGA 타입으로 반도체 칩을 패키징하는 방법에 있어서, 상기 반도체 칩을 수용할 수 있는 크기의 윈도우를 갖는 인쇄 회로 기판의 제1 면에 테이프를 붙이는 단계; 상기 인쇄 회로 기판의 제2 면에서 상기 윈도우를 통해 상기 반도체 칩을 상기 테이프에 붙이는 단계; 상기 제2 면에서 상기 반도체 칩과 상기 인쇄 회로 기판에 대해 와이어 본딩(wire bonding)과 몰딩(molding)을 행하는 단계; 상기 인쇄 회로 기판의 제1 면에서 상기 테이프를 제거하는 단계; 상기 테이프가 제거된 인쇄 회로 기판의 제1 면에 솔더볼을 부착하는 단계; 및 상기 솔더볼이 부착된 인쇄 회로 기판을 최종 패키지 형태로 절단하는 단계;를 포함한다. According to an aspect of the present invention, there is provided a method for packaging a semiconductor chip in an FBGA type, the method comprising: attaching a tape to a first surface of a printed circuit board having a window sized to accommodate the semiconductor chip; Attaching the semiconductor chip to the tape through the window at a second side of the printed circuit board; Wire bonding and molding the semiconductor chip and the printed circuit board on the second surface; Removing the tape from the first side of the printed circuit board; Attaching a solder ball to a first surface of the printed circuit board from which the tape is removed; And cutting the printed circuit board to which the solder balls are attached in a final package form.

바람직하게는 상기 인쇄 회로 기판은 일정한 크기의 복수의 윈도우를 갖는다. 그리고 상기 테이프는 UV 테이프 또는 PVC 테이프이다. 상기 와이어 본딩은 클램프 및 히터 블록의 온도가 150 내지 170℃에서 수행되며, 상기 몰딩은 에폭시 몰딩 화합물(epoxy molding compound)에 의해 상기 인쇄 회로 기판 전체에 대해 수행된다. Preferably the printed circuit board has a plurality of windows of constant size. And the tape is a UV tape or PVC tape. The wire bonding is performed at a temperature between 150 and 170 ° C. of the clamp and heater block, and the molding is performed on the entire printed circuit board by an epoxy molding compound.

이와 같은 본 발명의 구성에 의하면 종래와 같이 인쇄 회로 기판 위에 반도체 칩이 위치하는 것이 아니라, 인쇄 회로 기판의 윈도우 내에 반도체 칩이 위치하므로 기존의 FBGA 타입 패키지에 비해 인쇄 회로 기판의 두께만큼 전체 반도체 칩 패키지를 얇게 할 수 있다. 또한 인쇄 회로 기판의 윈도우를 막고 있던 테이프를 제거함에 따라 반도체 칩의 회로 비형성면이 패키지 외부로 노출되므로 본 발명에 의한 반도체 칩 패키지는 열 방출 특성에 있어서 매우 우수하다. According to the configuration of the present invention as described above, the semiconductor chip is not positioned on the printed circuit board as in the prior art, but the semiconductor chip is located in the window of the printed circuit board. The package can be made thinner. In addition, since the unformed surface of the semiconductor chip is exposed to the outside of the package by removing the tape blocking the window of the printed circuit board, the semiconductor chip package according to the present invention is very excellent in heat dissipation characteristics.

이하, 첨부된 도면을 참조하여 본 발명의 일 실시예를 상세히 설명한다. 설명의 일관성을 위하여 도면에서 동일한 참조부호는 동일 또는 유사한 구성요소 및 신호를 가리키는 것으로 사용한다. Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; In the drawings, the same reference numerals are used to refer to the same or similar components and signals for the sake of consistency of description.

도 1은 본 발명의 일 실시예에 의한 테이프 부착 공정을 설명하는 도면으로서, 도 1a는 측면도이고, 도 1b는 평면도이다. 도 1에 도시되어 있는 바와 같이 인쇄 회로 기판(102)은 일정한 크기의 윈도우(106)를 복수개 구비하고 있으며, 테이프(104)는 인쇄 회로 기판(102) 중에서 솔더볼 랜드(solder ball land)가 있는 후면에 부착된다. 1 is a view for explaining a tape applying process according to an embodiment of the present invention, Figure 1a is a side view, Figure 1b is a plan view. As shown in FIG. 1, the printed circuit board 102 includes a plurality of windows 106 having a predetermined size, and the tape 104 has a rear surface having a solder ball land in the printed circuit board 102. Is attached to.

인쇄 회로 기판(102)은 물리적/화학적으로 안정된 물성의 수지와 구리 패턴과 솔더볼 랜드로 이루어진다. 구리 패턴은 인쇄 회로 기판(102)의 전면(前面)에 형성되고, 솔더볼 랜드는 후면(後面)에 형성된다. 테이프(104)는 기본적으로 접착제와 베이스 필름의 2층 구조를 이루는데, 접착제는 적정 접착력을 유지할 수 있게 하며, 베이스 필름은 UV 또는 PVC 재질로 되어 있다.The printed circuit board 102 is made of a physically / chemically stable physical resin, a copper pattern, and a solder ball land. The copper pattern is formed on the front surface of the printed circuit board 102, and the solder ball lands are formed on the rear surface. Tape 104 is basically a two-layer structure of the adhesive and the base film, the adhesive can maintain the proper adhesion, the base film is made of UV or PVC material.

도 2는 본 발명의 일 실시예에 의한 칩 부착 공정을 설명하는 도면으로서, 도 2a는 하나의 윈도우에 대한 측면도이고, 도 2b는 전체 인쇄 회로 기판에 대한 평면도이다. 반도체 칩(202)은 테이프(104)를 이용하여 인쇄 회로 기판(102)의 윈도우(106) 내에 부착된다. 테이프(104)에 도포된 접착제가 반도체 칩(202)을 지지 및 고정한다. 윈도우(106)는 당연히 반도체 칩(202)을 수용(收容)할 수 있을 정도의 크기를 가진다.FIG. 2 is a view illustrating a chip attaching process according to an embodiment of the present invention. FIG. 2A is a side view of one window, and FIG. 2B is a plan view of the entire printed circuit board. The semiconductor chip 202 is attached into the window 106 of the printed circuit board 102 using the tape 104. An adhesive applied to the tape 104 supports and fixes the semiconductor chip 202. The window 106 is, of course, large enough to accommodate the semiconductor chip 202.

도 3은 본 발명의 일 실시예에 의한 와이어 본딩(wire bonding) 공정을 설명하는 도면으로서, 도 3a는 하나의 윈도우에 대한 측면도이고, 도 3b는 두 윈도우에 대한 평면도이다. 본딩 와이어(302)로는 금(gold)을 사용한다. 본딩 와이어(302)는 반도체 칩 상의 소정 위치와 인쇄 회로 기판(102)의 구리 패턴을 전기적으로 연결하는 역할을 한다. 와이어 본딩시에 테이프(104)의 특성을 감안하여 클램프(clamp) 및 히터 블록(heater block)의 온도를 150 내지 170℃ 정도로 설정한다.3 is a view illustrating a wire bonding process according to an embodiment of the present invention. FIG. 3A is a side view of one window, and FIG. 3B is a plan view of two windows. Gold is used as the bonding wire 302. The bonding wire 302 serves to electrically connect a predetermined position on the semiconductor chip with the copper pattern of the printed circuit board 102. In consideration of the characteristics of the tape 104 at the time of wire bonding, the temperature of the clamp and the heater block is set to about 150 to 170 ° C.

도 4는 본 발명의 일 실시예에 의한 몰딩 공정을 설명하는 도면으로서, 도 4a는 하나의 윈도우에 대한 측면도이고, 도 4b는 전체 인쇄 회로 기판에 대한 평면도이다. 도 3에 도시되어 있는 바와 같은 와이어 본딩 공정 이후에 플라즈마 세정(plasma cleaning)을 하고, 이후에 에폭시 몰딩 화합물(epoxy molding compound)(402)을 이용하여 인쇄 회로 기판(102) 전체 면에 대해 몰딩 공정을 수행한다. 몰딩 공정은 인쇄 회로 기판(102)에서 테이프(104)가 부착된 후면(後面)의 반대면인 전면(前面)에서 반도체 칩(202)과 인쇄 회로 기판에 대해 수행된다. 이때 에폭시 몰딩 화합물(402)은 특성상 테이프(104)와의 접착력이 타 소재와의 접착력에 비해 현저히 낮다. 플라즈마 세정 공정은 필요에 따라 선택적이다. 4 is a view for explaining a molding process according to an embodiment of the present invention, Figure 4a is a side view of one window, Figure 4b is a plan view of the entire printed circuit board. Plasma cleaning after the wire bonding process as shown in FIG. 3, followed by molding process for the entire surface of the printed circuit board 102 using an epoxy molding compound 402. Do this. The molding process is performed on the semiconductor chip 202 and the printed circuit board on the front side, which is the reverse side of the back side to which the tape 104 is attached on the printed circuit board 102. At this time, the epoxy molding compound 402 has a significantly lower adhesive force with the tape 104 than the adhesive material with other materials. The plasma cleaning process is optional as needed.

도 5는 본 발명의 일 실시예에 의한 테이프 제거 공정을 설명하는 도면으로서, 도 5a는 하나의 윈도우에 대한 측면도이고, 도 5b는 전체 인쇄 회로 기판에 대한 측면도이다. 포스트 몰드 경화(post mold cure) 이전 또는 이후에 인쇄 회로 기판(102)의 후면에 부착되어 있는 테이프(104)를 제거한다. 5 is a view illustrating a tape removal process according to an embodiment of the present invention, FIG. 5A is a side view of one window, and FIG. 5B is a side view of the entire printed circuit board. The tape 104 attached to the backside of the printed circuit board 102 is removed before or after post mold cure.

도 6은 본 발명의 일 실시예에 의한 솔더볼 부착 공정을 설명하는 도면으로서, 하나의 윈도우에 대한 측면도이다. 도 5에 도시되어 있는 바와 같이 인쇄 회로 기판(102)의 후면에 부착되어 있는 테이프(104)를 제거한 후에는 솔더볼(602)을 부착하고, 이후에 리플로우 플럭스 세정(reflow flux cleaning)을 진행한다. 다음에는 하나의 칩마다 단위화(singulation)를 진행하여 최종 패키지 형태로 완성한다. 이러한 과정을 통해 볼 높이가 최대 0.300㎜이고, 인쇄 회로 기판의 두께가 최대 0.180㎜이며, 몰드 몸체의 높이가 최대 0.220㎜인 패키지를 제조할 수 있다. 6 is a view illustrating a solder ball attaching process according to an embodiment of the present invention, and is a side view of one window. As shown in FIG. 5, after removing the tape 104 attached to the rear surface of the printed circuit board 102, the solder balls 602 are attached, and then reflow flux cleaning is performed. . Next, each chip is subjected to singulation to complete the final package. Through this process, a package having a ball height of up to 0.300 mm, a thickness of a printed circuit board up to 0.180 mm, and a height of a mold body up to 0.220 mm may be manufactured.

여기서 설명된 실시예들은 본 발명을 당업자가 용이하게 이해하고 실시할 수 있도록 하기 위한 것일 뿐이며, 본 발명의 범위를 한정하려는 것은 아니다. 따라서 당업자들은 본 발명의 범위 안에서 다양한 변형이나 변경이 가능함을 주목하여야 한다. 본 발명의 범위는 원칙적으로 후술하는 특허청구범위에 의하여 정하여진다.The embodiments described herein are merely intended to enable those skilled in the art to easily understand and practice the present invention, and are not intended to limit the scope of the present invention. Therefore, those skilled in the art should note that various modifications or changes are possible within the scope of the present invention. The scope of the invention is defined in principle by the claims that follow.

이와 같은 본 발명의 구성에 의하면 종래와 같이 인쇄 회로 기판 위에 반도체 칩이 위치하는 것이 아니라, 인쇄 회로 기판의 윈도우 내에 반도체 칩이 위치하 므로 기존의 FBGA 타입 패키지에 비해 인쇄 회로 기판의 두께만큼 전체 반도체 칩 패키지를 1.0㎜ 이하의 두께로 만들 수 있다. 또한 인쇄 회로 기판의 윈도우를 막고 있던 테이프를 제거함에 따라 반도체 칩의 회로 비형성면이 패키지 외부로 노출되므로 본 발명에 의한 반도체 칩 패키지는 열 방출 특성에 있어서 매우 우수하다. 또한 반도체 칩 패키지의 구조가 간단하여 패키징 공정이 단순하고 품질 및 생산성이 우수할 뿐만 아니라 가격 경쟁력이 높다는 이점 또한 가지고 있다. According to the configuration of the present invention as described above, the semiconductor chip is not positioned on the printed circuit board as in the prior art, but the semiconductor chip is located in the window of the printed circuit board. The chip package can be made to a thickness of 1.0 mm or less. In addition, since the unformed surface of the semiconductor chip is exposed to the outside of the package by removing the tape blocking the window of the printed circuit board, the semiconductor chip package according to the present invention is very excellent in heat dissipation characteristics. In addition, the simple structure of the semiconductor chip package has the advantages of a simple packaging process, excellent quality and productivity, and high price competitiveness.

Claims (5)

에프비지에이(FBGA) 타입으로 반도체 칩을 패키징하는 방법에 있어서,In the method of packaging a semiconductor chip in the FBGA (FBGA) type, 상기 반도체 칩을 수용할 수 있는 크기의 윈도우를 갖는 인쇄 회로 기판의 제1 면에 테이프를 붙이는 단계; Adhering a tape to a first side of a printed circuit board having a window sized to receive the semiconductor chip; 상기 인쇄 회로 기판의 제2 면에서 상기 윈도우를 통해 상기 반도체 칩을 상기 테이프에 붙이는 단계; Attaching the semiconductor chip to the tape through the window at a second side of the printed circuit board; 상기 제2 면에서 상기 반도체 칩과 상기 인쇄 회로 기판에 대해 와이어 본딩(wire bonding)과 몰딩(molding)을 행하는 단계; Wire bonding and molding the semiconductor chip and the printed circuit board on the second surface; 상기 인쇄 회로 기판의 제1 면에서 상기 테이프를 제거하는 단계; Removing the tape from the first side of the printed circuit board; 상기 테이프가 제거된 인쇄 회로 기판의 제1 면에 솔더볼을 부착하는 단계; 및 Attaching a solder ball to a first surface of the printed circuit board from which the tape is removed; And 상기 솔더볼이 부착된 인쇄 회로 기판을 최종 패키지 형태로 절단하는 단계; Cutting the solder ball-attached printed circuit board into a final package; 를 포함하는 것을 특징으로 하는 반도체 칩 패키징 방법.Semiconductor chip packaging method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 인쇄 회로 기판은 일정한 크기의 복수의 윈도우를 갖는 것을 특징으로 하는 반도체 칩 패키징 방법.And the printed circuit board has a plurality of windows of a constant size. 제 1 항에 있어서,The method of claim 1, 상기 테이프는 UV 테이프 또는 PVC 테이프인 것을 특징으로 하는 반도체 칩 패키징 방법.The tape is a semiconductor chip packaging method, characterized in that the UV tape or PVC tape. 제 3 항에 있어서,The method of claim 3, wherein 상기 와이어 본딩은 클램프 및 히터 블록의 온도가 150 내지 170℃에서 수행되는 것을 특징으로 하는 반도체 칩 패키징 방법.The wire bonding is a semiconductor chip packaging method, characterized in that the temperature of the clamp and the heater block is carried out at 150 to 170 ℃. 제 1 항에 있어서,The method of claim 1, 상기 몰딩은 에폭시 몰딩 화합물(epoxy molding compound)에 의해 상기 인쇄 회로 기판 전체에 대해 수행되는 것을 특징으로 하는 반도체 칩 패키징 방법.Wherein the molding is performed on the entire printed circuit board by an epoxy molding compound.
KR1020020039670A 2002-07-09 2002-07-09 Method for packaging a semiconductor chip in fbga type KR100886701B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020020039670A KR100886701B1 (en) 2002-07-09 2002-07-09 Method for packaging a semiconductor chip in fbga type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020020039670A KR100886701B1 (en) 2002-07-09 2002-07-09 Method for packaging a semiconductor chip in fbga type

Publications (2)

Publication Number Publication Date
KR20040006134A KR20040006134A (en) 2004-01-24
KR100886701B1 true KR100886701B1 (en) 2009-03-04

Family

ID=37316053

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020039670A KR100886701B1 (en) 2002-07-09 2002-07-09 Method for packaging a semiconductor chip in fbga type

Country Status (1)

Country Link
KR (1) KR100886701B1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100257420B1 (en) * 1995-08-02 2000-05-15 포만 제프리 엘 Systems interconnected by bumps of joining material
KR20010017024A (en) * 1999-08-06 2001-03-05 윤종용 Chip scale type semiconductor package
KR20010019775A (en) * 1999-08-30 2001-03-15 윤덕용 Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating and Their Use

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100257420B1 (en) * 1995-08-02 2000-05-15 포만 제프리 엘 Systems interconnected by bumps of joining material
KR20010017024A (en) * 1999-08-06 2001-03-05 윤종용 Chip scale type semiconductor package
KR20010019775A (en) * 1999-08-30 2001-03-15 윤덕용 Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating and Their Use

Also Published As

Publication number Publication date
KR20040006134A (en) 2004-01-24

Similar Documents

Publication Publication Date Title
KR100680668B1 (en) Semiconductor integrated circuit device
US6723583B2 (en) Method of manufacturing a semiconductor device using a mold
US6902955B2 (en) Method of manufacturing a semiconductor device having a flexible wiring substrate
US5859475A (en) Carrier strip and molded flex circuit ball grid array
US9024419B2 (en) Method of manufacturing semiconductor device
JPH08279591A (en) Semiconductor device and its manufacture
KR20040037575A (en) Micro leadless package having oblique etching line
JP2000077596A (en) Lead frame, manufacturing method therefor, and resin sealed semiconductor device and manufacturing method therefor
JPH05267555A (en) Semiconductor device and its manufacture, and lead frame used for it and its manufacture
JPH10256417A (en) Manufacture of semiconductor package
JP2000040676A (en) Manufacture of semiconductor device
KR100886701B1 (en) Method for packaging a semiconductor chip in fbga type
CN111799243A (en) Chip packaging substrate and manufacturing method thereof, chip packaging structure and packaging method
JPH09116045A (en) Resin-sealed semiconductor device of bga type using lead frame and its manufacture
JP2696532B2 (en) Semiconductor device and manufacturing method thereof
JPH0870082A (en) Semiconductor integrated circuit device and its manufacture, and lead frame
KR200159861Y1 (en) Semiconductor package
JP2004172647A (en) Semiconductor device
JP2002124596A (en) Semiconductor device and production method therefor
JP2001015630A (en) Bga-semiconductor package and its manufacture
KR100195507B1 (en) Slim type semiconductor chip package device
JP2002164497A (en) Semiconductor device and method for manufacturing the same
KR20000013555U (en) Ball grid array package
JPH09266273A (en) Semiconductor package device and its manufacturing method
KR20020043671A (en) Warpage reduction structure of heat sink for manufacturing semiconductor package

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee